From 6d8213dfd6f9bc561c6f9e0793c171321178a21b Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 18 Jun 2024 09:43:18 -0300 Subject: [PATCH 01/17] CommsCtrlFPGA,infra-cores: update submodules The infra-cores submodule now uses VHDL08's features, so, to ease things up, use this standard for all files. Also, IP cores in both submodules were migrated to Vivado 2022, which means that from now on we should use this version for building. --- hdl/ip_cores/CommsCtrlFPGA | 2 +- hdl/ip_cores/infra-cores | 2 +- hdl/syn/afc_v3/commands.tcl | 2 ++ hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py | 7 ++++++- hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py | 7 ++++++- hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py | 7 ++++++- hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py | 7 ++++++- hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/Manifest.py | 7 ++++++- hdl/syn/afc_v3/dbe_pbpm/Manifest.py | 7 ++++++- hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py | 7 ++++++- 10 files changed, 46 insertions(+), 9 deletions(-) create mode 100644 hdl/syn/afc_v3/commands.tcl diff --git a/hdl/ip_cores/CommsCtrlFPGA b/hdl/ip_cores/CommsCtrlFPGA index 66f314ff..73f76db4 160000 --- a/hdl/ip_cores/CommsCtrlFPGA +++ b/hdl/ip_cores/CommsCtrlFPGA @@ -1 +1 @@ -Subproject commit 66f314fff7eb36150c575fae52f9eb52d77eae13 +Subproject commit 73f76db43af853e0b1bf976499a761fb29d07f1e diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index 09482044..9257afdc 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit 0948204484cd07b903043a6a08d1ac1a86f8d1d7 +Subproject commit 9257afdcc505a6f745fc8d0efbf8822d2adfca07 diff --git a/hdl/syn/afc_v3/commands.tcl b/hdl/syn/afc_v3/commands.tcl new file mode 100644 index 00000000..36773b44 --- /dev/null +++ b/hdl/syn/afc_v3/commands.tcl @@ -0,0 +1,2 @@ +puts "Setting all VHDL source files file_type to VHDL 2008" +set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py index d1a08ff7..8fdc4177 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py @@ -35,13 +35,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "sirius_bo_250M"; # Pass more XDC to afc-gw so it will merge it last with diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py index 9649ab3c..e121c55b 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py @@ -35,13 +35,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "sirius_bo_250M"; # Pass more XDC to afc-gw so it will merge it last with diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py index b58ec1e2..556d7fac 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py @@ -35,13 +35,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "sirius_sr_250M"; # Pass more XDC to afc-gw so it will merge it last with diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py index c1e9e998..fbaf8c6e 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py @@ -35,13 +35,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "sirius_sr_250M"; # Pass more XDC to afc-gw so it will merge it last with diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/Manifest.py index 7661b4d6..22cbcfbf 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/Manifest.py @@ -35,13 +35,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "sirius_sr_250M"; # Pass more XDC to afc-gw so it will merge it last with diff --git a/hdl/syn/afc_v3/dbe_pbpm/Manifest.py b/hdl/syn/afc_v3/dbe_pbpm/Manifest.py index dba93664..ec86df19 100755 --- a/hdl/syn/afc_v3/dbe_pbpm/Manifest.py +++ b/hdl/syn/afc_v3/dbe_pbpm/Manifest.py @@ -30,13 +30,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "pbpm_fmcpico1M" # Pass more XDC to afc-gw so it will merge it last with diff --git a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py index 79360966..c9ad387f 100755 --- a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py @@ -24,13 +24,18 @@ # For appending the afc_ref_design.xdc to synthesis afc_base_xdc = ['acq'] +files = [] + import os import sys if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files = ["synthesis_descriptor_pkg.vhd"]; + files.append("synthesis_descriptor_pkg.vhd"); else: sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") +# TCL commands file +files.append("../commands.tcl") + machine_pkg = "pbpm_fmcpico1M" # Pass more XDC to afc-gw so it will merge it last with From 4796884afd374d52a76939b1fb544f4c2f2bf553 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 18 Jun 2024 09:35:59 -0300 Subject: [PATCH 02/17] dbe_pbpm_with_dcc/Manifest: point to the proper top-level This Manifest should point to the PBPM top-level that instantiates DCC cores. --- hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py index c9ad387f..eb573bd2 100755 --- a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py @@ -6,8 +6,8 @@ syn_device = "xc7a200t" syn_grade = "-2" syn_package = "ffg1156" -syn_top = "dbe_pbpm" -syn_project = "dbe_pbpm" +syn_top = "dbe_pbpm_with_dcc" +syn_project = "dbe_pbpm_with_dcc" syn_tool = "vivado" syn_properties = [ ["steps.synth_design.args.more options", "-verbose"], @@ -52,6 +52,6 @@ modules = { "local" : [ - "../../../top/afc_v3/dbe_pbpm" + "../../../top/afc_v3/dbe_pbpm_with_dcc" ] } From 42b31eaf9a35c3521b1e88f0dfd9614810a7eae2 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 18 Jun 2024 10:12:29 -0300 Subject: [PATCH 03/17] pbpm_fmcpico1M/machine_pkg.vhd: adjust PBPM rates Adjust PBPM rates so they're the closest possible to EBPM rates. Note that PBMs aren't synchronized to the Timing system, so no sampling frequency/phase relation should be assumed between them and EBPMs. --- hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd b/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd index f7caf4a3..61d5d4ba 100644 --- a/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd +++ b/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd @@ -65,17 +65,17 @@ package machine_pkg is constant c_pos_calc_fofb_cic_delay : natural := 1; constant c_pos_calc_fofb_cic_stages : natural := 1; - constant c_pos_calc_fofb_ratio : natural := 10; + constant c_pos_calc_fofb_ratio : natural := 21; constant c_pos_calc_fofb_decim_width : natural := 32; constant c_pos_calc_monit1_cic_delay : natural := 1; constant c_pos_calc_monit1_cic_stages : natural := 1; - constant c_pos_calc_monit1_ratio : natural := 100; --ratio between fofb and monit 1 + constant c_pos_calc_monit1_ratio : natural := 8; --ratio between fofb and monit 1 constant c_pos_calc_monit1_cic_ratio : natural := 8; constant c_pos_calc_monit2_cic_delay : natural := 1; constant c_pos_calc_monit2_cic_stages : natural := 1; - constant c_pos_calc_monit2_ratio : natural := 40; -- ratio between monit 1 and 2 + constant c_pos_calc_monit2_ratio : natural := 575; -- ratio between monit 1 and 2 constant c_pos_calc_monit2_cic_ratio : natural := 8; constant c_pos_calc_monit_decim_width : natural := 32; From 10a9fe06c1cf06c908420ce8d36915a49e4bf796 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 21 Jun 2024 13:01:43 -0300 Subject: [PATCH 04/17] pbpm_fmcpico1M/machine_pkg.vhd: better document rates --- .../machine/pbpm_fmcpico1M/machine_pkg.vhd | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd b/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd index 61d5d4ba..597a4841 100644 --- a/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd +++ b/hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd @@ -43,6 +43,8 @@ use ieee.numeric_std.all; use ieee.math_real.all; package machine_pkg is + -- NOTE: PBMs aren't synchronized to the Timing system, so no sampling + -- frequency/phase relation should be assumed between them and EBPMs. constant c_pos_calc_with_downconv : boolean := false; @@ -58,24 +60,29 @@ package machine_pkg is constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif"; constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif"; + -- TbT rate: 500 kHz + -- NOTE: This is way off EBPMs' TbT rate (~578 KHz) constant c_pos_calc_tbt_cic_delay : natural := 1; constant c_pos_calc_tbt_cic_stages : natural := 1; - constant c_pos_calc_tbt_ratio : natural := 2; + constant c_pos_calc_tbt_ratio : natural := 2; -- ratio between ADC and TbT rates constant c_pos_calc_tbt_decim_width : natural := 32; + -- FOFB rate: 47.619 kHz constant c_pos_calc_fofb_cic_delay : natural := 1; constant c_pos_calc_fofb_cic_stages : natural := 1; - constant c_pos_calc_fofb_ratio : natural := 21; + constant c_pos_calc_fofb_ratio : natural := 21; -- ratio between ADC and FOFB rates constant c_pos_calc_fofb_decim_width : natural := 32; + -- FAcq rate: 5.952 kHz constant c_pos_calc_monit1_cic_delay : natural := 1; constant c_pos_calc_monit1_cic_stages : natural := 1; - constant c_pos_calc_monit1_ratio : natural := 8; --ratio between fofb and monit 1 + constant c_pos_calc_monit1_ratio : natural := 8; -- ratio between FOFB and FAcq rates constant c_pos_calc_monit1_cic_ratio : natural := 8; + -- Monit rate: 10.352 Hz constant c_pos_calc_monit2_cic_delay : natural := 1; constant c_pos_calc_monit2_cic_stages : natural := 1; - constant c_pos_calc_monit2_ratio : natural := 575; -- ratio between monit 1 and 2 + constant c_pos_calc_monit2_ratio : natural := 575; -- ratio between FAcq and Monit rates constant c_pos_calc_monit2_cic_ratio : natural := 8; constant c_pos_calc_monit_decim_width : natural := 32; From 60f0e978cd585373b7b9191ace1d69d1978bd3b1 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 26 Jun 2024 09:43:53 -0300 Subject: [PATCH 05/17] Relax timing constraints for FMC ADC clocks The maximum FMC ADC clock for our use case is 220.9 MHz (4.52 ns). To improve timing closure prospects, increase the clock period from 4.3 ns to 4.5 ns. --- hdl/syn/afc_v3/dbe_common/dbe_bpm2.xdc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hdl/syn/afc_v3/dbe_common/dbe_bpm2.xdc b/hdl/syn/afc_v3/dbe_common/dbe_bpm2.xdc index 367bb39a..a8d73083 100644 --- a/hdl/syn/afc_v3/dbe_common/dbe_bpm2.xdc +++ b/hdl/syn/afc_v3/dbe_common/dbe_bpm2.xdc @@ -847,24 +847,24 @@ set clk_pll_ddr_period_less [expr $clk_pll_ddr_period - 1 set clk_125mhz_period [get_property PERIOD [get_clocks clk_125mhz]] # real jitter is about 22ps peak-to-peak -create_clock -period 4.300 -name fmc1_adc_clk0_p_i [get_ports fmc1_adc_clk0_p_i] +create_clock -period 4.500 -name fmc1_adc_clk0_p_i [get_ports fmc1_adc_clk0_p_i] set_input_jitter fmc1_adc_clk0_p_i 0.050 -create_clock -period 4.300 -name fmc2_adc_clk0_p_i [get_ports fmc2_adc_clk0_p_i] +create_clock -period 4.500 -name fmc2_adc_clk0_p_i [get_ports fmc2_adc_clk0_p_i] set_input_jitter fmc2_adc_clk0_p_i 0.050 -create_clock -period 4.300 -name fmc1_adc_clk1_p_i [get_ports fmc1_adc_clk1_p_i] +create_clock -period 4.500 -name fmc1_adc_clk1_p_i [get_ports fmc1_adc_clk1_p_i] set_input_jitter fmc1_adc_clk1_p_i 0.050 -create_clock -period 4.300 -name fmc2_adc_clk1_p_i [get_ports fmc2_adc_clk1_p_i] +create_clock -period 4.500 -name fmc2_adc_clk1_p_i [get_ports fmc2_adc_clk1_p_i] set_input_jitter fmc2_adc_clk1_p_i 0.050 -create_clock -period 4.300 -name fmc1_adc_clk2_p_i [get_ports fmc1_adc_clk2_p_i] +create_clock -period 4.500 -name fmc1_adc_clk2_p_i [get_ports fmc1_adc_clk2_p_i] set_input_jitter fmc1_adc_clk2_p_i 0.050 -create_clock -period 4.300 -name fmc2_adc_clk2_p_i [get_ports fmc2_adc_clk2_p_i] +create_clock -period 4.500 -name fmc2_adc_clk2_p_i [get_ports fmc2_adc_clk2_p_i] set_input_jitter fmc2_adc_clk2_p_i 0.050 -create_clock -period 4.300 -name fmc1_adc_clk3_p_i [get_ports fmc1_adc_clk3_p_i] +create_clock -period 4.500 -name fmc1_adc_clk3_p_i [get_ports fmc1_adc_clk3_p_i] set_input_jitter fmc1_adc_clk3_p_i 0.050 -create_clock -period 4.300 -name fmc2_adc_clk3_p_i [get_ports fmc2_adc_clk3_p_i] +create_clock -period 4.500 -name fmc2_adc_clk3_p_i [get_ports fmc2_adc_clk3_p_i] set_input_jitter fmc2_adc_clk3_p_i 0.050 # ADC generated clocks From a9a514145d8fab47c06839045d1b67d940cee3aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89rico=20Nogueira?= Date: Wed, 3 Apr 2024 11:59:06 -0300 Subject: [PATCH 06/17] position_calc: make fixed-point position read-only. Reported-by: Henrique F. Simoes --- hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html | 2 +- hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby | 2 +- hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html index 04b0003f..86c6c357 100644 --- a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html +++ b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html @@ -6216,7 +6216,7 @@

2.72. adc_gains_fixed_point_pos

  • data -[rw]: fixed-point position constant value +[ro]: fixed-point position constant value

2.73. adc_ch0_swclk_0_gain

diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby index 76873761..1b224483 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby @@ -2027,7 +2027,7 @@ memory-map: name: adc_gains_fixed_point_pos address: 0x0000011c width: 32 - access: rw + access: ro description: ADC gains fixed-point position constant children: - field: diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h index da5d7269..a3644c4c 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h @@ -679,7 +679,7 @@ struct pos_calc { /* [0x118]: REG (rw) BPM Y position offset parameter register */ uint32_t offset_y; - /* [0x11c]: REG (rw) ADC gains fixed-point position constant */ + /* [0x11c]: REG (ro) ADC gains fixed-point position constant */ uint32_t adc_gains_fixed_point_pos; /* [0x120]: REG (rw) ADC channel 0 gain on RFFE switch state 0 (inverted) */ From 34fc46f5b7486e51c6d9a76ffc4d1a2a8d36e779 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 20 May 2024 15:53:26 -0300 Subject: [PATCH 07/17] position_calc.vhd: name signals consistently --- hdl/modules/position_calc/position_calc.vhd | 31 +++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/hdl/modules/position_calc/position_calc.vhd b/hdl/modules/position_calc/position_calc.vhd index 23c785bd..a8aa0d3e 100644 --- a/hdl/modules/position_calc/position_calc.vhd +++ b/hdl/modules/position_calc/position_calc.vhd @@ -373,10 +373,11 @@ architecture rtl of position_calc is signal adc_input_d1 : t_input := (others => (others => '0')); signal adc_input_scaled : t_input := (others => (others => '0')); - type t_input_gain is array(3 downto 0) of std_logic_vector(g_adc_gain_width-1 downto 0); - signal adc_input_gain : t_input_gain := (others => (others => '0')); - signal adc_input_swclk_0_gain : t_input_gain := (others => (others => '0')); - signal adc_input_swclk_1_gain : t_input_gain := (others => (others => '0')); + type t_adc_gain_arr is array(3 downto 0) of std_logic_vector(g_adc_gain_width-1 downto 0); + signal adc_gain_arr : t_adc_gain_arr := (others => (others => '0')); + signal adc_gain_swclk_0_arr : t_adc_gain_arr := (others => (others => '0')); + signal adc_gain_swclk_1_arr : t_adc_gain_arr := (others => (others => '0')); + type t_input_valid is array(3 downto 0) of std_logic; signal adc_input_valid : t_input_valid := (others => '0'); @@ -458,15 +459,15 @@ begin adc_input_d0(2) <= adc_ch2_i; adc_input_d0(3) <= adc_ch3_i; - adc_input_swclk_0_gain(0) <= adc_ch0_swclk_0_gain_i; - adc_input_swclk_0_gain(1) <= adc_ch1_swclk_0_gain_i; - adc_input_swclk_0_gain(2) <= adc_ch2_swclk_0_gain_i; - adc_input_swclk_0_gain(3) <= adc_ch3_swclk_0_gain_i; + adc_gain_swclk_0_arr(0) <= adc_ch0_swclk_0_gain_i; + adc_gain_swclk_0_arr(1) <= adc_ch1_swclk_0_gain_i; + adc_gain_swclk_0_arr(2) <= adc_ch2_swclk_0_gain_i; + adc_gain_swclk_0_arr(3) <= adc_ch3_swclk_0_gain_i; - adc_input_swclk_1_gain(0) <= adc_ch0_swclk_1_gain_i; - adc_input_swclk_1_gain(1) <= adc_ch1_swclk_1_gain_i; - adc_input_swclk_1_gain(2) <= adc_ch2_swclk_1_gain_i; - adc_input_swclk_1_gain(3) <= adc_ch3_swclk_1_gain_i; + adc_gain_swclk_1_arr(0) <= adc_ch0_swclk_1_gain_i; + adc_gain_swclk_1_arr(1) <= adc_ch1_swclk_1_gain_i; + adc_gain_swclk_1_arr(2) <= adc_ch2_swclk_1_gain_i; + adc_gain_swclk_1_arr(3) <= adc_ch3_swclk_1_gain_i; -- adc gains mux (delay: 1 clock cycle) -- each adc channel has two associated gains, one for each rffe switch state (adc_tag_i) @@ -474,9 +475,9 @@ begin begin if rising_edge(clk_i) then if adc_tag_i(0) = '0' then - adc_input_gain <= adc_input_swclk_0_gain; + adc_gain_arr <= adc_gain_swclk_0_arr; else -- adc_tag_i(0) = '1' - adc_input_gain <= adc_input_swclk_1_gain; + adc_gain_arr <= adc_gain_swclk_1_arr; end if; end if; end process; @@ -588,7 +589,7 @@ begin g_levels => 1) port map ( a_i => adc_input(chan), - b_i => adc_input_gain(chan), + b_i => adc_gain_arr(chan), valid_i => adc_input_valid(chan), tag_i => adc_input_tag(chan), p_o => adc_input_scaled(chan), From f3f055dcfc74c4124c63189266d68ac8e6f7f1fa Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 3 May 2024 17:05:52 -0300 Subject: [PATCH 08/17] position_calc.vhd: add ADCs' offset removal stage The ADCs' offset removal is now the first DSP stage, followed by the gain stage. --- hdl/modules/bpm_cores_pkg.vhd | 11 +- hdl/modules/position_calc/position_calc.vhd | 133 +-- .../cheby/doc/wb_pos_calc_regs_wb.html | 890 ++++++++++++++++-- .../cheby/wb_pos_calc_regs.cheby | 147 +++ .../wb_position_calc/cheby/wb_pos_calc_regs.h | 68 +- .../cheby/wb_pos_calc_regs.vhd | 468 ++++++++- .../position_calc_core_pkg.vhd | 4 +- .../wb_position_calc_core.vhd | 45 +- hdl/sim/regs/wb_pos_calc_regs.vh | 30 +- 9 files changed, 1642 insertions(+), 154 deletions(-) diff --git a/hdl/modules/bpm_cores_pkg.vhd b/hdl/modules/bpm_cores_pkg.vhd index d460f540..01a29410 100644 --- a/hdl/modules/bpm_cores_pkg.vhd +++ b/hdl/modules/bpm_cores_pkg.vhd @@ -232,7 +232,8 @@ package bpm_cores_pkg is g_k_width : natural := 25; g_offset_width : natural := 32; g_IQ_width : natural := 32; - g_adc_gain_width : natural := 25); + g_adc_gain_width : natural := 25; + g_adc_offset_width : natural := 16); port ( adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0); adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0); @@ -254,6 +255,14 @@ package bpm_cores_pkg is adc_ch1_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0); adc_ch2_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0); adc_ch3_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0); + adc_ch0_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch1_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch2_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch3_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch0_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch1_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch2_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch3_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0); diff --git a/hdl/modules/position_calc/position_calc.vhd b/hdl/modules/position_calc/position_calc.vhd index a8aa0d3e..2aa7f6b0 100644 --- a/hdl/modules/position_calc/position_calc.vhd +++ b/hdl/modules/position_calc/position_calc.vhd @@ -107,7 +107,10 @@ entity position_calc is g_IQ_width : natural := 32; -- width of adc gains - g_adc_gain_width : natural := 25 + g_adc_gain_width : natural := 25; + + -- Width of ADC offsets + g_adc_offset_width : natural := 16 ); port( @@ -136,6 +139,16 @@ entity position_calc is adc_ch2_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0); adc_ch3_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0); + adc_ch0_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch1_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch2_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch3_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + + adc_ch0_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch1_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch2_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + adc_ch3_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0); + offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0'); @@ -368,26 +381,30 @@ architecture rtl of position_calc is --Signals-- ----------- type t_input is array(3 downto 0) of std_logic_vector(g_input_width-1 downto 0); - signal adc_input : t_input := (others => (others => '0')); signal adc_input_d0 : t_input := (others => (others => '0')); signal adc_input_d1 : t_input := (others => (others => '0')); - signal adc_input_scaled : t_input := (others => (others => '0')); + signal adc_input_offs : t_input := (others => (others => '0')); + signal adc_input_offs_scaled : t_input := (others => (others => '0')); type t_adc_gain_arr is array(3 downto 0) of std_logic_vector(g_adc_gain_width-1 downto 0); signal adc_gain_arr : t_adc_gain_arr := (others => (others => '0')); signal adc_gain_swclk_0_arr : t_adc_gain_arr := (others => (others => '0')); signal adc_gain_swclk_1_arr : t_adc_gain_arr := (others => (others => '0')); + type t_adc_offset_arr is array(3 downto 0) of std_logic_vector(g_adc_offset_width-1 downto 0); + signal adc_offset_arr : t_adc_offset_arr := (others => (others => '0')); + signal adc_offset_swclk_0_arr : t_adc_offset_arr := (others => (others => '0')); + signal adc_offset_swclk_1_arr : t_adc_offset_arr := (others => (others => '0')); type t_input_valid is array(3 downto 0) of std_logic; - signal adc_input_valid : t_input_valid := (others => '0'); signal iq_valid : t_input_valid := (others => '0'); - signal adc_input_scaled_valid : t_input_valid := (others => '0'); + signal adc_input_offs_valid : t_input_valid := (others => '0'); + signal adc_input_offs_scaled_valid : t_input_valid := (others => '0'); signal adc_input_valid_d1 : std_logic := '0'; type t_input_tag is array(3 downto 0) of std_logic_vector(c_adc_tag_width-1 downto 0); - signal adc_input_tag : t_input_tag := (others => (others => '0')); - signal adc_input_scaled_tag : t_input_tag := (others => (others => '0')); + signal adc_input_offs_tag : t_input_tag := (others => (others => '0')); + signal adc_input_offs_scaled_tag : t_input_tag := (others => (others => '0')); signal adc_input_tag_d1 : std_logic_vector(c_adc_tag_width-1 downto 0) := (others => '0'); signal full_i_tag : t_input_tag := (others => (others => '0')); @@ -469,40 +486,45 @@ begin adc_gain_swclk_1_arr(2) <= adc_ch2_swclk_1_gain_i; adc_gain_swclk_1_arr(3) <= adc_ch3_swclk_1_gain_i; - -- adc gains mux (delay: 1 clock cycle) - -- each adc channel has two associated gains, one for each rffe switch state (adc_tag_i) - p_adc_gains_mux: process(clk_i) + adc_offset_swclk_0_arr(0) <= adc_ch0_swclk_0_offset_i; + adc_offset_swclk_0_arr(1) <= adc_ch1_swclk_0_offset_i; + adc_offset_swclk_0_arr(2) <= adc_ch2_swclk_0_offset_i; + adc_offset_swclk_0_arr(3) <= adc_ch3_swclk_0_offset_i; + + adc_offset_swclk_1_arr(0) <= adc_ch0_swclk_1_offset_i; + adc_offset_swclk_1_arr(1) <= adc_ch1_swclk_1_offset_i; + adc_offset_swclk_1_arr(2) <= adc_ch2_swclk_1_offset_i; + adc_offset_swclk_1_arr(3) <= adc_ch3_swclk_1_offset_i; + + -- ADCs' offset (and gain mux) stage + p_adc_offs_stage : process(clk_i) begin if rising_edge(clk_i) then + -- 1st pipeline stage: mux offset if adc_tag_i(0) = '0' then + adc_offset_arr <= adc_offset_swclk_0_arr; + else + adc_offset_arr <= adc_offset_swclk_1_arr; + end if; + adc_input_d1 <= adc_input_d0; + adc_input_tag_d1 <= adc_tag_i; + adc_input_valid_d1 <= adc_valid_i; + + -- 2nd pipeline stage: apply the offset, mux gain + for chan in 3 downto 0 loop + adc_input_offs(chan) <= std_logic_vector( + signed(adc_input_d1(chan)) - signed(adc_offset_arr(chan))); + end loop; + adc_input_offs_tag <= (others => adc_input_tag_d1); + adc_input_offs_valid <= (others => adc_input_valid_d1); + + if adc_input_tag_d1(0) = '0' then adc_gain_arr <= adc_gain_swclk_0_arr; - else -- adc_tag_i(0) = '1' + else adc_gain_arr <= adc_gain_swclk_1_arr; end if; end if; - end process; - - -- pipeline stage to level the delay of p_adc_gains_mux - cmp_pipeline_adc_input_valid : pipeline - generic map ( - g_width => 1, - g_depth => 1) - port map ( - data_i(0) => adc_valid_i, - clk_i => clk_i, - ce_i => '1', - data_o(0) => adc_input_valid_d1); - - -- pipeline stage to level the delay of p_adc_gains_mux - cmp_pipeline_adc_input_tag : pipeline - generic map ( - g_width => 1, - g_depth => 1) - port map ( - data_i => adc_tag_i, - clk_i => clk_i, - ce_i => '1', - data_o => adc_input_tag_d1); + end process p_adc_offs_stage; -- Reset fof TBT rates sync'ed with external signal gen_ddc : for chan in 3 downto 0 generate @@ -563,21 +585,6 @@ begin ratio_i => c_monit2_cic_ratio_slv, strobe_o => ce_monit2(chan)); - -- pipeline stage to level the delay of p_adc_gains_mux - cmp_pipeline_adc_input : pipeline - generic map ( - g_width => g_input_width, - g_depth => 1) - port map ( - data_i => adc_input_d0(chan), - clk_i => clk_i, - ce_i => '1', - data_o => adc_input_d1(chan)); - - adc_input(chan) <= adc_input_d1(chan); - adc_input_tag(chan) <= adc_input_tag_d1; - adc_input_valid(chan) <= adc_input_valid_d1; - cmp_generic_multiplier : generic_multiplier generic map ( g_a_width => g_input_width, @@ -588,13 +595,13 @@ begin g_round_convergent => 1, g_levels => 1) port map ( - a_i => adc_input(chan), + a_i => adc_input_offs(chan), b_i => adc_gain_arr(chan), - valid_i => adc_input_valid(chan), - tag_i => adc_input_tag(chan), - p_o => adc_input_scaled(chan), - valid_o => adc_input_scaled_valid(chan), - tag_o => adc_input_scaled_tag(chan), + valid_i => adc_input_offs_valid(chan), + tag_i => adc_input_offs_tag(chan), + p_o => adc_input_offs_scaled(chan), + valid_o => adc_input_offs_scaled_valid(chan), + tag_o => adc_input_offs_scaled_tag(chan), ce_i => '1', clk_i => clk_i, rst_i => rst_i); @@ -615,9 +622,9 @@ begin rst_i => rst_i, clk_i => clk_i, ce_i => ce_adc(chan), - signal_i => adc_input_scaled(chan), - valid_i => adc_input_scaled_valid(chan), - tag_i => adc_input_scaled_tag(chan), + signal_i => adc_input_offs_scaled(chan), + valid_i => adc_input_offs_scaled_valid(chan), + tag_i => adc_input_offs_scaled_tag(chan), i_o => full_i(chan), q_o => full_q(chan), valid_o => iq_valid(chan), @@ -762,8 +769,8 @@ begin -- rate, so we don't have to -- change them downstream ce_out_i => ce_tbt_cordic(chan), - valid_i => adc_input_scaled_valid(chan), - data_i => adc_input_scaled(chan), + valid_i => adc_input_offs_scaled_valid(chan), + data_i => adc_input_offs_scaled(chan), ratio_i => c_tbt_ratio_slv, data_tag_i => tbt_tag_i, data_tag_en_i => tbt_tag_en_i, @@ -798,9 +805,9 @@ begin rst_i => rst_i, ce_i => ce_adc(chan), ce_out_i => ce_fofb_cordic(chan), - valid_i => adc_input_scaled_valid(chan), - data_i => adc_input_scaled(chan), - data_tag_i => adc_input_scaled_tag(chan), + valid_i => adc_input_offs_scaled_valid(chan), + data_i => adc_input_offs_scaled(chan), + data_tag_i => adc_input_offs_scaled_tag(chan), -- Don't use CIC synchronization feature data_tag_en_i => '0', data_mask_num_samples_beg_i => (others => '0'), diff --git a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html index 86c6c357..82ac75a9 100644 --- a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html +++ b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html @@ -44,7 +44,7 @@

wb_pos_calc_regs

Position Calculation Core registers

Wishbone slave for Position Calculation Core

-

1. Memory map summary

+

1. Memory map summary

@@ -641,11 +641,67 @@

1. Memory map summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HW address adc_ch3_swclk_1_gain adc_ch3_swclk_1_gain
0x140REGadc_ch0_swclk_0_offsetadc_ch0_swclk_0_offsetadc_ch0_swclk_0_offset
0x144REGadc_ch1_swclk_0_offsetadc_ch1_swclk_0_offsetadc_ch1_swclk_0_offset
0x148REGadc_ch2_swclk_0_offsetadc_ch2_swclk_0_offsetadc_ch2_swclk_0_offset
0x14cREGadc_ch3_swclk_0_offsetadc_ch3_swclk_0_offsetadc_ch3_swclk_0_offset
0x150REGadc_ch0_swclk_1_offsetadc_ch0_swclk_1_offsetadc_ch0_swclk_1_offset
0x154REGadc_ch1_swclk_1_offsetadc_ch1_swclk_1_offsetadc_ch1_swclk_1_offset
0x158REGadc_ch2_swclk_1_offsetadc_ch2_swclk_1_offsetadc_ch2_swclk_1_offset
0x15cREGadc_ch3_swclk_1_offsetadc_ch3_swclk_1_offsetadc_ch3_swclk_1_offset

2. Register description

-

2.1. ds_tbt_thres

+

2.1. ds_tbt_thres

@@ -721,7 +777,7 @@

2.1. ds_tbt_thres


Ignore on write, read as 0's -

2.2. ds_fofb_thres

+

2.2. ds_fofb_thres

HW prefix:ds_tbt_thres
HW address:0x0
@@ -797,7 +853,7 @@

2.2. ds_fofb_thres


Ignore on write, read as 0's -

2.3. ds_monit_thres

+

2.3. ds_monit_thres

HW prefix:ds_fofb_thres
HW address:0x4
@@ -873,7 +929,7 @@

2.3. ds_monit_thres


Ignore on write, read as 0's -

2.4. kx

+

2.4. kx

HW prefix:ds_monit_thres
HW address:0x8
@@ -949,7 +1005,7 @@

2.4. kx


Ignore on write, read as 0's -

2.5. ky

+

2.5. ky

HW prefix:kx
HW address:0xc
@@ -1025,7 +1081,7 @@

2.5. ky


Ignore on write, read as 0's -

2.6. ksum

+

2.6. ksum

HW prefix:ky
HW address:0x10
@@ -1101,7 +1157,7 @@

2.6. ksum


Ignore on write, read as 0's -

2.7. dsp_ctnr_tbt

+

2.7. dsp_ctnr_tbt

HW prefix:ksum
HW address:0x14
@@ -1176,7 +1232,7 @@

2.7. dsp_ctnr_tbt


This register holds the number of incorrect transfers
on TDM for channels 2/3 (multiplexed) -

2.8. dsp_ctnr_fofb

+

2.8. dsp_ctnr_fofb

HW prefix:dsp_ctnr_tbt
HW address:0x18
@@ -1251,7 +1307,7 @@

2.8. dsp_ctnr_fofb


This register holds the number of incorrect transfers
on TDM for channels 2/3 (multiplexed) -

2.9. dsp_ctnr1_monit

+

2.9. dsp_ctnr1_monit

HW prefix:dsp_ctnr_fofb
HW address:0x1c
@@ -1326,7 +1382,7 @@

2.9. dsp_ctnr1_monit


This register holds the number of incorrect transfers
on TDM for channels 0/1/2/3 (multiplexed) -

2.10. dsp_ctnr2_monit

+

2.10. dsp_ctnr2_monit

HW prefix:dsp_ctnr1_monit
HW address:0x20
@@ -1401,7 +1457,7 @@

2.10. dsp_ctnr2_monit


This register holds the number of incorrect transfers
on TDM for channels 0/1/2/3 (multiplexed) on Monit_01 chain -

2.11. dsp_err_clr

+

2.11. dsp_err_clr

HW prefix:dsp_ctnr2_monit
HW address:0x24
@@ -1512,7 +1568,7 @@

2.11. dsp_err_clr


This register clears the error counter for the Monit. PFIR
and Monit. 0.1 rate
write 0: no effect
write 1: clear error counter -

2.12. dds_cfg

+

2.12. dds_cfg

HW prefix:dsp_err_clr
HW address:0x28
@@ -1620,7 +1676,7 @@

2.12. dds_cfg


Ignore on write, read as 0's -

2.13. dds_pinc_ch0

+

2.13. dds_pinc_ch0

HW prefix:dds_cfg
HW address:0x2c
@@ -1696,7 +1752,7 @@

2.13. dds_pinc_ch0


Ignore on write, read as 0's -

2.14. dds_pinc_ch1

+

2.14. dds_pinc_ch1

HW prefix:dds_pinc_ch0
HW address:0x30
@@ -1772,7 +1828,7 @@

2.14. dds_pinc_ch1


Ignore on write, read as 0's -

2.15. dds_pinc_ch2

+

2.15. dds_pinc_ch2

HW prefix:dds_pinc_ch1
HW address:0x34
@@ -1848,7 +1904,7 @@

2.15. dds_pinc_ch2


Ignore on write, read as 0's -

2.16. dds_pinc_ch3

+

2.16. dds_pinc_ch3

HW prefix:dds_pinc_ch2
HW address:0x38
@@ -1924,7 +1980,7 @@

2.16. dds_pinc_ch3


Ignore on write, read as 0's -

2.17. dds_poff_ch0

+

2.17. dds_poff_ch0

HW prefix:dds_pinc_ch3
HW address:0x3c
@@ -2000,7 +2056,7 @@

2.17. dds_poff_ch0


Ignore on write, read as 0's -

2.18. dds_poff_ch1

+

2.18. dds_poff_ch1

HW prefix:dds_poff_ch0
HW address:0x40
@@ -2076,7 +2132,7 @@

2.18. dds_poff_ch1


Ignore on write, read as 0's -

2.19. dds_poff_ch2

+

2.19. dds_poff_ch2

HW prefix:dds_poff_ch1
HW address:0x44
@@ -2152,7 +2208,7 @@

2.19. dds_poff_ch2


Ignore on write, read as 0's -

2.20. dds_poff_ch3

+

2.20. dds_poff_ch3

HW prefix:dds_poff_ch2
HW address:0x48
@@ -2228,7 +2284,7 @@

2.20. dds_poff_ch3


Ignore on write, read as 0's -

2.21. dsp_monit_amp_ch0

+

2.21. dsp_monit_amp_ch0

HW prefix:dds_poff_ch3
HW address:0x4c
@@ -2299,7 +2355,7 @@

2.21. dsp_monit_amp_ch0


Monit. Amplitude Value for channel 0 -

2.22. dsp_monit_amp_ch1

+

2.22. dsp_monit_amp_ch1

HW prefix:dsp_monit_amp_ch0
HW address:0x50
@@ -2370,7 +2426,7 @@

2.22. dsp_monit_amp_ch1


Monit. Amplitude Value for channel 1 -

2.23. dsp_monit_amp_ch2

+

2.23. dsp_monit_amp_ch2

HW prefix:dsp_monit_amp_ch1
HW address:0x54
@@ -2441,7 +2497,7 @@

2.23. dsp_monit_amp_ch2


Monit. Amplitude Value for channel 2 -

2.24. dsp_monit_amp_ch3

+

2.24. dsp_monit_amp_ch3

HW prefix:dsp_monit_amp_ch2
HW address:0x58
@@ -2512,7 +2568,7 @@

2.24. dsp_monit_amp_ch3


Monit. Amplitude Value for channel 3 -

2.25. dsp_monit_pos_x

+

2.25. dsp_monit_pos_x

HW prefix:dsp_monit_amp_ch3
HW address:0x5c
@@ -2583,7 +2639,7 @@

2.25. dsp_monit_pos_x


Monit. X Position Value -

2.26. dsp_monit_pos_y

+

2.26. dsp_monit_pos_y

HW prefix:dsp_monit_pos_x
HW address:0x60
@@ -2654,7 +2710,7 @@

2.26. dsp_monit_pos_y


Monit. Y Position Value -

2.27. dsp_monit_pos_q

+

2.27. dsp_monit_pos_q

HW prefix:dsp_monit_pos_y
HW address:0x64
@@ -2725,7 +2781,7 @@

2.27. dsp_monit_pos_q


Monit. Q Position Value -

2.28. dsp_monit_pos_sum

+

2.28. dsp_monit_pos_sum

HW prefix:dsp_monit_pos_q
HW address:0x68
@@ -2796,7 +2852,7 @@

2.28. dsp_monit_pos_sum


Monit. Sum Position Value -

2.29. dsp_monit_updt

+

2.29. dsp_monit_updt

HW prefix:dsp_monit_pos_sum
HW address:0x6c
@@ -2867,7 +2923,7 @@

2.29. dsp_monit_updt


Monit. Amp/Pos update trigger -

2.30. dsp_monit1_amp_ch0

+

2.30. dsp_monit1_amp_ch0

HW prefix:dsp_monit_updt
HW address:0x70
@@ -2938,7 +2994,7 @@

2.30. dsp_monit1_amp_ch0


Monit. 1 Amplitude Value for channel 0 -

2.31. dsp_monit1_amp_ch1

+

2.31. dsp_monit1_amp_ch1

HW prefix:dsp_monit1_amp_ch0
HW address:0x74
@@ -3009,7 +3065,7 @@

2.31. dsp_monit1_amp_ch1


Monit. 1 Amplitude Value for channel 1 -

2.32. dsp_monit1_amp_ch2

+

2.32. dsp_monit1_amp_ch2

HW prefix:dsp_monit1_amp_ch1
HW address:0x78
@@ -3080,7 +3136,7 @@

2.32. dsp_monit1_amp_ch2


Monit. 1 Amplitude Value for channel 2 -

2.33. dsp_monit1_amp_ch3

+

2.33. dsp_monit1_amp_ch3

HW prefix:dsp_monit1_amp_ch2
HW address:0x7c
@@ -3151,7 +3207,7 @@

2.33. dsp_monit1_amp_ch3


Monit. 1 Amplitude Value for channel 3 -

2.34. dsp_monit1_pos_x

+

2.34. dsp_monit1_pos_x

HW prefix:dsp_monit1_amp_ch3
HW address:0x80
@@ -3222,7 +3278,7 @@

2.34. dsp_monit1_pos_x


Monit. 1 X Position Value -

2.35. dsp_monit1_pos_y

+

2.35. dsp_monit1_pos_y

HW prefix:dsp_monit1_pos_x
HW address:0x84
@@ -3293,7 +3349,7 @@

2.35. dsp_monit1_pos_y


Monit. 1 Y Position Value -

2.36. dsp_monit1_pos_q

+

2.36. dsp_monit1_pos_q

HW prefix:dsp_monit1_pos_y
HW address:0x88
@@ -3364,7 +3420,7 @@

2.36. dsp_monit1_pos_q


Monit. 1 Q Position Value -

2.37. dsp_monit1_pos_sum

+

2.37. dsp_monit1_pos_sum

HW prefix:dsp_monit1_pos_q
HW address:0x8c
@@ -3435,7 +3491,7 @@

2.37. dsp_monit1_pos_sum


Monit. 1 Sum Position Value -

2.38. dsp_monit1_updt

+

2.38. dsp_monit1_updt

HW prefix:dsp_monit1_pos_sum
HW address:0x90
@@ -3506,7 +3562,7 @@

2.38. dsp_monit1_updt


Monit. 1 Amp/Pos update trigger -

2.39. ampfifo_monit.ampfifo_monit_r0

+

2.39. ampfifo_monit.ampfifo_monit_r0

HW prefix:dsp_monit1_updt
HW address:0x94
@@ -3576,7 +3632,7 @@

2.39. ampfifo_monit.ampfifo_monit_r0

[ro]: Channel 0 Amplitude -

2.40. ampfifo_monit.ampfifo_monit_r1

+

2.40. ampfifo_monit.ampfifo_monit_r1

HW prefix:ampfifo_monit_ampfifo_monit_r0
HW address:0x98
@@ -3646,7 +3702,7 @@

2.40. ampfifo_monit.ampfifo_monit_r1

[ro]: Channel 1 Amplitude -

2.41. ampfifo_monit.ampfifo_monit_r2

+

2.41. ampfifo_monit.ampfifo_monit_r2

HW prefix:ampfifo_monit_ampfifo_monit_r1
HW address:0x9c
@@ -3716,7 +3772,7 @@

2.41. ampfifo_monit.ampfifo_monit_r2

[ro]: Channel 2 Amplitude -

2.42. ampfifo_monit.ampfifo_monit_r3

+

2.42. ampfifo_monit.ampfifo_monit_r3

HW prefix:ampfifo_monit_ampfifo_monit_r2
HW address:0xa0
@@ -3786,7 +3842,7 @@

2.42. ampfifo_monit.ampfifo_monit_r3

[ro]: Channel 3 Amplitude -

2.43. ampfifo_monit.ampfifo_monit_csr

+

2.43. ampfifo_monit.ampfifo_monit_csr

HW prefix:ampfifo_monit_ampfifo_monit_r3
HW address:0xa4
@@ -3890,7 +3946,7 @@

2.43. ampfifo_monit.ampfifo_monit_csr


Number of data records currently being stored in FIFO 'AMP FIFO Monitoring' -

2.44. posfifo_monit.posfifo_monit_r0

+

2.44. posfifo_monit.posfifo_monit_r0

HW prefix:ampfifo_monit_ampfifo_monit_csr
HW address:0xa8
@@ -3960,7 +4016,7 @@

2.44. posfifo_monit.posfifo_monit_r0

[ro]: Channel X Position -

2.45. posfifo_monit.posfifo_monit_r1

+

2.45. posfifo_monit.posfifo_monit_r1

HW prefix:posfifo_monit_posfifo_monit_r0
HW address:0xac
@@ -4030,7 +4086,7 @@

2.45. posfifo_monit.posfifo_monit_r1

[ro]: Channel Y Position -

2.46. posfifo_monit.posfifo_monit_r2

+

2.46. posfifo_monit.posfifo_monit_r2

HW prefix:posfifo_monit_posfifo_monit_r1
HW address:0xb0
@@ -4100,7 +4156,7 @@

2.46. posfifo_monit.posfifo_monit_r2

[ro]: Channel Q Position -

2.47. posfifo_monit.posfifo_monit_r3

+

2.47. posfifo_monit.posfifo_monit_r3

HW prefix:posfifo_monit_posfifo_monit_r2
HW address:0xb4
@@ -4170,7 +4226,7 @@

2.47. posfifo_monit.posfifo_monit_r3

[ro]: Channel Sum Position -

2.48. posfifo_monit.posfifo_monit_csr

+

2.48. posfifo_monit.posfifo_monit_csr

HW prefix:posfifo_monit_posfifo_monit_r3
HW address:0xb8
@@ -4274,7 +4330,7 @@

2.48. posfifo_monit.posfifo_monit_csr


Number of data records currently being stored in FIFO 'POS FIFO Monitoring' -

2.49. ampfifo_monit1.ampfifo_monit1_r0

+

2.49. ampfifo_monit1.ampfifo_monit1_r0

HW prefix:posfifo_monit_posfifo_monit_csr
HW address:0xbc
@@ -4344,7 +4400,7 @@

2.49. ampfifo_monit1.ampfifo_monit1_r0

[ro]: Channel 0 Amplitude -

2.50. ampfifo_monit1.ampfifo_monit1_r1

+

2.50. ampfifo_monit1.ampfifo_monit1_r1

HW prefix:ampfifo_monit1_ampfifo_monit1_r0
HW address:0xc0
@@ -4414,7 +4470,7 @@

2.50. ampfifo_monit1.ampfifo_monit1_r1

[ro]: Channel 1 Amplitude -

2.51. ampfifo_monit1.ampfifo_monit1_r2

+

2.51. ampfifo_monit1.ampfifo_monit1_r2

HW prefix:ampfifo_monit1_ampfifo_monit1_r1
HW address:0xc4
@@ -4484,7 +4540,7 @@

2.51. ampfifo_monit1.ampfifo_monit1_r2

[ro]: Channel 2 Amplitude -

2.52. ampfifo_monit1.ampfifo_monit1_r3

+

2.52. ampfifo_monit1.ampfifo_monit1_r3

HW prefix:ampfifo_monit1_ampfifo_monit1_r2
HW address:0xc8
@@ -4554,7 +4610,7 @@

2.52. ampfifo_monit1.ampfifo_monit1_r3

[ro]: Channel 3 Amplitude -

2.53. ampfifo_monit1.ampfifo_monit1_csr

+

2.53. ampfifo_monit1.ampfifo_monit1_csr

HW prefix:ampfifo_monit1_ampfifo_monit1_r3
HW address:0xcc
@@ -4658,7 +4714,7 @@

2.53. ampfifo_monit1.ampfifo_monit1_csr


Number of data records currently being stored in FIFO 'AMP FIFO Monitoring 1' -

2.54. posfifo_monit1.posfifo_monit1_r0

+

2.54. posfifo_monit1.posfifo_monit1_r0

HW prefix:ampfifo_monit1_ampfifo_monit1_csr
HW address:0xd0
@@ -4728,7 +4784,7 @@

2.54. posfifo_monit1.posfifo_monit1_r0

[ro]: Channel X Position -

2.55. posfifo_monit1.posfifo_monit1_r1

+

2.55. posfifo_monit1.posfifo_monit1_r1

HW prefix:posfifo_monit1_posfifo_monit1_r0
HW address:0xd4
@@ -4798,7 +4854,7 @@

2.55. posfifo_monit1.posfifo_monit1_r1

[ro]: Channel Y Position -

2.56. posfifo_monit1.posfifo_monit1_r2

+

2.56. posfifo_monit1.posfifo_monit1_r2

HW prefix:posfifo_monit1_posfifo_monit1_r1
HW address:0xd8
@@ -4868,7 +4924,7 @@

2.56. posfifo_monit1.posfifo_monit1_r2

[ro]: Channel Q Position -

2.57. posfifo_monit1.posfifo_monit1_r3

+

2.57. posfifo_monit1.posfifo_monit1_r3

HW prefix:posfifo_monit1_posfifo_monit1_r2
HW address:0xdc
@@ -4938,7 +4994,7 @@

2.57. posfifo_monit1.posfifo_monit1_r3

[ro]: Channel Sum Position -

2.58. posfifo_monit1.posfifo_monit1_csr

+

2.58. posfifo_monit1.posfifo_monit1_csr

HW prefix:posfifo_monit1_posfifo_monit1_r3
HW address:0xe0
@@ -5042,7 +5098,7 @@

2.58. posfifo_monit1.posfifo_monit1_csr


Number of data records currently being stored in FIFO 'POS FIFO Monitoring 1' -

2.59. sw_tag

+

2.59. sw_tag

HW prefix:posfifo_monit1_posfifo_monit1_csr
HW address:0xe4
@@ -5137,7 +5193,7 @@

2.59. sw_tag


Switching Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed -

2.60. sw_data_mask

+

2.60. sw_data_mask

HW prefix:sw_tag
HW address:0xe8
@@ -5227,7 +5283,7 @@

2.60. sw_data_mask


Switching Data Mask Samples
write: number of samples to mask
read: number of samples being masked -

2.61. tbt_tag

+

2.61. tbt_tag

HW prefix:sw_data_mask
HW address:0xec
@@ -5313,7 +5369,7 @@

2.61. tbt_tag


TbT Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed -

2.62. tbt_data_mask_ctl

+

2.62. tbt_data_mask_ctl

HW prefix:tbt_tag
HW address:0xf0
@@ -5412,7 +5468,7 @@

2.62. tbt_data_mask_ctl


TbT Masking
write 0: disable data mask
write 1: enable data mask -

2.63. tbt_data_mask_samples

+

2.63. tbt_data_mask_samples

HW prefix:tbt_data_mask_ctl
HW address:0xf4
@@ -5487,7 +5543,7 @@

2.63. tbt_data_mask_samples


Select the number of samples to mask at the ending of the TbT cycle
write: number of samples to mask
read: number of samples being masked -

2.64. monit1_tag

+

2.64. monit1_tag

HW prefix:tbt_data_mask_samples
HW address:0xf8
@@ -5573,7 +5629,7 @@

2.64. monit1_tag


MONIT1 Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed -

2.65. monit1_data_mask_ctl

+

2.65. monit1_data_mask_ctl

HW prefix:monit1_tag
HW address:0xfc
@@ -5672,7 +5728,7 @@

2.65. monit1_data_mask_ctl


MONIT1 Masking
write 0: disable data mask
write 1: enable data mask -

2.66. monit1_data_mask_samples

+

2.66. monit1_data_mask_samples

HW prefix:monit1_data_mask_ctl
HW address:0x100
@@ -5747,7 +5803,7 @@

2.66. monit1_data_mask_samples


Select the number of samples to mask at the ending of the MONIT1 cycle
write: number of samples to mask
read: number of samples being masked -

2.67. monit_tag

+

2.67. monit_tag

HW prefix:monit1_data_mask_samples
HW address:0x104
@@ -5833,7 +5889,7 @@

2.67. monit_tag


MONIT Desynchronization Counter
write: number of samples to delay trigger
read: number of samples being delayed -

2.68. monit_data_mask_ctl

+

2.68. monit_data_mask_ctl

HW prefix:monit_tag
HW address:0x108
@@ -5932,7 +5988,7 @@

2.68. monit_data_mask_ctl


MONIT Masking
write 0: disable data mask
write 1: enable data mask -

2.69. monit_data_mask_samples

+

2.69. monit_data_mask_samples

HW prefix:monit_data_mask_ctl
HW address:0x10c
@@ -6007,7 +6063,7 @@

2.69. monit_data_mask_samples


Select the number of samples to mask at the ending of the MONIT cycle
write: number of samples to mask
read: number of samples being masked -

2.70. offset_x

+

2.70. offset_x

HW prefix:monit_data_mask_samples
HW address:0x110
@@ -6078,7 +6134,7 @@

2.70. offset_x


BPM X position offset to be subtracted from calculated positions -

2.71. offset_y

+

2.71. offset_y

HW prefix:offset_x
HW address:0x114
@@ -6149,7 +6205,7 @@

2.71. offset_y


BPM Y position offset to be subtracted from calculated positions -

2.72. adc_gains_fixed_point_pos

+

2.72. adc_gains_fixed_point_pos

HW prefix:offset_y
HW address:0x118
@@ -6219,7 +6275,7 @@

2.72. adc_gains_fixed_point_pos

[ro]: fixed-point position constant value -

2.73. adc_ch0_swclk_0_gain

+

2.73. adc_ch0_swclk_0_gain

HW prefix:adc_gains_fixed_point_pos
HW address:0x11c
@@ -6290,7 +6346,7 @@

2.73. adc_ch0_swclk_0_gain


SFIX32_31. -

2.74. adc_ch1_swclk_0_gain

+

2.74. adc_ch1_swclk_0_gain

HW prefix:adc_ch0_swclk_0_gain
HW address:0x120
@@ -6361,7 +6417,7 @@

2.74. adc_ch1_swclk_0_gain


SFIX32_31. -

2.75. adc_ch2_swclk_0_gain

+

2.75. adc_ch2_swclk_0_gain

HW prefix:adc_ch1_swclk_0_gain
HW address:0x124
@@ -6432,7 +6488,7 @@

2.75. adc_ch2_swclk_0_gain


SFIX32_31. -

2.76. adc_ch3_swclk_0_gain

+

2.76. adc_ch3_swclk_0_gain

HW prefix:adc_ch2_swclk_0_gain
HW address:0x128
@@ -6503,7 +6559,7 @@

2.76. adc_ch3_swclk_0_gain


SFIX32_31. -

2.77. adc_ch0_swclk_1_gain

+

2.77. adc_ch0_swclk_1_gain

HW prefix:adc_ch3_swclk_0_gain
HW address:0x12c
@@ -6574,7 +6630,7 @@

2.77. adc_ch0_swclk_1_gain


SFIX32_31. -

2.78. adc_ch1_swclk_1_gain

+

2.78. adc_ch1_swclk_1_gain

HW prefix:adc_ch0_swclk_1_gain
HW address:0x130
@@ -6645,7 +6701,7 @@

2.78. adc_ch1_swclk_1_gain


SFIX32_31. -

2.79. adc_ch2_swclk_1_gain

+

2.79. adc_ch2_swclk_1_gain

HW prefix:adc_ch1_swclk_1_gain
HW address:0x134
@@ -6716,7 +6772,7 @@

2.79. adc_ch2_swclk_1_gain


SFIX32_31. -

2.80. adc_ch3_swclk_1_gain

+

2.80. adc_ch3_swclk_1_gain

HW prefix:adc_ch2_swclk_1_gain
HW address:0x138
@@ -6786,6 +6842,678 @@

2.80. adc_ch3_swclk_1_gain

[rw]: gain
SFIX32_31. + +

2.81. adc_ch0_swclk_0_offset

+
HW prefix:adc_ch3_swclk_1_gain
HW address:0x13c
+ + + + +
HW prefix:adc_ch0_swclk_0_offset
HW address:0x140
C prefix:adc_ch0_swclk_0_offset
C block offset:0x140
+

+ADC channel 0 offset on RFFE switch state 0 (inverted) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.82. adc_ch1_swclk_0_offset

+ + + + + +
HW prefix:adc_ch1_swclk_0_offset
HW address:0x144
C prefix:adc_ch1_swclk_0_offset
C block offset:0x144
+

+ADC channel 1 offset on RFFE switch state 0 (inverted) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.83. adc_ch2_swclk_0_offset

+ + + + + +
HW prefix:adc_ch2_swclk_0_offset
HW address:0x148
C prefix:adc_ch2_swclk_0_offset
C block offset:0x148
+

+ADC channel 2 offset on RFFE switch state 0 (inverted) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.84. adc_ch3_swclk_0_offset

+ + + + + +
HW prefix:adc_ch3_swclk_0_offset
HW address:0x14c
C prefix:adc_ch3_swclk_0_offset
C block offset:0x14c
+

+ADC channel 3 offset on RFFE switch state 0 (inverted) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.85. adc_ch0_swclk_1_offset

+ + + + + +
HW prefix:adc_ch0_swclk_1_offset
HW address:0x150
C prefix:adc_ch0_swclk_1_offset
C block offset:0x150
+

+ADC channel 0 offset on RFFE switch state 1 (direct) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.86. adc_ch1_swclk_1_offset

+ + + + + +
HW prefix:adc_ch1_swclk_1_offset
HW address:0x154
C prefix:adc_ch1_swclk_1_offset
C block offset:0x154
+

+ADC channel 1 offset on RFFE switch state 1 (direct) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.87. adc_ch2_swclk_1_offset

+ + + + + +
HW prefix:adc_ch2_swclk_1_offset
HW address:0x158
C prefix:adc_ch2_swclk_1_offset
C block offset:0x158
+

+ADC channel 2 offset on RFFE switch state 1 (direct) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
+ +

2.88. adc_ch3_swclk_1_offset

+ + + + + +
HW prefix:adc_ch3_swclk_1_offset
HW address:0x15c
C prefix:adc_ch3_swclk_1_offset
C block offset:0x15c
+

+ADC channel 3 offset on RFFE switch state 1 (direct) +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
data[15:8]
76543210
data[7:0]
+
    +
  • +data +[rw]: offset +
diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby index 1b224483..77911a7b 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby @@ -2199,3 +2199,150 @@ memory-map: access_bus: READ_WRITE access_dev: READ_ONLY clock: fs_clk2x_i +# --------------------------------------------- +# ----------- ADC Offset Registers ----------- +# --------------------------------------------- + - reg: + name: adc_ch0_swclk_0_offset + address: 0x00000140 + width: 32 + access: rw + description: ADC channel 0 offset on RFFE switch state 0 (inverted) + comment: | + ADC channel 0 offset on RFFE switch state 0 (inverted) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch1_swclk_0_offset + address: 0x00000144 + width: 32 + access: rw + description: ADC channel 1 offset on RFFE switch state 0 (inverted) + comment: | + ADC channel 1 offset on RFFE switch state 0 (inverted) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch2_swclk_0_offset + address: 0x00000148 + width: 32 + access: rw + description: ADC channel 2 offset on RFFE switch state 0 (inverted) + comment: | + ADC channel 2 offset on RFFE switch state 0 (inverted) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch3_swclk_0_offset + address: 0x0000014c + width: 32 + access: rw + description: ADC channel 3 offset on RFFE switch state 0 (inverted) + comment: | + ADC channel 3 offset on RFFE switch state 0 (inverted) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch0_swclk_1_offset + address: 0x00000150 + width: 32 + access: rw + description: ADC channel 0 offset on RFFE switch state 1 (direct) + comment: | + ADC channel 0 offset on RFFE switch state 1 (direct) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch1_swclk_1_offset + address: 0x00000154 + width: 32 + access: rw + description: ADC channel 1 offset on RFFE switch state 1 (direct) + comment: | + ADC channel 1 offset on RFFE switch state 1 (direct) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch2_swclk_1_offset + address: 0x00000158 + width: 32 + access: rw + description: ADC channel 2 offset on RFFE switch state 1 (direct) + comment: | + ADC channel 2 offset on RFFE switch state 1 (direct) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i + - reg: + name: adc_ch3_swclk_1_offset + address: 0x0000015c + width: 32 + access: rw + description: ADC channel 3 offset on RFFE switch state 1 (direct) + comment: | + ADC channel 3 offset on RFFE switch state 1 (direct) + children: + - field: + name: data + range: 15-0 + description: offset + x-wbgen: + type: SLV + access_bus: READ_WRITE + access_dev: READ_ONLY + clock: fs_clk2x_i diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h index a3644c4c..32653456 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h @@ -1,6 +1,6 @@ #ifndef __CHEBY__POS_CALC__H__ #define __CHEBY__POS_CALC__H__ -#define POS_CALC_SIZE 320 /* 0x140 */ +#define POS_CALC_SIZE 352 /* 0x160 */ /* Config divisor threshold TBT register */ #define POS_CALC_DS_TBT_THRES 0x0UL @@ -453,6 +453,47 @@ #define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_SHIFT 0 +/* ADC channel 0 offset on RFFE switch state 0 (inverted) */ +#define POS_CALC_ADC_CH0_SWCLK_0_OFFSET 0x140UL +#define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_SHIFT 0 + +/* ADC channel 1 offset on RFFE switch state 0 (inverted) */ +#define POS_CALC_ADC_CH1_SWCLK_0_OFFSET 0x144UL +#define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_SHIFT 0 + +/* ADC channel 2 offset on RFFE switch state 0 (inverted) */ +#define POS_CALC_ADC_CH2_SWCLK_0_OFFSET 0x148UL +#define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_SHIFT 0 + +/* ADC channel 3 offset on RFFE switch state 0 (inverted) */ +#define POS_CALC_ADC_CH3_SWCLK_0_OFFSET 0x14cUL +#define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_SHIFT 0 + +/* ADC channel 0 offset on RFFE switch state 1 (direct) */ +#define POS_CALC_ADC_CH0_SWCLK_1_OFFSET 0x150UL +#define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_SHIFT 0 + +/* ADC channel 1 offset on RFFE switch state 1 (direct) */ +#define POS_CALC_ADC_CH1_SWCLK_1_OFFSET 0x154UL +#define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_SHIFT 0 + +/* ADC channel 2 offset on RFFE switch state 1 (direct) */ +#define POS_CALC_ADC_CH2_SWCLK_1_OFFSET 0x158UL +#define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_SHIFT 0 + +/* ADC channel 3 offset on RFFE switch state 1 (direct) */ +#define POS_CALC_ADC_CH3_SWCLK_1_OFFSET 0x15cUL +#define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA_MASK 0xffffUL +#define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA_SHIFT 0 + +#ifndef __ASSEMBLER__ struct pos_calc { /* [0x0]: REG (rw) Config divisor threshold TBT register */ uint32_t ds_tbt_thres; @@ -705,6 +746,31 @@ struct pos_calc { /* [0x13c]: REG (rw) ADC channel 3 gain on RFFE switch state 1 (direct) */ uint32_t adc_ch3_swclk_1_gain; + + /* [0x140]: REG (rw) ADC channel 0 offset on RFFE switch state 0 (inverted) */ + uint32_t adc_ch0_swclk_0_offset; + + /* [0x144]: REG (rw) ADC channel 1 offset on RFFE switch state 0 (inverted) */ + uint32_t adc_ch1_swclk_0_offset; + + /* [0x148]: REG (rw) ADC channel 2 offset on RFFE switch state 0 (inverted) */ + uint32_t adc_ch2_swclk_0_offset; + + /* [0x14c]: REG (rw) ADC channel 3 offset on RFFE switch state 0 (inverted) */ + uint32_t adc_ch3_swclk_0_offset; + + /* [0x150]: REG (rw) ADC channel 0 offset on RFFE switch state 1 (direct) */ + uint32_t adc_ch0_swclk_1_offset; + + /* [0x154]: REG (rw) ADC channel 1 offset on RFFE switch state 1 (direct) */ + uint32_t adc_ch1_swclk_1_offset; + + /* [0x158]: REG (rw) ADC channel 2 offset on RFFE switch state 1 (direct) */ + uint32_t adc_ch2_swclk_1_offset; + + /* [0x15c]: REG (rw) ADC channel 3 offset on RFFE switch state 1 (direct) */ + uint32_t adc_ch3_swclk_1_offset; }; +#endif /* !__ASSEMBLER__*/ #endif /* __CHEBY__POS_CALC__H__ */ diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd index f0412aa6..35fc64a4 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- File : wb_pos_calc_regs.vhdl -- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb --- Created : Thu Nov 17 15:47:13 2022 +-- Created : Thu May 09 16:58:40 2024 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb @@ -286,7 +286,23 @@ entity wb_pos_calc_regs is -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 2 gain on RFFE switch state 1 (direct)' pos_calc_adc_ch2_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 3 gain on RFFE switch state 1 (direct)' - pos_calc_adc_ch3_swclk_1_gain_data_o : out std_logic_vector(31 downto 0) + pos_calc_adc_ch3_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 0 (inverted)' + pos_calc_adc_ch0_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 0 (inverted)' + pos_calc_adc_ch1_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 0 (inverted)' + pos_calc_adc_ch2_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 0 (inverted)' + pos_calc_adc_ch3_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 1 (direct)' + pos_calc_adc_ch0_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 1 (direct)' + pos_calc_adc_ch1_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 1 (direct)' + pos_calc_adc_ch2_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 1 (direct)' + pos_calc_adc_ch3_swclk_1_offset_data_o : out std_logic_vector(15 downto 0) ); end wb_pos_calc_regs; @@ -694,6 +710,54 @@ architecture syn of wb_pos_calc_regs is signal pos_calc_adc_ch3_swclk_1_gain_data_swb_s0 : std_logic; signal pos_calc_adc_ch3_swclk_1_gain_data_swb_s1 : std_logic; signal pos_calc_adc_ch3_swclk_1_gain_data_swb_s2 : std_logic; + signal pos_calc_adc_ch0_swclk_0_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch0_swclk_0_offset_data_swb : std_logic; + signal pos_calc_adc_ch0_swclk_0_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch0_swclk_0_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch0_swclk_0_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch0_swclk_0_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch1_swclk_0_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch1_swclk_0_offset_data_swb : std_logic; + signal pos_calc_adc_ch1_swclk_0_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch1_swclk_0_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch1_swclk_0_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch1_swclk_0_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch2_swclk_0_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch2_swclk_0_offset_data_swb : std_logic; + signal pos_calc_adc_ch2_swclk_0_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch2_swclk_0_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch2_swclk_0_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch2_swclk_0_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch3_swclk_0_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch3_swclk_0_offset_data_swb : std_logic; + signal pos_calc_adc_ch3_swclk_0_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch3_swclk_0_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch3_swclk_0_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch3_swclk_0_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch0_swclk_1_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch0_swclk_1_offset_data_swb : std_logic; + signal pos_calc_adc_ch0_swclk_1_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch0_swclk_1_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch0_swclk_1_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch0_swclk_1_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch1_swclk_1_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch1_swclk_1_offset_data_swb : std_logic; + signal pos_calc_adc_ch1_swclk_1_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch1_swclk_1_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch1_swclk_1_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch1_swclk_1_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch2_swclk_1_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch2_swclk_1_offset_data_swb : std_logic; + signal pos_calc_adc_ch2_swclk_1_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch2_swclk_1_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch2_swclk_1_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch2_swclk_1_offset_data_swb_s2 : std_logic; + signal pos_calc_adc_ch3_swclk_1_offset_data_int : std_logic_vector(15 downto 0); + signal pos_calc_adc_ch3_swclk_1_offset_data_swb : std_logic; + signal pos_calc_adc_ch3_swclk_1_offset_data_swb_delay : std_logic; + signal pos_calc_adc_ch3_swclk_1_offset_data_swb_s0 : std_logic; + signal pos_calc_adc_ch3_swclk_1_offset_data_swb_s1 : std_logic; + signal pos_calc_adc_ch3_swclk_1_offset_data_swb_s2 : std_logic; signal pos_calc_ampfifo_monit_full_int : std_logic; signal pos_calc_ampfifo_monit_empty_int : std_logic; signal pos_calc_ampfifo_monit_usedw_int : std_logic_vector(3 downto 0); @@ -909,6 +973,30 @@ begin pos_calc_adc_ch3_swclk_1_gain_data_int <= "00000000000000000000000000000000"; pos_calc_adc_ch3_swclk_1_gain_data_swb <= '0'; pos_calc_adc_ch3_swclk_1_gain_data_swb_delay <= '0'; + pos_calc_adc_ch0_swclk_0_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch0_swclk_0_offset_data_swb <= '0'; + pos_calc_adc_ch0_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch1_swclk_0_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch1_swclk_0_offset_data_swb <= '0'; + pos_calc_adc_ch1_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch2_swclk_0_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch2_swclk_0_offset_data_swb <= '0'; + pos_calc_adc_ch2_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch3_swclk_0_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch3_swclk_0_offset_data_swb <= '0'; + pos_calc_adc_ch3_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch0_swclk_1_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch0_swclk_1_offset_data_swb <= '0'; + pos_calc_adc_ch0_swclk_1_offset_data_swb_delay <= '0'; + pos_calc_adc_ch1_swclk_1_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch1_swclk_1_offset_data_swb <= '0'; + pos_calc_adc_ch1_swclk_1_offset_data_swb_delay <= '0'; + pos_calc_adc_ch2_swclk_1_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch2_swclk_1_offset_data_swb <= '0'; + pos_calc_adc_ch2_swclk_1_offset_data_swb_delay <= '0'; + pos_calc_adc_ch3_swclk_1_offset_data_int <= "0000000000000000"; + pos_calc_adc_ch3_swclk_1_offset_data_swb <= '0'; + pos_calc_adc_ch3_swclk_1_offset_data_swb_delay <= '0'; pos_calc_ampfifo_monit_rdreq_int <= '0'; pos_calc_posfifo_monit_rdreq_int <= '0'; pos_calc_ampfifo_monit1_rdreq_int <= '0'; @@ -1095,6 +1183,22 @@ begin pos_calc_adc_ch2_swclk_1_gain_data_swb_delay <= '0'; pos_calc_adc_ch3_swclk_1_gain_data_swb <= pos_calc_adc_ch3_swclk_1_gain_data_swb_delay; pos_calc_adc_ch3_swclk_1_gain_data_swb_delay <= '0'; + pos_calc_adc_ch0_swclk_0_offset_data_swb <= pos_calc_adc_ch0_swclk_0_offset_data_swb_delay; + pos_calc_adc_ch0_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch1_swclk_0_offset_data_swb <= pos_calc_adc_ch1_swclk_0_offset_data_swb_delay; + pos_calc_adc_ch1_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch2_swclk_0_offset_data_swb <= pos_calc_adc_ch2_swclk_0_offset_data_swb_delay; + pos_calc_adc_ch2_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch3_swclk_0_offset_data_swb <= pos_calc_adc_ch3_swclk_0_offset_data_swb_delay; + pos_calc_adc_ch3_swclk_0_offset_data_swb_delay <= '0'; + pos_calc_adc_ch0_swclk_1_offset_data_swb <= pos_calc_adc_ch0_swclk_1_offset_data_swb_delay; + pos_calc_adc_ch0_swclk_1_offset_data_swb_delay <= '0'; + pos_calc_adc_ch1_swclk_1_offset_data_swb <= pos_calc_adc_ch1_swclk_1_offset_data_swb_delay; + pos_calc_adc_ch1_swclk_1_offset_data_swb_delay <= '0'; + pos_calc_adc_ch2_swclk_1_offset_data_swb <= pos_calc_adc_ch2_swclk_1_offset_data_swb_delay; + pos_calc_adc_ch2_swclk_1_offset_data_swb_delay <= '0'; + pos_calc_adc_ch3_swclk_1_offset_data_swb <= pos_calc_adc_ch3_swclk_1_offset_data_swb_delay; + pos_calc_adc_ch3_swclk_1_offset_data_swb_delay <= '0'; end if; else if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then @@ -1906,6 +2010,206 @@ begin rddata_reg(31 downto 0) <= pos_calc_adc_ch3_swclk_1_gain_data_int; ack_sreg(3) <= '1'; ack_in_progress <= '1'; + when "1010000" => + if (wb_we_i = '1') then + pos_calc_adc_ch0_swclk_0_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch0_swclk_0_offset_data_swb <= '1'; + pos_calc_adc_ch0_swclk_0_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch0_swclk_0_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010001" => + if (wb_we_i = '1') then + pos_calc_adc_ch1_swclk_0_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch1_swclk_0_offset_data_swb <= '1'; + pos_calc_adc_ch1_swclk_0_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch1_swclk_0_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010010" => + if (wb_we_i = '1') then + pos_calc_adc_ch2_swclk_0_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch2_swclk_0_offset_data_swb <= '1'; + pos_calc_adc_ch2_swclk_0_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch2_swclk_0_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010011" => + if (wb_we_i = '1') then + pos_calc_adc_ch3_swclk_0_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch3_swclk_0_offset_data_swb <= '1'; + pos_calc_adc_ch3_swclk_0_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch3_swclk_0_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010100" => + if (wb_we_i = '1') then + pos_calc_adc_ch0_swclk_1_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch0_swclk_1_offset_data_swb <= '1'; + pos_calc_adc_ch0_swclk_1_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch0_swclk_1_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010101" => + if (wb_we_i = '1') then + pos_calc_adc_ch1_swclk_1_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch1_swclk_1_offset_data_swb <= '1'; + pos_calc_adc_ch1_swclk_1_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch1_swclk_1_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010110" => + if (wb_we_i = '1') then + pos_calc_adc_ch2_swclk_1_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch2_swclk_1_offset_data_swb <= '1'; + pos_calc_adc_ch2_swclk_1_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch2_swclk_1_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; + when "1010111" => + if (wb_we_i = '1') then + pos_calc_adc_ch3_swclk_1_offset_data_int <= wrdata_reg(15 downto 0); + pos_calc_adc_ch3_swclk_1_offset_data_swb <= '1'; + pos_calc_adc_ch3_swclk_1_offset_data_swb_delay <= '1'; + end if; + rddata_reg(15 downto 0) <= pos_calc_adc_ch3_swclk_1_offset_data_int; + rddata_reg(16) <= 'X'; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(3) <= '1'; + ack_in_progress <= '1'; when "0100110" => if (wb_we_i = '1') then end if; @@ -3603,6 +3907,166 @@ begin end process; + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch0_swclk_0_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch0_swclk_0_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch0_swclk_0_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch0_swclk_0_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch0_swclk_0_offset_data_swb_s0 <= pos_calc_adc_ch0_swclk_0_offset_data_swb; + pos_calc_adc_ch0_swclk_0_offset_data_swb_s1 <= pos_calc_adc_ch0_swclk_0_offset_data_swb_s0; + pos_calc_adc_ch0_swclk_0_offset_data_swb_s2 <= pos_calc_adc_ch0_swclk_0_offset_data_swb_s1; + if ((pos_calc_adc_ch0_swclk_0_offset_data_swb_s2 = '0') and (pos_calc_adc_ch0_swclk_0_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch0_swclk_0_offset_data_o <= pos_calc_adc_ch0_swclk_0_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch1_swclk_0_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch1_swclk_0_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch1_swclk_0_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch1_swclk_0_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch1_swclk_0_offset_data_swb_s0 <= pos_calc_adc_ch1_swclk_0_offset_data_swb; + pos_calc_adc_ch1_swclk_0_offset_data_swb_s1 <= pos_calc_adc_ch1_swclk_0_offset_data_swb_s0; + pos_calc_adc_ch1_swclk_0_offset_data_swb_s2 <= pos_calc_adc_ch1_swclk_0_offset_data_swb_s1; + if ((pos_calc_adc_ch1_swclk_0_offset_data_swb_s2 = '0') and (pos_calc_adc_ch1_swclk_0_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch1_swclk_0_offset_data_o <= pos_calc_adc_ch1_swclk_0_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch2_swclk_0_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch2_swclk_0_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch2_swclk_0_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch2_swclk_0_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch2_swclk_0_offset_data_swb_s0 <= pos_calc_adc_ch2_swclk_0_offset_data_swb; + pos_calc_adc_ch2_swclk_0_offset_data_swb_s1 <= pos_calc_adc_ch2_swclk_0_offset_data_swb_s0; + pos_calc_adc_ch2_swclk_0_offset_data_swb_s2 <= pos_calc_adc_ch2_swclk_0_offset_data_swb_s1; + if ((pos_calc_adc_ch2_swclk_0_offset_data_swb_s2 = '0') and (pos_calc_adc_ch2_swclk_0_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch2_swclk_0_offset_data_o <= pos_calc_adc_ch2_swclk_0_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch3_swclk_0_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch3_swclk_0_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch3_swclk_0_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch3_swclk_0_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch3_swclk_0_offset_data_swb_s0 <= pos_calc_adc_ch3_swclk_0_offset_data_swb; + pos_calc_adc_ch3_swclk_0_offset_data_swb_s1 <= pos_calc_adc_ch3_swclk_0_offset_data_swb_s0; + pos_calc_adc_ch3_swclk_0_offset_data_swb_s2 <= pos_calc_adc_ch3_swclk_0_offset_data_swb_s1; + if ((pos_calc_adc_ch3_swclk_0_offset_data_swb_s2 = '0') and (pos_calc_adc_ch3_swclk_0_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch3_swclk_0_offset_data_o <= pos_calc_adc_ch3_swclk_0_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch0_swclk_1_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch0_swclk_1_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch0_swclk_1_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch0_swclk_1_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch0_swclk_1_offset_data_swb_s0 <= pos_calc_adc_ch0_swclk_1_offset_data_swb; + pos_calc_adc_ch0_swclk_1_offset_data_swb_s1 <= pos_calc_adc_ch0_swclk_1_offset_data_swb_s0; + pos_calc_adc_ch0_swclk_1_offset_data_swb_s2 <= pos_calc_adc_ch0_swclk_1_offset_data_swb_s1; + if ((pos_calc_adc_ch0_swclk_1_offset_data_swb_s2 = '0') and (pos_calc_adc_ch0_swclk_1_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch0_swclk_1_offset_data_o <= pos_calc_adc_ch0_swclk_1_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch1_swclk_1_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch1_swclk_1_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch1_swclk_1_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch1_swclk_1_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch1_swclk_1_offset_data_swb_s0 <= pos_calc_adc_ch1_swclk_1_offset_data_swb; + pos_calc_adc_ch1_swclk_1_offset_data_swb_s1 <= pos_calc_adc_ch1_swclk_1_offset_data_swb_s0; + pos_calc_adc_ch1_swclk_1_offset_data_swb_s2 <= pos_calc_adc_ch1_swclk_1_offset_data_swb_s1; + if ((pos_calc_adc_ch1_swclk_1_offset_data_swb_s2 = '0') and (pos_calc_adc_ch1_swclk_1_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch1_swclk_1_offset_data_o <= pos_calc_adc_ch1_swclk_1_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch2_swclk_1_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch2_swclk_1_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch2_swclk_1_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch2_swclk_1_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch2_swclk_1_offset_data_swb_s0 <= pos_calc_adc_ch2_swclk_1_offset_data_swb; + pos_calc_adc_ch2_swclk_1_offset_data_swb_s1 <= pos_calc_adc_ch2_swclk_1_offset_data_swb_s0; + pos_calc_adc_ch2_swclk_1_offset_data_swb_s2 <= pos_calc_adc_ch2_swclk_1_offset_data_swb_s1; + if ((pos_calc_adc_ch2_swclk_1_offset_data_swb_s2 = '0') and (pos_calc_adc_ch2_swclk_1_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch2_swclk_1_offset_data_o <= pos_calc_adc_ch2_swclk_1_offset_data_int; + end if; + end if; + end process; + + + -- offset + -- asynchronous std_logic_vector register : offset (type RW/RO, fs_clk2x_i <-> clk_sys_i) + process (fs_clk2x_i, rst_n_i) + begin + if (rst_n_i = '0') then + pos_calc_adc_ch3_swclk_1_offset_data_swb_s0 <= '0'; + pos_calc_adc_ch3_swclk_1_offset_data_swb_s1 <= '0'; + pos_calc_adc_ch3_swclk_1_offset_data_swb_s2 <= '0'; + pos_calc_adc_ch3_swclk_1_offset_data_o <= "0000000000000000"; + elsif rising_edge(fs_clk2x_i) then + pos_calc_adc_ch3_swclk_1_offset_data_swb_s0 <= pos_calc_adc_ch3_swclk_1_offset_data_swb; + pos_calc_adc_ch3_swclk_1_offset_data_swb_s1 <= pos_calc_adc_ch3_swclk_1_offset_data_swb_s0; + pos_calc_adc_ch3_swclk_1_offset_data_swb_s2 <= pos_calc_adc_ch3_swclk_1_offset_data_swb_s1; + if ((pos_calc_adc_ch3_swclk_1_offset_data_swb_s2 = '0') and (pos_calc_adc_ch3_swclk_1_offset_data_swb_s1 = '1')) then + pos_calc_adc_ch3_swclk_1_offset_data_o <= pos_calc_adc_ch3_swclk_1_offset_data_int; + end if; + end if; + end process; + + -- extra code for reg/fifo/mem: FIFO 'AMP FIFO Monitoring' data output register 0 process (clk_sys_i, rst_n_i) begin diff --git a/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd b/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd index 249d9827..5fbe8349 100644 --- a/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd +++ b/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd @@ -70,7 +70,7 @@ package position_calc_core_pkg is constant c_xwb_pos_calc_core_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device abi_ver_major => x"01", - abi_ver_minor => x"00", + abi_ver_minor => x"01", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 8/16/32-bit port granularity (0100) sdb_component => ( @@ -80,7 +80,7 @@ package position_calc_core_pkg is vendor_id => x"1000000000001215", -- LNLS device_id => x"1bafbf1e", version => x"00000001", - date => x"20130703", + date => x"20240604", name => "LNLS_POS_CALC_REGS "))); end position_calc_core_pkg; diff --git a/hdl/modules/wb_position_calc/wb_position_calc_core.vhd b/hdl/modules/wb_position_calc/wb_position_calc_core.vhd index 32977f8c..79bc9ba2 100644 --- a/hdl/modules/wb_position_calc/wb_position_calc_core.vhd +++ b/hdl/modules/wb_position_calc/wb_position_calc_core.vhd @@ -350,6 +350,9 @@ architecture rtl of wb_position_calc_core is constant c_k_width : natural := g_k_width; constant c_offset_width : natural := g_offset_width; + -- Defined by cheby/wb_pos_calc_regs.cheby + constant c_adc_offset_width : natural := 16; + -- Wishbone ADC gains fixed-point position constant c_adc_gains_fixed_point_pos : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(31, 32)); @@ -555,6 +558,14 @@ architecture rtl of wb_position_calc_core is signal regs_adc_ch1_swclk_1_gain_data_o : std_logic_vector(31 downto 0); signal regs_adc_ch2_swclk_1_gain_data_o : std_logic_vector(31 downto 0); signal regs_adc_ch3_swclk_1_gain_data_o : std_logic_vector(31 downto 0); + signal regs_adc_ch0_swclk_0_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch1_swclk_0_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch2_swclk_0_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch3_swclk_0_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch0_swclk_1_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch1_swclk_1_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch2_swclk_1_offset_data_o : std_logic_vector(15 downto 0); + signal regs_adc_ch3_swclk_1_offset_data_o : std_logic_vector(15 downto 0); ----------------------------- -- Wishbone crossbar signals @@ -1015,7 +1026,15 @@ architecture rtl of wb_position_calc_core is pos_calc_adc_ch0_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); pos_calc_adc_ch1_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); pos_calc_adc_ch2_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); - pos_calc_adc_ch3_swclk_1_gain_data_o : out std_logic_vector(31 downto 0) + pos_calc_adc_ch3_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); + pos_calc_adc_ch0_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch1_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch2_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch3_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch0_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch1_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch2_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); + pos_calc_adc_ch3_swclk_1_offset_data_o : out std_logic_vector(15 downto 0) ); end component wb_pos_calc_regs; @@ -1289,7 +1308,15 @@ begin pos_calc_adc_ch0_swclk_1_gain_data_o => regs_adc_ch0_swclk_1_gain_data_o, pos_calc_adc_ch1_swclk_1_gain_data_o => regs_adc_ch1_swclk_1_gain_data_o, pos_calc_adc_ch2_swclk_1_gain_data_o => regs_adc_ch2_swclk_1_gain_data_o, - pos_calc_adc_ch3_swclk_1_gain_data_o => regs_adc_ch3_swclk_1_gain_data_o + pos_calc_adc_ch3_swclk_1_gain_data_o => regs_adc_ch3_swclk_1_gain_data_o, + pos_calc_adc_ch0_swclk_0_offset_data_o => regs_adc_ch0_swclk_0_offset_data_o, + pos_calc_adc_ch1_swclk_0_offset_data_o => regs_adc_ch1_swclk_0_offset_data_o, + pos_calc_adc_ch2_swclk_0_offset_data_o => regs_adc_ch2_swclk_0_offset_data_o, + pos_calc_adc_ch3_swclk_0_offset_data_o => regs_adc_ch3_swclk_0_offset_data_o, + pos_calc_adc_ch0_swclk_1_offset_data_o => regs_adc_ch0_swclk_1_offset_data_o, + pos_calc_adc_ch1_swclk_1_offset_data_o => regs_adc_ch1_swclk_1_offset_data_o, + pos_calc_adc_ch2_swclk_1_offset_data_o => regs_adc_ch2_swclk_1_offset_data_o, + pos_calc_adc_ch3_swclk_1_offset_data_o => regs_adc_ch3_swclk_1_offset_data_o ); -- Unused wishbone signals @@ -1762,7 +1789,10 @@ begin g_IQ_width => g_IQ_width, -- width of adc gains - g_adc_gain_width => g_adc_gain_width + g_adc_gain_width => g_adc_gain_width, + + -- Width of ADC offsets + g_adc_offset_width => c_adc_offset_width ) port map ( @@ -1791,6 +1821,15 @@ begin adc_ch2_swclk_1_gain_i => regs_adc_ch2_swclk_1_gain_data_o(31 downto 32-g_adc_gain_width), adc_ch3_swclk_1_gain_i => regs_adc_ch3_swclk_1_gain_data_o(31 downto 32-g_adc_gain_width), + adc_ch0_swclk_0_offset_i => regs_adc_ch0_swclk_0_offset_data_o, + adc_ch1_swclk_0_offset_i => regs_adc_ch1_swclk_0_offset_data_o, + adc_ch2_swclk_0_offset_i => regs_adc_ch2_swclk_0_offset_data_o, + adc_ch3_swclk_0_offset_i => regs_adc_ch3_swclk_0_offset_data_o, + adc_ch0_swclk_1_offset_i => regs_adc_ch0_swclk_1_offset_data_o, + adc_ch1_swclk_1_offset_i => regs_adc_ch1_swclk_1_offset_data_o, + adc_ch2_swclk_1_offset_i => regs_adc_ch2_swclk_1_offset_data_o, + adc_ch3_swclk_1_offset_i => regs_adc_ch3_swclk_1_offset_data_o, + offset_x_i => regs_pos_calc_offset_x_o(c_offset_width-1 downto 0), offset_y_i => regs_pos_calc_offset_y_o(c_offset_width-1 downto 0), diff --git a/hdl/sim/regs/wb_pos_calc_regs.vh b/hdl/sim/regs/wb_pos_calc_regs.vh index 39b5bead..cba8172b 100644 --- a/hdl/sim/regs/wb_pos_calc_regs.vh +++ b/hdl/sim/regs/wb_pos_calc_regs.vh @@ -1,4 +1,8 @@ -`define POS_CALC_SIZE 320 +// Do not edit. Generated by cheby 1.6.dev0 using these options: +// -i wb_pos_calc_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_pos_calc_regs.vhd --doc html --gen-doc doc/wb_pos_calc_regs_wb.html --gen-c wb_pos_calc_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_pos_calc_regs.vh +// Generated on Thu May 09 16:58:40 2024 by guilherme.ricioli + +`define POS_CALC_SIZE 352 `define ADDR_POS_CALC_DS_TBT_THRES 'h0 `define POS_CALC_DS_TBT_THRES_VAL_OFFSET 0 `define POS_CALC_DS_TBT_THRES_VAL 'h3ffffff @@ -311,3 +315,27 @@ `define ADDR_POS_CALC_ADC_CH3_SWCLK_1_GAIN 'h13c `define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_OFFSET 0 `define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA 'hffffffff +`define ADDR_POS_CALC_ADC_CH0_SWCLK_0_OFFSET 'h140 +`define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH1_SWCLK_0_OFFSET 'h144 +`define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH2_SWCLK_0_OFFSET 'h148 +`define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH3_SWCLK_0_OFFSET 'h14c +`define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH0_SWCLK_1_OFFSET 'h150 +`define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH1_SWCLK_1_OFFSET 'h154 +`define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH2_SWCLK_1_OFFSET 'h158 +`define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA 'hffff +`define ADDR_POS_CALC_ADC_CH3_SWCLK_1_OFFSET 'h15c +`define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA_OFFSET 0 +`define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA 'hffff From 0c97f74e615b948c85ba9e9c840cd4e04c43ac92 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 22 Jul 2024 14:16:32 -0300 Subject: [PATCH 09/17] wb_pos_calc_regs.cheby: better document registers --- .../cheby/doc/wb_pos_calc_regs_wb.html | 16 ++--- .../cheby/wb_pos_calc_regs.cheby | 40 +++++++++--- .../wb_position_calc/cheby/wb_pos_calc_regs.h | 64 ++++++++++++++----- .../cheby/wb_pos_calc_regs.vhd | 34 +++++++--- hdl/sim/regs/wb_pos_calc_regs.vh | 2 +- 5 files changed, 114 insertions(+), 42 deletions(-) diff --git a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html index 82ac75a9..33b6c908 100644 --- a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html +++ b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html @@ -6851,7 +6851,7 @@

2.81. adc_ch0_swclk_0_offset

C block offset:0x140

-ADC channel 0 offset on RFFE switch state 0 (inverted) +ADC channel 0 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -6935,7 +6935,7 @@

2.82. adc_ch1_swclk_0_offset

C block offset:0x144

-ADC channel 1 offset on RFFE switch state 0 (inverted) +ADC channel 1 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7019,7 +7019,7 @@

2.83. adc_ch2_swclk_0_offset

C block offset:0x148

-ADC channel 2 offset on RFFE switch state 0 (inverted) +ADC channel 2 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7103,7 +7103,7 @@

2.84. adc_ch3_swclk_0_offset

C block offset:0x14c

-ADC channel 3 offset on RFFE switch state 0 (inverted) +ADC channel 3 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7187,7 +7187,7 @@

2.85. adc_ch0_swclk_1_offset

C block offset:0x150

-ADC channel 0 offset on RFFE switch state 1 (direct) +ADC channel 0 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7271,7 +7271,7 @@

2.86. adc_ch1_swclk_1_offset

C block offset:0x154

-ADC channel 1 offset on RFFE switch state 1 (direct) +ADC channel 1 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7355,7 +7355,7 @@

2.87. adc_ch2_swclk_1_offset

C block offset:0x158

-ADC channel 2 offset on RFFE switch state 1 (direct) +ADC channel 2 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7439,7 +7439,7 @@

2.88. adc_ch3_swclk_1_offset

C block offset:0x15c

-ADC channel 3 offset on RFFE switch state 1 (direct) +ADC channel 3 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby index 77911a7b..724281d6 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby @@ -2207,9 +2207,12 @@ memory-map: address: 0x00000140 width: 32 access: rw - description: ADC channel 0 offset on RFFE switch state 0 (inverted) + description: | + ADC channel 0 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 0 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2225,9 +2228,12 @@ memory-map: address: 0x00000144 width: 32 access: rw - description: ADC channel 1 offset on RFFE switch state 0 (inverted) + description: | + ADC channel 1 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 1 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2243,9 +2249,12 @@ memory-map: address: 0x00000148 width: 32 access: rw - description: ADC channel 2 offset on RFFE switch state 0 (inverted) + description: | + ADC channel 2 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 2 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2261,9 +2270,12 @@ memory-map: address: 0x0000014c width: 32 access: rw - description: ADC channel 3 offset on RFFE switch state 0 (inverted) + description: | + ADC channel 3 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 3 offset on RFFE switch state 0 (inverted) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2279,9 +2291,12 @@ memory-map: address: 0x00000150 width: 32 access: rw - description: ADC channel 0 offset on RFFE switch state 1 (direct) + description: | + ADC channel 0 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 0 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2297,9 +2312,12 @@ memory-map: address: 0x00000154 width: 32 access: rw - description: ADC channel 1 offset on RFFE switch state 1 (direct) + description: | + ADC channel 1 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 1 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2315,9 +2333,12 @@ memory-map: address: 0x00000158 width: 32 access: rw - description: ADC channel 2 offset on RFFE switch state 1 (direct) + description: | + ADC channel 2 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 2 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data @@ -2333,9 +2354,12 @@ memory-map: address: 0x0000015c width: 32 access: rw - description: ADC channel 3 offset on RFFE switch state 1 (direct) + description: | + ADC channel 3 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. comment: | ADC channel 3 offset on RFFE switch state 1 (direct) + Uses 2's complement representation and is subtracted from ADC samples. children: - field: name: data diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h index 32653456..779aa9c2 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h @@ -453,42 +453,58 @@ #define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_SHIFT 0 -/* ADC channel 0 offset on RFFE switch state 0 (inverted) */ +/* ADC channel 0 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH0_SWCLK_0_OFFSET 0x140UL #define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 1 offset on RFFE switch state 0 (inverted) */ +/* ADC channel 1 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH1_SWCLK_0_OFFSET 0x144UL #define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 2 offset on RFFE switch state 0 (inverted) */ +/* ADC channel 2 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH2_SWCLK_0_OFFSET 0x148UL #define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 3 offset on RFFE switch state 0 (inverted) */ +/* ADC channel 3 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH3_SWCLK_0_OFFSET 0x14cUL #define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 0 offset on RFFE switch state 1 (direct) */ +/* ADC channel 0 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH0_SWCLK_1_OFFSET 0x150UL #define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_SHIFT 0 -/* ADC channel 1 offset on RFFE switch state 1 (direct) */ +/* ADC channel 1 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH1_SWCLK_1_OFFSET 0x154UL #define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_SHIFT 0 -/* ADC channel 2 offset on RFFE switch state 1 (direct) */ +/* ADC channel 2 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH2_SWCLK_1_OFFSET 0x158UL #define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_SHIFT 0 -/* ADC channel 3 offset on RFFE switch state 1 (direct) */ +/* ADC channel 3 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ #define POS_CALC_ADC_CH3_SWCLK_1_OFFSET 0x15cUL #define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH3_SWCLK_1_OFFSET_DATA_SHIFT 0 @@ -747,28 +763,44 @@ struct pos_calc { /* [0x13c]: REG (rw) ADC channel 3 gain on RFFE switch state 1 (direct) */ uint32_t adc_ch3_swclk_1_gain; - /* [0x140]: REG (rw) ADC channel 0 offset on RFFE switch state 0 (inverted) */ + /* [0x140]: REG (rw) ADC channel 0 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch0_swclk_0_offset; - /* [0x144]: REG (rw) ADC channel 1 offset on RFFE switch state 0 (inverted) */ + /* [0x144]: REG (rw) ADC channel 1 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch1_swclk_0_offset; - /* [0x148]: REG (rw) ADC channel 2 offset on RFFE switch state 0 (inverted) */ + /* [0x148]: REG (rw) ADC channel 2 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch2_swclk_0_offset; - /* [0x14c]: REG (rw) ADC channel 3 offset on RFFE switch state 0 (inverted) */ + /* [0x14c]: REG (rw) ADC channel 3 offset on RFFE switch state 0 (inverted) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch3_swclk_0_offset; - /* [0x150]: REG (rw) ADC channel 0 offset on RFFE switch state 1 (direct) */ + /* [0x150]: REG (rw) ADC channel 0 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch0_swclk_1_offset; - /* [0x154]: REG (rw) ADC channel 1 offset on RFFE switch state 1 (direct) */ + /* [0x154]: REG (rw) ADC channel 1 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch1_swclk_1_offset; - /* [0x158]: REG (rw) ADC channel 2 offset on RFFE switch state 1 (direct) */ + /* [0x158]: REG (rw) ADC channel 2 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch2_swclk_1_offset; - /* [0x15c]: REG (rw) ADC channel 3 offset on RFFE switch state 1 (direct) */ + /* [0x15c]: REG (rw) ADC channel 3 offset on RFFE switch state 1 (direct) +Uses 2's complement representation and is subtracted from ADC samples. + */ uint32_t adc_ch3_swclk_1_offset; }; #endif /* !__ASSEMBLER__*/ diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd index 35fc64a4..60c73d20 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- File : wb_pos_calc_regs.vhdl -- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb --- Created : Thu May 09 16:58:40 2024 +-- Created : Mon Jul 22 15:15:26 2024 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb @@ -287,21 +287,37 @@ entity wb_pos_calc_regs is pos_calc_adc_ch2_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 3 gain on RFFE switch state 1 (direct)' pos_calc_adc_ch3_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 0 (inverted) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch0_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 0 (inverted) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch1_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 0 (inverted) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch2_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 0 (inverted) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch3_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 1 (direct) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch0_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 1 (direct) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch1_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 1 (direct) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch2_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 1 (direct) + -- Uses 2's complement representation and is subtracted from ADC samples. + -- ' pos_calc_adc_ch3_swclk_1_offset_data_o : out std_logic_vector(15 downto 0) ); end wb_pos_calc_regs; diff --git a/hdl/sim/regs/wb_pos_calc_regs.vh b/hdl/sim/regs/wb_pos_calc_regs.vh index cba8172b..7e3058ec 100644 --- a/hdl/sim/regs/wb_pos_calc_regs.vh +++ b/hdl/sim/regs/wb_pos_calc_regs.vh @@ -1,6 +1,6 @@ // Do not edit. Generated by cheby 1.6.dev0 using these options: // -i wb_pos_calc_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_pos_calc_regs.vhd --doc html --gen-doc doc/wb_pos_calc_regs_wb.html --gen-c wb_pos_calc_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_pos_calc_regs.vh -// Generated on Thu May 09 16:58:40 2024 by guilherme.ricioli +// Generated on Mon Jul 22 15:15:26 2024 by guilherme.ricioli `define POS_CALC_SIZE 352 `define ADDR_POS_CALC_DS_TBT_THRES 'h0 From 16e90b02f9daed7ea1204ca67848407badc23247 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 22 Jul 2024 15:19:27 -0300 Subject: [PATCH 10/17] wb_pos_calc_regs.cheby: fix wrong documentation Fix wrong RFFE switch state assignment. --- .../cheby/doc/wb_pos_calc_regs_wb.html | 32 +++++----- .../cheby/wb_pos_calc_regs.cheby | 64 +++++++++---------- .../wb_position_calc/cheby/wb_pos_calc_regs.h | 64 +++++++++---------- .../cheby/wb_pos_calc_regs.vhd | 34 +++++----- hdl/sim/regs/wb_pos_calc_regs.vh | 2 +- 5 files changed, 98 insertions(+), 98 deletions(-) diff --git a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html index 33b6c908..63b15596 100644 --- a/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html +++ b/hdl/modules/wb_position_calc/cheby/doc/wb_pos_calc_regs_wb.html @@ -6283,7 +6283,7 @@

2.73. adc_ch0_swclk_0_gain

C block offset:0x120

-ADC channel 0 gain on RFFE switch state 0 (inverted) +ADC channel 0 gain on RFFE switch state 0 (direct)

@@ -6354,7 +6354,7 @@

2.74. adc_ch1_swclk_0_gain

C block offset:0x124

-ADC channel 1 gain on RFFE switch state 0 (inverted) +ADC channel 1 gain on RFFE switch state 0 (direct)

@@ -6425,7 +6425,7 @@

2.75. adc_ch2_swclk_0_gain

C block offset:0x128

-ADC channel 2 gain on RFFE switch state 0 (inverted) +ADC channel 2 gain on RFFE switch state 0 (direct)

@@ -6496,7 +6496,7 @@

2.76. adc_ch3_swclk_0_gain

C block offset:0x12c

-ADC channel 3 gain on RFFE switch state 0 (inverted) +ADC channel 3 gain on RFFE switch state 0 (direct)

@@ -6567,7 +6567,7 @@

2.77. adc_ch0_swclk_1_gain

C block offset:0x130

-ADC channel 0 gain on RFFE switch state 1 (direct) +ADC channel 0 gain on RFFE switch state 1 (inverted)

@@ -6638,7 +6638,7 @@

2.78. adc_ch1_swclk_1_gain

C block offset:0x134

-ADC channel 1 gain on RFFE switch state 1 (direct) +ADC channel 1 gain on RFFE switch state 1 (inverted)

@@ -6709,7 +6709,7 @@

2.79. adc_ch2_swclk_1_gain

C block offset:0x138

-ADC channel 2 gain on RFFE switch state 1 (direct) +ADC channel 2 gain on RFFE switch state 1 (inverted)

@@ -6780,7 +6780,7 @@

2.80. adc_ch3_swclk_1_gain

C block offset:0x13c

-ADC channel 3 gain on RFFE switch state 1 (direct) +ADC channel 3 gain on RFFE switch state 1 (inverted)

@@ -6851,7 +6851,7 @@

2.81. adc_ch0_swclk_0_offset

C block offset:0x140

-ADC channel 0 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 0 offset on RFFE switch state 0 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -6935,7 +6935,7 @@

2.82. adc_ch1_swclk_0_offset

C block offset:0x144

-ADC channel 1 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 1 offset on RFFE switch state 0 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7019,7 +7019,7 @@

2.83. adc_ch2_swclk_0_offset

C block offset:0x148

-ADC channel 2 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 2 offset on RFFE switch state 0 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7103,7 +7103,7 @@

2.84. adc_ch3_swclk_0_offset

C block offset:0x14c

-ADC channel 3 offset on RFFE switch state 0 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 3 offset on RFFE switch state 0 (direct)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7187,7 +7187,7 @@

2.85. adc_ch0_swclk_1_offset

C block offset:0x150

-ADC channel 0 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 0 offset on RFFE switch state 1 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7271,7 +7271,7 @@

2.86. adc_ch1_swclk_1_offset

C block offset:0x154

-ADC channel 1 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 1 offset on RFFE switch state 1 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7355,7 +7355,7 @@

2.87. adc_ch2_swclk_1_offset

C block offset:0x158

-ADC channel 2 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 2 offset on RFFE switch state 1 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

@@ -7439,7 +7439,7 @@

2.88. adc_ch3_swclk_1_offset

C block offset:0x15c

-ADC channel 3 offset on RFFE switch state 1 (direct)
Uses 2's complement representation and is subtracted from ADC samples.
+ADC channel 3 offset on RFFE switch state 1 (inverted)
Uses 2's complement representation and is subtracted from ADC samples.

diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby index 724281d6..5e83a0e1 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.cheby @@ -2044,9 +2044,9 @@ memory-map: address: 0x00000120 width: 32 access: rw - description: ADC channel 0 gain on RFFE switch state 0 (inverted) + description: ADC channel 0 gain on RFFE switch state 0 (direct) comment: | - ADC channel 0 gain on RFFE switch state 0 (inverted) + ADC channel 0 gain on RFFE switch state 0 (direct) children: - field: name: data @@ -2064,9 +2064,9 @@ memory-map: address: 0x00000124 width: 32 access: rw - description: ADC channel 1 gain on RFFE switch state 0 (inverted) + description: ADC channel 1 gain on RFFE switch state 0 (direct) comment: | - ADC channel 1 gain on RFFE switch state 0 (inverted) + ADC channel 1 gain on RFFE switch state 0 (direct) children: - field: name: data @@ -2084,9 +2084,9 @@ memory-map: address: 0x00000128 width: 32 access: rw - description: ADC channel 2 gain on RFFE switch state 0 (inverted) + description: ADC channel 2 gain on RFFE switch state 0 (direct) comment: | - ADC channel 2 gain on RFFE switch state 0 (inverted) + ADC channel 2 gain on RFFE switch state 0 (direct) children: - field: name: data @@ -2104,9 +2104,9 @@ memory-map: address: 0x0000012c width: 32 access: rw - description: ADC channel 3 gain on RFFE switch state 0 (inverted) + description: ADC channel 3 gain on RFFE switch state 0 (direct) comment: | - ADC channel 3 gain on RFFE switch state 0 (inverted) + ADC channel 3 gain on RFFE switch state 0 (direct) children: - field: name: data @@ -2124,9 +2124,9 @@ memory-map: address: 0x00000130 width: 32 access: rw - description: ADC channel 0 gain on RFFE switch state 1 (direct) + description: ADC channel 0 gain on RFFE switch state 1 (inverted) comment: | - ADC channel 0 gain on RFFE switch state 1 (direct) + ADC channel 0 gain on RFFE switch state 1 (inverted) children: - field: name: data @@ -2144,9 +2144,9 @@ memory-map: address: 0x00000134 width: 32 access: rw - description: ADC channel 1 gain on RFFE switch state 1 (direct) + description: ADC channel 1 gain on RFFE switch state 1 (inverted) comment: | - ADC channel 1 gain on RFFE switch state 1 (direct) + ADC channel 1 gain on RFFE switch state 1 (inverted) children: - field: name: data @@ -2164,9 +2164,9 @@ memory-map: address: 0x00000138 width: 32 access: rw - description: ADC channel 2 gain on RFFE switch state 1 (direct) + description: ADC channel 2 gain on RFFE switch state 1 (inverted) comment: | - ADC channel 2 gain on RFFE switch state 1 (direct) + ADC channel 2 gain on RFFE switch state 1 (inverted) children: - field: name: data @@ -2184,9 +2184,9 @@ memory-map: address: 0x0000013c width: 32 access: rw - description: ADC channel 3 gain on RFFE switch state 1 (direct) + description: ADC channel 3 gain on RFFE switch state 1 (inverted) comment: | - ADC channel 3 gain on RFFE switch state 1 (direct) + ADC channel 3 gain on RFFE switch state 1 (inverted) children: - field: name: data @@ -2208,10 +2208,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 0 offset on RFFE switch state 0 (inverted) + ADC channel 0 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 0 offset on RFFE switch state 0 (inverted) + ADC channel 0 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2229,10 +2229,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 1 offset on RFFE switch state 0 (inverted) + ADC channel 1 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 1 offset on RFFE switch state 0 (inverted) + ADC channel 1 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2250,10 +2250,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 2 offset on RFFE switch state 0 (inverted) + ADC channel 2 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 2 offset on RFFE switch state 0 (inverted) + ADC channel 2 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2271,10 +2271,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 3 offset on RFFE switch state 0 (inverted) + ADC channel 3 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 3 offset on RFFE switch state 0 (inverted) + ADC channel 3 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2292,10 +2292,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 0 offset on RFFE switch state 1 (direct) + ADC channel 0 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 0 offset on RFFE switch state 1 (direct) + ADC channel 0 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2313,10 +2313,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 1 offset on RFFE switch state 1 (direct) + ADC channel 1 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 1 offset on RFFE switch state 1 (direct) + ADC channel 1 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2334,10 +2334,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 2 offset on RFFE switch state 1 (direct) + ADC channel 2 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 2 offset on RFFE switch state 1 (direct) + ADC channel 2 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. children: - field: @@ -2355,10 +2355,10 @@ memory-map: width: 32 access: rw description: | - ADC channel 3 offset on RFFE switch state 1 (direct) + ADC channel 3 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. comment: | - ADC channel 3 offset on RFFE switch state 1 (direct) + ADC channel 3 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. children: - field: diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h index 779aa9c2..7a0a9559 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.h @@ -413,96 +413,96 @@ #define POS_CALC_ADC_GAINS_FIXED_POINT_POS_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_GAINS_FIXED_POINT_POS_DATA_SHIFT 0 -/* ADC channel 0 gain on RFFE switch state 0 (inverted) */ +/* ADC channel 0 gain on RFFE switch state 0 (direct) */ #define POS_CALC_ADC_CH0_SWCLK_0_GAIN 0x120UL #define POS_CALC_ADC_CH0_SWCLK_0_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH0_SWCLK_0_GAIN_DATA_SHIFT 0 -/* ADC channel 1 gain on RFFE switch state 0 (inverted) */ +/* ADC channel 1 gain on RFFE switch state 0 (direct) */ #define POS_CALC_ADC_CH1_SWCLK_0_GAIN 0x124UL #define POS_CALC_ADC_CH1_SWCLK_0_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH1_SWCLK_0_GAIN_DATA_SHIFT 0 -/* ADC channel 2 gain on RFFE switch state 0 (inverted) */ +/* ADC channel 2 gain on RFFE switch state 0 (direct) */ #define POS_CALC_ADC_CH2_SWCLK_0_GAIN 0x128UL #define POS_CALC_ADC_CH2_SWCLK_0_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH2_SWCLK_0_GAIN_DATA_SHIFT 0 -/* ADC channel 3 gain on RFFE switch state 0 (inverted) */ +/* ADC channel 3 gain on RFFE switch state 0 (direct) */ #define POS_CALC_ADC_CH3_SWCLK_0_GAIN 0x12cUL #define POS_CALC_ADC_CH3_SWCLK_0_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH3_SWCLK_0_GAIN_DATA_SHIFT 0 -/* ADC channel 0 gain on RFFE switch state 1 (direct) */ +/* ADC channel 0 gain on RFFE switch state 1 (inverted) */ #define POS_CALC_ADC_CH0_SWCLK_1_GAIN 0x130UL #define POS_CALC_ADC_CH0_SWCLK_1_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH0_SWCLK_1_GAIN_DATA_SHIFT 0 -/* ADC channel 1 gain on RFFE switch state 1 (direct) */ +/* ADC channel 1 gain on RFFE switch state 1 (inverted) */ #define POS_CALC_ADC_CH1_SWCLK_1_GAIN 0x134UL #define POS_CALC_ADC_CH1_SWCLK_1_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH1_SWCLK_1_GAIN_DATA_SHIFT 0 -/* ADC channel 2 gain on RFFE switch state 1 (direct) */ +/* ADC channel 2 gain on RFFE switch state 1 (inverted) */ #define POS_CALC_ADC_CH2_SWCLK_1_GAIN 0x138UL #define POS_CALC_ADC_CH2_SWCLK_1_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH2_SWCLK_1_GAIN_DATA_SHIFT 0 -/* ADC channel 3 gain on RFFE switch state 1 (direct) */ +/* ADC channel 3 gain on RFFE switch state 1 (inverted) */ #define POS_CALC_ADC_CH3_SWCLK_1_GAIN 0x13cUL #define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_MASK 0xffffffffUL #define POS_CALC_ADC_CH3_SWCLK_1_GAIN_DATA_SHIFT 0 -/* ADC channel 0 offset on RFFE switch state 0 (inverted) +/* ADC channel 0 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH0_SWCLK_0_OFFSET 0x140UL #define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH0_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 1 offset on RFFE switch state 0 (inverted) +/* ADC channel 1 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH1_SWCLK_0_OFFSET 0x144UL #define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH1_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 2 offset on RFFE switch state 0 (inverted) +/* ADC channel 2 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH2_SWCLK_0_OFFSET 0x148UL #define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH2_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 3 offset on RFFE switch state 0 (inverted) +/* ADC channel 3 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH3_SWCLK_0_OFFSET 0x14cUL #define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH3_SWCLK_0_OFFSET_DATA_SHIFT 0 -/* ADC channel 0 offset on RFFE switch state 1 (direct) +/* ADC channel 0 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH0_SWCLK_1_OFFSET 0x150UL #define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH0_SWCLK_1_OFFSET_DATA_SHIFT 0 -/* ADC channel 1 offset on RFFE switch state 1 (direct) +/* ADC channel 1 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH1_SWCLK_1_OFFSET 0x154UL #define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH1_SWCLK_1_OFFSET_DATA_SHIFT 0 -/* ADC channel 2 offset on RFFE switch state 1 (direct) +/* ADC channel 2 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH2_SWCLK_1_OFFSET 0x158UL #define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_MASK 0xffffUL #define POS_CALC_ADC_CH2_SWCLK_1_OFFSET_DATA_SHIFT 0 -/* ADC channel 3 offset on RFFE switch state 1 (direct) +/* ADC channel 3 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ #define POS_CALC_ADC_CH3_SWCLK_1_OFFSET 0x15cUL @@ -739,66 +739,66 @@ struct pos_calc { /* [0x11c]: REG (ro) ADC gains fixed-point position constant */ uint32_t adc_gains_fixed_point_pos; - /* [0x120]: REG (rw) ADC channel 0 gain on RFFE switch state 0 (inverted) */ + /* [0x120]: REG (rw) ADC channel 0 gain on RFFE switch state 0 (direct) */ uint32_t adc_ch0_swclk_0_gain; - /* [0x124]: REG (rw) ADC channel 1 gain on RFFE switch state 0 (inverted) */ + /* [0x124]: REG (rw) ADC channel 1 gain on RFFE switch state 0 (direct) */ uint32_t adc_ch1_swclk_0_gain; - /* [0x128]: REG (rw) ADC channel 2 gain on RFFE switch state 0 (inverted) */ + /* [0x128]: REG (rw) ADC channel 2 gain on RFFE switch state 0 (direct) */ uint32_t adc_ch2_swclk_0_gain; - /* [0x12c]: REG (rw) ADC channel 3 gain on RFFE switch state 0 (inverted) */ + /* [0x12c]: REG (rw) ADC channel 3 gain on RFFE switch state 0 (direct) */ uint32_t adc_ch3_swclk_0_gain; - /* [0x130]: REG (rw) ADC channel 0 gain on RFFE switch state 1 (direct) */ + /* [0x130]: REG (rw) ADC channel 0 gain on RFFE switch state 1 (inverted) */ uint32_t adc_ch0_swclk_1_gain; - /* [0x134]: REG (rw) ADC channel 1 gain on RFFE switch state 1 (direct) */ + /* [0x134]: REG (rw) ADC channel 1 gain on RFFE switch state 1 (inverted) */ uint32_t adc_ch1_swclk_1_gain; - /* [0x138]: REG (rw) ADC channel 2 gain on RFFE switch state 1 (direct) */ + /* [0x138]: REG (rw) ADC channel 2 gain on RFFE switch state 1 (inverted) */ uint32_t adc_ch2_swclk_1_gain; - /* [0x13c]: REG (rw) ADC channel 3 gain on RFFE switch state 1 (direct) */ + /* [0x13c]: REG (rw) ADC channel 3 gain on RFFE switch state 1 (inverted) */ uint32_t adc_ch3_swclk_1_gain; - /* [0x140]: REG (rw) ADC channel 0 offset on RFFE switch state 0 (inverted) + /* [0x140]: REG (rw) ADC channel 0 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch0_swclk_0_offset; - /* [0x144]: REG (rw) ADC channel 1 offset on RFFE switch state 0 (inverted) + /* [0x144]: REG (rw) ADC channel 1 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch1_swclk_0_offset; - /* [0x148]: REG (rw) ADC channel 2 offset on RFFE switch state 0 (inverted) + /* [0x148]: REG (rw) ADC channel 2 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch2_swclk_0_offset; - /* [0x14c]: REG (rw) ADC channel 3 offset on RFFE switch state 0 (inverted) + /* [0x14c]: REG (rw) ADC channel 3 offset on RFFE switch state 0 (direct) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch3_swclk_0_offset; - /* [0x150]: REG (rw) ADC channel 0 offset on RFFE switch state 1 (direct) + /* [0x150]: REG (rw) ADC channel 0 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch0_swclk_1_offset; - /* [0x154]: REG (rw) ADC channel 1 offset on RFFE switch state 1 (direct) + /* [0x154]: REG (rw) ADC channel 1 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch1_swclk_1_offset; - /* [0x158]: REG (rw) ADC channel 2 offset on RFFE switch state 1 (direct) + /* [0x158]: REG (rw) ADC channel 2 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch2_swclk_1_offset; - /* [0x15c]: REG (rw) ADC channel 3 offset on RFFE switch state 1 (direct) + /* [0x15c]: REG (rw) ADC channel 3 offset on RFFE switch state 1 (inverted) Uses 2's complement representation and is subtracted from ADC samples. */ uint32_t adc_ch3_swclk_1_offset; diff --git a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd index 60c73d20..41d75bb9 100644 --- a/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd +++ b/hdl/modules/wb_position_calc/cheby/wb_pos_calc_regs.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- -- File : wb_pos_calc_regs.vhdl -- Author : auto-generated by wbgen2 from wb_pos_calc_regs.wb --- Created : Mon Jul 22 15:15:26 2024 +-- Created : Mon Jul 22 15:19:13 2024 -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_pos_calc_regs.wb @@ -271,51 +271,51 @@ entity wb_pos_calc_regs is pos_calc_offset_y_o : out std_logic_vector(31 downto 0); -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'fixed-point position constant value' in reg: 'ADC gains fixed-point position constant' pos_calc_adc_gains_fixed_point_pos_data_i : in std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 0 gain on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 0 gain on RFFE switch state 0 (direct)' pos_calc_adc_ch0_swclk_0_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 1 gain on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 1 gain on RFFE switch state 0 (direct)' pos_calc_adc_ch1_swclk_0_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 2 gain on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 2 gain on RFFE switch state 0 (direct)' pos_calc_adc_ch2_swclk_0_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 3 gain on RFFE switch state 0 (inverted)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 3 gain on RFFE switch state 0 (direct)' pos_calc_adc_ch3_swclk_0_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 0 gain on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 0 gain on RFFE switch state 1 (inverted)' pos_calc_adc_ch0_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 1 gain on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 1 gain on RFFE switch state 1 (inverted)' pos_calc_adc_ch1_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 2 gain on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 2 gain on RFFE switch state 1 (inverted)' pos_calc_adc_ch2_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 3 gain on RFFE switch state 1 (direct)' + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'gain' in reg: 'ADC channel 3 gain on RFFE switch state 1 (inverted)' pos_calc_adc_ch3_swclk_1_gain_data_o : out std_logic_vector(31 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 0 (inverted) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 0 (direct) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch0_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 0 (inverted) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 0 (direct) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch1_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 0 (inverted) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 0 (direct) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch2_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 0 (inverted) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 0 (direct) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch3_swclk_0_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 1 (direct) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 0 offset on RFFE switch state 1 (inverted) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch0_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 1 (direct) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 1 offset on RFFE switch state 1 (inverted) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch1_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 1 (direct) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 2 offset on RFFE switch state 1 (inverted) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch2_swclk_1_offset_data_o : out std_logic_vector(15 downto 0); - -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 1 (direct) + -- Port for asynchronous (clock: fs_clk2x_i) std_logic_vector field: 'offset' in reg: 'ADC channel 3 offset on RFFE switch state 1 (inverted) -- Uses 2's complement representation and is subtracted from ADC samples. -- ' pos_calc_adc_ch3_swclk_1_offset_data_o : out std_logic_vector(15 downto 0) diff --git a/hdl/sim/regs/wb_pos_calc_regs.vh b/hdl/sim/regs/wb_pos_calc_regs.vh index 7e3058ec..c6dd103a 100644 --- a/hdl/sim/regs/wb_pos_calc_regs.vh +++ b/hdl/sim/regs/wb_pos_calc_regs.vh @@ -1,6 +1,6 @@ // Do not edit. Generated by cheby 1.6.dev0 using these options: // -i wb_pos_calc_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_pos_calc_regs.vhd --doc html --gen-doc doc/wb_pos_calc_regs_wb.html --gen-c wb_pos_calc_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_pos_calc_regs.vh -// Generated on Mon Jul 22 15:15:26 2024 by guilherme.ricioli +// Generated on Mon Jul 22 15:19:13 2024 by guilherme.ricioli `define POS_CALC_SIZE 352 `define ADDR_POS_CALC_DS_TBT_THRES 'h0 From 6d17d82e6f9601fbdb3f9d045e093c1246f425a9 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Mon, 24 Jun 2024 10:19:40 -0300 Subject: [PATCH 11/17] Update infra-cores submodule (wb-si57x-ctrl support) This is a breaking change, now the Si57x oscillators for the FMC250/130 boards are not accessible directly from a 'dumb' I2C master controller, but from the wb-si57x-ctrl core. --- hdl/ip_cores/infra-cores | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index 9257afdc..590a6369 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit 9257afdcc505a6f745fc8d0efbf8822d2adfca07 +Subproject commit 590a63690a5cdf876a565928585048d45a2c5402 From bc9c4515edc2eb91e3bc93ab893332dc1b921933 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 4 Sep 2024 17:05:26 -0300 Subject: [PATCH 12/17] Delete all unsupported/unused targets Most of these synthesis targets are broken, and not used anymore. No good motives to keep them around. --- .../Manifest.py | 70 - .../build_bitstream_local.sh | 11 - .../build_bitstream_remote.sh | 11 - .../build_synthesis_sdb.sh | 17 - hdl/syn/afc_v3/wb_trigger/Manifest.py | 13 - .../ml605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py | 11 - hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/README | 2 - .../build_bitstream_local.sh | 6 - .../build_bitstream_remote.sh | 6 - .../dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xise | 1813 - .../ml605/dbe_bpm_dsp_fmc130m_4ch/make_output | 45661 ---------------- hdl/syn/ml605/dbe_bpm_dsp_fmc516/Manifest.py | 10 - .../ml605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.xise | 1614 - hdl/syn/ml605/dbe_bpm_dsp_fmc516/make_output | 27346 --------- hdl/syn/ml605/dbe_bpm_ebone/Manifest.py | 10 - .../ml605/dbe_bpm_ebone/dbe_bpm_ebone.xise | 1606 - hdl/syn/ml605/dbe_bpm_ebone/make_output | 7588 --- hdl/syn/ml605/dbe_bpm_fmc130m_4ch/Manifest.py | 10 - .../dbe_bpm_fmc130m_4ch.xise | 1610 - hdl/syn/ml605/dbe_bpm_fmc130m_4ch/make_output | 12270 ----- .../dbe_bpm_fmc130m_4ch_pcie/Manifest.py | 13 - .../build_bitstream_local.sh | 6 - .../build_bitstream_remote.sh | 6 - .../dbe_bpm_fmc130m_4ch_pcie.xise | 1714 - .../dbe_bpm_fmc130m_4ch_pcie/make_output | 23946 -------- hdl/syn/ml605/dbe_bpm_fmc516/Manifest.py | 14 - .../ml605/dbe_bpm_fmc516/dbe_bpm_fmc516.xise | 1610 - hdl/syn/ml605/dbe_bpm_fmc516/make_output | 13895 ----- hdl/syn/ml605/dbe_bpm_simple/Makefile | 24 - hdl/syn/ml605/dbe_bpm_simple/Manifest.py | 10 - .../ml605/dbe_bpm_simple/dbe_bpm_simple.xise | 1611 - hdl/syn/ml605/dbe_bpm_simple/make_output | 5960 -- hdl/syn/pcie/.gitignore | 10 - hdl/syn/pcie/HDLMAKE_NOT_SUPPORTED | 3 - hdl/syn/pcie/Manifest.py | 29 - hdl/syn/pcie/afck.xdc | 46 - hdl/syn/pcie/afcv3.xdc | 55 - hdl/syn/pcie/bpm_pcie_afck.tcl | 544 - hdl/syn/pcie/bpm_pcie_afcv3.tcl | 536 - hdl/syn/pcie/bpm_pcie_kc705.tcl | 544 - hdl/syn/pcie/kc705.xdc | 38 - .../afc_v3/dbe_bpm2_with_dcc_rtm/Manifest.py | 10 - .../dbe_bpm2_with_dcc_rtm.vhd | 759 - hdl/top/afc_v3/test_adc_clk/Manifest.py | 10 - hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.vhd | 136 - hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.xdc | 64 - hdl/top/afc_v3/wb_trigger/Manifest.py | 12 - hdl/top/afc_v3/wb_trigger/clk_gen.vhd | 50 - hdl/top/afc_v3/wb_trigger/sys_pll.vhd | 155 - hdl/top/afc_v3/wb_trigger/wb_trigger_top.vhd | 569 - hdl/top/afc_v3/wb_trigger/wb_trigger_top.xdc | 668 - .../dbe_bpm_dsp_fmc130m_4ch/Manifest.py | 12 - .../dbe_bpm_dsp_fmc130m_4ch/chipscope.cpj | 13503 ----- ..._130m_postition_large_fofb_amp_buffers.cpj | 30261 ---------- .../dbe_bpm_dsp_fmc130m_4ch/chipscope_2.cpj | 13480 ----- .../dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd | 50 - .../dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf | 703 - .../dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd | 2391 - .../dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xcf | 28 - .../dbe_bpm_dsp_fmc130m_4ch/dsp_chipscope.cpj | 30265 ---------- .../position_calc_core.ucf | 348 - .../dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd | 149 - hdl/top/ml_605/dbe_bpm_dsp_fmc516/Manifest.py | 3 - .../ml_605/dbe_bpm_dsp_fmc516/adc_data.txt | 4097 -- .../ml_605/dbe_bpm_dsp_fmc516/chipscope.cpj | 13503 ----- .../ml_605/dbe_bpm_dsp_fmc516/chipscope_2.cpj | 13480 ----- hdl/top/ml_605/dbe_bpm_dsp_fmc516/clk_gen.vhd | 47 - .../ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.ucf | 350 - .../ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.vhd | 1561 - .../dbe_bpm_dsp_fmc516/dsp_chipscope.cpj | 6869 --- .../dbe_bpm_dsp_fmc516/position_calc_core.ucf | 3091 -- hdl/top/ml_605/dbe_bpm_dsp_fmc516/sys_pll.vhd | 149 - hdl/top/ml_605/dbe_bpm_ebone/Manifest.py | 3 - hdl/top/ml_605/dbe_bpm_ebone/chipscope.cpj | 6536 --- hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd | 47 - .../ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf | 96 - .../ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd | 833 - hdl/top/ml_605/dbe_bpm_ebone/make_output | 3 - hdl/top/ml_605/dbe_bpm_ebone/run.tcl | 2 - hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd | 149 - .../ml_605/dbe_bpm_fmc130m_4ch/Manifest.py | 3 - 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hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd | 47 - .../ml_605/dbe_bpm_simple/dbe_bpm_simple.cpj | 4074 -- .../dbe_bpm_simple/dbe_bpm_simple_top.ucf | 227 - .../dbe_bpm_simple/dbe_bpm_simple_top.vhd | 755 - hdl/top/ml_605/dbe_bpm_simple/sw/Makefile | 29 - hdl/top/ml_605/dbe_bpm_simple/sw/dma.c | 27 - hdl/top/ml_605/dbe_bpm_simple/sw/fmc150.c | 3 - hdl/top/ml_605/dbe_bpm_simple/sw/genraminit | Bin 8698 -> 0 bytes hdl/top/ml_605/dbe_bpm_simple/sw/genraminit.c | 24 - hdl/top/ml_605/dbe_bpm_simple/sw/gpio.c | 23 - .../ml_605/dbe_bpm_simple/sw/include/board.h | 38 - .../ml_605/dbe_bpm_simple/sw/include/dma.h | 30 - .../ml_605/dbe_bpm_simple/sw/include/fmc150.h | 19 - .../ml_605/dbe_bpm_simple/sw/include/gpio.h | 28 - .../dbe_bpm_simple/sw/include/hw/wb_fmc150.h | 117 - .../dbe_bpm_simple/sw/include/hw/wb_uart.h | 103 - .../dbe_bpm_simple/sw/include/hw/wb_vuart.h | 96 - .../dbe_bpm_simple/sw/include/inttypes.h | 14 - .../ml_605/dbe_bpm_simple/sw/include/uart.h | 19 - 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"../../ip_cores" - -syn_device = "xc7a200t" -syn_grade = "-2" -syn_package = "ffg1156" -syn_top = "dbe_bpm2_with_dcc_rtm" -syn_project = "dbe_bpm2_with_dcc_rtm" -syn_tool = "vivado" -syn_properties = [ - ["steps.synth_design.args.more options", "-verbose"], - ["steps.synth_design.args.retiming", "1"], - ["steps.synth_design.args.assert", "1"], - ["steps.opt_design.args.verbose", "1"], - ["steps.opt_design.is_enabled", "1"], - ["steps.phys_opt_design.args.directive", "Explore"], - ["steps.phys_opt_design.args.more options", "-verbose"], - ["steps.phys_opt_design.is_enabled", "1"], - ["steps.post_route_phys_opt_design.args.directive", "Explore"], - ["steps.post_route_phys_opt_design.args.more options", "-verbose"], - ["steps.post_route_phys_opt_design.is_enabled", "1"], - ["steps.write_bitstream.args.verbose", "1"], - ["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"] -] - -board = "afc" - -# For appending the afc_ref_design.xdc to synthesis -afc_base_xdc = ['acq'] - -files = [] - -import os -import sys -if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files.append("synthesis_descriptor_pkg.vhd"); -else: - sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") - -# TCL commands file -files.append("../commands.tcl") - -machine_pkg = "sirius_sr_250M"; - -# Pass more XDC to afc-gw so it will merge it last with -# other .xdc. We need this as we depend on variables defined -# on afc_base xdc files. -xdc_files = [ - "../dbe_common/dbe_bpm2.xdc", - "../dbe_common/afc_p2p_gts.xdc", - "../dbe_common/afc_rtm_8sfp+_ohwr.xdc", - "../dbe_common/afc_rtm_8sfp+_ohwr_gts.xdc", -] - -additional_xdc = [] -for f in xdc_files: - additional_xdc.append(os.path.abspath(f)) - -modules = { - "local" : [ - "../../../top/afc_v3/dbe_bpm2_with_dcc_rtm" - ] -} diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_bitstream_local.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_bitstream_local.sh deleted file mode 100755 index 047fff83..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_bitstream_local.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_synthesis_sdb.sh deleted file mode 100755 index c370434d..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc_rtm/build_synthesis_sdb.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -# Maximum of 16 chars -SYNTH_INFO_PROJECT="bpm-gw-sr-sirius" -SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) - -SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" - -# Generate synthesis file -echo $SYNTH_INFO_COMMAND -eval $SYNTH_INFO_COMMAND diff --git a/hdl/syn/afc_v3/wb_trigger/Manifest.py b/hdl/syn/afc_v3/wb_trigger/Manifest.py deleted file mode 100755 index fecf06c0..00000000 --- a/hdl/syn/afc_v3/wb_trigger/Manifest.py +++ /dev/null @@ -1,13 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc7a200t" -syn_grade = "-1" -syn_package = "ffg1156" -syn_top = "wb_trigger_top" -syn_project = "wb_trigger_top" -syn_tool = "vivado" - -machine_pkg = "uvx_130M" - -modules = { "local" : [ "../../../top/afc_v3/vivado/wb_trigger/" ] } diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py b/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py deleted file mode 100755 index 5713cefa..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py +++ /dev/null @@ -1,11 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_dsp" -syn_project = "dbe_bpm_dsp.xise" -syn_tool = "ise" - -modules = { "local" : [ "../../../top/ml_605/dbe_bpm_dsp_fmc130m_4ch" ] }; diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/README b/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/README deleted file mode 100644 index dcd69e9b..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/README +++ /dev/null @@ -1,2 +0,0 @@ -You should enable -register-duplication MAP option to true in order -to achieve timing with dsp-cores design! diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/build_bitstream_local.sh b/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/build_bitstream_local.sh deleted file mode 100755 index d84ef6a2..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/build_bitstream_local.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash - -COMMAND="(make clean; time make; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/build_bitstream_remote.sh b/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/build_bitstream_remote.sh deleted file mode 100755 index 30d0f3f9..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/build_bitstream_remote.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash - -COMMAND="(hdlmake-devel; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xise b/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xise deleted file mode 100644 index 053d9d38..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xise +++ /dev/null @@ -1,1813 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/make_output b/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/make_output deleted file mode 100644 index e2d9a5c8..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/make_output +++ /dev/null @@ -1,45661 +0,0 @@ -rm -f *.b dbe_bpm_dsp_summary.html *.tcl dbe_bpm_dsp.bld dbe_bpm_dsp.cmd_log *.drc dbe_bpm_dsp.lso *.ncd dbe_bpm_dsp.ngc dbe_bpm_dsp.ngd dbe_bpm_dsp.ngr dbe_bpm_dsp.pad dbe_bpm_dsp.par dbe_bpm_dsp.pcf dbe_bpm_dsp.prj dbe_bpm_dsp.ptwx dbe_bpm_dsp.stx dbe_bpm_dsp.syr dbe_bpm_dsp.twr dbe_bpm_dsp.twx dbe_bpm_dsp.gise dbe_bpm_dsp.unroutes dbe_bpm_dsp.ut dbe_bpm_dsp.xpi dbe_bpm_dsp.xst dbe_bpm_dsp_bitgen.xwbt dbe_bpm_dsp_envsettings.html dbe_bpm_dsp_guide.ncd dbe_bpm_dsp_map.map dbe_bpm_dsp_map.mrp dbe_bpm_dsp_map.ncd dbe_bpm_dsp_map.ngm dbe_bpm_dsp_map.xrpt dbe_bpm_dsp_ngdbuild.xrpt dbe_bpm_dsp_pad.csv dbe_bpm_dsp_pad.txt dbe_bpm_dsp_par.xrpt dbe_bpm_dsp_summary.xml dbe_bpm_dsp_usage.xml dbe_bpm_dsp_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl -rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo -echo "project open dbe_bpm_dsp.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.syr" -Reading design: dbe_bpm_dsp.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/ip_cores/dds_adc_input.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 94. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_cop.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" included at line 64. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 65. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 165. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 166. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 87. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 74. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" into library work -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 317: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 318: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 322: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 323: Macro is redefined. -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 67. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 42. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 80. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 112. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xilinx_dist_ram_16x32.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 74. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 83. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 240. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 241. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 82. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" into library work -Parsing module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 133: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 159: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_clocking_v6.v" into library work -Parsing module . -INFO:HDLCompiler:693 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_top.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_rx_valid_filter_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_thrtl_ctl.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_upconfig_fix_3451_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_gtx_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_lane_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_misc_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_drp_chanalign_fix_3752_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_brams_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_pipeline.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_null_gen.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_tx_sync_rate_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_pipeline.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_reset_delay_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/dsp_cores_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/v6abb64Package_efifo_elink.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_private_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_a7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_k7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_6_port/chipscope_icon_6_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024_5_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192_5_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/data_checker.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDR_Blinker.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_Calculate.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/FF_tagram64x36.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Registers.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/RxIn_Delays.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/bram_DDRs_Control_Loopback.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_Transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_mem.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_fifo_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_u16x16_DSP.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_16x10_DSP.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_counters_single.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_counters.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/xwb_bpm_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/counter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/generic_multiplier.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/input_conditioner.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_239e4f614ba09ab1.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_26986301a9f671cd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_8b0747970e52f130.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_0f9a053cdbbdc75e.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_8b75732071ae5375.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cmpy_v5_0_fc1d91881e8e8ae6.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cntr_11_0_3166d4cc5b09c744.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/crdc_v5_0_19fb63dead3076ad.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dds_cmplr_v5_0_757016b8a434f5d8.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_e1825854b6ed410d.vhd" into library work -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_f359164f94f65852.vhd" into library work -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_0c61ac74cf3e5cc7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_8eb87633bf98cbda.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_b5b882c8c4a87b90.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_d5f4b3c608d95215.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_ef8269b30b0e0deb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_fe47fe6ccabc2305.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/mult_11_2_6d8e463c710483da.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/nonleaf_results.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/perl_results.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/un_cross_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/swap_cnt_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/rf_ch_swap.vhd" into library work -Parsing entity . -WARNING:HDLCompiler:685 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/rf_ch_swap.vhd" Line 34: Overwriting existing primary unit rf_ch_swap -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/inv_ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/delay_inv_ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/inv_chs_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/dyn_mult_2chs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_mach.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_mach.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_merge_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_dec_fix.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/iodelay_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/clk_ibuf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/infrastructure.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr2_ddr3_chipscope.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_read.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/circ_buffer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdctrl_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_ck_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rddata_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_clock_io.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_wr_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 786: Using initial value "00000000" for buttons_dummy since it is never assigned - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 1202: Assignment to clk_200mhz_rstn ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 1203: Assignment to clk_200mhz_rst ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "Wishbone slave device #1 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." -Warning: "Wishbone slave device #0 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x3e0000]" -Note: "Mapping slave #1[0x100000/0x3e0000]" -Note: "Mapping slave #2[0x200000/0x3fc000]" -Note: "Mapping slave #3[0x304000/0x3fffe0]" -Note: "Mapping slave #4[0x305000/0x3ffe00]" -Note: "Mapping slave #5[0x306000/0x3fff00]" -Note: "Mapping slave #6[0x307000/0x3fff00]" -Note: "Mapping slave #7[0x308000/0x3ff000]" -Note: "Mapping slave #8[0x310000/0x3ff000]" -Note: "Mapping slave #9[0x320000/0x3ff000]" -Note: "Mapping slave #10[0x330000/0x3ff000]" -Note: "Mapping slave #11[0x300000/0x3ffc00]" -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 1252: Assignment to lm32_rstn ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" Line 829: Assignment to cfg_mgmt_byte_en ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" Line 830: Assignment to cfg_mgmt_wr_en ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" Line 831: Assignment to cfg_mgmt_rd_en ignored, since the identifier is never used -Going to verilog side to elaborate module pcie_core - -Elaborating module -. - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_thrtl_ctl.v" Line 650: Assignment to reg_tlast ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" Line 788: Assignment to trn_tecrc_gen ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" Line 874: Assignment to block_clk ignored, since the identifier is never used - -Elaborating module -. - -Elaborating module -. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module -. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. - -Elaborating module . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 - -Elaborating module . -WARNING:HDLCompiler:1016 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" Line 1140: Assignment to rx_func_level_reset_n ignored, since the identifier is never used -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/RxIn_Delays.vhd" Line 808. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" Line 284. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" Line 119: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" Line 582. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" Line 343. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 493: Assignment to m_axis_rx_tvalid_r4 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 525: Assignment to m_axis_rx_tdata_little ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 527: Assignment to m_axis_rx_tdata_little_r2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 528: Assignment to m_axis_rx_tdata_little_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 540: Assignment to dsp_tag_on_fifo_r4p ignored, since the identifier is never used -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 765. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 1257: Assignment to tram_douta_r2 ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_Calculate.vhd" Line 572. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 369. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 751. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 791. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 895. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" Line 289: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" Line 664. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" Line 698: Assignment to ustlp_nempty_r1 ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" Line 318: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" Line 260. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" Line 94: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" Line 97: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" Line 480. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" Line 712: Assignment to regs_write_mbuf_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" Line 795: Assignment to wb_fifo_rden_mask_rise_r2 ignored, since the identifier is never used -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" Line 310: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" Line 176. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" Line 269: prior_init_value should be on the sensitivity list of the process -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" Line 607: Assignment to maddr_ustlp ignored, since the identifier is never used -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" Line 1156. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd" Line 300. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 258: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 101: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 116: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 874. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 176: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 241: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 248: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" Line 70: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" Line 115: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd" Line 721: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd" Line 766: Assignment to wire39 ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" Line 279: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" Line 299: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 245: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 246: Range is empty (null range) -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 87: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 434. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 451: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 505: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 238: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" Line 170: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" Line 194: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" Line 196: Range is empty (null range) - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 403: Assignment to rank_busy_ns_tmp ignored, since the identifier is never used -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 149: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 150: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 155: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 366: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 367: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 368: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 463: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 367: Range is empty (null range) -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 637: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 639: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 406: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd" Line 635: Assignment to tsta ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 571: Assignment to slot_0_read ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 580: Assignment to slot_0_dynamic_odt ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 581: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 234: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 265: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 304: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" Line 123: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" Line 237: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 347: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 348: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 357: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 359: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 368: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 377: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 303: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 1289: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 1305: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 239: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 809: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 892: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 901: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1249: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1527: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1697: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2383: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2389: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2395: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2401: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2447: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 3140: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 3296. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 169: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 160: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 447: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 457: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd" Line 126: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd" Line 130. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd" Line 162. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 116: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 172: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 208: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 272. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 131: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 284: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 313: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 377. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd" Line 231: Assignment to dqs_oe_r ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd" Line 365: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 212: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 242: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 303: Assignment to wrdata_en_r7 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 401: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 1370: Assignment to wrlvl_done_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 1541: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 1589: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 446: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 590: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 682: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 830: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 850: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 718: Assignment to wl_state_r1 ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" Line 395. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" Line 191: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" Line 194: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 641. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 688: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 719: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1077: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1133: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1173: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1346: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1568: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1306: Assignment to found_two_edge_r ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1963: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2093: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2124: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2196: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2225: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2290: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2325: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2340: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2393: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 275: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 283: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 352: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 353: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 354: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 355: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 358: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 359: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 363: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 364: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 368: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 121: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 133: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 143: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 238: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 271: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 399: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 360: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 365: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 419: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 439: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 547: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" Line 286: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" Line 352: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" Line 179: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" Line 678: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 779: Assignment to dbg_ocb_mon_off ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 786: Assignment to dbg_pd_msb_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 787: Assignment to dbg_sel_idel_cpt ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 788: Assignment to dbg_sel_idel_rsync ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 789: Assignment to dbg_pd_byte_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 791: Assignment to modify_enable_sel ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 794: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 459: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 460: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 1372: Assignment to wb_ma_pcie_rstn ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module rs232_syscon_top_1_0 - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 322: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 357: Result of 17-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 363: Result of 17-bit expression is truncated to fit in 16-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 656: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 668: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 539: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 472: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 524: Result of 6-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1066: Result of 32-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1067: Result of 6-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1096: Result of 32-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1168: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1176: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1186: Result of 17-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:552 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" Line 30: Input port master_adr_i[31] is not connected on this instance -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 157: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 175: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 134: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 71: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 73: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module ethmac - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 883: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used -"/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted - -Elaborating module . -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "generic_sync_fifo[xilinx]: using FIFO18E1 primitive [dw=32]." -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 292: Using initial value (('0','0',"00000000"),('0','0',"00000000"),('0','0',"00000000"),('0','0',"00000000")) for adc_in_dummy since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 317: Using initial value ("UUUU","UUUU","UUUU","UUUU") for adc_cs_dly_in since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 457: Using initial value '0' for dummy_bit_low since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 458: Using initial value "0000000000000000" for dummy_adc_vector_low since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xf00]" -Note: "Mapping slave #1[0x100/0xf00]" -Note: "Mapping slave #2[0x200/0xf00]" -Note: "Mapping slave #3[0x300/0xf00]" -Note: "Mapping slave #4[0x400/0xf00]" -Note: "Mapping slave #5[0x800/0xe00]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 114: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 115: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 116: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 117: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 118: Assignment to allzeros ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 826: Assignment to adc_rst ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "[ map vector(0) = -1 ]" -Note: "[ map vector(1) = -1 ]" -Note: "[ map vector(2) = -1 ]" -Note: "[ map vector(3) = -1 ]" -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 615: Range is empty (null range) -Note: "[ intercon(0) = 0 ]" -Note: "[ intercon(1) = 1 ]" -Note: "[ intercon(2) = 2 ]" -Note: "[ intercon(3) = 3 ]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" Line 164: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" Line 207: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "generic_sync_fifo[xilinx]: using FIFO18E1 primitive [dw=16]." -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" Line 76: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" Line 77: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" Line 90: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_bidir_top - -Elaborating module . - -Elaborating module . - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" Line 65: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" Line 25: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 314: Net does not have a driver. -Going to verilog side to elaborate module dds_adc_input - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 1807: Assignment to dds_cosine ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 333: Using initial value '1' for bpf_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 343: Using initial value '1' for mix_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 357: Using initial value '1' for tbt_decim_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 366: Using initial value '1' for tbt_amp_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 372: Using initial value '1' for tbt_pha_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 386: Using initial value '1' for fofb_decim_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 395: Using initial value '1' for fofb_amp_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 401: Using initial value '1' for fofb_pha_valid since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 411: Using initial value '1' for monit_amp_valid since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x700]" -Note: "Mapping slave #1[0x100/0x700]" -Note: "Mapping slave #2[0x600/0x700]" - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" Line 292: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" Line 293: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" Line 294: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" Line 295: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" Line 296: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" Line 151: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" Line 152: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" Line 153: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" Line 154: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" Line 155: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 157: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 175: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:244 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/input_conditioner.vhd" Line 76: Binding entity counter does not have generic g_switch_delay -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/counter.vhd" Line 30. counter is declared here - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/counter.vhd" Line 30. counter is declared here - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:244 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/dsp_cores_pkg.vhd" Line 851: Binding entity default_clock_driver does not have generic pipeline_regs -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" Line 396. default_clock_driver is declared here - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 123788: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 123799: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" Line 396. default_clock_driver is declared here -WARNING:HDLCompiler:244 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/dsp_cores_pkg.vhd" Line 184: Binding entity ddc_bpm_476_066_cw does not have generic pipeline_regs -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" Line 762. ddc_bpm_476_066_cw is declared here - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 124811: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 124456: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 124549: Assignment to rst_limit_join_44_1 ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 124660: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 123551: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 123563: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127315: Using initial value false for op_mem_22_20_front_din since it is never assigned -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127321: Assignment to op_mem_22_20_back ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127498: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127513: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127514: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127895: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127910: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 127911: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 125078: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 125910: Assignment to internal_core_ce ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 125912: Assignment to nd ignored, since the identifier is never used - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . -WARNING:HDLCompiler:758 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 121999: Replacing existing netlist mult_11_2_6d8e463c710483da() - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" Line 128033: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture <>) from library . -WARNING:HDLCompiler:758 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.vhd" Line 43: Replacing existing netlist fifo_generator_virtex6_8_4_5960d79e895706a2() - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" Line 762. ddc_bpm_476_066_cw is declared here - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" Line 294: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x700]" -Note: "Mapping slave #1[0x100/0x700]" -Note: "Mapping slave #2[0x200/0x700]" -Note: "Mapping slave #3[0x300/0x7f0]" -Note: "Mapping slave #4[0x400/0x600]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" Line 65: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 167: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 168: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 169: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 170: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 171: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd" Line 472. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd" Line 546. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 198: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" Line 217: Assignment to lmt_shots_nb ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -Note: "generic_async_fifo[xilinx]: using inferred BRAM-based FIFO." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" Line 656: Assignment to lmt_valid ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" Line 364: Assignment to valid_trans_app_d0 ignored, since the identifier is never used -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd" Line 619: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd" Line 621: Range is empty (null range) - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2752: Assignment to un_cross_gain_aa ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2753: Assignment to un_cross_gain_bb ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2754: Assignment to un_cross_gain_cc ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2755: Assignment to un_cross_gain_dd ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2756: Assignment to un_cross_gain_ac ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2757: Assignment to un_cross_gain_bd ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2758: Assignment to un_cross_gain_ca ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2759: Assignment to un_cross_gain_db ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2761: Assignment to un_cross_delay_1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2762: Assignment to un_cross_delay_2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2764: Assignment to un_cross_mode_1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2765: Assignment to un_cross_mode_2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2767: Assignment to un_cross_div_f ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2769: Assignment to dsp_del_sig_div_thres_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2770: Assignment to dsp_kx_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2771: Assignment to dsp_ky_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2772: Assignment to dsp_ksum_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2781: Assignment to dsp_dds_pinc_ch0 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2782: Assignment to dsp_dds_pinc_ch1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2783: Assignment to dsp_dds_pinc_ch2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2784: Assignment to dsp_dds_pinc_ch3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2785: Assignment to dsp_dds_poff_ch0 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2786: Assignment to dsp_dds_poff_ch1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2787: Assignment to dsp_dds_poff_ch2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2788: Assignment to dsp_dds_poff_ch3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2790: Assignment to dsp_dds_config_valid_ch0 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2791: Assignment to dsp_dds_config_valid_ch1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2792: Assignment to dsp_dds_config_valid_ch2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 2793: Assignment to dsp_dds_config_valid_ch3 ignored, since the identifier is never used -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 815: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 816: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 817: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 818: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 819: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 828: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 829: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 830: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 831: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 832: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 841: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 842: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 843: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 844: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 845: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 854: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 855: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 856: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 857: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 858: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 867: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 868: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 869: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 870: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 871: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 880: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 881: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 882: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 883: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 884: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 893: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 894: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 895: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 896: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 897: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 906: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 907: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 908: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 909: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 910: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 919: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 920: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 921: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 922: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 923: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 932: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 933: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 934: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 935: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" Line 936: Net does not have a driver. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd". - g_pcieLanes = 4 - pcieLanes = 4 - DDR_DQ_WIDTH = 64 - DDR_PAYLOAD_WIDTH = 256 - DDR_DQS_WIDTH = 8 - DDR_DM_WIDTH = 8 - DDR_ROW_WIDTH = 14 - DDR_BANK_WIDTH = 3 - DDR_CK_WIDTH = 1 - DDR_CKE_WIDTH = 1 - DDR_ODT_WIDTH = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1164: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1207: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1207: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1281: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1374: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1448: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1486: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1486: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1486: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1486: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1486: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1486: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1508: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1625: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1799: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 1915: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2186: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2186: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2186: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2186: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2320: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" line 2775: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit tristate buffer for signal created at line 1561 - Summary: - inferred 4 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 2 - g_logdelay = 10 - g_syncdepth = 3 - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 3-bit register for signal >. - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Set property "shreg_extract = no" for signal . - Set property "shreg_extract = no" for signal . - Set property "shreg_extract = no" for signal . - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 11 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001100110000000000000000000000000000000000000000000000000000000000110011000011111111111100010000000000000000000000000000000000000000000000010010000101010100010100011001101000001010110100000000000000000000000000000001001000000001001100010000000100010100110001001110010011000101001101011111010000100101000001001101010111110100000101000011010100010101111101000011010011110101001001000101001000000010000000000001","000000000000000000000000000000000000000000110010000001000000000000000000000000000000000000000000000000000011001000000000000000000000000000000000000000000000000000000000001100100000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000000000000000000000011000100001000000000000000000000000000000000000000000000000000001100010000000000000000000000000000000000000000000000000000000000110001000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000000000000110000100001100000000000000000000000000000000000000000000000000011000010000000000000000000000000000000000000000000000000000000001100001000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100 -00000000010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000001100000111000000000000000000000000000000000000000000000000000000110000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000011000001100000000000000000000000000000000000000000000000000000001100000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000001100000101000000000000000000000000000000000000000000000000000000110000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000011000001000000000000000000000000000000000000000000000000000000001100000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010 -10111110011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000001111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001 -00000001000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_sdb_addr = "00000000001100000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001100110000000000000000000000000000000000000000000000000000000000110011000011111111111100010000000000000000000000000000000000000000000000010010000101010100010100011001101000001010110100000000000000000000000000000001001000000001001100010000000100010100110001001110010011000101001101011111010000100101000001001101010111110100000101000011010100010101111101000011010011110101001001000101001000000010000000000001","000000000000000000000000000000000000000000110010000001000000000000000000000000000000000000000000000000000011001000000000000000000000000000000000000000000000000000000000001100100000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000000000000000000000011000100001000000000000000000000000000000000000000000000000000001100010000000000000000000000000000000000000000000000000000000000110001000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000000000000110000100001100000000000000000000000000000000000000000000000000011000010000000000000000000000000000000000000000000000000000000001100001000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100 -00000000010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000001100000111000000000000000000000000000000000000000000000000000000110000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000011000001100000000000000000000000000000000000000000000000000000001100000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000001100000101000000000000000000000000000000000000000000000000000000110000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000011000001000000000000000000000000000000000000000000000000000000001100000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010 -10111110011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000001111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001 -00000001000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000001111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value. - Found 256x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 12 - g_registered = true - g_address = ("00000000001100000000000000000000","00000000001100110000000000000000","00000000001100100000000000000000","00000000001100010000000000000000","00000000001100001000000000000000","00000000001100000111000000000000","00000000001100000110000000000000","00000000001100000101000000000000","00000000001100000100000000000000","00000000001000000000000000000000","00000000000100000000000000000000","00000000000000000000000000000000") - g_mask = ("00000000001111111111110000000000","00000000001111111111000000000000","00000000001111111111000000000000","00000000001111111111000000000000","00000000001111111111000000000000","00000000001111111111111100000000","00000000001111111111111100000000","00000000001111111111111000000000","00000000001111111111111111100000","00000000001111111100000000000000","00000000001111100000000000000000","00000000001111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 13-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 105 D-type flip-flop(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd". - SIMULATION = "FALSE" - pcieLanes = 4 - PL_FAST_TRAIN = "FALSE" - PIPE_SIM_MODE = "FALSE" - DDR_DQ_WIDTH = 64 - DDR_PAYLOAD_WIDTH = 256 - DDR_DQS_WIDTH = 8 - DDR_DM_WIDTH = 8 - DDR_ROW_WIDTH = 14 - DDR_BANK_WIDTH = 3 - DDR_CK_WIDTH = 1 - DDR_CKE_WIDTH = 1 - DDR_ODT_WIDTH = 1 - SIM_BYPASS_INIT_CAL = "OFF" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1261: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v". - ALLOW_X8_GEN2 = "FALSE" - BAR0 = -1012 - BAR1 = -1 - BAR2 = -1048564 - BAR3 = -1 - BAR4 = -524276 - BAR5 = -1 - CARDBUS_CIS_POINTER = 0 - CLASS_CODE = 327680 - CMD_INTX_IMPLEMENTED = "TRUE" - CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE" - CPL_TIMEOUT_RANGES_SUPPORTED = 2 - DEV_CAP_ENDPOINT_L0S_LATENCY = 0 - DEV_CAP_ENDPOINT_L1_LATENCY = 7 - DEV_CAP_EXT_TAG_SUPPORTED = "FALSE" - DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2 - DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0 - DEVICE_ID = 24596 - DISABLE_LANE_REVERSAL = "TRUE" - DISABLE_SCRAMBLING = "FALSE" - DSN_BASE_PTR = 256 - DSN_CAP_NEXTPTR = 0 - DSN_CAP_ON = "TRUE" - ENABLE_MSG_ROUTE = 0 - ENABLE_RX_TD_ECRC_TRIM = "TRUE" - EXPANSION_ROM = 0 - EXT_CFG_CAP_PTR = 63 - EXT_CFG_XP_CAP_PTR = 1023 - HEADER_TYPE = 0 - INTERRUPT_PIN = 1 - LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE" - LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE" - LINK_CAP_MAX_LINK_SPEED = 1 - LINK_CAP_MAX_LINK_WIDTH = 4 - LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE" - LINK_CTRL2_DEEMPHASIS = "FALSE" - LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE" - LINK_CTRL2_TARGET_LINK_SPEED = 0 - LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE" - LL_ACK_TIMEOUT = 0 - LL_ACK_TIMEOUT_EN = "FALSE" - LL_ACK_TIMEOUT_FUNC = 0 - LL_REPLAY_TIMEOUT = 38 - LL_REPLAY_TIMEOUT_EN = "TRUE" - LL_REPLAY_TIMEOUT_FUNC = 1 - LTSSM_MAX_LINK_WIDTH = 4 - MSI_CAP_MULTIMSGCAP = 0 - MSI_CAP_MULTIMSG_EXTENSION = 0 - MSI_CAP_ON = "TRUE" - MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE" - MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE" - MSIX_CAP_ON = "FALSE" - MSIX_CAP_PBA_BIR = 0 - MSIX_CAP_PBA_OFFSET = 0 - MSIX_CAP_TABLE_BIR = 0 - MSIX_CAP_TABLE_OFFSET = 0 - MSIX_CAP_TABLE_SIZE = 0 - PCIE_CAP_DEVICE_PORT_TYPE = 0 - PCIE_CAP_INT_MSG_NUM = 1 - PCIE_CAP_NEXTPTR = 0 - PCIE_DRP_ENABLE = "FALSE" - PIPE_PIPELINE_STAGES = 0 - PM_CAP_DSI = "FALSE" - PM_CAP_D1SUPPORT = "FALSE" - PM_CAP_D2SUPPORT = "FALSE" - PM_CAP_NEXTPTR = 72 - PM_CAP_PMESUPPORT = 15 - PM_CSR_NOSOFTRST = "TRUE" - PM_DATA_SCALE0 = 0 - PM_DATA_SCALE1 = 0 - PM_DATA_SCALE2 = 0 - PM_DATA_SCALE3 = 0 - PM_DATA_SCALE4 = 0 - PM_DATA_SCALE5 = 0 - PM_DATA_SCALE6 = 0 - PM_DATA_SCALE7 = 0 - PM_DATA0 = 0 - PM_DATA1 = 0 - PM_DATA2 = 0 - PM_DATA3 = 0 - PM_DATA4 = 0 - PM_DATA5 = 0 - PM_DATA6 = 0 - PM_DATA7 = 0 - REF_CLK_FREQ = 0 - REVISION_ID = 0 - SPARE_BIT0 = 0 - SUBSYSTEM_ID = 7 - SUBSYSTEM_VENDOR_ID = 4334 - TL_RX_RAM_RADDR_LATENCY = 1 - TL_RX_RAM_RDATA_LATENCY = 3 - TL_RX_RAM_WRITE_LATENCY = 1 - TL_TX_RAM_RADDR_LATENCY = 1 - TL_TX_RAM_RDATA_LATENCY = 3 - TL_TX_RAM_WRITE_LATENCY = 1 - UPCONFIG_CAPABLE = "TRUE" - USER_CLK_FREQ = 2 - VC_BASE_PTR = 0 - VC_CAP_NEXTPTR = 0 - VC_CAP_ON = "FALSE" - VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE" - VC0_CPL_INFINITE = "TRUE" - VC0_RX_RAM_LIMIT = 2047 - VC0_TOTAL_CREDITS_CD = 308 - VC0_TOTAL_CREDITS_CH = 36 - VC0_TOTAL_CREDITS_NPH = 12 - VC0_TOTAL_CREDITS_PD = 308 - VC0_TOTAL_CREDITS_PH = 32 - VC0_TX_LASTPACKET = 29 - VENDOR_ID = 4334 - VSEC_BASE_PTR = 0 - VSEC_CAP_NEXTPTR = 0 - VSEC_CAP_ON = "FALSE" - AER_BASE_PTR = 296 - AER_CAP_ECRC_CHECK_CAPABLE = "FALSE" - AER_CAP_ECRC_GEN_CAPABLE = "FALSE" - AER_CAP_ID = 1 - AER_CAP_INT_MSG_NUM_MSI = 10 - AER_CAP_INT_MSG_NUM_MSIX = 21 - AER_CAP_NEXTPTR = 352 - AER_CAP_ON = "FALSE" - AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE" - AER_CAP_VERSION = 1 - CAPABILITIES_PTR = 64 - CRM_MODULE_RSTS = 0 - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE" - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE" - DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE" - DEV_CAP_ROLE_BASED_ERROR = "TRUE" - DEV_CAP_RSVD_14_12 = 0 - DEV_CAP_RSVD_17_16 = 0 - DEV_CAP_RSVD_31_29 = 0 - DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE" - DISABLE_ASPM_L1_TIMER = "FALSE" - DISABLE_BAR_FILTERING = "FALSE" - DISABLE_ID_CHECK = "FALSE" - DISABLE_RX_TC_FILTER = "FALSE" - DNSTREAM_LINK_NUM = 0 - DSN_CAP_ID = 3 - DSN_CAP_VERSION = 1 - ENTER_RVRY_EI_L0 = "TRUE" - INFER_EI = 12 - IS_SWITCH = "FALSE" - LAST_CONFIG_DWORD = 1023 - LINK_CAP_ASPM_SUPPORT = 1 - LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE" - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_RSVD_23_22 = 0 - LINK_CONTROL_RCB = 0 - MSI_BASE_PTR = 72 - MSI_CAP_ID = 5 - MSI_CAP_NEXTPTR = 96 - MSIX_BASE_PTR = 156 - MSIX_CAP_ID = 17 - MSIX_CAP_NEXTPTR = 0 - N_FTS_COMCLK_GEN1 = 255 - N_FTS_COMCLK_GEN2 = 254 - N_FTS_GEN1 = 255 - N_FTS_GEN2 = 255 - PCIE_BASE_PTR = 96 - PCIE_CAP_CAPABILITY_ID = 16 - PCIE_CAP_CAPABILITY_VERSION = 2 - PCIE_CAP_ON = "TRUE" - PCIE_CAP_RSVD_15_14 = 0 - PCIE_CAP_SLOT_IMPLEMENTED = "FALSE" - PCIE_REVISION = 2 - PGL0_LANE = 0 - PGL1_LANE = 1 - PGL2_LANE = 2 - PGL3_LANE = 3 - PGL4_LANE = 4 - PGL5_LANE = 5 - PGL6_LANE = 6 - PGL7_LANE = 7 - PL_AUTO_CONFIG = 0 - PL_FAST_TRAIN = "FALSE" - PM_BASE_PTR = 64 - PM_CAP_AUXCURRENT = 0 - PM_CAP_ID = 1 - PM_CAP_ON = "TRUE" - PM_CAP_PME_CLOCK = "FALSE" - PM_CAP_RSVD_04 = 0 - PM_CAP_VERSION = 3 - PM_CSR_BPCCEN = "FALSE" - PM_CSR_B2B3 = "FALSE" - RECRC_CHK = 0 - RECRC_CHK_TRIM = "FALSE" - ROOT_CAP_CRS_SW_VISIBILITY = "FALSE" - SELECT_DLL_IF = "FALSE" - SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE" - SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE" - SLOT_CAP_HOTPLUG_CAPABLE = "FALSE" - SLOT_CAP_HOTPLUG_SURPRISE = "FALSE" - SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE" - SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE" - SLOT_CAP_PHYSICAL_SLOT_NUM = 0 - SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE" - SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0 - SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 0 - SPARE_BIT1 = 0 - SPARE_BIT2 = 0 - SPARE_BIT3 = 0 - SPARE_BIT4 = 0 - SPARE_BIT5 = 0 - SPARE_BIT6 = 0 - SPARE_BIT7 = 0 - SPARE_BIT8 = 0 - SPARE_BYTE0 = 0 - SPARE_BYTE1 = 0 - SPARE_BYTE2 = 0 - SPARE_BYTE3 = 0 - SPARE_WORD0 = 0 - SPARE_WORD1 = 0 - SPARE_WORD2 = 0 - SPARE_WORD3 = 0 - TL_RBYPASS = "FALSE" - TL_TFC_DISABLE = "FALSE" - TL_TX_CHECKS_DISABLE = "FALSE" - EXIT_LOOPBACK_ON_EI = "TRUE" - UPSTREAM_FACING = "TRUE" - UR_INV_REQ = "TRUE" - VC_CAP_ID = 2 - VC_CAP_VERSION = 1 - VSEC_CAP_HDR_ID = 4660 - VSEC_CAP_HDR_LENGTH = 24 - VSEC_CAP_HDR_REVISION = 1 - VSEC_CAP_ID = 11 - VSEC_CAP_IS_LINK_VISIBLE = "TRUE" - VSEC_CAP_VERSION = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 744: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 744: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 864: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_top.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_pipeline.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 22-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Summary: - inferred 180 D-type flip-flop(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_null_gen.v". - C_DATA_WIDTH = 64 - TCQ = 1 - KEEP_WIDTH = 8 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 12-bit register for signal . - Found 1-bit register for signal . - Found 12-bit subtractor for signal created at line 238. - Found 12-bit adder for signal created at line 233. - Found 12-bit comparator lessequal for signal created at line 239 - Found 12-bit comparator lessequal for signal created at line 374 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 13 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_pipeline.v". - C_DATA_WIDTH = 64 - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 75 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_thrtl_ctl.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - TCQ = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit subtractor for signal created at line 302. - Found 2-bit subtractor for signal created at line 352. - Found 6-bit comparator lessequal for signal created at line 237 - Found 6-bit comparator lessequal for signal created at line 270 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_reset_delay_v6.v". - PL_FAST_TRAIN = "FALSE" - REF_CLK_FREQ = 0 - TCQ = 1 - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 99. - Found 8-bit adder for signal created at line 100. - Found 8-bit adder for signal created at line 101. - Summary: - inferred 3 Adder/Subtractor(s). - inferred 24 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_clocking_v6.v". - IS_ENDPOINT = "TRUE" - CAP_LINK_WIDTH = 4 - CAP_LINK_SPEED = 1 - REF_CLK_FREQ = 0 - USER_CLK_FREQ = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 2-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v". - TCQ = 1 - REF_CLK_FREQ = 0 - PIPE_PIPELINE_STAGES = 0 - AER_BASE_PTR = 296 - AER_CAP_ECRC_CHECK_CAPABLE = "FALSE" - AER_CAP_ECRC_GEN_CAPABLE = "FALSE" - AER_CAP_ID = 1 - AER_CAP_INT_MSG_NUM_MSI = 10 - AER_CAP_INT_MSG_NUM_MSIX = 21 - AER_CAP_NEXTPTR = 352 - AER_CAP_ON = "FALSE" - AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE" - AER_CAP_VERSION = 1 - ALLOW_X8_GEN2 = "FALSE" - BAR0 = -1012 - BAR1 = -1 - BAR2 = -1048564 - BAR3 = -1 - BAR4 = -524276 - BAR5 = -1 - CAPABILITIES_PTR = 64 - CARDBUS_CIS_POINTER = 0 - CLASS_CODE = 327680 - CMD_INTX_IMPLEMENTED = "TRUE" - CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE" - CPL_TIMEOUT_RANGES_SUPPORTED = 2 - CRM_MODULE_RSTS = 0 - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE" - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE" - DEV_CAP_ENDPOINT_L0S_LATENCY = 0 - DEV_CAP_ENDPOINT_L1_LATENCY = 7 - DEV_CAP_EXT_TAG_SUPPORTED = "FALSE" - DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE" - DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2 - DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0 - DEV_CAP_ROLE_BASED_ERROR = "TRUE" - DEV_CAP_RSVD_14_12 = 0 - DEV_CAP_RSVD_17_16 = 0 - DEV_CAP_RSVD_31_29 = 0 - DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE" - DEVICE_ID = 24596 - DISABLE_ASPM_L1_TIMER = "FALSE" - DISABLE_BAR_FILTERING = "FALSE" - DISABLE_ID_CHECK = "FALSE" - DISABLE_LANE_REVERSAL = "TRUE" - DISABLE_RX_TC_FILTER = "FALSE" - DISABLE_SCRAMBLING = "FALSE" - DNSTREAM_LINK_NUM = 0 - DSN_BASE_PTR = 256 - DSN_CAP_ID = 3 - DSN_CAP_NEXTPTR = 0 - DSN_CAP_ON = "TRUE" - DSN_CAP_VERSION = 1 - ENABLE_MSG_ROUTE = 0 - ENABLE_RX_TD_ECRC_TRIM = "TRUE" - ENTER_RVRY_EI_L0 = "TRUE" - EXPANSION_ROM = 0 - EXT_CFG_CAP_PTR = 63 - EXT_CFG_XP_CAP_PTR = 1023 - HEADER_TYPE = 0 - INFER_EI = 12 - INTERRUPT_PIN = 1 - IS_SWITCH = "FALSE" - LAST_CONFIG_DWORD = 1023 - LINK_CAP_ASPM_SUPPORT = 1 - LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE" - LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE" - LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE" - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_MAX_LINK_SPEED = 1 - LINK_CAP_MAX_LINK_WIDTH = 4 - LINK_CAP_RSVD_23_22 = 0 - LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE" - LINK_CONTROL_RCB = 0 - LINK_CTRL2_DEEMPHASIS = "FALSE" - LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE" - LINK_CTRL2_TARGET_LINK_SPEED = 0 - LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE" - LL_ACK_TIMEOUT = 0 - LL_ACK_TIMEOUT_EN = "FALSE" - LL_ACK_TIMEOUT_FUNC = 0 - LL_REPLAY_TIMEOUT = 38 - LL_REPLAY_TIMEOUT_EN = "TRUE" - LL_REPLAY_TIMEOUT_FUNC = 1 - LTSSM_MAX_LINK_WIDTH = 4 - MSI_BASE_PTR = 72 - MSI_CAP_ID = 5 - MSI_CAP_MULTIMSGCAP = 0 - MSI_CAP_MULTIMSG_EXTENSION = 0 - MSI_CAP_NEXTPTR = 96 - MSI_CAP_ON = "TRUE" - MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE" - MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE" - MSIX_BASE_PTR = 156 - MSIX_CAP_ID = 17 - MSIX_CAP_NEXTPTR = 0 - MSIX_CAP_ON = "FALSE" - MSIX_CAP_PBA_BIR = 0 - MSIX_CAP_PBA_OFFSET = 0 - MSIX_CAP_TABLE_BIR = 0 - MSIX_CAP_TABLE_OFFSET = 0 - MSIX_CAP_TABLE_SIZE = 0 - N_FTS_COMCLK_GEN1 = 255 - N_FTS_COMCLK_GEN2 = 254 - N_FTS_GEN1 = 255 - N_FTS_GEN2 = 255 - PCIE_BASE_PTR = 96 - PCIE_CAP_CAPABILITY_ID = 16 - PCIE_CAP_CAPABILITY_VERSION = 2 - PCIE_CAP_DEVICE_PORT_TYPE = 0 - PCIE_CAP_INT_MSG_NUM = 1 - PCIE_CAP_NEXTPTR = 0 - PCIE_CAP_ON = "TRUE" - PCIE_CAP_RSVD_15_14 = 0 - PCIE_CAP_SLOT_IMPLEMENTED = "FALSE" - PCIE_REVISION = 2 - PGL0_LANE = 0 - PGL1_LANE = 1 - PGL2_LANE = 2 - PGL3_LANE = 3 - PGL4_LANE = 4 - PGL5_LANE = 5 - PGL6_LANE = 6 - PGL7_LANE = 7 - PL_AUTO_CONFIG = 0 - PL_FAST_TRAIN = "FALSE" - PM_BASE_PTR = 64 - PM_CAP_AUXCURRENT = 0 - PM_CAP_DSI = "FALSE" - PM_CAP_D1SUPPORT = "FALSE" - PM_CAP_D2SUPPORT = "FALSE" - PM_CAP_ID = 1 - PM_CAP_NEXTPTR = 72 - PM_CAP_ON = "TRUE" - PM_CAP_PME_CLOCK = "FALSE" - PM_CAP_PMESUPPORT = 15 - PM_CAP_RSVD_04 = 0 - PM_CAP_VERSION = 3 - PM_CSR_BPCCEN = "FALSE" - PM_CSR_B2B3 = "FALSE" - PM_CSR_NOSOFTRST = "TRUE" - PM_DATA_SCALE0 = 0 - PM_DATA_SCALE1 = 0 - PM_DATA_SCALE2 = 0 - PM_DATA_SCALE3 = 0 - PM_DATA_SCALE4 = 0 - PM_DATA_SCALE5 = 0 - PM_DATA_SCALE6 = 0 - PM_DATA_SCALE7 = 0 - PM_DATA0 = 0 - PM_DATA1 = 0 - PM_DATA2 = 0 - PM_DATA3 = 0 - PM_DATA4 = 0 - PM_DATA5 = 0 - PM_DATA6 = 0 - PM_DATA7 = 0 - RECRC_CHK = 0 - RECRC_CHK_TRIM = "FALSE" - REVISION_ID = 0 - ROOT_CAP_CRS_SW_VISIBILITY = "FALSE" - SELECT_DLL_IF = "FALSE" - SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE" - SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE" - SLOT_CAP_HOTPLUG_CAPABLE = "FALSE" - SLOT_CAP_HOTPLUG_SURPRISE = "FALSE" - SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE" - SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE" - SLOT_CAP_PHYSICAL_SLOT_NUM = 0 - SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE" - SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0 - SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 0 - SPARE_BIT0 = 0 - SPARE_BIT1 = 0 - SPARE_BIT2 = 0 - SPARE_BIT3 = 0 - SPARE_BIT4 = 0 - SPARE_BIT5 = 0 - SPARE_BIT6 = 0 - SPARE_BIT7 = 0 - SPARE_BIT8 = 0 - SPARE_BYTE0 = 0 - SPARE_BYTE1 = 0 - SPARE_BYTE2 = 0 - SPARE_BYTE3 = 0 - SPARE_WORD0 = 0 - SPARE_WORD1 = 0 - SPARE_WORD2 = 0 - SPARE_WORD3 = 0 - SUBSYSTEM_ID = 7 - SUBSYSTEM_VENDOR_ID = 4334 - TL_RBYPASS = "FALSE" - TL_RX_RAM_RADDR_LATENCY = 1 - TL_RX_RAM_RDATA_LATENCY = 3 - TL_RX_RAM_WRITE_LATENCY = 1 - TL_TFC_DISABLE = "FALSE" - TL_TX_CHECKS_DISABLE = "FALSE" - TL_TX_RAM_RADDR_LATENCY = 1 - TL_TX_RAM_RDATA_LATENCY = 3 - TL_TX_RAM_WRITE_LATENCY = 1 - UPCONFIG_CAPABLE = "TRUE" - UPSTREAM_FACING = "TRUE" - EXIT_LOOPBACK_ON_EI = "TRUE" - UR_INV_REQ = "TRUE" - USER_CLK_FREQ = 2 - VC_BASE_PTR = 0 - VC_CAP_ID = 2 - VC_CAP_NEXTPTR = 0 - VC_CAP_ON = "FALSE" - VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE" - VC_CAP_VERSION = 1 - VC0_CPL_INFINITE = "TRUE" - VC0_RX_RAM_LIMIT = 2047 - VC0_TOTAL_CREDITS_CD = 308 - VC0_TOTAL_CREDITS_CH = 36 - VC0_TOTAL_CREDITS_NPH = 12 - VC0_TOTAL_CREDITS_PD = 308 - VC0_TOTAL_CREDITS_PH = 32 - VC0_TX_LASTPACKET = 29 - VENDOR_ID = 4334 - VSEC_BASE_PTR = 0 - VSEC_CAP_HDR_ID = 4660 - VSEC_CAP_HDR_LENGTH = 24 - VSEC_CAP_HDR_REVISION = 1 - VSEC_CAP_ID = 11 - VSEC_CAP_IS_LINK_VISIBLE = "TRUE" - VSEC_CAP_NEXTPTR = 0 - VSEC_CAP_ON = "FALSE" - VSEC_CAP_VERSION = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. - Summary: - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v". - NO_OF_LANES = 4 - LINK_CAP_MAX_LINK_SPEED = 1 - PIPE_PIPELINE_STAGES = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_misc_v6.v". - PIPE_PIPELINE_STAGES = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_lane_v6.v". - PIPE_PIPELINE_STAGES = 0 - TCQ = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_gtx_v6.v". - TCQ = 1 - NO_OF_LANES = 4 - LINK_CAP_MAX_LINK_SPEED = 1 - REF_CLK_FREQ = 0 - PL_FAST_TRAIN = "FALSE" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_gtx_v6.v" line 255: Output port of the instance is unconnected or connected to loadless signal. - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit subtractor for signal created at line 485. - Found 5-bit adder for signal created at line 465. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v". - NO_OF_LANES = 4 - REF_CLK_FREQ = 0 - PL_FAST_TRAIN = "FALSE" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_drp_chanalign_fix_3752_v6.v". - TCQ = 1 - C_SIMULATION = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 13 | - | Inputs | 5 | - | Outputs | 11 | - | Clock | drp_clk (rising_edge) | - | Reset | Reset_n_INV_471_o (positive) | - | Reset type | synchronous | - | Reset State | 0011 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 179. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 10 D-type flip-flop(s). - inferred 7 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_rx_valid_filter_v6.v". - CLK_COR_MIN_LAT = 28 - TCQ = 1 - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 22 | - | Inputs | 7 | - | Outputs | 5 | - | Clock | USER_CLK (rising_edge) | - | Reset | RESET (positive) | - | Reset type | synchronous | - | Reset State | 00001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 10 | - | Inputs | 6 | - | Outputs | 4 | - | Clock | USER_CLK (rising_edge) | - | Reset | RESET (positive) | - | Reset type | synchronous | - | Reset State | 0001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 5-bit adder for signal created at line 309. - Found 4-bit adder for signal created at line 329. - Found 4-bit adder for signal created at line 361. - Found 5-bit comparator greater for signal created at line 284 - Found 4-bit comparator lessequal for signal created at line 357 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 44 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_tx_sync_rate_v6.v". - TCQ = 1 - C_SIMULATION = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 25-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 21 | - | Transitions | 40 | - | Inputs | 10 | - | Outputs | 21 | - | Clock | USER_CLK (rising_edge) | - | Reset | RESET (positive) | - | Reset type | synchronous | - | Reset State | 0000000000000100000000000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 179. - Found 8-bit adder for signal created at line 180. - Found 1-bit comparator equal for signal created at line 534 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 19 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v". - DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2 - VC0_TX_LASTPACKET = 29 - TLM_TX_OVERHEAD = 24 - TL_TX_RAM_RADDR_LATENCY = 1 - TL_TX_RAM_RDATA_LATENCY = 3 - TL_TX_RAM_WRITE_LATENCY = 1 - VC0_RX_LIMIT = 2047 - TL_RX_RAM_RADDR_LATENCY = 1 - TL_RX_RAM_RDATA_LATENCY = 3 - TL_RX_RAM_WRITE_LATENCY = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_brams_v6.v". - NUM_BRAMS = 4 - RAM_RADDR_LATENCY = 1 - RAM_RDATA_LATENCY = 3 - RAM_WRITE_LATENCY = 1 - TCQ = 1 - Found 13-bit register for signal . - Found 72-bit register for signal . - Found 1-bit register for signal . - Found 13-bit register for signal . - Found 72-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 172 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_v6.v". - DOB_REG = 1 - WIDTH = 7'b0010010 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_upconfig_fix_3451_v6.v". - UPSTREAM_FACING = "TRUE" - PL_FAST_TRAIN = "FALSE" - LINK_CAP_MAX_LINK_WIDTH = 4 - TCQ = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd" line 783: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd" line 783: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 280 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_Transact.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_Transact.vhd" line 787: Output port of the instance is unconnected or connected to loadless signal. - Summary: - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/RxIn_Delays.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 35 | - | Inputs | 9 | - | Outputs | 4 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | tk_rst | - | Power Up State | tk_rst | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 10-bit comparator equal for signal created at line 896 - Found 16-bit comparator equal for signal created at line 919 - Found 8-bit comparator equal for signal created at line 936 - Found 8-bit comparator equal for signal created at line 953 - Summary: - inferred 113 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 9 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" line 511: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" line 511: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal >. - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 55-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 27 | - | Inputs | 6 | - | Outputs | 2 | - | Clock | user_clk (rising_edge) | - | Reset | local_Reset (positive) | - | Reset type | asynchronous | - | Reset State | st_mrd_reset | - | Power Up State | st_mrd_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 2 | - | Clock | user_clk (rising_edge) | - | Reset | local_Reset (positive) | - | Reset type | asynchronous | - | Reset State | reqst_idle | - | Power Up State | reqst_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Summary: - inferred 423 D-type flip-flop(s). - inferred 123 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MWr_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 10-bit register for signal . - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal >. - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 26 | - | Inputs | 4 | - | Outputs | 4 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | st_mwr_reset | - | Power Up State | st_mwr_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 10-bit adder for signal created at line 404. - Found 10-bit adder for signal created at line 463. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 334 D-type flip-flop(s). - inferred 74 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" line 1150: Output port of the instance is unconnected or connected to loadless signal. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 36-bit register for signal . - Found 8-bit register for signal . - Found 13-bit register for signal . - Found 4-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 11-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 36-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 36-bit register for signal . - Found 13-bit register for signal >. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 76 | - | Inputs | 9 | - | Outputs | 6 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | st_cpld_reset | - | Power Up State | st_cpld_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 1077. - Found 4-bit adder for signal created at line 1107. - Found 4-bit adder for signal created at line 1113. - Found 32-bit adder for signal created at line 1302. - Found 6-bit subtractor for signal > created at line 877. - Found 6-bit subtractor for signal > created at line 879. - Found 8-bit comparator equal for signal created at line 1106 - Found 8-bit comparator equal for signal created at line 1112 - Found 8-bit comparator equal for signal created at line 1225 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 6 Adder/Subtractor(s). - inferred 827 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 172 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/FF_tagram64x36.vhd". - Found 1-bit register for signal . - Found 36-bit register for signal . - Found 36-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2542 D-type flip-flop(s). - inferred 128 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" line 365: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" line 543: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" line 543: Output port of the instance is unconnected or connected to loadless signal. - Found 8-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . -INFO:Xst:1799 - State reqst_quantity is never reached in FSM . -INFO:Xst:1799 - State reqst_fifo_req is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 2 | - | Clock | user_clk (rising_edge) | - | Reset | usDMA_Channel_Rst (positive) | - | Reset type | asynchronous | - | Reset State | reqst_idle | - | Power Up State | reqst_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 530. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 1 Adder/Subtractor(s). - inferred 279 D-type flip-flop(s). - inferred 5 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_Calculate.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 13-bit register for signal . - Found 13-bit register for signal . - Found 13-bit register for signal . - Found 10-bit register for signal >. - Found 12-bit register for signal . - Found 12-bit register for signal . - Found 33-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 18-bit subtractor for signal created at line 684. - Found 48-bit adder for signal created at line 365. - Found 48-bit adder for signal created at line 374. - Found 17-bit adder for signal created at line 398. - Found 17-bit adder for signal created at line 415. - Found 48-bit adder for signal created at line 432. - Found 48-bit adder for signal created at line 450. - Found 13-bit adder for signal created at line 518. - Found 17-bit adder for signal created at line 635. - Found 17-bit adder for signal created at line 652. - Found 12-bit adder for signal created at line 708. - Found 26-bit adder for signal created at line 758. - Found 57-bit adder for signal created at line 792. - Found 16-bit adder for signal created at line 844. - Found 48-bit adder for signal created at line 855. - Found 48-bit adder for signal created at line 865. - Found 13-bit subtractor for signal > created at line 619. - Found 64-bit subtractor for signal > created at line 667. - Found 48-bit subtractor for signal > created at line 922. - Found 8x18-bit Read Only RAM for signal <_n0634> - Summary: - inferred 1 RAM(s). - inferred 19 Adder/Subtractor(s). - inferred 821 D-type flip-flop(s). - inferred 174 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 128-bit register for signal . - Found 32-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 20 | - | Inputs | 7 | - | Outputs | 11 | - | Clock | dma_clk (rising_edge) | - | Reset | dma_reset (positive) | - | Reset type | asynchronous | - | Reset State | dmast_init | - | Power Up State | dmast_init | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 14 | - | Inputs | 6 | - | Outputs | 4 | - | Clock | dma_clk (rising_edge) | - | Reset | dma_reset (positive) | - | Reset type | asynchronous | - | Reset State | fsm_idle | - | Power Up State | fsm_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 8 | - | Inputs | 4 | - | Outputs | 2 | - | Clock | dma_clk (rising_edge) | - | Reset | dma_reset (positive) | - | Reset type | asynchronous | - | Reset State | toutst_idle | - | Power Up State | toutst_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 870. - Found 16-bit adder for signal created at line 877. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 175 D-type flip-flop(s). - inferred 150 Multiplexer(s). - inferred 3 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" line 654: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" line 654: Output port of the instance is unconnected or connected to loadless signal. - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 36-bit register for signal . - Found 64-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit adder for signal created at line 639. - Found 6-bit adder for signal created at line 716. - Found 6-bit subtractor for signal > created at line 718. - Found 1-bit 6-to-1 multiplexer for signal created at line 792. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 2 Adder/Subtractor(s). - inferred 148 D-type flip-flop(s). - inferred 138 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'Irpt_Qout_i<127:95>', unconnected in block 'Interrupts', is tied to its initial value (000000000000000000000000000000000). -WARNING:Xst:2935 - Signal 'Irpt_Qout_i<93:35>', unconnected in block 'Interrupts', is tied to its initial value (00000000000000000000000000000000000000000000000000000000000). -WARNING:Xst:2935 - Signal 'Irpt_Qout_i<16:10>', unconnected in block 'Interrupts', is tied to its initial value (0000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Register equivalent to has been removed - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 10 | - | Inputs | 4 | - | Outputs | 3 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | intst_rst | - | Power Up State | intst_rst | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 4-to-1 multiplexer for signal created at line 205. - Summary: - inferred 5 D-type flip-flop(s). - inferred 6 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 31-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 8-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 31-bit register for signal . - Found 1-bit register for signal . - Found 12-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 37 | - | Inputs | 9 | - | Outputs | 4 | - | Clock | user_clk (rising_edge) | - | Reset | trn_tx_Reset_n (negative) | - | Reset type | asynchronous | - | Reset State | st_txidle | - | Power Up State | st_txidle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 965 D-type flip-flop(s). - inferred 195 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 33 | - | Inputs | 16 | - | Outputs | 10 | - | Clock | user_clk (rising_edge) | - | Reset | mReader_Rst_n (negative) | - | Reset type | asynchronous | - | Reset State | st_mr_idle | - | Power Up State | st_mr_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 10-bit adder for signal created at line 467. - Found 10-bit adder for signal created at line 635. - Found 10-bit adder for signal created at line 638. - Found 22-bit adder for signal created at line 854. - Found 10-bit subtractor for signal > created at line 340. - Found 10-bit subtractor for signal > created at line 565. - Found 10-bit subtractor for signal > created at line 599. - Found 10-bit subtractor for signal > created at line 652. - Found 10-bit subtractor for signal > created at line 691. - Summary: - inferred 8 Adder/Subtractor(s). - inferred 477 D-type flip-flop(s). - inferred 352 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd". - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal >. - Found 4-bit register for signal >. - Found 4-bit register for signal >. - Found 4-bit register for signal >. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 8 | - | Inputs | 2 | - | Outputs | 2 | - | Clock | clk (rising_edge) | - | Reset | rst_n (negative) | - | Reset type | asynchronous | - | Reset State | ast_reset | - | Power Up State | ast_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal created at line 277 - Found 4-bit comparator equal for signal created at line 277 - Found 4-bit comparator equal for signal created at line 277 - Found 4-bit comparator equal for signal created at line 277 - Summary: - inferred 36 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 11 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Registers.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 25-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 28-bit register for signal . - Found 28-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal >. - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit adder for signal created at line 1899. - Found 32-bit adder for signal created at line 1919. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 1395 D-type flip-flop(s). - inferred 1437 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd". - SIMULATION = "FALSE" - DATA_WIDTH = 64 - ADDR_WIDTH = 28 - DDR_UI_DATAWIDTH = 256 - DDR_DQ_WIDTH = 32 - DEVICE_TYPE = "VIRTEX6" - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd" line 535: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 4-to-1 multiplexer for signal created at line 251. - Found 1-bit 4-to-1 multiplexer for signal created at line 251. - Summary: - inferred 7 D-type flip-flop(s). - inferred 789 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd". - C_ASYNFIFO_WIDTH = 72 - DATA_WIDTH = 64 - ADDR_WIDTH = 28 - P_SIMULATION = "FALSE" - DDR_DQ_WIDTH = 32 - DDR_PAYLOAD_WIDTH = 256 - DEVICE_TYPE = "VIRTEX6" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 313: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 313: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 345: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 369: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'wpipe_f2m_din<127:74>', unconnected in block 'DDRs_Control', is tied to its initial value (000000000000000000000000000000000000000000000000000000). -WARNING:Xst:2935 - Signal 'memc_rd_addr<27>', unconnected in block 'DDRs_Control', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'memc_rd_addr<1:0>', unconnected in block 'DDRs_Control', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'memc_wr_addr<27>', unconnected in block 'DDRs_Control', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'memc_wr_addr<1:0>', unconnected in block 'DDRs_Control', is tied to its initial value (00). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 33-bit register for signal . - Found 33-bit register for signal . - Found 8-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 30-bit register for signal . - Found 3-bit register for signal . - Found 256-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 30-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 9-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 256-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 72-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 20 | - | Inputs | 11 | - | Outputs | 5 | - | Clock | memc_ui_clk (rising_edge) | - | Reset | Rst_i (positive) | - | Reset type | asynchronous | - | Reset State | rdst_reset | - | Power Up State | rdst_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State wrst_1st_data_b2b is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 23 | - | Inputs | 9 | - | Outputs | 5 | - | Clock | memc_ui_clk (rising_edge) | - | Reset | Rst_i (positive) | - | Reset type | asynchronous | - | Reset State | wrst_bram_reset | - | Power Up State | wrst_bram_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 30-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 811. - Found 30-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 859. - Found 9-bit adder for signal created at line 901. - Found 5-bit adder for signal created at line 1241. - Found 30-bit subtractor for signal > created at line 661. - Found 9-bit subtractor for signal > created at line 671. - Found 6-bit subtractor for signal > created at line 703. - Found 30-bit subtractor for signal > created at line 858. - Found 9-bit subtractor for signal created at line 0. - Found 4-bit comparator lessequal for signal created at line 335 - Found 9-bit comparator greater for signal created at line 834 - Found 6-bit comparator greater for signal created at line 839 - Found 9-bit comparator lessequal for signal created at line 931 - Found 5-bit comparator lessequal for signal created at line 932 - Found 6-bit comparator greater for signal created at line 934 - Found 6-bit comparator lessequal for signal created at line 935 - Summary: - inferred 11 Adder/Subtractor(s). - inferred 1420 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 478 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd". - C_ASYNFIFO_WIDTH = 72 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" line 298: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" line 340: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" line 357: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'rpiped_din<71:64>', unconnected in block 'wb_transact', is tied to its initial value (00000000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 29-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 66-bit register for signal . - Found 66-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 18 | - | Inputs | 9 | - | Outputs | 6 | - | Clock | wb_clk (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | st_reset | - | Power Up State | st_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 29-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit comparator greater for signal created at line 204 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 2 Adder/Subtractor(s). - inferred 309 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 19 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd". - REFCLK_FREQ = 200.0 - IODELAY_GRP = "IODELAY_MIG" - MMCM_ADV_BANDWIDTH = "OPTIMIZED" - CLKFBOUT_MULT_F = 6 - DIVCLK_DIVIDE = 1 - CLKOUT_DIVIDE = 3 - nCK_PER_CLK = 2 - tCK = 2500 - DEBUG_PORT = "OFF" - SIM_BYPASS_INIT_CAL = "OFF" - nCS_PER_RANK = 1 - DQS_CNT_WIDTH = 3 - RANK_WIDTH = 1 - BANK_WIDTH = 3 - CK_WIDTH = 1 - CKE_WIDTH = 1 - COL_WIDTH = 10 - CS_WIDTH = 1 - DM_WIDTH = 8 - DQ_WIDTH = 64 - DQS_WIDTH = 8 - ROW_WIDTH = 14 - BURST_MODE = "4" - BM_CNT_WIDTH = 2 - ADDR_CMD_MODE = "1T" - ORDERING = "NORM" - WRLVL = "ON" - PHASE_DETECT = "ON" - RTT_NOM = "60" - RTT_WR = "OFF" - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000100000000100000000" - DQS_LOC_COL1 = "0000011100000110000001010000010000000011" - DQS_LOC_COL2 = "0" - DQS_LOC_COL3 = "0" - tPRDI = 1000000 - tREFI = 7800000 - tZQI = 128000000 - ADDR_WIDTH = 28 - ECC = "OFF" - ECC_TEST = "OFF" - TCQ = 100 - DATA_WIDTH = 64 - PAYLOAD_WIDTH = 64 - RST_ACT_LOW = 0 - INPUT_CLK_TYPE = "SINGLE_ENDED" - STARVE_LIMIT = 2 - Set property "KEEP = TRUE" for signal . - Set property "KEEP = TRUE" for signal . -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/clk_ibuf.vhd". - INPUT_CLK_TYPE = "SINGLE_ENDED" - Set property "KEEP = TRUE" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/iodelay_ctrl.vhd". - TCQ = 100 - IODELAY_GRP = "IODELAY_MIG" - INPUT_CLK_TYPE = "SINGLE_ENDED" - RST_ACT_LOW = 0 - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "syn_maxfan = 10" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 15-bit register for signal . - Summary: - inferred 15 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/infrastructure.vhd". - TCQ = 100 - CLK_PERIOD = 5000 - nCK_PER_CLK = 2 - INPUT_CLK_TYPE = "DIFFERENTIAL" - MMCM_ADV_BANDWIDTH = "OPTIMIZED" - CLKFBOUT_MULT_F = 6 - DIVCLK_DIVIDE = 1 - CLKOUT_DIVIDE = 3 - RST_ACT_LOW = 0 - Set property "syn_maxfan = 10" for signal . - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd". - REFCLK_FREQ = 200.0 - SIM_BYPASS_INIT_CAL = "OFF" - IODELAY_GRP = "IODELAY_MIG" - nCK_PER_CLK = 2 - DRAM_TYPE = "DDR3" - nCS_PER_RANK = 1 - DQ_CNT_WIDTH = 6 - DQS_CNT_WIDTH = 3 - RANK_WIDTH = 1 - BANK_WIDTH = 3 - CK_WIDTH = 1 - CKE_WIDTH = 1 - COL_WIDTH = 10 - CS_WIDTH = 1 - DM_WIDTH = 8 - USE_DM_PORT = 1 - DQ_WIDTH = 64 - DRAM_WIDTH = 8 - DQS_WIDTH = 8 - ROW_WIDTH = 14 - AL = "0" - BURST_MODE = "4" - BURST_TYPE = "SEQ" - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - nAL = 0 - CL = 6 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - BM_CNT_WIDTH = 2 - ADDR_CMD_MODE = "1T" - nBANK_MACHS = 4 - ORDERING = "NORM" - RANKS = 1 - WRLVL = "ON" - PHASE_DETECT = "ON" - CAL_WIDTH = "HALF" - RTT_NOM = "60" - RTT_WR = "OFF" - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000100000000100000000" - DQS_LOC_COL1 = "0000011100000110000001010000010000000011" - DQS_LOC_COL2 = "0" - DQS_LOC_COL3 = "0" - tCK = 2500 - tFAW = 45000 - tPRDI = 1000000 - tRRD = 7500 - tRAS = 36000 - tRCD = 13500 - tREFI = 7800000 - tRFC = 160000 - tRP = 13500 - tRTP = 7500 - tWTR = 7500 - tZQI = 128000000 - tZQCS = 64 - SLOT_0_CONFIG = "00000001" - SLOT_1_CONFIG = "00000000" - DEBUG_PORT = "OFF" - ADDR_WIDTH = 28 - MEM_ADDR_ORDER = "ROW_BANK_COLUMN" - STARVE_LIMIT = 2 - TCQ = 100 - ECC = "OFF" - DATA_WIDTH = 64 - ECC_TEST = "OFF" - PAYLOAD_WIDTH = 64 - APP_DATA_WIDTH = 256 - APP_MASK_WIDTH = 32 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 895: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd". - TCQ = 100 - PAYLOAD_WIDTH = 64 - ADDR_CMD_MODE = "1T" - AL = "0" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - BURST_TYPE = "SEQ" - CK_WIDTH = 1 - CL = 6 - COL_WIDTH = 10 - CMD_PIPE_PLUS1 = "ON" - CS_WIDTH = 1 - CKE_WIDTH = 1 - CWL = 5 - DATA_WIDTH = 64 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - DM_WIDTH = 8 - DQ_CNT_WIDTH = 6 - DQ_WIDTH = 64 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - DRAM_TYPE = "DDR3" - DRAM_WIDTH = 8 - ECC = "OFF" - ECC_WIDTH = 0 - MC_ERR_ADDR_WIDTH = 28 - nAL = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - ORDERING = "NORM" - PHASE_DETECT = "ON" - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - RTT_NOM = "60" - RTT_WR = "OFF" - STARVE_LIMIT = 2 - tCK = 2500 - tFAW = 45000 - tPRDI = 1000000 - tRAS = 36000 - tRCD = 13500 - tREFI = 7800000 - tRFC = 160000 - tRP = 13500 - tRRD = 7500 - tRTP = 7500 - tWTR = 7500 - tZQI = 128000000 - tZQCS = 64 - WRLVL = "ON" - DEBUG_PORT = "OFF" - CAL_WIDTH = "HALF" - RANK_WIDTH = 1 - RANKS = 1 - ROW_WIDTH = 14 - SLOT_0_CONFIG = "00000001" - SLOT_1_CONFIG = "00000000" - SIM_BYPASS_INIT_CAL = "OFF" - REFCLK_FREQ = 200.0 - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - USE_DM_PORT = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CL = 6 - COL_WIDTH = 10 - CMD_PIPE_PLUS1 = "ON" - CS_WIDTH = 1 - CWL = 5 - DATA_WIDTH = 64 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - nREFRESH_BANK = 1 - DRAM_TYPE = "DDR3" - DQS_WIDTH = 8 - DQ_WIDTH = 64 - ECC = "OFF" - ECC_WIDTH = 0 - MC_ERR_ADDR_WIDTH = 28 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - ORDERING = "NORM" - PAYLOAD_WIDTH = 64 - RANK_WIDTH = 1 - RANKS = 1 - PHASE_DETECT = "ON" - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - STARVE_LIMIT = 2 - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" - nSLOTS = 1 - tCK = 2500 - tFAW = 45000 - tPRDI = 1000000 - tRAS = 36000 - tRCD = 13500 - tREFI = 7800000 - tRFC = 160000 - tRP = 13500 - tRRD = 7500 - tRTP = 7500 - tWTR = 7500 - tZQI = 128000000 - tZQCS = 64 - Set property "MAX_FANOUT = 10" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" line 1012: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" line 1012: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 14-bit register for signal . - Found 14-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 10-bit register for signal . - Summary: - inferred 82 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_mach.vhd". - BURST_MODE = "4" - CS_WIDTH = 1 - DRAM_TYPE = "DDR3" - MAINT_PRESCALER_DIV = 40 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - CL = 6 - nFAW = 18 - nREFRESH_BANK = 1 - nRRD = 4 - nWTR = 4 - PERIODIC_RD_TIMER_DIV = 5 - RANK_BM_BV_WIDTH = 4 - RANK_WIDTH = 1 - RANKS = 1 - PHASE_DETECT = "ON" - REFRESH_TIMER_DIV = 39 - ZQ_TIMER_DIV = 640000 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd". - TCQ = 100 - BURST_MODE = "4" - ID = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - CL = 6 - nFAW = 18 - nREFRESH_BANK = 1 - nRRD = 4 - nWTR = 4 - PERIODIC_RD_TIMER_DIV = 5 - RANK_BM_BV_WIDTH = 4 - RANK_WIDTH = 1 - RANKS = 1 - PHASE_DETECT = "ON" - REFRESH_TIMER_DIV = 39 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" line 305: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 2-bit subtractor for signal created at line 428. - Found 3-bit adder for signal created at line 325. - Found 1-bit adder for signal > created at line 433. - Found 3-bit subtractor for signal > created at line 328. - Found 3-bit subtractor for signal > created at line 372. - Found 3-bit subtractor for signal > created at line 473. - Found 3-bit comparator lessequal for signal created at line 381 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 14 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd". - TCQ = 100 - DRAM_TYPE = "DDR3" - MAINT_PRESCALER_DIV = 40 - nBANK_MACHS = 4 - RANK_WIDTH = 1 - RANKS = 1 - REFRESH_TIMER_DIV = 39 - ZQ_TIMER_DIV = 640000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd" line 392: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd" line 477: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 20-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit adder for signal created at line 417. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 6-bit subtractor for signal > created at line 276. - Found 6-bit subtractor for signal > created at line 301. - Found 20-bit subtractor for signal > created at line 323. - Summary: - inferred 12 Adder/Subtractor(s). - inferred 43 D-type flip-flop(s). - inferred 21 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd". - TCQ = 100 - WIDTH = 2 - Found 2-bit register for signal . - Found 2-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd". - TCQ = 100 - WIDTH = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_mach.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CS_WIDTH = 1 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - LOW_IDLE_CNT = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nCS_PER_RANK = 1 - nOP_WAIT = 0 - nRAS = 15 - nRCD = 6 - nRFC = 64 - nRTP = 4 - nRP = 6 - nSLOTS = 1 - nWR = 6 - ORDERING = "NORM" - RANK_BM_BV_WIDTH = 4 - RANK_WIDTH = 1 - RANKS = 1 - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - STARVE_LIMIT = 2 - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" - tZQCS = 64 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_mach.vhd" line 909: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd". - BANK_WIDTH = 3 - TCQ = 100 - BURST_MODE = "4" - COL_WIDTH = 10 - DATA_BUF_ADDR_WIDTH = 4 - ECC = "OFF" - RANK_WIDTH = 1 - RANKS = 1 - ROW_WIDTH = 14 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'req_col_r<11:10>', unconnected in block 'bank_compare', is tied to its initial value (00). - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 14-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit shifter logical left for signal > created at line 404 - Found 3-bit comparator equal for signal created at line 338 - Found 14-bit comparator equal for signal created at line 346 - Summary: - inferred 41 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 5 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_1', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Summary: - inferred 5 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 1 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 1 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_2', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 467. - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Summary: - inferred 7 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 15 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 2 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 2 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_3', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 467. - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Found 2-bit adder for signal created at line 377. - Summary: - inferred 8 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 15 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 3 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 3 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_4', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 368. - Found 2-bit adder for signal created at line 368. - Found 2-bit adder for signal created at line 467. - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Summary: - inferred 9 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 15 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - LOW_IDLE_CNT = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nOP_WAIT = 0 - nRFC = 64 - RANK_WIDTH = 1 - RANKS = 1 - CWL = 5 - tZQCS = 64 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 455. - Found 2-bit adder for signal created at line 455. - Found 2-bit adder for signal created at line 455. - Found 2-bit adder for signal created at line 467. - Found 2-bit adder for signal created at line 467. - Found 2-bit adder for signal created at line 467. - Found 2-bit adder for signal created at line 482. - Found 2-bit adder for signal created at line 482. - Found 2-bit adder for signal created at line 482. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit subtractor for signal > created at line 686. - Found 6-bit subtractor for signal > created at line 727. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 18 Adder/Subtractor(s). - inferred 21 D-type flip-flop(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_mux.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_VECT_INDX = 11 - BANK_WIDTH = 3 - BURST_MODE = "4" - CS_WIDTH = 1 - DATA_BUF_ADDR_VECT_INDX = 15 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - nCNFG2WR = 2 - nSLOTS = 1 - RANK_VECT_INDX = 3 - RANK_WIDTH = 1 - ROW_VECT_INDX = 55 - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - EARLY_WR_DATA_ADDR = "OFF" - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2WR = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" line 242: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" line 270: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" line 323: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd". - TCQ = 100 - WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_VECT_INDX = 11 - BANK_WIDTH = 3 - BURST_MODE = "4" - CS_WIDTH = 1 - DATA_BUF_ADDR_VECT_INDX = 15 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - nSLOTS = 1 - RANK_VECT_INDX = 3 - RANK_WIDTH = 1 - ROW_VECT_INDX = 55 - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:2935 - Signal 'row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (000000000000000000000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit shifter logical left for signal > created at line 526 - Found 1-bit shifter logical left for signal > created at line 527 - Found 1-bit shifter logical left for signal created at line 242 - Summary: - inferred 9 D-type flip-flop(s). - inferred 40 Multiplexer(s). - inferred 3 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd". - TCQ = 100 - BANK_WIDTH = 3 - BURST_MODE = "4" - COL_WIDTH = 10 - CS_WIDTH = 1 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - DELAY_WR_DATA_CNTRL = 0 - DQS_WIDTH = 8 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - MC_ERR_ADDR_WIDTH = 28 - nCK_PER_CLK = 2 - nPHY_WRLAT = 0 - nRD_EN2CNFG_WR = 7 - nWR_EN2CNFG_RD = 4 - nWR_EN2CNFG_WR = 4 - RANK_WIDTH = 1 - ROW_WIDTH = 14 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). - Found 3-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 7-bit register for signal >. - Found 1-bit register for signal >. - Found 7-bit register for signal . - Found 5-bit adder for signal created at line 529. - Found 5-bit adder for signal created at line 547. - Found 3-bit subtractor for signal > created at line 430. - Found 2-bit subtractor for signal > created at line 455. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 4 Adder/Subtractor(s). - inferred 37 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200.0 - DRAM_TYPE = "DDR3" - SLOT_0_CONFIG = "00000001" - SLOT_1_CONFIG = "00000000" - BANK_WIDTH = 3 - CK_WIDTH = 1 - COL_WIDTH = 10 - nCS_PER_RANK = 1 - DQ_CNT_WIDTH = 6 - DQ_WIDTH = 64 - DM_WIDTH = 8 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - ROW_WIDTH = 14 - RANK_WIDTH = 1 - CS_WIDTH = 1 - CKE_WIDTH = 1 - CAL_WIDTH = "HALF" - CALIB_ROW_ADD = "0000000000000000" - CALIB_COL_ADD = "000000000000" - CALIB_BA_ADD = "000" - AL = "0" - BURST_MODE = "4" - BURST_TYPE = "SEQ" - nAL = 0 - nCL = 6 - nCWL = 5 - tRFC = 160000 - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - RTT_NOM = "60" - RTT_WR = "OFF" - WRLVL = "ON" - PHASE_DETECT = "ON" - PD_TAP_REQ = 0 - PD_MSB_SEL = 8 - PD_DQS0_ONLY = "ON" - PD_LHC_WIDTH = 16 - PD_CALIB_MODE = "PARALLEL" - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - USE_DM_PORT = 1 - SIM_BYPASS_INIT_CAL = "OFF" - SIM_INIT_OPTION = "NONE" - SIM_CAL_OPTION = "NONE" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1723: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1723: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1891: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . - Summary: - inferred 5 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - BANK_WIDTH = 3 - COL_WIDTH = 10 - nCS_PER_RANK = 1 - DQ_WIDTH = 64 - ROW_WIDTH = 14 - CS_WIDTH = 1 - CKE_WIDTH = 1 - DRAM_TYPE = "DDR3" - REG_CTRL = "OFF" - CALIB_ROW_ADD = "0000000000000000" - CALIB_COL_ADD = "000000000000" - CALIB_BA_ADD = "000" - AL = "0" - BURST_MODE = "4" - BURST_TYPE = "SEQ" - nAL = 0 - nCL = 6 - nCWL = 5 - tRFC = 160000 - OUTPUT_DRV = "HIGH" - RTT_NOM = "60" - RTT_WR = "OFF" - WRLVL = "ON" - PHASE_DETECT = "ON" - DDR2_DQSN_ENABLE = "YES" - nSLOTS = 1 - SIM_INIT_OPTION = "NONE" - SIM_CAL_OPTION = "NONE" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Register equivalent to has been removed - Register > equivalent to > has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Register > equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 1-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal >. - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 14-bit register for signal . - Found 1-bit register for signal . -INFO:Xst:1799 - State 011110 is never reached in FSM . -INFO:Xst:1799 - State 100101 is never reached in FSM . -INFO:Xst:1799 - State 100100 is never reached in FSM . -INFO:Xst:1799 - State 100111 is never reached in FSM . -INFO:Xst:1799 - State 011101 is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 42 | - | Transitions | 90 | - | Inputs | 30 | - | Outputs | 34 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 000000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 7-bit adder for signal created at line 1182. - Found 10-bit adder for signal created at line 1217. - Found 9-bit adder for signal created at line 1236. - Found 8-bit adder for signal created at line 1305. - Found 8-bit adder for signal created at line 1358. - Found 2-bit adder for signal created at line 1395. - Found 2-bit adder for signal created at line 1458. - Found 3-bit adder for signal created at line 1478. - Found 2-bit adder for signal created at line 2034. - Found 2-bit adder for signal created at line 2051. - Found 2-bit adder for signal created at line 2141. - Found 4-bit adder for signal created at line 2243. - Found 5-bit subtractor for signal > created at line 1066. - Found 3-bit subtractor for signal > created at line 2033. - Found 4x3-bit Read Only RAM for signal - Found 2-bit comparator greater for signal created at line 1618 - Found 2-bit comparator greater for signal created at line 1650 - Found 3-bit comparator not equal for signal created at line 2033 - Found 2-bit comparator greater for signal created at line 2079 - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <13:11>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . - WARNING:Xst:2404 - FFs/Latches <2:1>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 1 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . - Summary: - inferred 1 RAM(s). - inferred 14 Adder/Subtractor(s). - inferred 471 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 24 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd". - Set property "MAX_FANOUT = 1" for signal . - TCQ = 100 - BANK_WIDTH = 3 - RANK_WIDTH = 1 - nCS_PER_RANK = 1 - CS_WIDTH = 1 - CKE_WIDTH = 1 - ROW_WIDTH = 14 - WRLVL = "ON" - nCWL = 5 - DRAM_TYPE = "DDR3" - REG_CTRL = "OFF" - REFCLK_FREQ = 200.0 - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - DDR2_EARLY_CS = 0 - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit tristate buffer for signal created at line 597 - Found 1-bit tristate buffer for signal created at line 598 - Found 1-bit tristate buffer for signal created at line 603 - Found 1-bit tristate buffer for signal created at line 604 - Found 1-bit tristate buffer for signal created at line 607 - Found 1-bit tristate buffer for signal created at line 608 - Found 1-bit tristate buffer for signal created at line 695 - Found 1-bit tristate buffer for signal created at line 696 - Found 1-bit tristate buffer for signal created at line 701 - Found 1-bit tristate buffer for signal created at line 702 - Found 1-bit tristate buffer for signal created at line 705 - Found 1-bit tristate buffer for signal created at line 706 - Found 1-bit tristate buffer for signal created at line 793 - Found 1-bit tristate buffer for signal created at line 794 - Found 1-bit tristate buffer for signal created at line 799 - Found 1-bit tristate buffer for signal created at line 800 - Found 1-bit tristate buffer for signal created at line 803 - Found 1-bit tristate buffer for signal created at line 804 - Found 1-bit tristate buffer for signal created at line 889 - Found 1-bit tristate buffer for signal created at line 890 - Found 1-bit tristate buffer for signal created at line 895 - Found 1-bit tristate buffer for signal created at line 896 - Found 1-bit tristate buffer for signal created at line 992 - Found 1-bit tristate buffer for signal created at line 993 - Found 1-bit tristate buffer for signal created at line 998 - Found 1-bit tristate buffer for signal created at line 999 - Found 1-bit tristate buffer for signal created at line 1002 - Found 1-bit tristate buffer for signal created at line 1003 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1188 - Found 1-bit tristate buffer for signal created at line 1189 - Found 1-bit tristate buffer for signal created at line 1194 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1198 - Found 1-bit tristate buffer for signal created at line 1199 - Found 1-bit tristate buffer for signal created at line 1188 - Found 1-bit tristate buffer for signal created at line 1189 - Found 1-bit tristate buffer for signal created at line 1194 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1198 - Found 1-bit tristate buffer for signal created at line 1199 - Found 1-bit tristate buffer for signal created at line 1188 - Found 1-bit tristate buffer for signal created at line 1189 - Found 1-bit tristate buffer for signal created at line 1194 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1198 - Found 1-bit tristate buffer for signal created at line 1199 - Found 1-bit tristate buffer for signal created at line 1286 - Found 1-bit tristate buffer for signal created at line 1287 - Found 1-bit tristate buffer for signal created at line 1292 - Found 1-bit tristate buffer for signal created at line 1293 - Found 1-bit tristate buffer for signal created at line 1390 - Found 1-bit tristate buffer for signal created at line 1391 - Found 1-bit tristate buffer for signal created at line 1396 - Found 1-bit tristate buffer for signal created at line 1397 - Found 1-bit tristate buffer for signal created at line 1400 - Found 1-bit tristate buffer for signal created at line 1401 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 5 D-type flip-flop(s). - inferred 17 Multiplexer(s). - inferred 140 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_clock_io.vhd". - TCQ = 100 - CK_WIDTH = 1 - WRLVL = "ON" - DRAM_TYPE = "DDR3" - REFCLK_FREQ = 200.0 - IODELAY_GRP = "IODELAY_MIG" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_ck_iob.vhd". - TCQ = 100 - WRLVL = "ON" - DRAM_TYPE = "DDR3" - REFCLK_FREQ = 200.0 - IODELAY_GRP = "IODELAY_MIG" - Found 1-bit tristate buffer for signal created at line 154 - Found 1-bit tristate buffer for signal created at line 155 - Found 1-bit tristate buffer for signal created at line 160 - Found 1-bit tristate buffer for signal created at line 161 - Summary: - inferred 4 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd". - Set property "MAX_FANOUT = 1" for signal . - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - DRAM_WIDTH = 8 - DM_WIDTH = 8 - DQ_WIDTH = 64 - DQS_WIDTH = 8 - DRAM_TYPE = "DDR3" - nCWL = 5 - WRLVL = "ON" - REFCLK_FREQ = 200.0 - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - USE_DM_PORT = 1 - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Summary: - inferred 88 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd". - TCQ = 100 - DRAM_TYPE = "DDR3" - REFCLK_FREQ = 200.0 - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit tristate buffer for signal created at line 232 - Found 1-bit tristate buffer for signal created at line 264 - Found 1-bit tristate buffer for signal created at line 265 - Found 1-bit tristate buffer for signal created at line 270 - Found 1-bit tristate buffer for signal created at line 271 - Found 1-bit tristate buffer for signal created at line 274 - Found 1-bit tristate buffer for signal created at line 275 - Found 1-bit tristate buffer for signal created at line 310 - Found 1-bit tristate buffer for signal created at line 311 - Found 1-bit tristate buffer for signal created at line 316 - Found 1-bit tristate buffer for signal created at line 317 - Found 1-bit tristate buffer for signal created at line 320 - Found 1-bit tristate buffer for signal created at line 321 - Found 1-bit tristate buffer for signal created at line 376 - Summary: - inferred 12 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 14 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd". - TCQ = 100 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit 4-to-1 multiplexer for signal created at line 121. - Found 4-bit 4-to-1 multiplexer for signal created at line 153. - Summary: - inferred 17 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd". - TCQ = 100 - nCWL = 5 - DRAM_TYPE = "DDR3" - WRLVL = "ON" - REFCLK_FREQ = 200.0 - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit tristate buffer for signal created at line 451 - Found 1-bit tristate buffer for signal created at line 452 - Found 1-bit tristate buffer for signal created at line 457 - Found 1-bit tristate buffer for signal created at line 458 - Found 1-bit tristate buffer for signal created at line 461 - Found 1-bit tristate buffer for signal created at line 462 - Found 1-bit tristate buffer for signal created at line 490 - Found 1-bit tristate buffer for signal created at line 491 - Found 1-bit tristate buffer for signal created at line 495 - Found 1-bit tristate buffer for signal created at line 498 - Summary: - inferred 14 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 10 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd". - TCQ = 100 - nCWL = 5 - DRAM_TYPE = "DDR3" - WRLVL = "ON" - REFCLK_FREQ = 200.0 - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit tristate buffer for signal created at line 260 - Found 1-bit tristate buffer for signal created at line 562 - Found 1-bit tristate buffer for signal created at line 563 - Found 1-bit tristate buffer for signal created at line 568 - Found 1-bit tristate buffer for signal created at line 569 - Found 1-bit tristate buffer for signal created at line 572 - Found 1-bit tristate buffer for signal created at line 573 - Found 1-bit tristate buffer for signal created at line 628 - Summary: - inferred 26 D-type flip-flop(s). - inferred 5 Multiplexer(s). - inferred 8 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd". - TCQ = 100 - DQ_WIDTH = 64 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - RANK_WIDTH = 1 - nCWL = 5 - REG_CTRL = "OFF" - WRLVL = "ON" - PHASE_DETECT = "ON" - DRAM_TYPE = "DDR3" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Summary: - inferred 108 D-type flip-flop(s). - inferred 124 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd". - TCQ = 100 - WRLVL = "ON" - DRAM_TYPE = "DDR3" - DQ_WIDTH = 64 - DQS_WIDTH = 8 - nCWL = 5 - REG_CTRL = "OFF" - RANK_WIDTH = 1 - CLKPERF_DLY_USED = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 20-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit adder for signal created at line 1474. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 137 D-type flip-flop(s). - inferred 145 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd". - TCQ = 100 - DQS_CNT_WIDTH = 3 - DQ_WIDTH = 64 - SHIFT_TBY4_TAP = 8 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - CS_WIDTH = 1 - CAL_WIDTH = "HALF" - DQS_TAP_CNT_INDEX = 39 - SIM_CAL_OPTION = "NONE" - Found 40-bit register for signal >. - Found 16-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 5-bit register for signal <0>>. - Found 5-bit register for signal <1>>. - Found 5-bit register for signal <2>>. - Found 5-bit register for signal <3>>. - Found 5-bit register for signal <4>>. - Found 5-bit register for signal <5>>. - Found 5-bit register for signal <6>>. - Found 5-bit register for signal <7>>. - Found 1-bit register for signal . - Found 8-bit register for signal >. - Found 40-bit register for signal >. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <34>>. - Found 1-bit register for signal <33>>. - Found 1-bit register for signal <32>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <39>>. - Found 1-bit register for signal <38>>. - Found 1-bit register for signal <37>>. - Found 1-bit register for signal <36>>. - Found 1-bit register for signal <35>>. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal >. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 23 | - | Inputs | 10 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 369. - Found 2-bit adder for signal created at line 386. - Found 7-bit adder for signal created at line 678. - Found 7-bit adder for signal created at line 678. - Found 7-bit adder for signal created at line 678. - Found 7-bit adder for signal created at line 678. - Found 5-bit adder for signal created at line 761. - Found 4-bit adder for signal created at line 837. - Found 4-bit adder for signal created at line 838. - Found 4-bit adder for signal created at line 839. - Found 2-bit adder for signal created at line 856. - Found 4-bit adder for signal created at line 926. - Found 5-bit subtractor for signal > created at line 808. - Found 3-bit subtractor for signal <_n1469> created at line 851. - Found 3x4-bit multiplier for signal created at line 678. - Found 1-bit 8-to-1 multiplexer for signal created at line 341. - Found 1-bit 8-to-1 multiplexer for signal created at line 370. - Found 1-bit 8-to-1 multiplexer for signal created at line 370. - Found 1-bit 8-to-1 multiplexer for signal created at line 387. - Found 5-bit 8-to-1 multiplexer for signal created at line 444. - Found 1-bit 8-to-1 multiplexer for signal created at line 780. - Found 1-bit 8-to-1 multiplexer for signal created at line 797. - Found 1-bit 16-to-1 multiplexer for signal created at line 925. - Found 1-bit 16-to-1 multiplexer for signal created at line 926. - Found 1-bit 8-to-1 multiplexer for signal created at line 942. - Found 1-bit 8-to-1 multiplexer for signal created at line 945. - Found 2-bit comparator greater for signal created at line 222 - Found 5-bit comparator greater for signal created at line 365 - Found 2-bit comparator greater for signal created at line 368 - Found 2-bit comparator greater for signal created at line 385 - Found 2-bit comparator greater for signal created at line 442 - Found 4-bit comparator greater for signal created at line 442 - Found 5-bit comparator greater for signal created at line 798 - Found 5-bit comparator greater for signal created at line 811 - Found 4-bit comparator lessequal for signal created at line 818 - Found 3-bit comparator equal for signal created at line 851 - Summary: - inferred 1 Multiplier(s). - inferred 14 Adder/Subtractor(s). - inferred 351 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 319 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_read.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200.0 - DQS_WIDTH = 8 - DQ_WIDTH = 64 - DRAM_WIDTH = 8 - IODELAY_GRP = "IODELAY_MIG" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd". - Set property "MAX_FANOUT = 10" for signal . - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200.0 - DQS_WIDTH = 8 - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal >. - Found 8-bit register for signal . - Found 2-bit register for signal >. - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 9-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 11 | - | Inputs | 4 | - | Outputs | 27 | - | Clock | clk (rising_edge) | - | Reset | rst_oserdes (positive) | - | Reset type | synchronous | - | Reset State | reset_idle | - | Power Up State | reset_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 345. - Found 4-bit adder for signal created at line 358. - Found 4-bit adder for signal created at line 365. - Found 4-bit adder for signal created at line 373. - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 592 - Found 1-bit tristate buffer for signal created at line 597 - Found 1-bit tristate buffer for signal created at line 598 - Found 1-bit tristate buffer for signal created at line 601 - Found 1-bit tristate buffer for signal created at line 602 - Found 1-bit tristate buffer for signal created at line 629 - Found 1-bit tristate buffer for signal created at line 630 - Found 1-bit tristate buffer for signal created at line 634 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal created at line 637 - Found 1-bit tristate buffer for signal created at line 684 - Found 1-bit tristate buffer for signal created at line 689 - Found 1-bit tristate buffer for signal created at line 690 - Found 1-bit tristate buffer for signal created at line 693 - Found 1-bit tristate buffer for signal created at line 694 - Found 1-bit tristate buffer for signal created at line 722 - Found 1-bit tristate buffer for signal created at line 723 - Found 1-bit tristate buffer for signal created at line 727 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal created at line 730 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -INFO:Xst:2774 - HDL ADVISOR - MAX_FANOUT property attached to signal rst_oserdes may hinder XST clustering optimizations. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 81 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 140 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdctrl_sync.vhd". - TCQ = 100 - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rddata_sync.vhd". - TCQ = 100 - DQ_WIDTH = 64 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32-bit register for signal . - Found 256-bit register for signal . - Summary: - inferred 288 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/circ_buffer.vhd". - TCQ = 100 - BUF_DEPTH = 6 - DATA_WIDTH = 108 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit adder for signal created at line 153. - Found 3-bit adder for signal created at line 183. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/circ_buffer.vhd". - TCQ = 100 - BUF_DEPTH = 6 - DATA_WIDTH = 180 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit adder for signal created at line 153. - Found 3-bit adder for signal created at line 183. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200 - DQ_WIDTH = 64 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - DRAM_TYPE = "DDR3" - PD_TAP_REQ = 0 - nCL = 6 - SIM_CAL_OPTION = "NONE" - REG_CTRL = "OFF" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 3-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 40-bit register for signal . - Found 40-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 12-bit register for signal . - Found 1-bit register for signal . - Found 12-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 40-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 42 | - | Inputs | 18 | - | Outputs | 18 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 00000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 22 | - | Inputs | 10 | - | Outputs | 6 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 15 | - | Inputs | 9 | - | Outputs | 5 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 7-bit subtractor for signal created at line 186. - Found 6-bit subtractor for signal created at line 1528. - Found 7-bit subtractor for signal created at line 1773. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 752. - Found 6-bit adder for signal created at line 752. - Found 6-bit adder for signal created at line 752. - Found 6-bit adder for signal created at line 752. - Found 4-bit adder for signal created at line 807. - Found 4-bit adder for signal created at line 870. - Found 12-bit adder for signal created at line 1120. - Found 12-bit adder for signal created at line 1158. - Found 3-bit adder for signal created at line 1248. - Found 5-bit adder for signal created at line 1272. - Found 7-bit adder for signal created at line 186. - Found 6-bit adder for signal created at line 1522. - Found 6-bit adder for signal created at line 1528. - Found 3-bit adder for signal created at line 1574. - Found 5-bit adder for signal created at line 1642. - Found 6-bit adder for signal created at line 1707. - Found 6-bit adder for signal created at line 1775. - Found 3-bit adder for signal created at line 1897. - Found 5-bit adder for signal created at line 2037. - Found 3-bit adder for signal created at line 2131. - Found 5-bit adder for signal created at line 2278. - Found 2-bit adder for signal created at line 2288. - Found 6-bit adder for signal created at line 2332. - Found 6-bit adder for signal created at line 2332. - Found 6-bit adder for signal created at line 2332. - Found 6-bit adder for signal created at line 2332. - Found 3-bit adder for signal created at line 2349. - Found 4-bit adder for signal created at line 2369. - Found 5-bit subtractor for signal > created at line 1275. - Found 6-bit subtractor for signal > created at line 1524. - Found 6-bit subtractor for signal > created at line 1602. - Found 5-bit subtractor for signal > created at line 1623. - Found 5-bit subtractor for signal > created at line 201. - Found 5-bit subtractor for signal > created at line 201. - Found 5-bit subtractor for signal > created at line 1724. - Found 5-bit subtractor for signal > created at line 1751. - Found 5-bit subtractor for signal > created at line 2061. - Found 5-bit subtractor for signal > created at line 2420. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 3x3-bit multiplier for signal created at line 752. - Found 3x3-bit multiplier for signal created at line 2332. - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 3-bit 3-to-1 multiplexer for signal created at line 632. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 16-to-1 multiplexer for signal created at line 2298. - Found 1-bit 16-to-1 multiplexer for signal created at line 2301. - Found 5-bit comparator lessequal for signal created at line 1521 - Found 6-bit comparator greater for signal created at line 1522 - Found 3-bit comparator greater for signal created at line 1568 - Found 6-bit comparator greater for signal created at line 1611 - Found 6-bit comparator lessequal for signal created at line 1705 - Found 6-bit comparator lessequal for signal created at line 1707 - Found 5-bit comparator lessequal for signal created at line 2012 - Found 3-bit comparator greater for signal created at line 2124 - Found 5-bit comparator lessequal for signal created at line 2322 - Found 3-bit comparator greater for signal created at line 2340 - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . - Summary: - inferred 8 RAM(s). - inferred 2 Multiplier(s). - inferred 51 Adder/Subtractor(s). - inferred 870 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 559 Multiplexer(s). - inferred 3 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd". - TCQ = 100 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - PD_LHC_WIDTH = 16 - PD_CALIB_MODE = "PARALLEL" - PD_MSB_SEL = 8 - PD_DQS0_ONLY = "ON" - SIM_CAL_OPTION = "NONE" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd". - TCQ = 100 - SIM_CAL_OPTION = "NONE" - PD_LHC_WIDTH = 16 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 6-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 8 | - | Inputs | 3 | - | Outputs | 9 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 5-bit adder for signal created at line 488. - Found 6-bit adder for signal created at line 597. - Found 16-bit adder for signal created at line 637. - Found 16-bit adder for signal created at line 659. - Found 4-bit adder for signal created at line 716. - Found 5-bit subtractor for signal > created at line 490. - Found 16x1-bit Read Only RAM for signal - Found 1-bit 16-to-1 multiplexer for signal created at line 243. - Found 1-bit 16-to-1 multiplexer for signal created at line 248. - Summary: - inferred 1 RAM(s). - inferred 5 Adder/Subtractor(s). - inferred 67 D-type flip-flop(s). - inferred 10 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_top.vhd". - TCQ = 100 - APP_DATA_WIDTH = 256 - APP_MASK_WIDTH = 32 - BANK_WIDTH = 3 - COL_WIDTH = 10 - CWL = 5 - ECC = "OFF" - ECC_TEST = "OFF" - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - ROW_WIDTH = 14 - MEM_ADDR_ORDER = "ROW_BANK_COLUMN" - Set property "MAX_FANOUT = 10" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 10-bit register for signal . - Summary: - inferred 11 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_cmd.vhd". - Set property "MAX_FANOUT = 20" for signal . - TCQ = 100 - ADDR_WIDTH = 28 - BANK_WIDTH = 3 - COL_WIDTH = 10 - RANK_WIDTH = 1 - ROW_WIDTH = 14 - RANKS = 1 - MEM_ADDR_ORDER = "ROW_BANK_COLUMN" - Found 1-bit register for signal . - Found 28-bit register for signal . - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . -INFO:Xst:2774 - HDL ADVISOR - MAX_FANOUT property attached to signal app_rdy_r may hinder XST clustering optimizations. - Summary: - inferred 70 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_wr_data.vhd". - Set property "MAX_FANOUT = 20" for signal . - TCQ = 100 - APP_DATA_WIDTH = 256 - APP_MASK_WIDTH = 32 - ECC = "OFF" - ECC_TEST = "OFF" - CWL = 5 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 400. - Found 4-bit adder for signal created at line 424. - Found 4-bit adder for signal created at line 443. - Found 5-bit adder for signal created at line 544. - Found 5-bit subtractor for signal > created at line 542. - Found 5-bit 4-to-1 multiplexer for signal created at line 540. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 339 D-type flip-flop(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd". - Set property "MAX_FANOUT = 20". - TCQ = 100 - APP_DATA_WIDTH = 256 - ECC = "OFF" - ORDERING = "NORM" - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). - Found 6-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 6-bit adder for signal created at line 273. - Found 6-bit adder for signal created at line 273. - Found 5-bit adder for signal created at line 546. - Found 4-bit adder for signal created at line 586. - Found 5-bit subtractor for signal created at line 237. - Found 5-bit 4-to-1 multiplexer for signal created at line 555. - Found 5-bit comparator equal for signal created at line 491 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 289 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd". - g_ma_interface_mode = pipelined - g_ma_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd". - g_ma_interface_mode = pipelined - g_ma_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = false - g_master_mode = pipelined - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v". -WARNING:Xst:2898 - Port 'master_adr_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. -WARNING:Xst:2898 - Port 'master_stb_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. -WARNING:Xst:2898 - Port 'master_we_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v". - ADR_DIGITS_PP = 8 - DAT_DIGITS_PP = 8 - QTY_DIGITS_PP = 2 - CMD_BUFFER_SIZE_PP = 64 - CMD_PTR_BITS_PP = 5 - WATCHDOG_TIMER_VALUE_PP = 65000 - WATCHDOG_TIMER_BITS_PP = 16 - RD_FIELDS_PP = 8 - RD_FIELD_COUNT_BITS_PP = 4 - RD_DIGIT_COUNT_BITS_PP = 4 - m1_initial_state = 5'b00000 - m1_send_ok = 5'b00001 - m1_send_prompt = 5'b00010 - m1_check_received_char = 5'b00011 - m1_send_crlf = 5'b00100 - m1_parse_error_indicator_crlf = 5'b00101 - m1_parse_error_indicator = 5'b00110 - m1_ack_error_indicator = 5'b00111 - m1_bg_error_indicator = 5'b01000 - m1_cmd_error_indicator = 5'b01001 - m1_adr_error_indicator = 5'b01010 - m1_dat_error_indicator = 5'b01011 - m1_qty_error_indicator = 5'b01100 - m1_scan_command = 5'b10000 - m1_scan_adr_whitespace = 5'b10001 - m1_get_adr_field = 5'b10010 - m1_scan_dat_whitespace = 5'b10011 - m1_get_dat_field = 5'b10100 - m1_scan_qty_whitespace = 5'b10101 - m1_get_qty_field = 5'b10110 - m1_start_execution = 5'b10111 - m1_request_bus = 5'b11000 - m1_bus_granted = 5'b11001 - m1_execute = 5'b11010 - m1_rd_send_adr_sr = 5'b11011 - m1_rd_send_separator = 5'b11100 - m1_rd_send_dat_sr = 5'b11101 - m1_rd_send_space = 5'b11110 - m1_rd_send_crlf = 5'b11111 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" line 371: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:3015 - Contents of array may be accessed with an index that does not cover the full array size or with a negative index. The RAM size is reduced to the index upper access or for only positive index values. - Found 32x8-bit single-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . -INFO:Xst:1799 - State 00101 is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 29 | - | Transitions | 90 | - | Inputs | 24 | - | Outputs | 21 | - | Clock | clk_i (rising_edge) | - | Reset | reset_i (positive) | - | Reset type | synchronous | - | Reset State | 00000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 472. - Found 32-bit adder for signal created at line 475. - Found 5-bit adder for signal created at line 524. - Found 5-bit adder for signal created at line 526. - Found 5-bit adder for signal created at line 1067. - Found 5-bit adder for signal created at line 1096. - Found 4-bit adder for signal created at line 1168. - Found 4-bit adder for signal created at line 1176. - Found 16-bit adder for signal created at line 1186. - Found 5-bit subtractor for signal > created at line 1066. - Found 32x8-bit Read Only RAM for signal - Found 4x2-bit Read Only RAM for signal <_n0714> - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 8-bit comparator equal for signal created at line 939 - Found 8-bit comparator lessequal for signal created at line 1089 - Found 8-bit comparator lessequal for signal created at line 1089 - Found 8-bit comparator lessequal for signal created at line 1090 - Found 8-bit comparator lessequal for signal created at line 1090 - Summary: - inferred 3 RAM(s). - inferred 9 Adder/Subtractor(s). - inferred 148 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 93 Multiplexer(s). - inferred 32 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v". - CLOCK_FACTOR_PP = 8 - LOG2_MAX_COUNT_PP = 16 - m1_idle = 4'b0000 - m1_measure_0 = 4'b0001 - m1_measure_1 = 4'b0010 - m1_measure_2 = 4'b0011 - m1_measure_3 = 4'b0100 - m1_measure_4 = 4'b0101 - m1_verify_0 = 4'b1000 - m1_verify_1 = 4'b1001 - m1_run = 4'b0110 - m1_verify_failed = 4'b0111 - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 24 | - | Inputs | 6 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | reset_i (positive) | - | Reset type | asynchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 322. - Found 16-bit adder for signal created at line 363. - Found 16-bit comparator equal for signal created at line 423 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 46 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 6 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v". - START_BITS_PP = 1 - DATA_BITS_PP = 8 - STOP_BITS_PP = 1 - CLOCK_FACTOR_PP = 8 - TX_BIT_COUNT_BITS_PP = 4 - m1_idle = 0 - m1_waiting = 1 - m1_sending = 3 - m1_sending_last_bit = 2 - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 10-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 12 | - | Inputs | 4 | - | Outputs | 1 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 00 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 656. - Found 4-bit adder for signal created at line 668. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 3 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v". - START_BITS_PP = 1 - DATA_BITS_PP = 8 - STOP_BITS_PP = 1 - CLOCK_FACTOR_PP = 8 - m1_idle = 0 - m1_start = 1 - m1_shift = 3 - m1_over_run = 2 - m1_under_run = 4 - m1_all_low = 5 - m1_extra_1 = 6 - m1_extra_2 = 7 - m2_data_ready_flag = 1 - m2_data_ready_ack = 0 - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 10-bit register for signal . - Found 8-bit register for signal . - Found 3-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 16 | - | Inputs | 7 | - | Outputs | 5 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 539. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 23 D-type flip-flop(s). - inferred 2 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 224. - Found 32-bit adder for signal created at line 228. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 214. - Found 4-bit comparator equal for signal created at line 165 - Found 5-bit comparator not equal for signal created at line 233 - Found 5-bit comparator not equal for signal created at line 234 - Found 5-bit comparator not equal for signal created at line 235 - Summary: - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 174 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 77: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 22528 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = pipelined - g_slave2_interface_mode = pipelined - g_slave1_granularity = byte - g_slave2_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. - Found 22528x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 15-bit comparator greater for signal created at line 119 - Found 15-bit comparator greater for signal created at line 119 - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 4096 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = byte - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 4096 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 4096 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4096x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 54 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 409. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v". - Tp = 1 - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 92. - Found 8-bit subtractor for signal created at line 107. - Found 8-bit comparator greater for signal created at line 91 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v". - Tp = 1 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 25 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit comparator greater for signal created at line 100 - Found 7-bit comparator greater for signal created at line 101 - Found 7-bit comparator greater for signal created at line 138 - Summary: - inferred 6 D-type flip-flop(s). - inferred 3 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861. - Found 32-bit comparator lessequal for signal created at line 388 - Found 32-bit comparator greater for signal created at line 907 - Found 32-bit comparator greater for signal created at line 908 - Summary: - inferred 21 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b10100000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 1'b0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0000000 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0010010 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0001100 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000110 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 6 - RESET_VALUE = 6'b111111 - Found 6-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 4 - RESET_VALUE = 4'b1111 - Found 4-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 3 - RESET_VALUE = 3'b000 - Found 3-bit register for signal . - Summary: - inferred 3 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01100100 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 5 - RESET_VALUE = 5'b00000 - Found 5-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 16 - RESET_VALUE = 16'b0000000000000000 - Found 16-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 16-bit subtractor for signal created at line 356. - Found 3-bit adder for signal created at line 304. - Found 5-bit adder for signal created at line 323. - Found 6-bit adder for signal created at line 417. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 72 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 6-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 255. - Found 6-bit adder for signal created at line 274. - Found 6-bit adder for signal created at line 277. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 20 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v". - Tp = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 344. - Found 6-bit comparator equal for signal created at line 249 - Found 4-bit comparator equal for signal created at line 349 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v". - Tp = 1 - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 17-bit subtractor for signal created at line 170. - Found 32-bit subtractor for signal created at line 170. - Found 16-bit adder for signal created at line 162. - Found 16-bit adder for signal created at line 194. - Found 3-bit adder for signal created at line 215. - Found 32-bit comparator lessequal for signal created at line 170 - Found 16-bit comparator equal for signal created at line 199 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 35 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 187 - Found 7-bit comparator not equal for signal created at line 187 - Summary: - inferred 12 D-type flip-flop(s). - inferred 4 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v". - Tp = 1 - Found 32-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 4-bit comparator greater for signal created at line 114 - Found 4-bit comparator greater for signal created at line 115 - Found 4-bit comparator greater for signal created at line 116 - Found 4-bit comparator greater for signal created at line 117 - Found 4-bit comparator greater for signal created at line 118 - Found 4-bit comparator greater for signal created at line 119 - Found 4-bit comparator greater for signal created at line 120 - Found 4-bit comparator greater for signal created at line 121 - Found 4-bit comparator greater for signal created at line 122 - Found 10-bit comparator equal for signal created at line 139 - Summary: - inferred 20 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit comparator greater for signal created at line 213 - Found 4-bit comparator lessequal for signal created at line 314 - Summary: - inferred 40 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v". - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 116. - Found 16-bit adder for signal created at line 120. - Found 5-bit adder for signal created at line 151. - Found 4-bit adder for signal created at line 173. - Found 16-bit comparator greater for signal created at line 131 - Found 16-bit comparator greater for signal created at line 132 - Found 16-bit comparator equal for signal created at line 134 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v". -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 7-bit register for signal . - Found 7-bit register for signal . - Found 2-bit register for signal . - Found 24-bit register for signal . - Found 9-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 773. - Found 16-bit subtractor for signal created at line 777. - Found 16-bit subtractor for signal created at line 781. - Found 16-bit subtractor for signal created at line 785. - Found 30-bit adder for signal created at line 821. - Found 3-bit adder for signal created at line 960. - Found 30-bit adder for signal created at line 964. - Found 3-bit adder for signal created at line 996. - Found 8-bit adder for signal created at line 1395. - Found 8-bit adder for signal created at line 1398. - Found 2-bit adder for signal created at line 1745. - Found 30-bit adder for signal created at line 2001. - Found 2-bit adder for signal created at line 2098. - Found 2-bit adder for signal created at line 2117. - Found 4x2-bit Read Only RAM for signal - Found 4x6-bit Read Only RAM for signal <_n1580> - Found 1-bit 4-to-1 multiplexer for signal created at line 1630. - Found 8-bit 4-to-1 multiplexer for signal created at line 1648. - Found 8-bit 4-to-1 multiplexer for signal created at line 1660. - Found 16-bit 4-to-1 multiplexer for signal created at line 776. - Found 16-bit comparator greater for signal created at line 627 - Found 16-bit comparator greater for signal created at line 803 - Found 16-bit comparator lessequal for signal created at line 898 - Found 8-bit comparator greater for signal created at line 1062 - Found 16-bit comparator greater for signal created at line 1062 - Found 8-bit comparator lessequal for signal created at line 2417 - Found 1-bit comparator equal for signal created at line 2422 - Found 8-bit comparator greater for signal created at line 2423 - Summary: - inferred 2 RAM(s). - inferred 11 Adder/Subtractor(s). - inferred 461 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v". - we_width = 1 - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v". - DATA_WIDTH = 32 - DEPTH = 256 - CNT_WIDTH = 8 - Set property "syn_ramstyle = no_rw_check" for signal . - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 83. - Found 8-bit adder for signal created at line 114. - Found 8-bit adder for signal created at line 122. - Found 8-bit subtractor for signal > created at line 81. - Summary: - inferred 1 RAM(s). - inferred 3 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 16-bit comparator greater for signal created at line 236 - Found 16-bit comparator greater for signal created at line 236 - Found 6-bit comparator equal for signal created at line 310 - Summary: - inferred 18 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 3 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_3412_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_3412_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 299. - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 320. - Found 16-bit adder for signal created at line 1241. - Found 32-bit 7-to-1 multiplexer for signal <_n0442> created at line 206. - Found 32-bit comparator greater for signal created at line 299 - Found 16-bit comparator greater for signal created at line 320 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 254 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 2 - g_adr_width_B = 32 - g_dat_width_A = 16 - g_dat_width_B = 32 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 32 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 32 - g_adr_width_B = 2 - g_dat_width_A = 32 - g_dat_width_B = 16 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 32 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd". - g_sdb_address = "0000000000000000000000000000000000000000001100000000000000000000" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 15-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 13-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 160-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 11-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 12 | - | Transitions | 41 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | _n0497 (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 11-bit adder for signal created at line 222. - Found 6-bit adder for signal created at line 464. - Found 7-bit adder for signal created at line 472. - Found 16-bit adder for signal created at line 1241. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit 3-to-1 multiplexer for signal created at line 242. - Found 1-bit 3-to-1 multiplexer for signal created at line 242. - Found 11-bit comparator equal for signal created at line 456 - Found 11-bit comparator equal for signal created at line 464 - Found 11-bit comparator equal for signal created at line 472 - Found 11-bit comparator greater for signal created at line 482 - Found 16-bit comparator equal for signal created at line 485 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 499 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 84 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 96 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 106 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd". - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 1 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3428_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 28-bit adder for signal created at line 91. - Found 28-bit adder for signal created at line 102. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 61 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 160 - g_width_OUT = 16 - g_protected = 0 - Found 9-bit register for signal . - Found 160-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 170 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 15-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 29 | - | Inputs | 10 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3473_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State ipv4_chksum is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 15 | - | Transitions | 34 | - | Inputs | 13 | - | Outputs | 12 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_parser_reset_OR_17686_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | eth | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 14-bit subtractor for signal created at line 426. - Found 11-bit adder for signal created at line 291. - Found 12-bit adder for signal created at line 405. - Found 12-bit adder for signal created at line 426. - Found 13-bit adder for signal created at line 426. - Found 17-bit adder for signal created at line 504. - Found 15-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 504. - Found 11-bit comparator equal for signal created at line 347 - Found 12-bit comparator equal for signal created at line 405 - Found 12-bit comparator greater for signal created at line 420 - Found 14-bit comparator equal for signal created at line 426 - Found 16-bit comparator equal for signal created at line 447 - Found 11-bit comparator greater for signal created at line 520 - Found 11-bit comparator equal for signal created at line 529 - Summary: - inferred 8 Adder/Subtractor(s). - inferred 244 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 14 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 160 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 160-bit register for signal . - Found 4-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 166 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 15-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . -INFO:Xst:1799 - State zero_pad_wait is never reached in FSM . -INFO:Xst:1799 - State error is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 716 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3517_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 19 | - | Transitions | 145 | - | Inputs | 19 | - | Outputs | 16 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3517_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit subtractor for signal > created at line 1308. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 4-bit comparator greater for signal created at line 363 - Found 16-bit comparator greater for signal created at line 504 - Found 8-bit comparator greater for signal created at line 584 - Found 8-bit comparator greater for signal created at line 619 - Found 16-bit comparator equal for signal created at line 659 - Found 4-bit comparator greater for signal created at line 716 - Found 8-bit comparator greater for signal created at line 986 - Summary: - inferred 13 Adder/Subtractor(s). - inferred 367 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 65 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 32 - g_size = 16 - g_show_ahead = true - g_with_empty = true - g_with_full = true - g_with_almost_empty = true - g_with_almost_full = true - g_with_count = true - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 - g_register_flag_outputs = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 165: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd". - g_data_width = 32 - g_size = 16 - g_dual_clock = false - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 - Found 4-bit subtractor for signal created at line 64. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd". - g_sdb_address = "0000000000000000000000000000000000000000001100000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 8-to-1 multiplexer for signal <_n0271> created at line 137. - Found 32-bit 8-to-1 multiplexer for signal <_n0289> created at line 168. - Summary: - inferred 328 D-type flip-flop(s). - inferred 22 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (8.88,8.88,8.88,8.88) - g_use_clk_chains = "1111" - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (8.88,8.88,8.88,8.88) - g_use_clk_chains = "1111" - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 547: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1022: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1059: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1059: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1094: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1130: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 1-bit tristate buffer for signal created at line 1043 - Found 1-bit tristate buffer for signal created at line 1046 - Found 1-bit tristate buffer for signal created at line 1115 - Found 1-bit tristate buffer for signal created at line 1118 - Found 1-bit tristate buffer for signal created at line 1151 - Found 1-bit tristate buffer for signal created at line 1154 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 6 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd". - g_pipeline = 4 - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010111000010000101111011110001010100000000000000000000000000000001001000000001001100100000000010000100110001001110010011000101001101011111010001100100110101000011001100010011001100110000010011010101111101010010010001010100011101010011001000000010000000000001") - g_sdb_addr = "00000000000000000000100000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010111000010000101111011110001010100000000000000000000000000000001001000000001001100100000000010000100110001001110010011000101001101011111010001100100110101000011001100010011001100110000010011010101111101010010010001010100011101010011001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 6 - g_registered = true - g_address = ("00000000000000000000100000000000","00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000111000000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 7-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 7 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 297 D-type flip-flop(s). - inferred 35 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd". - g_with_var_loadable = true - g_with_variable = false - g_with_fn_dly_select = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Summary: - inferred 12 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd". - g_with_clk_single_ended = true - g_with_data_single_ended = true - g_with_data_sdr = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clk_period_values = (8.88,8.88,8.88,8.88) - g_use_clk_chains = "1111" - g_clk_default_dly = (5,5,5,5) - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_data_default_dly = (9,9,9,9) - g_ref_clk = 1 - g_mmcm_param = (1,8.0,8.88,8.0,4) - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_with_data_sdr = true - g_with_fn_dly_select = true - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.88 - g_default_adc_clk_delay = 5 - g_with_ref_clk = false - g_mmcm_param = (1,8.0,8.88,8.0,4) - g_with_fn_dly_select = true - g_with_bufio = false - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.88 - g_default_adc_clk_delay = 5 - g_with_ref_clk = true - g_mmcm_param = (1,8.0,8.88,8.0,4) - g_with_fn_dly_select = true - g_with_bufio = false - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd". - g_delay_type = "VAR_LOADABLE" - g_default_adc_data_delay = 9 - g_with_data_sdr = true - g_with_fn_dly_select = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Summary: - inferred 81 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 16 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd". - g_data_width = 16 - g_size = 16 - g_dual_clock = true - g_almost_empty_threshold = 8 - g_almost_full_threshold = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 64 - g_size = 16 - g_show_ahead = false - g_with_empty = true - g_with_full = true - g_with_almost_empty = false - g_with_almost_full = false - g_with_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 - g_register_flag_outputs = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 165: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd". - g_data_width = 64 - g_size = 16 - g_dual_clock = false - g_almost_empty_threshold = 8 - g_almost_full_threshold = 8 - Found 4-bit subtractor for signal created at line 64. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd". - ARST_LVL = '0' -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit 8-to-1 multiplexer for signal created at line 191. - Summary: - inferred 54 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 26 | - | Inputs | 9 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | st_idle | - | Power Up State | st_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 3-bit subtractor for signal > created at line 1308. - Found 4-bit 6-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 34 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 14-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 64 | - | Inputs | 6 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit subtractor for signal > created at line 1308. - Found 14-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 57 D-type flip-flop(s). - inferred 26 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 12-to-1 multiplexer for signal created at line 126. - Summary: - inferred 80 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v". - Tp = 1 - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 80. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v". - Tp = 1 - Found 12-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 91. - Found 8-bit subtractor for signal created at line 91. - Found 8-bit subtractor for signal created at line 92. - Found 8-bit adder for signal created at line 92. - Found 12-bit adder for signal created at line 116. - Found 1-bit 128-to-1 multiplexer for signal created at line 164. - Found 1-bit 128-to-1 multiplexer for signal created at line 293. - Found 1-bit 128-to-1 multiplexer for signal created at line 294. - Found 12-bit comparator lessequal for signal created at line 137 - Found 12-bit comparator greater for signal created at line 139 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 407 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd". - g_wbs_interface_width = narrow2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd". - g_data_width = 25 - g_size = 32 - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 5-bit adder for signal created at line 150. - Found 5-bit subtractor for signal > created at line 152. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd". - g_size = 32 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd". - g_min_pulse_width = 1 - g_clk_frequency = 130 - g_output_polarity = '0' - g_output_retrig = false - g_output_length = 1 - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 20000000 - Found 25-bit register for signal . - Found 1-bit register for signal . - Found 25-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 26 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_with_switching = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_with_switching = 0 - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 604: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 604: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 604: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 744: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 744: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 863: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 1033: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 1033: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 1033: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 1051: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 1051: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" line 1051: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Found 1-bit register for signal . - Found 192-bit register for signal . - Found 192-bit register for signal . - Found 1-bit register for signal . - Found 96-bit register for signal . - Found 96-bit register for signal . - Found 104-bit register for signal . - Found 1-bit register for signal . - Found 192-bit register for signal . - Found 1-bit register for signal . - Found 96-bit register for signal . - Found 96-bit register for signal . - Found 104-bit register for signal . - Found 1-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 104-bit register for signal . - Found 1-bit register for signal . - Found 104-bit register for signal . - Found 1-bit register for signal . - Found 96-bit register for signal . -INFO:Xst:2774 - HDL ADVISOR - MAX_FANOUT property attached to signal sys_clr may hinder XST clustering optimizations. - Summary: - inferred 1576 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 2 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100010000000000000000000000000000000000000000000000010010000101010001001010001001011101011001001000000000000000000000000000000001001000000001001100000111000000110100110001001110010011000101001101011111010000100101000001001101010111110101001101010111010000010101000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000100000000000000000000000000000000000000000000000100100001010100011011101011111011111100011110000000000000000000000000000000010010000000010011000001110000001101001100010011100100110001010011010111110101000001001111010100110101111101000011010000010100110001000011010111110101001001000101010001110101001100100000000 -00001") - g_sdb_addr = "00000000000000000000011000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100010000000000000000000000000000000000000000000000010010000101010001001010001001011101011001001000000000000000000000000000000001001000000001001100000111000000110100110001001110010011000101001101011111010000100101000001001101010111110101001101010111010000010101000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000100000000000000000000000000000000000000000000000100100001010100011011101011111011111100011110000000000000000000000000000000010010000000010011000001110000001101001100010011100100110001010011010111110101000001001111010100110101111101000011010000010100110001000011010111110101001001000101010001110101001100100000000 -00001") - g_bus_end = "0000000000000000000000000000000000000000000000000000011111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_3', is tied to its initial value. - Found 64x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 3 - g_registered = true - g_address = ("00000000000000000000011000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000011100000000","00000000000000000000011100000000","00000000000000000000011100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 7-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 26-bit register for signal . - Found 26-bit register for signal . - Found 26-bit register for signal . - Found 26-bit register for signal . - Found 26-bit register for signal . - Found 26-bit register for signal . - Found 25-bit register for signal . - Found 25-bit register for signal . - Found 25-bit register for signal . - Found 25-bit register for signal . - Found 25-bit register for signal . - Found 25-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 1424 D-type flip-flop(s). - inferred 209 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 187: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 220: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 220: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 246: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" line 246: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 519 D-type flip-flop(s). - inferred 31 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/un_cross_top.vhd". - g_delay_vec_width = 16 - g_swap_div_freq_vec_width = 16 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/swap_cnt_top.vhd". - g_swap_div_freq_vec_width = 16 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 95. - Found 16-bit adder for signal created at line 145. - Found 16-bit comparator equal for signal created at line 141 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 21 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/rf_ch_swap.vhd". - g_direct = "10100101" - g_inverted = "01011010" - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 18 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/inv_chs_top.vhd". - g_delay_vec_width = 16 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/delay_inv_ch.vhd". - g_delay_vec_width = 16 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 54. - Found 16-bit subtractor for signal > created at line 65. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/inv_ch.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 35 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/dyn_mult_2chs.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 35 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/input_conditioner.vhd". - g_sw_interval = 1000 - g_input_width = 16 - g_output_width = 16 - g_window_width = 24 - g_input_delay = 2 - g_window_coef_file = "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window.ram" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 24 - g_size = 501 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window.ram" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 77: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 24 - g_size = 501 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window.ram" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 24 - g_size = 501 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window.ram" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. - Found 501x24-bit dual-port RAM for signal . - Found 24-bit register for signal . - Found 24-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 48 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/counter.vhd". - g_mem_size = 501 - g_bus_size = 9 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 9-bit register for signal . - Found 9-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1314. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit comparator not equal for signal created at line 82 - Found 9-bit comparator not equal for signal created at line 95 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 21 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/sw_windowing/generic_multiplier.vhd". - g_a_width = 16 - g_b_width = 24 - g_signed = true - g_p_width = 16 - Found 16-bit register for signal . - Found 16x24-bit multiplier for signal created at line 69. - Summary: - inferred 1 Multiplier(s). - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd". - g_pipeline_regs = 8 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - Set property "syn_noprune = true". - Set property "optimize_primitives = false". - Set property "dont_touch = true". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 538: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 553: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 553: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 567: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 582: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 597: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 612: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 627: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 627: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 641: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 641: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 655: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 670: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 670: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 684: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 684: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 698: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 728: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 728: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 742: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 1 - log_2_period = 1 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" line 254: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 1112 - log_2_period = 11 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 11-bit register for signal . - Found 11-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 11 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 1390000 - log_2_period = 21 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 21-bit register for signal . - Found 21-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 21 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 2 - log_2_period = 2 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 1-bit register for signal . - Found 1-bit adder for signal > created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 1 - init_value = "0000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 1 - init_value = "0000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 2224 - log_2_period = 12 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 12-bit register for signal . - Found 12-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 22240000 - log_2_period = 25 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 25-bit register for signal . - Found 25-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 222400000 - log_2_period = 28 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 28-bit register for signal . - Found 28-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 28 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 2500 - log_2_period = 12 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 12-bit register for signal . - Found 12-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 2780000 - log_2_period = 22 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 22-bit register for signal . - Found 22-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 22 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 35 - log_2_period = 6 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 6-bit register for signal . - Found 6-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 5000 - log_2_period = 13 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 13-bit register for signal . - Found 13-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 13 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 556 - log_2_period = 10 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 10-bit register for signal . - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 10 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 5560000 - log_2_period = 23 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 23-bit register for signal . - Found 23-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 23 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 55600000 - log_2_period = 26 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 26-bit register for signal . - Found 26-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 26 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 70 - log_2_period = 7 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "syn_keep = true" for signal . - Set property "KEEP = TRUE" for signal . -WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128175: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - init_value = "000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - init_index = 2 - init_value = "000000000000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - init_index = 2 - init_value = "000000000000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 136882: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128615: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128615: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128627: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128627: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128639: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128651: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 128651: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_config_tdata_net<63:62>', unconnected in block 'xldds_compiler_6ef2934d572b7cd1757292caa5710be5', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 's_axis_config_tdata_net<31:30>', unconnected in block 'xldds_compiler_6ef2934d572b7cd1757292caa5710be5', is tied to its initial value (00). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - q_width = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit adder for signal > created at line 124544. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 1 - init_value = "0" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 2 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - init_index = 2 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - sampling_ratio = 2 - latency = 0 - copy_samples = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 124674: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137538: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137602: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137764: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137796: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137828: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137966: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 137998: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 138030: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 138385: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 138691: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 138723: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 138737: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - core_name0 = "addsb_11_0_26986301a9f671cd" - a_width = 24 - a_bin_pt = 22 - a_arith = 2 - c_in_width = 16 - c_in_bin_pt = 4 - c_in_arith = 1 - c_out_width = 16 - c_out_bin_pt = 4 - c_out_arith = 1 - b_width = 24 - b_bin_pt = 22 - b_arith = 2 - s_width = 25 - s_bin_pt = 22 - s_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - full_s_width = 25 - full_s_arith = 2 - mode = 1 - extra_registers = 0 - latency = 0 - quantization = 1 - overflow = 1 - c_latency = 0 - c_output_width = 25 - c_has_c_in = 0 - c_has_c_out = 0 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 1 - dout_width = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - dout_width = 25 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 1 - q_width = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 26 - din_bin_pt = 22 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 21 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 26 - din_bin_pt = 22 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 21 - dout_arith = 2 - quantization = 2 - overflow = 2 - Found 27-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - init_value = "0000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 25 - init_index = 2 - init_value = "0000000000000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 25 - init_index = 2 - init_value = "0000000000000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - latency = 56 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - latency = 56 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - latency = 17 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - latency = 5 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 56 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 56 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 17 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 5 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - core_name0 = "addsb_11_0_8b0747970e52f130" - a_width = 25 - a_bin_pt = 22 - a_arith = 2 - c_in_width = 16 - c_in_bin_pt = 4 - c_in_arith = 1 - c_out_width = 16 - c_out_bin_pt = 4 - c_out_arith = 1 - b_width = 25 - b_bin_pt = 22 - b_arith = 2 - s_width = 26 - s_bin_pt = 22 - s_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - full_s_width = 26 - full_s_arith = 2 - mode = 1 - extra_registers = 0 - latency = 0 - quantization = 1 - overflow = 1 - c_latency = 0 - c_output_width = 26 - c_has_c_in = 0 - c_has_c_out = 0 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 1112 - phase = 1111 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2224 - phase = 2223 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 25 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 25 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 1 - d_bin_pt = 0 - d_arith = 1 - q_width = 1 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2224 - phase = 2223 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2224 - phase = 2223 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_dividend_tdata_net<31:26>', unconnected in block 'xldivider_generator_ee95dc360423b121d9ecd626691cc2ae', is tied to its initial value (000000). -WARNING:Xst:2935 - Signal 's_axis_divisor_tdata_net<31:26>', unconnected in block 'xldivider_generator_ee95dc360423b121d9ecd626691cc2ae', is tied to its initial value (000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - init_value = "00000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - init_index = 2 - init_value = "00000000000000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - init_index = 2 - init_value = "00000000000000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 26-bit comparator greater for signal created at line 127597 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - core_name0 = "addsb_11_0_239e4f614ba09ab1" - a_width = 25 - a_bin_pt = 22 - a_arith = 2 - c_in_width = 16 - c_in_bin_pt = 4 - c_in_arith = 1 - c_out_width = 16 - c_out_bin_pt = 4 - c_out_arith = 1 - b_width = 25 - b_bin_pt = 22 - b_arith = 2 - s_width = 26 - s_bin_pt = 22 - s_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - full_s_width = 26 - full_s_arith = 2 - mode = 1 - extra_registers = 0 - latency = 0 - quantization = 1 - overflow = 1 - c_latency = 0 - c_output_width = 26 - c_has_c_in = 0 - c_has_c_out = 0 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139451: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139483: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139515: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139677: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139709: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139741: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139879: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139911: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 139943: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140190: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140496: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140528: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140542: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 5000 - phase = 4999 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 1 - d_bin_pt = 0 - d_arith = 1 - q_width = 1 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 1 - d_bin_pt = 0 - d_arith = 1 - q_width = 1 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 5000 - phase = 4999 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 5000 - phase = 4999 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2500 - phase = 2499 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140894: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140926: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 140958: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141120: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141184: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141322: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141354: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141386: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 141741: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 142047: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 142079: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 142093: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 35 - phase = 34 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 70 - phase = 69 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 1 - d_bin_pt = 0 - d_arith = 1 - q_width = 1 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 70 - phase = 69 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 70 - phase = 69 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_dividend_tdata_net<31:26>', unconnected in block 'xldivider_generator_f42228f055beed40ccf45b1ffc83de1a', is tied to its initial value (000000). -WARNING:Xst:2935 - Signal 's_axis_divisor_tdata_net<31:26>', unconnected in block 'xldivider_generator_f42228f055beed40ccf45b1ffc83de1a', is tied to its initial value (000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129717: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129717: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129717: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129717: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129717: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129732: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129732: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129732: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129732: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 129732: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 80 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 80 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 1 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 80 - din_bin_pt = 77 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 23 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 80 - din_bin_pt = 77 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 23 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 28-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 2-bit comparator equal for signal created at line 125460 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 23 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 23 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 26-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2 - phase = 1 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit comparator equal for signal created at line 125036 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_cartesian_tdata_net<63:57>', unconnected in block 'xlcordic_67422259e33cafe86cb2beaf1e4ed91a', is tied to its initial value (0000000). -WARNING:Xst:2935 - Signal 's_axis_cartesian_tdata_net<31:25>', unconnected in block 'xlcordic_67422259e33cafe86cb2beaf1e4ed91a', is tied to its initial value (0000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 21 - d_arith = 2 - q_width = 24 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2 - phase = 1 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130341: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130341: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130341: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130341: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130341: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130356: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130356: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130356: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130356: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 130356: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - new_msb = 49 - new_lsb = 24 - x_width = 50 - y_width = 26 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 9 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 9 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 1 - latency = 9 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - core_name0 = "mult_11_2_6d8e463c710483da" - a_width = 25 - a_bin_pt = 24 - a_arith = 2 - b_width = 25 - b_bin_pt = 0 - b_arith = 2 - p_width = 50 - p_bin_pt = 24 - p_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - quantization = 1 - overflow = 1 - extra_registers = 0 - c_a_width = 25 - c_b_width = 25 - c_type = 0 - c_a_type = 0 - c_b_type = 0 - c_pipelined = 1 - c_baat = 25 - multsign = 2 - c_output_width = 50 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - core_name0 = "mult_11_2_6d8e463c710483da" - a_width = 25 - a_bin_pt = 21 - a_arith = 2 - b_width = 25 - b_bin_pt = 23 - b_arith = 2 - p_width = 50 - p_bin_pt = 44 - p_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - quantization = 1 - overflow = 1 - extra_registers = 0 - c_a_width = 25 - c_b_width = 25 - c_type = 0 - c_a_type = 0 - c_b_type = 0 - c_pipelined = 1 - c_baat = 25 - multsign = 2 - c_output_width = 50 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 24 - din_bin_pt = 19 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 1 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 24 - din_bin_pt = 19 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 1 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 133602: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 133622: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 133622: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 133622: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 133622: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 133640: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 22 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 22 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 27-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 21 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 21 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 28-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - latency = 3 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - latency = 3 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - latency = 3 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 3 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 3 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 3 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - latency = 1 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 2 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 2 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 24 - latency = 2 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 25 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 25 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 86 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 86 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 86 - din_bin_pt = 83 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 86 - din_bin_pt = 83 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 27-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 2 - init_value = "00" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - init_index = 2 - init_value = "00" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 2 - init_index = 2 - init_value = "00" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 2-bit comparator equal for signal created at line 126228 - Summary: - inferred 4 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4 - phase = 3 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 2-bit comparator equal for signal created at line 126176 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 142736: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 26 - din_bin_pt = 24 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 24 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 26 - din_bin_pt = 24 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 24 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 28-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 's_axis_data_tdata_net<31:25>', unconnected in block 'xlfir_compiler_45bf4b3837d8237712f93dc8ae18a85b', is tied to its initial value (0000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 26 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 0 - d_arith = 1 - q_width = 26 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4 - phase = 3 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - din_width = 1 - din_bin_pt = 0 - din_arith = 1 - dout_width = 1 - dout_bin_pt = 0 - dout_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 1 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 16 - init_value = "0000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 16 - init_index = 2 - init_value = "0000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - width = 16 - init_index = 2 - init_value = "0000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 134886: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - new_msb = 24 - new_lsb = 1 - x_width = 25 - y_width = 24 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 135512: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - q_width = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 0 - d_arith = 1 - q_width = 26 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2224 - phase = 2223 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 0 - d_arith = 1 - q_width = 26 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2500 - phase = 2499 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 2 - d_bin_pt = 0 - d_arith = 1 - q_width = 2 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2224 - phase = 2223 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 2 - d_bin_pt = 0 - d_arith = 1 - q_width = 2 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2500 - phase = 2499 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 26-bit 4-to-1 multiplexer for signal created at line 127223. - Summary: - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - core_name0 = "cntr_11_0_3166d4cc5b09c744" - op_width = 2 - op_arith = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 0 - d_arith = 1 - q_width = 26 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - sampling_ratio = 2 - latency = 0 - copy_samples = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" line 124674: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 2 - d_bin_pt = 0 - d_arith = 1 - q_width = 2 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 556 - phase = 555 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 556 - phase = 555 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 24-bit 4-to-1 multiplexer for signal created at line 127074. - Summary: - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 11120000 - log_2_period = 24 - pipeline_regs = 8 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 24-bit register for signal . - Found 24-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 24 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd". - period = 111200000 - log_2_period = 24 - pipeline_regs = 8 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 27-bit register for signal . - Found 27-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_counters.vhd". - g_cntr_size = 16 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_counters_single.vhd". - g_cntr_size = 16 - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 16-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd". - g_data_width = 96 - g_size = 16 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd". - g_data_width = 96 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 2 - g_almost_full_threshold = 14 - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16x96-bit dual-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit subtractor for signal created at line 245. - Found 5-bit subtractor for signal created at line 259. - Found 5-bit comparator equal for signal created at line 209 - Found 5-bit comparator equal for signal created at line 209 - Found 4-bit comparator equal for signal created at line 219 - Found 4-bit comparator equal for signal created at line 223 - Found 5-bit comparator lessequal for signal created at line 249 - Found 5-bit comparator lessequal for signal created at line 263 - Summary: - inferred 1 RAM(s). - inferred 4 Adder/Subtractor(s). - inferred 150 D-type flip-flop(s). - inferred 6 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd". - g_data_width = 192 - g_size = 16 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd". - g_data_width = 192 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 2 - g_almost_full_threshold = 14 - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16x192-bit dual-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 192-bit register for signal . - Found 1-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit subtractor for signal created at line 245. - Found 5-bit subtractor for signal created at line 259. - Found 5-bit comparator equal for signal created at line 209 - Found 5-bit comparator equal for signal created at line 209 - Found 4-bit comparator equal for signal created at line 219 - Found 4-bit comparator equal for signal created at line 223 - Found 5-bit comparator lessequal for signal created at line 249 - Found 5-bit comparator lessequal for signal created at line 263 - Summary: - inferred 1 RAM(s). - inferred 4 Adder/Subtractor(s). - inferred 246 D-type flip-flop(s). - inferred 6 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd". - g_data_width = 104 - g_size = 16 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" line 58: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd". - g_data_width = 104 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 2 - g_almost_full_threshold = 14 - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16x104-bit dual-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 104-bit register for signal . - Found 1-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit subtractor for signal created at line 245. - Found 5-bit subtractor for signal created at line 259. - Found 5-bit comparator equal for signal created at line 209 - Found 5-bit comparator equal for signal created at line 209 - Found 4-bit comparator equal for signal created at line 219 - Found 4-bit comparator equal for signal created at line 223 - Found 5-bit comparator lessequal for signal created at line 249 - Found 5-bit comparator lessequal for signal created at line 263 - Summary: - inferred 1 RAM(s). - inferred 4 Adder/Subtractor(s). - inferred 158 D-type flip-flop(s). - inferred 6 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 84: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 119: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 158: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 4 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_sdb_addr = "00000000000000000000010000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000011111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_4', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_address = ("00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000011000000000","00000000000000000000011111110000","00000000000000000000011100000000","00000000000000000000011100000000","00000000000000000000011100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 44 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_4389_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_4399_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal created at line 68. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 24-bit register for signal . - Found 24-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 90 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_acq_addr_width = 28 - g_acq_num_channels = 8 - g_acq_channels = (("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("01000000")) - g_ddr_payload_width = 256 - g_ddr_dq_width = 64 - g_ddr_addr_width = 28 - g_multishot_ram_size = 2048 - g_fifo_fc_size = 256 - g_sim_readback = false -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_acq_addr_width = 28 - g_acq_num_channels = 8 - g_acq_channels = (("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("01000000")) - g_ddr_payload_width = 256 - g_ddr_dq_width = 64 - g_ddr_addr_width = 28 - g_multishot_ram_size = 2048 - g_fifo_fc_size = 256 - g_sim_readback = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 739: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 739: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 873: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit adder for signal created at line 645. - Found 1-bit 8-to-1 multiplexer for signal created at line 496. - Found 1-bit 8-to-1 multiplexer for signal created at line 497. - Found 128-bit 8-to-1 multiplexer for signal created at line 502. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 51 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 14-bit register for signal . - Found 15-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 10-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 564 D-type flip-flop(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 30 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | fs_clk_i (rising_edge) | - | Reset | fs_rst_n_i_INV_4551_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 1241. - Found 16-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 123 D-type flip-flop(s). - inferred 7 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd". - g_data_width = 128 - g_multishot_ram_size = 2048 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. - Found 11-bit register for signal . - Found 11-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 11-bit adder for signal created at line 1241. - Found 11-bit adder for signal created at line 1241. - Found 11-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 200. - Found 11-bit comparator equal for signal created at line 202 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 46 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 7 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 128 - g_size = 2048 - g_with_byte_enable = false - g_addr_conflict_resolution = "read_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 128 - g_size = 2048 - g_with_byte_enable = false - g_addr_conflict_resolution = "read_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 2048x128-bit dual-port RAM for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 256 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd". - g_data_width = 128 - g_addr_width = 28 - g_fifo_size = 256 - g_fc_pipe_size = 4 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 368: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 368: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 380: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 428: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 452: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 474: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 128-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 32-bit comparator not equal for signal created at line 280 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 227 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 128 - g_size = 256 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = true - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd". - g_data_width = 128 - g_size = 256 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = true - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 256x128-bit dual-port RAM for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 128-bit register for signal . - Found 9-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 248. - Found 9-bit subtractor for signal > created at line 262. - Found 9-bit comparator equal for signal created at line 209 - Found 9-bit comparator equal for signal created at line 209 - Found 8-bit comparator equal for signal created at line 219 - Found 8-bit comparator equal for signal created at line 223 - Found 9-bit comparator lessequal for signal created at line 263 - Summary: - inferred 1 RAM(s). - inferred 4 Adder/Subtractor(s). - inferred 222 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd". - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 11 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd". - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 32-bit comparator equal for signal created at line 134 - Found 16-bit comparator equal for signal created at line 191 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 98 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd". - g_data_width = 128 - g_pkt_size_width = 32 - g_addr_width = 28 - g_pipe_size = 4 - Found 32-bit register for signal . - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 128-bit register for signal . - Found 2-bit register for signal . - Found 28-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 2-bit subtractor for signal > created at line 1308. -INFO:Xst:3019 - HDL ADVISOR - 512 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 128-bit 4-to-1 multiplexer for signal created at line 388. - Found 28-bit 4-to-1 multiplexer for signal created at line 389. - Found 2-bit 4-to-1 multiplexer for signal created at line 390. - Found 1-bit 4-to-1 multiplexer for signal created at line 391. - Found 32-bit comparator equal for signal created at line 247 - Found 2-bit comparator not equal for signal created at line 408 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 869 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 19 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd". - g_acq_addr_width = 28 - g_acq_num_channels = 8 - g_acq_channels = (("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("10000000"),("01000000")) - g_ddr_payload_width = 256 - g_ddr_dq_width = 64 - g_ddr_addr_width = 28 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 545: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 637: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 637: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 637: Output port of the instance is unconnected or connected to loadless signal. - Found 16-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 28-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit subtractor for signal created at line 399. - Found 4-bit adder for signal created at line 438. - Found 4-bit adder for signal created at line 1241. - Found 28-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 418. - Found 9-bit subtractor for signal > created at line 427. - Found 9-bit subtractor for signal > created at line 438. - Found 8x3-bit Read Only RAM for signal - Found 8x2-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal > - Found 32-bit 3-to-1 multiplexer for signal created at line 329. - Found 3-bit 3-to-1 multiplexer for signal created at line 419. - Found 1-bit 4-to-1 multiplexer for signal created at line 509. - Found 5-bit comparator equal for signal created at line 399 - Summary: - inferred 3 RAM(s). - inferred 7 Adder/Subtractor(s). - inferred 345 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 263 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd". - g_data_width = 1 - g_pkt_size_width = 32 - g_addr_width = 28 - g_pipe_size = 4 - Found 32-bit register for signal . - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 28-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 2-bit subtractor for signal > created at line 1308. - Found 28-bit 4-to-1 multiplexer for signal created at line 389. - Found 2-bit 4-to-1 multiplexer for signal created at line 390. - Found 1-bit 4-to-1 multiplexer for signal created at line 391. - Found 32-bit comparator equal for signal created at line 247 - Found 2-bit comparator equal for signal <_n0301> created at line 408 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 229 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 14 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd". - g_data_width = 288 - g_pkt_size_width = 32 - g_addr_width = 1 - g_pipe_size = 4 - Found 32-bit register for signal . - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 288-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 2-bit subtractor for signal > created at line 1308. -INFO:Xst:3019 - HDL ADVISOR - 1152 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 2-bit 4-to-1 multiplexer for signal created at line 390. - Found 1-bit 4-to-1 multiplexer for signal created at line 391. - Found 32-bit comparator equal for signal created at line 247 - Found 2-bit comparator equal for signal <_n0301> created at line 408 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 1529 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 50 - 128x32-bit single-port Read Only RAM : 2 - 16x1-bit single-port Read Only RAM : 1 - 16x104-bit dual-port RAM : 4 - 16x192-bit dual-port RAM : 3 - 16x32-bit dual-port RAM : 1 - 16x96-bit dual-port RAM : 6 - 2048x128-bit dual-port RAM : 2 - 22528x32-bit dual-port RAM : 1 - 256x128-bit dual-port RAM : 1 - 256x32-bit dual-port RAM : 4 - 256x32-bit single-port Read Only RAM : 1 - 32x8-bit single-port RAM : 1 - 32x8-bit single-port Read Only RAM : 1 - 4096x32-bit dual-port RAM : 1 - 4x2-bit single-port Read Only RAM : 2 - 4x3-bit single-port Read Only RAM : 1 - 4x6-bit single-port Read Only RAM : 1 - 501x24-bit dual-port RAM : 1 - 64x32-bit single-port Read Only RAM : 1 - 8x1-bit single-port Read Only RAM : 11 - 8x18-bit single-port Read Only RAM : 2 - 8x2-bit single-port Read Only RAM : 1 - 8x3-bit single-port Read Only RAM : 1 -# Multipliers : 7 - 24x16-bit multiplier : 4 - 3x3-bit multiplier : 2 - 4x3-bit multiplier : 1 -# Adders/Subtractors : 598 - 1-bit adder : 18 - 10-bit adder : 8 - 10-bit addsub : 1 - 10-bit subtractor : 4 - 11-bit adder : 5 - 11-bit addsub : 1 - 11-bit subtractor : 2 - 12-bit adder : 12 - 12-bit subtractor : 1 - 13-bit adder : 5 - 13-bit subtractor : 2 - 14-bit subtractor : 4 - 15-bit subtractor : 3 - 16-bit adder : 34 - 16-bit addsub : 2 - 16-bit subtractor : 10 - 17-bit adder : 10 - 17-bit subtractor : 1 - 18-bit subtractor : 2 - 2-bit adder : 48 - 2-bit addsub : 3 - 2-bit subtractor : 42 - 20-bit subtractor : 1 - 21-bit adder : 2 - 22-bit adder : 3 - 23-bit adder : 2 - 24-bit adder : 2 - 25-bit adder : 2 - 25-bit subtractor : 1 - 26-bit adder : 8 - 27-bit adder : 6 - 28-bit adder : 10 - 29-bit adder : 1 - 3-bit adder : 19 - 3-bit subtractor : 14 - 30-bit adder : 5 - 30-bit subtractor : 2 - 32-bit adder : 19 - 32-bit subtractor : 9 - 4-bit adder : 43 - 4-bit subtractor : 5 - 48-bit adder : 12 - 48-bit subtractor : 2 - 5-bit adder : 45 - 5-bit addsub : 11 - 5-bit subtractor : 41 - 57-bit adder : 2 - 6-bit adder : 27 - 6-bit addsub : 2 - 6-bit subtractor : 7 - 64-bit subtractor : 2 - 7-bit adder : 10 - 7-bit subtractor : 2 - 8-bit adder : 30 - 8-bit addsub : 3 - 8-bit subtractor : 9 - 9-bit adder : 6 - 9-bit subtractor : 15 -# Registers : 6623 - 1-bit register : 4689 - 10-bit register : 22 - 104-bit register : 8 - 11-bit register : 11 - 12-bit register : 13 - 128-bit register : 22 - 13-bit register : 22 - 14-bit register : 11 - 15-bit register : 5 - 16-bit register : 151 - 160-bit register : 3 - 17-bit register : 13 - 192-bit register : 6 - 2-bit register : 212 - 20-bit register : 2 - 21-bit register : 2 - 22-bit register : 3 - 23-bit register : 2 - 24-bit register : 5 - 25-bit register : 10 - 256-bit register : 9 - 26-bit register : 8 - 27-bit register : 1 - 28-bit register : 18 - 288-bit register : 5 - 29-bit register : 1 - 3-bit register : 85 - 30-bit register : 23 - 31-bit register : 2 - 32-bit register : 107 - 33-bit register : 4 - 36-bit register : 71 - 4-bit register : 386 - 40-bit register : 6 - 48-bit register : 8 - 5-bit register : 228 - 55-bit register : 1 - 6-bit register : 174 - 64-bit register : 66 - 66-bit register : 2 - 7-bit register : 19 - 72-bit register : 5 - 8-bit register : 142 - 9-bit register : 27 - 96-bit register : 13 -# Comparators : 334 - 1-bit comparator equal : 47 - 10-bit comparator equal : 2 - 11-bit comparator equal : 6 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 2 - 12-bit comparator lessequal : 3 - 14-bit comparator equal : 5 - 15-bit comparator greater : 2 - 16-bit comparator equal : 10 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 2-bit comparator equal : 27 - 2-bit comparator greater : 7 - 2-bit comparator not equal : 1 - 26-bit comparator greater : 3 - 3-bit comparator equal : 5 - 3-bit comparator greater : 3 - 3-bit comparator lessequal : 5 - 3-bit comparator not equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 32-bit comparator not equal : 1 - 4-bit comparator equal : 36 - 4-bit comparator greater : 13 - 4-bit comparator lessequal : 7 - 5-bit comparator equal : 28 - 5-bit comparator greater : 7 - 5-bit comparator lessequal : 30 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 6-bit comparator greater : 4 - 6-bit comparator lessequal : 5 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 20 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 5 - 9-bit comparator equal : 2 - 9-bit comparator greater : 2 - 9-bit comparator lessequal : 2 - 9-bit comparator not equal : 2 -# Multiplexers : 8724 - 1-bit 128-to-1 multiplexer : 3 - 1-bit 16-to-1 multiplexer : 6 - 1-bit 2-to-1 multiplexer : 6734 - 1-bit 3-to-1 multiplexer : 7 - 1-bit 4-to-1 multiplexer : 16 - 1-bit 6-to-1 multiplexer : 1 - 1-bit 64-to-1 multiplexer : 32 - 1-bit 8-to-1 multiplexer : 300 - 10-bit 2-to-1 multiplexer : 40 - 11-bit 2-to-1 multiplexer : 4 - 12-bit 2-to-1 multiplexer : 4 - 128-bit 2-to-1 multiplexer : 16 - 128-bit 4-to-1 multiplexer : 1 - 128-bit 8-to-1 multiplexer : 1 - 13-bit 2-to-1 multiplexer : 11 - 14-bit 2-to-1 multiplexer : 18 - 15-bit 2-to-1 multiplexer : 4 - 16-bit 2-to-1 multiplexer : 97 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 127 - 2-bit 4-to-1 multiplexer : 3 - 20-bit 2-to-1 multiplexer : 1 - 21-bit 2-to-1 multiplexer : 12 - 22-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 12 - 24-bit 4-to-1 multiplexer : 1 - 25-bit 2-to-1 multiplexer : 4 - 26-bit 4-to-1 multiplexer : 1 - 28-bit 2-to-1 multiplexer : 15 - 28-bit 4-to-1 multiplexer : 2 - 29-bit 2-to-1 multiplexer : 2 - 3-bit 2-to-1 multiplexer : 106 - 3-bit 3-to-1 multiplexer : 2 - 30-bit 2-to-1 multiplexer : 7 - 31-bit 2-to-1 multiplexer : 1 - 32-bit 12-to-1 multiplexer : 1 - 32-bit 2-to-1 multiplexer : 186 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 1 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 33-bit 2-to-1 multiplexer : 6 - 36-bit 2-to-1 multiplexer : 133 - 4-bit 2-to-1 multiplexer : 105 - 4-bit 4-to-1 multiplexer : 144 - 4-bit 6-to-1 multiplexer : 3 - 40-bit 2-to-1 multiplexer : 7 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 48 - 5-bit 8-to-1 multiplexer : 1 - 6-bit 2-to-1 multiplexer : 90 - 64-bit 2-to-1 multiplexer : 117 - 7-bit 2-to-1 multiplexer : 7 - 72-bit 2-to-1 multiplexer : 1 - 8-bit 2-to-1 multiplexer : 245 - 8-bit 4-to-1 multiplexer : 2 - 8-bit 8-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 15 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 7 - 1-bit shifter logical left : 7 -# Tristates : 1029 - 1-bit tristate buffer : 1027 - 8-bit tristate buffer : 2 -# FSMs : 63 -# Xors : 396 - 1-bit xor2 : 190 - 1-bit xor3 : 66 - 1-bit xor4 : 2 - 32-bit xor2 : 110 - 4-bit xor2 : 26 - 8-bit xor2 : 2 - -========================================================================= -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. -WARNING:Xst:638 - in unit xlclockdriver_2 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_3 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_4 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_5 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_6 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_7 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_8 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_9 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_10 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_11 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_12 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_13 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_14 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_15 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_16 Conflict on KEEP property on signal ce_vec_logic<8> and ce_vec<8> ce_vec<8> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_17 Conflict on KEEP property on signal ce_vec_logic<8> and ce_vec<8> ce_vec<8> signal will be lost. -WARNING:Xst:638 - in unit wb_position_calc_core Conflict on KEEP property on signal sys_clr and sys_clr2x sys_clr2x signal will be lost. - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -WARNING:Xst:453 - Model 'SRLC32E' has different characteristics in destination library, some ports are missing: - Q31 -Reading core <../../../platform/virtex6/ip_cores/dds_adc_input.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_16x10_DSP.ngc>. -Reading core <../../../platform/virtex6/chipscope/ila/chipscope_ila_8192_5_port.ngc>. -Reading core <../../../platform/virtex6/chipscope/ila/chipscope_ila_1024.ngc>. -Reading core <../../../platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.ngc>. -Reading core <../../../platform/virtex6/chipscope/vio/chipscope_vio_256.ngc>. -Reading core <../../../ip_cores/pcie/ml605/prime_FIFO_plain.ngc>. -Reading core <../../../ip_cores/pcie/ml605/sfifo_15x128.ngc>. -Reading core <../../../ip_cores/pcie/ml605/mbuf_128x72.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_u16x16_DSP.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/xlpersistentdff.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_26986301a9f671cd.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_e1825854b6ed410d.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_8b0747970e52f130.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_239e4f614ba09ab1.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_f359164f94f65852.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dds_cmplr_v5_0_757016b8a434f5d8.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/mult_11_2_6d8e463c710483da.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_ef8269b30b0e0deb.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_8b75732071ae5375.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/crdc_v5_0_19fb63dead3076ad.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cmpy_v5_0_fc1d91881e8e8ae6.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_0c61ac74cf3e5cc7.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_0f9a053cdbbdc75e.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_b5b882c8c4a87b90.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_d5f4b3c608d95215.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_8eb87633bf98cbda.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_fe47fe6ccabc2305.ngc>. -Reading core <../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cntr_11_0_3166d4cc5b09c744.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance blk0000033b in unit blk0000033b of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000033c in unit blk0000033c of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000033d in unit blk0000033d of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000033e in unit blk0000033e of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000033f in unit blk0000033f of type DSP48E has been replaced by DSP48E1 -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000033b in unit blk0000033b is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000033c in unit blk0000033c is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000033d in unit blk0000033d is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000033e in unit blk0000033e is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000033f in unit blk0000033f is not supported -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 21 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 21 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 14 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 12 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 34 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 18-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 3-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM > will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . - The following adders/subtractors are grouped into adder tree : - in block , in block , in block . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 6-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4096-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 4096-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 96-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 96-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | enB | connected to signal | high | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 192-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 192-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | enB | connected to signal | high | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 104-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 104-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | enB | connected to signal | high | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 128-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 128-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | enB | connected to signal | high | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 501-word x 24-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 501-word x 24-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 3-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 8-bit | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 8-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 64-word x 32-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 50 - 128x32-bit single-port block Read Only RAM : 2 - 16x1-bit single-port distributed Read Only RAM : 1 - 16x104-bit dual-port block RAM : 4 - 16x192-bit dual-port block RAM : 3 - 16x32-bit dual-port block RAM : 1 - 16x96-bit dual-port block RAM : 6 - 2048x128-bit dual-port block RAM : 2 - 22528x32-bit dual-port block RAM : 1 - 256x128-bit dual-port block RAM : 1 - 256x32-bit dual-port block RAM : 3 - 256x32-bit single-port block RAM : 1 - 256x32-bit single-port block Read Only RAM : 1 - 32x8-bit single-port distributed RAM : 1 - 32x8-bit single-port distributed Read Only RAM : 1 - 4096x32-bit dual-port block RAM : 1 - 4x2-bit single-port distributed Read Only RAM : 2 - 4x3-bit single-port distributed Read Only RAM : 1 - 4x6-bit single-port distributed Read Only RAM : 1 - 501x24-bit dual-port block RAM : 1 - 64x32-bit single-port distributed Read Only RAM : 1 - 8x1-bit single-port distributed Read Only RAM : 11 - 8x18-bit single-port distributed Read Only RAM : 2 - 8x2-bit single-port distributed Read Only RAM : 1 - 8x3-bit single-port distributed Read Only RAM : 1 -# Multipliers : 7 - 24x16-bit multiplier : 4 - 3x3-bit multiplier : 2 - 4x3-bit multiplier : 1 -# Adders/Subtractors : 356 - 1-bit adder : 9 - 1-bit subtractor : 5 - 10-bit adder : 4 - 10-bit addsub : 1 - 10-bit subtractor : 4 - 11-bit adder : 1 - 11-bit addsub : 1 - 11-bit subtractor : 2 - 12-bit adder : 5 - 12-bit subtractor : 1 - 13-bit adder : 2 - 13-bit subtractor : 2 - 14-bit adder : 1 - 14-bit subtractor : 3 - 16-bit adder : 13 - 16-bit addsub : 2 - 16-bit subtractor : 4 - 17-bit adder : 9 - 17-bit subtractor : 3 - 2-bit adder : 16 - 2-bit adder carry in : 1 - 2-bit subtractor : 26 - 22-bit adder : 1 - 24-bit adder : 7 - 25-bit adder : 5 - 26-bit adder : 2 - 27-bit adder : 3 - 28-bit adder : 2 - 3-bit adder : 4 - 3-bit subtractor : 12 - 30-bit adder : 3 - 30-bit subtractor : 2 - 32-bit adder : 10 - 32-bit subtractor : 9 - 4-bit adder : 11 - 4-bit subtractor : 4 - 48-bit adder : 12 - 48-bit subtractor : 2 - 5-bit adder : 33 - 5-bit addsub : 3 - 5-bit subtractor : 39 - 57-bit adder : 2 - 6-bit adder : 25 - 6-bit adder carry in : 1 - 6-bit addsub : 1 - 6-bit subtractor : 5 - 64-bit subtractor : 2 - 7-bit adder : 4 - 7-bit subtractor : 3 - 8-bit adder : 16 - 8-bit subtractor : 3 - 9-bit adder : 5 - 9-bit subtractor : 10 -# Adder Trees : 1 - 2-bit / 4-inputs adder tree : 1 -# Counters : 259 - 1-bit down counter : 4 - 1-bit up counter : 9 - 10-bit up counter : 4 - 11-bit up counter : 3 - 12-bit up counter : 7 - 13-bit up counter : 2 - 15-bit down counter : 3 - 16-bit down counter : 6 - 16-bit up counter : 19 - 2-bit down counter : 7 - 2-bit up counter : 24 - 2-bit updown counter : 3 - 20-bit down counter : 1 - 21-bit up counter : 2 - 22-bit up counter : 2 - 23-bit up counter : 2 - 24-bit up counter : 2 - 25-bit down counter : 1 - 25-bit up counter : 2 - 26-bit up counter : 2 - 27-bit up counter : 1 - 28-bit up counter : 2 - 29-bit up counter : 1 - 3-bit down counter : 2 - 3-bit up counter : 16 - 30-bit up counter : 2 - 32-bit up counter : 9 - 4-bit down counter : 1 - 4-bit up counter : 31 - 5-bit down counter : 2 - 5-bit up counter : 42 - 5-bit updown counter : 8 - 6-bit down counter : 3 - 6-bit up counter : 3 - 6-bit updown counter : 1 - 7-bit up counter : 3 - 8-bit down counter : 4 - 8-bit up counter : 12 - 8-bit updown counter : 3 - 9-bit down counter : 5 - 9-bit up counter : 3 -# Accumulators : 8 - 11-bit up accumulator : 2 - 16-bit up accumulator : 2 - 5-bit updown loadable accumulator : 2 - 6-bit up accumulator : 1 - 6-bit up loadable accumulator : 1 -# Registers : 41337 - Flip-Flops : 41337 -# Comparators : 334 - 1-bit comparator equal : 47 - 10-bit comparator equal : 2 - 11-bit comparator equal : 6 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 2 - 12-bit comparator lessequal : 3 - 14-bit comparator equal : 5 - 15-bit comparator greater : 2 - 16-bit comparator equal : 10 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 2-bit comparator equal : 27 - 2-bit comparator greater : 7 - 2-bit comparator not equal : 1 - 26-bit comparator greater : 3 - 3-bit comparator equal : 5 - 3-bit comparator greater : 3 - 3-bit comparator lessequal : 5 - 3-bit comparator not equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 32-bit comparator not equal : 1 - 4-bit comparator equal : 36 - 4-bit comparator greater : 13 - 4-bit comparator lessequal : 7 - 5-bit comparator equal : 28 - 5-bit comparator greater : 7 - 5-bit comparator lessequal : 30 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 6-bit comparator greater : 4 - 6-bit comparator lessequal : 5 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 20 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 5 - 9-bit comparator equal : 2 - 9-bit comparator greater : 2 - 9-bit comparator lessequal : 2 - 9-bit comparator not equal : 2 -# Multiplexers : 9576 - 1-bit 12-to-1 multiplexer : 32 - 1-bit 128-to-1 multiplexer : 3 - 1-bit 16-to-1 multiplexer : 6 - 1-bit 2-to-1 multiplexer : 7456 - 1-bit 3-to-1 multiplexer : 23 - 1-bit 4-to-1 multiplexer : 304 - 1-bit 6-to-1 multiplexer : 1 - 1-bit 64-to-1 multiplexer : 32 - 1-bit 8-to-1 multiplexer : 324 - 10-bit 2-to-1 multiplexer : 37 - 11-bit 2-to-1 multiplexer : 3 - 12-bit 2-to-1 multiplexer : 3 - 128-bit 2-to-1 multiplexer : 16 - 128-bit 4-to-1 multiplexer : 1 - 128-bit 8-to-1 multiplexer : 1 - 13-bit 2-to-1 multiplexer : 11 - 14-bit 2-to-1 multiplexer : 18 - 15-bit 2-to-1 multiplexer : 2 - 16-bit 2-to-1 multiplexer : 73 - 2-bit 2-to-1 multiplexer : 117 - 2-bit 4-to-1 multiplexer : 3 - 21-bit 2-to-1 multiplexer : 12 - 22-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 11 - 24-bit 4-to-1 multiplexer : 1 - 25-bit 2-to-1 multiplexer : 3 - 26-bit 4-to-1 multiplexer : 1 - 28-bit 2-to-1 multiplexer : 15 - 28-bit 4-to-1 multiplexer : 2 - 29-bit 2-to-1 multiplexer : 1 - 3-bit 2-to-1 multiplexer : 98 - 3-bit 3-to-1 multiplexer : 2 - 30-bit 2-to-1 multiplexer : 5 - 31-bit 2-to-1 multiplexer : 1 - 32-bit 2-to-1 multiplexer : 168 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 1 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 33-bit 2-to-1 multiplexer : 6 - 36-bit 2-to-1 multiplexer : 132 - 4-bit 2-to-1 multiplexer : 86 - 4-bit 4-to-1 multiplexer : 72 - 4-bit 6-to-1 multiplexer : 3 - 40-bit 2-to-1 multiplexer : 7 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 39 - 5-bit 8-to-1 multiplexer : 1 - 6-bit 2-to-1 multiplexer : 85 - 64-bit 2-to-1 multiplexer : 112 - 7-bit 2-to-1 multiplexer : 6 - 72-bit 2-to-1 multiplexer : 1 - 8-bit 2-to-1 multiplexer : 210 - 8-bit 4-to-1 multiplexer : 2 - 9-bit 2-to-1 multiplexer : 10 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 7 - 1-bit shifter logical left : 7 -# FSMs : 63 -# Xors : 396 - 1-bit xor2 : 190 - 1-bit xor3 : 66 - 1-bit xor4 : 2 - 32-bit xor2 : 110 - 4-bit xor2 : 26 - 8-bit xor2 : 2 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - st_idle | 000 - st_start | 001 - st_read | 010 - st_write | 011 - st_ack | 100 - st_stop | 101 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 00000 - start_a | 00001 - start_b | 00010 - start_c | 00011 - start_d | 00100 - start_e | 00101 - stop_a | 00110 - stop_b | 00111 - stop_c | 01000 - stop_d | 01001 - rd_a | 01010 - rd_b | 01011 - rd_c | 01100 - rd_d | 01101 - wr_a | 01110 - wr_b | 01111 - wr_c | 10000 - wr_d | 10001 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -Optimizing FSM on signal with sequential encoding. -Optimizing FSM on signal with sequential encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 00001 | 000 - 00010 | 001 - 00100 | 010 - 01000 | 011 - 10000 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0001 | 00 - 0010 | 01 - 0100 | 11 - 1000 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0011 | 000 - 0110 | 001 - 0111 | 011 - 0001 | 010 - 1000 | 110 - 1001 | 111 - 0010 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. ----------------------------------------------------- - State | Encoding ----------------------------------------------------- - 0000000000000100000000000 | 000000000000000000001 - 0010000000000000000000000 | 000000000000000000010 - 0000100000000000000000000 | 000000000000000000100 - 0100000000000000000000000 | 000000000000000001000 - 1000000000000000000000000 | 000000000000000010000 - 0000000010000000000000000 | 000000000000000100000 - 0000000100000000000000000 | 000000000000001000000 - 0000000000000000000000010 | 000000000000010000000 - 0000001000000000000000000 | 000000000000100000000 - 0000000000000000000000001 | 000000000001000000000 - 0000000000010000000000000 | 000000000010000000000 - 0000000000000000010000000 | 000000000100000000000 - 0000010000000000000000000 | 000000001000000000000 - 0000000000000000000000100 | 000000010000000000000 - 0000000000000000000001000 | 000000100000000000000 - 0000000000000000001000000 | 000001000000000000000 - 0000000000100000000000000 | 000010000000000000000 - 0001000000000000000000000 | 000100000000000000000 - 0000000000000000100000000 | 001000000000000000000 - 0000000000000001000000000 | 010000000000000000000 - 0000000000000010000000000 | 100000000000000000000 ----------------------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. --------------------------- - State | Encoding --------------------------- - rdst_reset | 0000 - rdst_idle | 0001 - rdst_acc_req | 0010 - rdst_b4_la | 0011 - rdst_la | 0100 - rdst_cmd | 0101 - rdst_data | 0110 - rdst_wait | 0111 - rdst_last_qw | 1000 --------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------------------- - State | Encoding -------------------------------- - wrst_bram_reset | 000 - wrst_idle | 001 - wrst_acc_req | 011 - wrst_address | 010 - wrst_1st_data | 110 - wrst_1st_data_b2b | unreached - wrst_more_data | 111 - wrst_last_dw | 101 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------- - State | Encoding ------------------------- - st_reset | 000 - st_idle | 001 - st_la | 010 - st_wr_load | 011 - st_wr_send | 100 - st_rd | 101 ------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. --------------------------------- - State | Encoding --------------------------------- - reset_idle | 0000001 - reset_pulse_wc | 0000010 - reset_enable_clk | 0000100 - reset_disable_clk | 0001000 - reset_deassert_rst | 0010000 - reset_pulse_clk | 0100000 - reset_done | 1000000 --------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------------------- - State | Encoding -------------------------------------------------- - 000000 | 0000000000000000000000000000000000001 - 000001 | 0000000000000000000000000000000000010 - 000010 | 0000000000000000000000000000000000100 - 000011 | 0000000000000000000000000000000001000 - 000100 | 0000000000000000000000000000000010000 - 010110 | 0000000000000000000000000000000100000 - 000101 | 0000000000000000000000000000001000000 - 000110 | 0000000000000000000000000000010000000 - 000111 | 0000000000000000000000000000100000000 - 001000 | 0000000000000000000000000001000000000 - 001001 | 0000000000000000000000000010000000000 - 001010 | 0000000000000000000000000100000000000 - 001011 | 0000000000000000000000001000000000000 - 001100 | 0000000000000000000000010000000000000 - 001101 | 0000000000000000000000100000000000000 - 010101 | 0000000000000000000001000000000000000 - 011010 | 0000000000000000000010000000000000000 - 011001 | 0000000000000000000100000000000000000 - 001111 | 0000000000000000001000000000000000000 - 010010 | 0000000000000000010000000000000000000 - 010100 | 0000000000000000100000000000000000000 - 010011 | 0000000000000001000000000000000000000 - 010111 | 0000000000000010000000000000000000000 - 011111 | 0000000000000100000000000000000000000 - 011000 | 0000000000001000000000000000000000000 - 011011 | 0000000000010000000000000000000000000 - 011100 | 0000000000100000000000000000000000000 - 010001 | 0000000001000000000000000000000000000 - 101000 | 0000000010000000000000000000000000000 - 001110 | 0000000100000000000000000000000000000 - 100011 | 0000001000000000000000000000000000000 - 101010 | 0000010000000000000000000000000000000 - 010000 | 0000100000000000000000000000000000000 - 011110 | unreached - 100000 | 0001000000000000000000000000000000000 - 100001 | 0010000000000000000000000000000000000 - 100010 | 0100000000000000000000000000000000000 - 100101 | unreached - 100100 | unreached - 100111 | unreached - 011101 | unreached - 101001 | 1000000000000000000000000000000000000 -------------------------------------------------- -INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 0111 | 0111 - 0110 | 0110 - 0101 | 0101 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 110 | 011 - 100 | 100 - 101 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 00000 | 00000 - 00001 | 00001 - 00010 | 00010 - 00011 | 00011 - 01100 | 01100 - 01011 | 01011 - 00100 | 00100 - 00111 | 00111 - 00101 | 00101 - 01101 | 01101 - 00110 | 00110 - 01000 | 01000 - 10010 | 10010 - 01010 | 01010 - 01111 | 01111 - 01110 | 01110 - 10000 | 10000 - 01001 | 01001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0010 | 0010 - 0011 | 0011 - 0100 | 0100 - 0110 | 0110 - 0101 | 0101 - 0111 | 0111 - 1000 | 1000 - 1001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 011 | 011 - 100 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------------------- - State | Encoding -------------------------------- - st_txidle | 0000 - st_d_cmdreq | 0001 - st_d_cmdack | 0010 - st_d_header0 | 0011 - st_d_header2 | 0100 - st_d_1st_data | 0101 - st_d_payload | 0110 - st_d_payload_used | 0111 - st_d_tail | 1000 - st_d_tail_chk | 1001 - st_nd_prepare | 1010 - st_nd_header2 | 1011 - st_nd_headerlast | 1100 - st_nd_arbitration | 1101 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - st_mr_idle | 000 - st_mr_cmdlatch | 001 - st_mr_transfer | 010 - st_mr_wb_a | 011 - st_mr_ddr_a | 100 - st_mr_ddr_c | 101 - st_mr_last | 110 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------------- - State | Encoding -------------------------- - ast_reset | 00 - ast_idle | 01 - ast_readone | 10 - ast_ready | 11 -------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - tk_rst | 000 - tk_idle | 001 - tk_mwr_3hdr_c | 010 - tk_mwr_4hdr_c | 011 - tk_cpld_hdr_c | 100 - tk_body | 101 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. --------------------------- - State | Encoding --------------------------- - st_mrd_reset | 00 - st_mrd_idle | 01 - st_mrd_head2 | 11 - st_mrd_tail | 10 --------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------ - State | Encoding ------------------------------ - reqst_idle | 00 - reqst_1read | 01 - reqst_decision | 10 - reqst_nfifo_req | 11 ------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. --------------------------------------- - State | Encoding --------------------------------------- - st_mwr_reset | 0000 - st_mwr_idle | 0001 - st_mwr3_head2 | 0010 - st_mwr4_head2 | 0011 - st_mwr4_1st_data | 0100 - st_mwr_1st_data | 0101 - st_mwr_1st_data_throttle | 0110 - st_mwr_data | 0111 - st_mwr_data_throttle | 1000 --------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------- - State | Encoding -------------------------------- - intst_rst | 00001 - intst_idle | 00010 - intst_asserting | 00100 - intst_asserted | 01000 - intst_deasserting | 10000 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - toutst_idle | 00 - toutst_countup | 01 - toutst_pause | 10 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ------------------------------- - State | Encoding ------------------------------- - dmast_init | 000 - dmast_load_param | 001 - dmast_snout | 010 - dmast_stomp | 011 - dmast_body | 100 - dmast_tail | 101 - dmast_nextdex | 110 - dmast_await_dex | 111 ------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ------------------------ - State | Encoding ------------------------ - fsm_idle | 000 - fsm_busy1 | 001 - fsm_busy2 | 010 - fsm_busy3 | 011 - fsm_busy4 | 100 - fsm_busy5 | 101 - fsm_done | 110 ------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. ------------------------------ - State | Encoding ------------------------------ - reqst_idle | 00 - reqst_1read | 01 - reqst_decision | 10 - reqst_nfifo_req | 11 - reqst_quantity | unreached - reqst_fifo_req | unreached ------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------------ - State | Encoding ------------------------------------------ - st_cpld_reset | 0000 - st_cpld_idle | 0001 - st_cpl_head2 | 0010 - st_cpld_head2 | 0011 - st_cpld_afetch_special | 0100 - st_cpld_afetch_special_tail | 0101 - st_cpld_afetch | 0110 - st_cpld_afetch_throttle | 0111 - st_cpld_only_1dw | 1000 - st_cpld_1st_data | 1001 - st_cpld_1st_data_throttle | 1010 - st_cpld_data | 1011 - st_cpld_data_throttle | 1100 - st_cpld_last_data | 1101 ------------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 00000 | 00000 - 00010 | 00001 - 00001 | 00011 - 00011 | 00010 - 00100 | 00110 - 10000 | 00111 - 00101 | unreached - 00110 | 00101 - 00111 | 00100 - 01000 | 01100 - 01001 | 01101 - 01010 | 01111 - 01011 | 01110 - 01100 | 01010 - 10111 | 01011 - 10001 | 01001 - 10010 | 01000 - 10011 | 11000 - 10100 | 11001 - 10101 | 11011 - 10110 | 11010 - 11000 | 11110 - 11001 | 11111 - 11010 | 11101 - 11101 | 11100 - 11011 | 10100 - 11100 | 10101 - 11110 | 10111 - 11111 | 10110 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0010 | 0010 - 0011 | 0011 - 0100 | 0100 - 0101 | 0101 - 1000 | 1000 - 0110 | 0110 - 1001 | 1001 - 0111 | 0111 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------- - State | Encoding -------------------- - 00 | 001 - 11 | 010 - 10 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 100 | 010 - 011 | 011 - 010 | 100 - 101 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - idle | 000 - pre_trig | 001 - wait_trig | 010 - wait_trig_skip | 011 - post_trig | 100 - post_trig_skip | 101 - decr_shot | 110 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - eth | 0001 - eth_capture | 0010 - eth_chk | 0011 - ipv4 | 0100 - ipv4_capture | 0101 - ipv4_chksum | unreached - ipv4_opt | 0111 - udp | 1000 - udp_fetch_buf | 1001 - udp_capture | 1010 - chk | 1011 - done | 1100 - errors | 1101 - waits | 1110 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 000 - header | 001 - payload | 010 - padding | 011 - done | 100 - errors | 101 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------ - State | Encoding ------------------------------------ - idle | 00000 - eb_hdr_rec | 00001 - eb_hdr_proc | 00010 - eb_hdr_probe_id | 00011 - eb_hdr_probe_rdy | 00100 - cyc_hdr_rec | 00101 - cyc_hdr_read_proc | 00110 - cyc_hdr_read_get_adr | 00111 - wb_read_rdy | 01000 - wb_read | 01001 - cyc_hdr_write_proc | 01010 - cyc_hdr_write_get_adr | 01011 - wb_write_rdy | 01100 - wb_write | 01101 - wb_write_done | 01110 - cyc_done | 01111 - eb_done | 10000 - error | 10001 - error_wait | 10010 ------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------- - State | Encoding -------------------------------------- - idle | 000000000001 - eb_hdr_init | 000000000100 - eb_hdr_probe_id | 001000000000 - eb_hdr_probe_wait | 000010000000 - packet_hdr_send | 000001000000 - eb_hdr_send | 000100000000 - rdy | 000000000010 - cyc_hdr_init | 000000001000 - cyc_hdr_send | 010000000000 - base_write_adr_send | 000000010000 - data_send | 100000000000 - zero_pad_write | 000000100000 - zero_pad_wait | unreached - error | unreached -------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - calc_chksum | 0001 - wait_send_req | 0010 - prep_eth | 0011 - eth | 0100 - ipv4 | 0101 - udp | 0110 - hdr_send | 0111 - payload_send | 1000 - padding | 1001 - wait_ifgap | 1010 - error | 1011 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - addup | 001 - carries | 010 - finalise | 011 - output | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ----------------------- - State | Encoding ----------------------- - idle | 00 - init | 01 - transfer | 11 - waiting | unreached - done | 10 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - init | 001 - transfer | 010 - waiting | unreached - done | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL. - You should achieve better results by setting this init to 1. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:1901 - Instance num_brams.brams[3].ram/use_ramb36.ramb36 in unit num_brams.brams[3].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance num_brams.brams[2].ram/use_ramb36.ramb36 in unit num_brams.brams[2].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance num_brams.brams[1].ram/use_ramb36.ramb36 in unit num_brams.brams[1].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance num_brams.brams[0].ram/use_ramb36.ramb36 in unit num_brams.brams[0].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 32 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit rs232_syscon: 32 internal tristates are replaced by logic (pull-up yes): data_out<0>, data_out<10>, data_out<11>, data_out<12>, data_out<13>, data_out<14>, data_out<15>, data_out<16>, data_out<17>, data_out<18>, data_out<19>, data_out<1>, data_out<20>, data_out<21>, data_out<22>, data_out<23>, data_out<24>, data_out<25>, data_out<26>, data_out<27>, data_out<28>, data_out<29>, data_out<2>, data_out<30>, data_out<31>, data_out<3>, data_out<4>, data_out<5>, data_out<6>, data_out<7>, data_out<8>, data_out<9>. -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:638 - in unit dbe_bpm_dsp Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_dsp Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_dsp Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<71> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<70> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<70> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<70> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<69> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<69> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<69> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<71> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<71> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<70> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<70> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<69> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<69> signal will be lost. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : - - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : - - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : - -Mapping all equations... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -Annotating constraints using XCF file '/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xcf' -XCF parsing done. -Building and optimizing final netlist ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_dsp, actual ratio is 30. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches : - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches : - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches : - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches : - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/rstdiv0_sync_r_6 has been replicated 7 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/rstdiv0_sync_r_7 has been replicated 70 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 15 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_oserdes_sync_r_8 has been replicated 3 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/rst_final has been replicated 5 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 4 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/ram_init_done_r_lcl has been replicated 1 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_0 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_1 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_2 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_3 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_4 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_r_0 has been replicated 1 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_r_3 has been replicated 1 time(s) -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_3 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_2 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_1 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_0 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_7 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_6 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_5 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_4 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_3 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_2 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_1 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_0 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxEn has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxErr has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/miim1/clkgen/Mdc has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_pga_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_shdn_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_dith_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_rand_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_trigger_dir_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_trigger_term_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_vcxo_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_vcxo_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_clk_distrib_si571_oe_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_ad9510_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_ad9510_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_clk_distrib_pll_function_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_clk_distrib_clk_sel_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_eeprom_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_eeprom_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_lm75_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_lm75_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_monitor_led2_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_monitor_led3_int has been replicated 1 time(s) to handle iob=true attribute. - -Final Macro Processing ... - -Processing Unit : - Found 6-bit shift register for signal . - Found 3-bit shift register for signal . - Found 19-bit shift register for signal . - Found 16-bit shift register for signal . - Found 3-bit shift register for signal . - Found 16-bit shift register for signal . - Found 16-bit shift register for signal . - Found 16-bit shift register for signal . - Found 16-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 4-bit shift register for signal . -INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal and currently occupies 7 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -Unit processed. - -Processing Unit : - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . -Unit processed. - -Processing Unit : - Found 3-bit shift register for signal . -Unit processed. - -Processing Unit : - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 37855 - Flip-Flops : 37855 -# Shift Registers : 262 - 16-bit shift register : 5 - 19-bit shift register : 1 - 2-bit shift register : 104 - 3-bit shift register : 142 - 4-bit shift register : 1 - 5-bit shift register : 8 - 6-bit shift register : 1 - -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 6035 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly | MMCM_ADV:CLKOUT0 | 11050 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly | MMCM_ADV:CLKOUT1 | 78391 | -mrx_clk_pad_i | IBUF | 287 | -mtx_clk_pad_i | IBUF | 231 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[3].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly | BUFR | 34 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[2].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly | BUFR | 34 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly | BUFR | 34 | -cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk | MMCM_ADV:CLKOUT1 | 9029 | -cmp_bpm_pcie_ml605/cfg_err_ecrc | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_block_i) | 1 | -cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk | BUFG | 21 | -sys_clk_p_i | MMCM_ADV:CLKOUT1+MMCM_ADV:CLKOUT1 | 8156 | -cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> | BUFR | 1542 | -cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> | BUFR | 928 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/sig00000393| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/blk0000015d)| 1 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/sig000003af| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/blk00000160)| 1 | -cmp_chipscope_icon_13/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 4111 | -cmp_chipscope_icon_13/CONTROL0<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL10<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[10].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL9<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[9].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL8<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[8].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL7<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[7].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL6<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[6].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL5<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[5].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL4<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[4].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL3<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL2<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/CONTROL1<13>(cmp_chipscope_icon_13/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_13/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_13/U0/U_ICON/U_iDATA_CMD) | 1 | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -(*) These 11 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -FindSrcOfAsyncThruGates : 100 (1) -FindSrcOfAsyncThruGates : 200 (1) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_adc/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 160 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_dds_adc_input/sig00000001(cmp_dds_adc_input/blk00000001:P) | NONE(cmp_dds_adc_input/blk000002a3) | 124 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/sig00000394(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/blk0000015c:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/blk0000015d) | 124 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_dds_adc_input/sig00000002(cmp_dds_adc_input/blk00000002:G) | NONE(cmp_dds_adc_input/blk000002a3) | 72 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/sig00000393(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/blk0000015b:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015a/blk0000015d) | 72 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch0/dds_cmplr_v5_0_757016b8a434f5d8_instance/s_axis_config_tready(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch0/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000001:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch0/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch1/dds_cmplr_v5_0_757016b8a434f5d8_instance/s_axis_config_tready(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch1/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000001:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch1/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch2/dds_cmplr_v5_0_757016b8a434f5d8_instance/s_axis_config_tready(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch2/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000001:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch2/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch3/dds_cmplr_v5_0_757016b8a434f5d8_instance/s_axis_config_tready(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch3/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000001:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch3/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/sig0000037e(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk0000014a:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk0000014b) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk000002d5/blk00000318/sig00002209(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk000002d5/blk00000318/blk0000031a:P)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk00000340/blk00000383/sig00002301(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk00000340/blk00000383/blk00000385:P)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/sig00002209(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031a:P)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/sig00002301(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000385:P)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 62 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch0/dds_cmplr_v5_0_757016b8a434f5d8_instance/sig00000275(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch0/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000002:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch0/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 38 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch1/dds_cmplr_v5_0_757016b8a434f5d8_instance/sig00000275(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch1/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000002:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch1/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000324) | 38 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch2/dds_cmplr_v5_0_757016b8a434f5d8_instance/sig00000275(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch2/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000002:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch2/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 38 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch3/dds_cmplr_v5_0_757016b8a434f5d8_instance/sig00000275(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch3/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000002:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/dds_ch3/dds_cmplr_v5_0_757016b8a434f5d8_instance/blk00000323) | 38 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 36 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/sig0000037d(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk00000149:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk0000014b) | 36 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk000002d5/blk00000318/sig00002208(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk000002d5/blk00000318/blk00000319:G)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 36 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk00000340/blk00000383/sig00002300(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk00000340/blk00000383/blk00000384:G)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_8eb87633bf98cbda_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 36 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/sig00002208(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk00000319:G)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 36 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/sig00002300(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000384:G)| NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 36 | -cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G) | NONE(cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_interconnect/rom/Mram_rom1) | 30 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/sig000003af(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/blk0000015f:G) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/blk00000160) | 20 | -cmp_bpm_pcie_ml605/cfg_err_ecrc(cmp_bpm_pcie_ml605/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 16 | -cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_bpf_mix/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_fofb_amp/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_fofb_pha/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_fofb_pos/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_monit_amp/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_monit_pos/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_monit_pos_1/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_monit_pos_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)| 16 | -cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_tbt_amp/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_tbt_pha/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pha/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1024_tbt_pos/XST_VCC:P) | NONE(cmp_chipscope_ila_1024_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 16 | -cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/sig000003b0(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/blk00000161:P) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_cmplr_v6_3_d5f4b3c608d95215_instance/blk0000015e/blk00000160) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_amp/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_amp/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_amp/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_phase/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_phase/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_phase/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_pos/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_pos/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_fofb_pos/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_1_pos/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_1_pos/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_1_pos/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_amp/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_amp/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_amp/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_pos/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_pos/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_monit_pos/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_amp/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_amp/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_amp/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_phase/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_phase/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_phase/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_pos/cmp_position_calc_cdc_fifo/we_int(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_pos/cmp_position_calc_cdc_fifo/we_int1:O) | NONE(cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc_cdc_fifo_tbt_pos/cmp_position_calc_cdc_fifo/Mram_mem2) | 8 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1) | 6 | -acq_chan_array[0]_dvalid(XST_VCC:P) | NONE(cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr) | 4 | -cmp_bpm_pcie_ml605/LoopBack_BRAM_Off.DDRs_ctrl_module/u_ddr_control/DDR_pipe_write_f2m_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/LoopBack_BRAM_Off.DDRs_ctrl_module/u_ddr_control/DDR_pipe_write_f2m_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/LoopBack_BRAM_Off.DDRs_ctrl_module/u_ddr_control/DDR_pipe_write_f2m_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Downstream_DMA_Engine/DMA_DSP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Downstream_DMA_Engine/DMA_DSP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Downstream_DMA_Engine/DMA_DSP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/MRd_Channel/pioCplD_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/MRd_Channel/pioCplD_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/MRd_Channel/pioCplD_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Upstream_DMA_Engine/US_TLP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Upstream_DMA_Engine/US_TLP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Upstream_DMA_Engine/US_TLP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_15456_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_15456_o1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo) | 4 | -cmp_bpm_pcie_ml605/m_axis_rx_tkeep<0>(cmp_bpm_pcie_ml605/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync) | 2 | -cmp_bpm_pcie_ml605/pcie_core_i/phy_rdy_n_INV_547_o(cmp_bpm_pcie_ml605/pcie_core_i/phy_rdy_n_INV_547_o1_INV_0:O) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_block_i) | 2 | -cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_xhdl2_0(cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_xhdl2_0:Q) | NONE(cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync) | 2 | -cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/dpram0_wea(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/Mmux_dpram0_wea11:O) | NONE(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/cmp_multishot_dpram0/gen_single_clk.U_RAM_SC/Mram_ram8) | 2 | -cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/dpram1_wea(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/Mmux_dpram1_wea11:O) | NONE(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/cmp_multishot_dpram1/gen_single_clk.U_RAM_SC/Mram_ram8) | 2 | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 9.390ns (Maximum Frequency: 106.497MHz) - Minimum input arrival time before clock: 4.645ns - Maximum output required time after clock: 2.722ns - Maximum combinational path delay: 0.485ns -WARNING:Xst:1415 - No path found for this constraint. -WARNING:Xst:2245 - Timing constraint is not met. - -========================================================================= - -Process "Synthesize - XST" completed successfully - -Started : "Translate". -Running ngdbuild... -Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../../ip_cores/pcie/ml605 -sd ../../../platform/virtex6/chipscope/icon_1_port -sd ../../../platform/virtex6/chipscope/icon_2_port -sd ../../../platform/virtex6/chipscope/icon_4_port -sd ../../../platform/virtex6/chipscope/icon_6_port -sd ../../../platform/virtex6/chipscope/icon_7_port -sd ../../../platform/virtex6/chipscope/icon_8_port -sd ../../../platform/virtex6/chipscope/icon_13_port -sd ../../../platform/virtex6/chipscope/ila -sd ../../../platform/virtex6/chipscope/vio -sd ../../../platform/virtex6/ip_cores -sd ../../../modules/dbe_wishbone/wb_fmc150/netlist -sd ../../../ip_cores/dsp-cores/hdl/platform/virtex6 -sd ../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6 -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_core.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_dsp.ngc dbe_bpm_dsp.ngd - -Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle -ise -dd _ngo -sd ../../../ip_cores/pcie/ml605 -sd -../../../platform/virtex6/chipscope/icon_1_port -sd -../../../platform/virtex6/chipscope/icon_2_port -sd -../../../platform/virtex6/chipscope/icon_4_port -sd -../../../platform/virtex6/chipscope/icon_6_port -sd -../../../platform/virtex6/chipscope/icon_7_port -sd -../../../platform/virtex6/chipscope/icon_8_port -sd -../../../platform/virtex6/chipscope/icon_13_port -sd -../../../platform/virtex6/chipscope/ila -sd -../../../platform/virtex6/chipscope/vio -sd ../../../platform/virtex6/ip_cores --sd ../../../modules/dbe_wishbone/wb_fmc150/netlist -sd -../../../ip_cores/dsp-cores/hdl/platform/virtex6 -sd -../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6 -nt -timestamp -uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf --uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_c -ore.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_dsp.ngc dbe_bpm_dsp.ngd - -Reading NGO file -"/home/lerwys/Repos/bpm-sw/hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ngc -" ... -Loading design module "../../../ip_cores/pcie/ml605/sfifo_15x128.ngc"... -Loading design module "../../../ip_cores/pcie/ml605/mbuf_128x72.ngc"... -Loading design module "../../../ip_cores/pcie/ml605/prime_FIFO_plain.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_1 -1_0_26986301a9f671cd.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v -4_0_e1825854b6ed410d.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_1 -1_0_8b0747970e52f130.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_1 -1_0_239e4f614ba09ab1.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v -4_0_f359164f94f65852.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dds_cmp -lr_v5_0_757016b8a434f5d8.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/mult_11 -_2_6d8e463c710483da.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmpl -r_v6_3_ef8269b30b0e0deb.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmpl -r_v3_0_8b75732071ae5375.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/crdc_v5 -_0_19fb63dead3076ad.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cmpy_v5 -_0_fc1d91881e8e8ae6.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmpl -r_v6_3_0c61ac74cf3e5cc7.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmpl -r_v3_0_0f9a053cdbbdc75e.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmpl -r_v6_3_b5b882c8c4a87b90.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmpl -r_v6_3_d5f4b3c608d95215.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmpl -r_v6_3_8eb87633bf98cbda.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmpl -r_v6_3_fe47fe6ccabc2305.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cntr_11 -_0_3166d4cc5b09c744.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/xlpersi -stentdff.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_ge -nerator_virtex6_8_4_5960d79e895706a2.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_u16x16_DSP.ngc"... -Loading design module "../../../platform/virtex6/ip_cores/dds_adc_input.ngc"... -Loading design module -"../../../ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_16x10_DSP.ngc"... -Loading design module -"../../../platform/virtex6/chipscope/ila/chipscope_ila_8192_5_port.ngc"... -Loading design module -"../../../platform/virtex6/chipscope/ila/chipscope_ila_1024.ngc"... -Loading design module -"../../../platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.ngc"... -Loading design module -"../../../platform/virtex6/chipscope/vio/chipscope_vio_256.ngc"... - /dbe_bpm_dsp/cmp_chipscope_ila_adc - /dbe_bpm_dsp/cmp_chipscope_ila_1024_fofb_pha - /dbe_bpm_dsp/cmp_chipscope_ila_1024_tbt_pha - /dbe_bpm_dsp/cmp_chipscope_ila_1024_monit_pos_1 - /dbe_bpm_dsp/cmp_chipscope_ila_1024_monit_pos - /dbe_bpm_dsp/cmp_chipscope_ila_1024_monit_amp - /dbe_bpm_dsp/cmp_chipscope_ila_1024_fofb_pos - /dbe_bpm_dsp/cmp_chipscope_ila_1024_fofb_amp - /dbe_bpm_dsp/cmp_chipscope_ila_1024_tbt_pos - /dbe_bpm_dsp/cmp_chipscope_ila_1024_tbt_amp - /dbe_bpm_dsp/cmp_chipscope_ila_1024_bpf_mix - - /dbe_bpm_dsp/cmp_chipscope_vio_256_dsp_config - /dbe_bpm_dsp/cmp_chipscope_vio_256 - ------------------------------------------------ -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - ------------------------------------------------ - ------------------------------------------------ -Gathering constraint information from source properties... -Done. - -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.uc -f" ... -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_ -core.ucf" ... -Resolving constraint associations... -Checking Constraint Associations... -WARNING:ConstraintSystem - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp - .ucf(644)] was not distributed to the output pin TXOUTCLK of block - pcie_core_i/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX because the - signal path to this output pin depends upon block attribute settings. - Constraint distribution does not support attribute dependent distribution. - - - - - - - - - - - - - - -WARNING:NgdBuild:1345 - The constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp - .ucf(68)] is overridden by the constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp - .ucf(295)]. The overriden constraint usually comes from the input netlist or - ncf files. Please set XIL_NGDBUILD_CONSTR_OVERRIDE_ERROR to promote this - message to an error. -Done... - -Checking expanded design ... -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/cmp_fmc_adc_sync_ch - ains/cmp_adc_data_sync_fifo/gen_native.U_Native_FIFO/gen_fifo36.U_Wrapped_FIF - O36" of type "FIFO36E1". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_adc_data_chains - [0].gen_adc_data_chains_check.cmp_fmc_adc_data/cmp_adc_data_async_fifo/gen_na - tive.U_Native_FIFO/gen_fifo18.U_Wrapped_FIFO18" of type "FIFO18E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_adc_data_chains - [1].gen_adc_data_chains_check.cmp_fmc_adc_data/cmp_adc_data_async_fifo/gen_na - tive.U_Native_FIFO/gen_fifo18.U_Wrapped_FIFO18" of type "FIFO18E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_adc_data_chains - [2].gen_adc_data_chains_check.cmp_fmc_adc_data/cmp_adc_data_async_fifo/gen_na - tive.U_Native_FIFO/gen_fifo18.U_Wrapped_FIFO18" of type "FIFO18E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_adc_data_chains - [3].gen_adc_data_chains_check.cmp_fmc_adc_data/cmp_adc_data_async_fifo/gen_na - tive.U_Native_FIFO/gen_fifo18.U_Wrapped_FIFO18" of type "FIFO18E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v6_fifo.fblk/gextw[1].gnll_fifo. - inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1" of type "FIFO36E1". This - attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_eb_slave_core/EB/TX_FIFO/gen_native.U_Native_FIFO/gen_fifo18.U_Wrapped_F - IFO18" of type "FIFO18E1". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol - "cmp_eb_slave_core/EB/RX_FIFO/gen_native.U_Native_FIFO/gen_fifo18.U_Wrapped_F - IFO18" of type "FIFO18E1". This attribute will be ignored. -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6e8/tdm_mix_ch0_2_e932714 - 1fc/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6e8/tdm_mix_ch0_2_e932714 - 1fc/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6e8/tdm_mix_ch0_1_b9bb73d - d5f/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6e8/tdm_mix_ch0_1_b9bb73d - d5f/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch23_sine_782 - ff6a42a/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch23_sine_782 - ff6a42a/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch23_cosine_3 - 98d5cee32/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch23_cosine_3 - 98d5cee32/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch01_sine_112 - 9eb9762/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch01_sine_112 - 9eb9762/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch01_cosine_4 - b8bfc9243/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_sub_a4b6b880f6/tdm_dds_ch01_cosine_4 - b8bfc9243/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_i/m_axis_data_tuser_chan_sy - nc_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].b - it_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_i/m_axis_data_tlast_ps_net_ - synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fd - re_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/m_axis_data_tuser_chan_ou - t_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bi - t_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/m_axis_data_tuser_chan_sy - nc_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].b - it_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/m_axis_data_tlast_ps_net_ - synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fd - re_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_i/m_axis_data_tuser_chan_sy - nc_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].b - it_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_i/m_axis_data_tlast_ps_net_ - synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fd - re_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/m_axis_data_tuser_chan_ou - t_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bi - t_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/m_axis_data_tuser_chan_sy - nc_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].b - it_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/m_axis_data_tlast_ps_net_ - synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fd - re_comp' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_i_f95b8f24ad/down_sample1/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[0].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_i_f95b8f24ad/down_sample1/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[1].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_i_f95b8f24ad/down_sample1/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[2].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_i_f95b8f24ad/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[0].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_i_f95b8f24ad/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[1].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_i_f95b8f24ad/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[2].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_q_2c5e18f496/down_sample1/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[0].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_q_2c5e18f496/down_sample1/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[1].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_q_2c5e18f496/down_sample1/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[2].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_q_2c5e18f496/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[0].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_q_2c5e18f496/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[1].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer0_q_2c5e18f496/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[2].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer1_i_1afc4ccdba/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[0].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer1_i_1afc4ccdba/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[1].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer1_i_1afc4ccdba/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[2].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer1_q_ee4acbed30/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[0].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer1_q_ee4acbed30/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[1].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/mixer_a1cd828545/tddm_mixer_8537ade7b6/t - ddm_mixer1_q_ee4acbed30/down_sample2/latency_gt_0.latency_pipe/partial_one.la - st_srl17e/reg_array[2].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_pfir/m_axis_data_tdata_ps_net_synchronizer/latency_gt_0.fd_array[1] - .reg_comp/fd_prim_array[24].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/m_axis_data_tdata_ps_net_synchronizer/latency_gt_0.fd_array[1] - .reg_comp/fd_prim_array[24].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/m_axis_data_tdata_ps_net_synchronizer/latency_gt_0.fd_array[1] - .reg_comp/fd_prim_array[23].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cic/m_axis_data_tuser_chan_sync_ps_net_synchronizer_1/latency_gt_0. - fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected - output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cic/m_axis_data_tlast_ps_net_synchronizer_1/latency_gt_0.fd_array[1 - ].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/m_a - xis_data_tdata_ps_net_synchronizer/latency_gt_0.fd_array[1].reg_comp/fd_prim_ - array[25].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_1_746ecf54b0/downsample1_312d5 - 31c6b/down_sample/latency_gt_0.latency_pipe/partial_one.last_srl17e/reg_array - [25].fde_used.u2' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_1_746ecf54b0/up_sample_ch0/sel - _gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_1_746ecf54b0/up_sample_ch1/sel - _gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_1_746ecf54b0/up_sample_ch2/sel - _gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_1_746ecf54b0/up_sample_ch3/sel - _gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e38292ecb/up_sample_ch0/sel_g - en' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e38292ecb/up_sample_ch1/sel_g - en' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e38292ecb/up_sample_ch2/sel_g - en' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e38292ecb/up_sample_ch3/sel_g - en' has unconnected output pin -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "blk00000324" of type "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "blk00000324" of type "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "blk00000324" of type "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "blk00000324" of type "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/default_clock_driver_x0/xlclockdriver_1/clr_reg/latency_gt_ - 0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected - output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - efault_clock_driver/xlclockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp - /fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_chipscope_vio_256_dsp_config/U0/I_VIO/reset_f_edge/I_H2L.U_DOUT' has - unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_chipscope_vio_256/U0/I_VIO/reset_f_edge/I_H2L.U_DOUT' has unconnected - output pin -WARNING:NgdBuild:452 - logical net 'N1416' has no driver -WARNING:NgdBuild:452 - logical net 'N1417' has no driver -WARNING:NgdBuild:452 - logical net 'N1418' has no driver -WARNING:NgdBuild:452 - logical net 'N1419' has no driver -WARNING:NgdBuild:452 - logical net 'N1420' has no driver -WARNING:NgdBuild:452 - logical net 'N1421' has no driver -WARNING:NgdBuild:452 - logical net 'N1422' has no driver -WARNING:NgdBuild:452 - logical net 'N1423' has no driver -WARNING:NgdBuild:452 - logical net 'N1424' has no driver -WARNING:NgdBuild:452 - logical net 'N1425' has no driver -WARNING:NgdBuild:452 - logical net 'N1426' has no driver -WARNING:NgdBuild:452 - logical net 'N1427' has no driver -WARNING:NgdBuild:452 - logical net 'N1428' has no driver -WARNING:NgdBuild:452 - logical net 'N1429' has no driver -WARNING:NgdBuild:452 - logical net 'N1430' has no driver -WARNING:NgdBuild:452 - logical net 'N1431' has no driver -WARNING:NgdBuild:452 - logical net 'N1432' has no driver -WARNING:NgdBuild:452 - logical net 'N1433' has no driver -WARNING:NgdBuild:452 - logical net 'N1434' has no driver -WARNING:NgdBuild:452 - logical net 'N1435' has no driver -WARNING:NgdBuild:452 - logical net 'N1436' has no driver -WARNING:NgdBuild:452 - logical net 'N1437' has no driver -WARNING:NgdBuild:452 - logical net 'N1438' has no driver -WARNING:NgdBuild:452 - logical net 'N1439' has no driver -WARNING:NgdBuild:452 - logical net 'N1440' has no driver -WARNING:NgdBuild:452 - logical net 'N1441' has no driver -WARNING:NgdBuild:452 - logical net 'N1442' has no driver -WARNING:NgdBuild:452 - logical net 'N1443' has no driver -WARNING:NgdBuild:452 - logical net 'N1444' has no driver -WARNING:NgdBuild:452 - logical net 'N1445' has no driver -WARNING:NgdBuild:452 - logical net 'N1446' has no driver -WARNING:NgdBuild:452 - logical net 'N1447' has no driver -WARNING:NgdBuild:452 - logical net 'N1448' has no driver -WARNING:NgdBuild:452 - logical net 'N1449' has no driver -WARNING:NgdBuild:452 - logical net 'N1450' has no driver -WARNING:NgdBuild:452 - logical net 'N1451' has no driver -WARNING:NgdBuild:452 - logical net 'N1452' has no driver -WARNING:NgdBuild:452 - logical net 'N1453' has no driver -WARNING:NgdBuild:452 - logical net 'N1454' has no driver -WARNING:NgdBuild:452 - logical net 'N1455' has no driver -WARNING:NgdBuild:452 - logical net 'N1456' has no driver -WARNING:NgdBuild:452 - logical net 'N1457' has no driver -WARNING:NgdBuild:452 - logical net 'N1458' has no driver -WARNING:NgdBuild:452 - logical net 'N1459' has no driver -WARNING:NgdBuild:452 - logical net 'N1460' has no driver -WARNING:NgdBuild:452 - logical net 'N1461' has no driver -WARNING:NgdBuild:452 - logical net 'N1462' has no driver -WARNING:NgdBuild:452 - logical net 'N1463' has no driver -WARNING:NgdBuild:452 - logical net 'N1464' has no driver -WARNING:NgdBuild:452 - logical net 'N1465' has no driver -WARNING:NgdBuild:452 - logical net 'N1466' has no driver -WARNING:NgdBuild:452 - logical net 'N1467' has no driver -WARNING:NgdBuild:452 - logical net 'N1468' has no driver -WARNING:NgdBuild:452 - logical net 'N1469' has no driver -WARNING:NgdBuild:452 - logical net 'N1470' has no driver -WARNING:NgdBuild:452 - logical net 'N1471' has no driver -WARNING:NgdBuild:452 - logical net 'N1472' has no driver -WARNING:NgdBuild:452 - logical net 'N1473' has no driver -WARNING:NgdBuild:452 - logical net 'N1474' has no driver -WARNING:NgdBuild:452 - logical net 'N1475' has no driver -WARNING:NgdBuild:452 - logical net 'N1476' has no driver -WARNING:NgdBuild:452 - logical net 'N1477' has no driver -WARNING:NgdBuild:452 - logical net 'N1478' has no driver -WARNING:NgdBuild:452 - logical net 'N1479' has no driver -WARNING:NgdBuild:452 - logical net 'N1480' has no driver -WARNING:NgdBuild:452 - logical net 'N1481' has no driver -WARNING:NgdBuild:452 - logical net 'N1482' has no driver -WARNING:NgdBuild:452 - logical net 'N1483' has no driver -WARNING:NgdBuild:452 - logical net 'N1484' has no driver -WARNING:NgdBuild:452 - logical net 'N1485' has no driver -WARNING:NgdBuild:452 - logical net 'N1486' has no driver -WARNING:NgdBuild:452 - logical net 'N1487' has no driver -WARNING:NgdBuild:452 - logical net 'N1488' has no driver -WARNING:NgdBuild:452 - logical net 'N1489' has no driver -WARNING:NgdBuild:452 - logical net 'N1490' has no driver -WARNING:NgdBuild:452 - logical net 'N1491' has no driver -WARNING:NgdBuild:452 - logical net 'N1492' has no driver -WARNING:NgdBuild:452 - logical net 'N1493' has no driver -WARNING:NgdBuild:452 - logical net 'N1494' has no driver -WARNING:NgdBuild:452 - logical net 'N1495' has no driver -WARNING:NgdBuild:452 - logical net 'N1497' has no driver -WARNING:NgdBuild:452 - logical net 'cmp_bpm_pcie_ml605/ext_rst_o' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4c/sig00002578' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4c/sig00002579' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4c/sig0000257a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4c/sig0000257c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4c/sig0000257d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4c/sig0000257e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4d/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4d/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4d/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4d/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4d/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4e/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4e/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4e/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4e/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4e/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4f/sig0000259c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4f/sig0000259d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4f/sig0000259e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4f/sig000025a0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c4f/sig000025a1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c50/sig000025a8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c50/sig000025a9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c50/sig000025aa' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c50/sig000025ac' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c50/sig000025ad' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c51/sig000025b4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c51/sig000025b5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c51/sig000025b6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c51/sig000025b8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c51/sig000025b9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c52/sig000025c0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c52/sig000025c1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c52/sig000025c2' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c52/sig000025c4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c52/sig000025c5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c53/sig000025cc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c53/sig000025cd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c53/sig000025ce' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c53/sig000025d0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c53/sig000025d1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c54/sig000025d8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c54/sig000025d9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c54/sig000025da' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c54/sig000025dc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c54/sig000025dd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c55/sig000025e4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c55/sig000025e5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c55/sig000025e6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c55/sig000025e8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c55/sig000025e9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c56/sig000025f0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c56/sig000025f1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c56/sig000025f2' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c56/sig000025f4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c56/sig000025f5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c56/sig000025f6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c57/sig000025fc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c57/sig000025fd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c57/sig000025fe' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c57/sig00002600' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c57/sig00002601' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c58/sig00002608' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c58/sig00002609' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c58/sig0000260a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c58/sig0000260c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c58/sig0000260d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c59/sig00002614' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c59/sig00002615' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c59/sig00002616' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c59/sig00002618' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c59/sig00002619' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5a/sig00002620' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5a/sig00002621' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5a/sig00002622' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5a/sig00002624' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5a/sig00002625' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5b/sig0000262c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5b/sig0000262d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5b/sig0000262e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5b/sig00002630' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5b/sig00002631' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5c/sig00002638' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5c/sig00002639' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5c/sig0000263a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5c/sig0000263c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5c/sig0000263d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5d/sig00002644' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5d/sig00002645' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5d/sig00002646' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5d/sig00002648' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5d/sig00002649' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5e/sig00002650' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5e/sig00002651' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5e/sig00002652' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5e/sig00002654' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5e/sig00002655' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5f/sig0000265c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5f/sig0000265d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5f/sig0000265e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5f/sig00002660' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c5f/sig00002661' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c60/sig00002668' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c60/sig00002669' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c60/sig0000266a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c60/sig0000266c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c60/sig0000266d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c60/sig0000266e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c61/sig00002674' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c61/sig00002675' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c61/sig00002676' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c61/sig00002678' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c61/sig00002679' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c62/sig00002680' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c62/sig00002681' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c62/sig00002682' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c62/sig00002684' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c62/sig00002685' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c63/sig0000268c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c63/sig0000268d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c63/sig0000268e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c63/sig00002690' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c63/sig00002691' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c64/sig00002698' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c64/sig00002699' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c64/sig0000269a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c64/sig0000269c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c64/sig0000269d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c65/sig000026a4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c65/sig000026a5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c65/sig000026a6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c65/sig000026a8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c65/sig000026a9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c66/sig000026b0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c66/sig000026b1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c66/sig000026b2' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c66/sig000026b4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c66/sig000026b5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c67/sig000026bc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c67/sig000026bd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c67/sig000026be' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c67/sig000026c0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c67/sig000026c1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c68/sig000026c8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c68/sig000026c9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c68/sig000026ca' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c68/sig000026cc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c68/sig000026cd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c69/sig000026d4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c69/sig000026d5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c69/sig000026d6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c69/sig000026d8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c69/sig000026d9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6a/sig000026e0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6a/sig000026e1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6a/sig000026e2' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6a/sig000026e4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6a/sig000026e5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6a/sig000026e6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6b/sig000026ec' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6b/sig000026ed' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6b/sig000026ee' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6b/sig000026f0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6b/sig000026f1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6c/sig000026f8' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6c/sig000026f9' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6c/sig000026fa' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6c/sig000026fc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6c/sig000026fd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6d/sig00002704' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6d/sig00002705' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6d/sig00002706' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6d/sig00002708' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6d/sig00002709' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6e/sig00002710' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6e/sig00002711' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6e/sig00002712' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6e/sig00002714' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6e/sig00002715' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6f/sig0000271c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6f/sig0000271d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6f/sig0000271e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6f/sig00002720' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c6f/sig00002721' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c70/sig00002728' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c70/sig00002729' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c70/sig0000272a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c70/sig0000272c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c70/sig0000272d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c71/sig00002734' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c71/sig00002735' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c71/sig00002736' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c71/sig00002738' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c71/sig00002739' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c72/sig00002740' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c72/sig00002741' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c72/sig00002742' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c72/sig00002744' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c72/sig00002745' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c73/sig0000274c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c73/sig0000274d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c73/sig0000274e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c73/sig00002750' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/bpf_fpga/fr_cmplr_v6_3_ef - 8269b30b0e0deb_instance/blk00000c73/sig00002751' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/t - bt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/t - bt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001bd4 - /sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp1_a049562dde - /fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b0b6/fofb_amp0_95b23bfc2c - /fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead3076ad_instance/blk00001 - bd4/sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk0000017d/sig000003b - c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk0000017d/sig000003b - d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk0000017d/sig000003b - f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk0000017d/sig000003c - 0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk0000017d/sig000003c - 1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793e - a71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/sig000001a1' has no - driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_ - cmplr_v6_3_d5f4b3c608d95215_instance/blk00000162/sig000003c3' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_ - cmplr_v6_3_d5f4b3c608d95215_instance/blk00000162/sig000003c5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_d - dc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_pos_1_522c8cf08d/monit_pos_1_c/fr_ - cmplr_v6_3_d5f4b3c608d95215_instance/blk00000162/sig000003c6' has no driver - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 482 - -Writing NGD file "dbe_bpm_dsp.ngd" ... -Total REAL time to NGDBUILD completion: 4 min 11 sec -Total CPU time to NGDBUILD completion: 4 min 11 sec - -Writing NGDBUILD log file "dbe_bpm_dsp.bld"... - -NGDBUILD done. - -Process "Translate" completed successfully - -Started : "Map". -Running map... -Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_dsp_map.ncd dbe_bpm_dsp.ngd dbe_bpm_dsp.pcf -Using target part "6vlx240tff1156-1". -INFO:Map:284 - Map is running with the multi-threading option on. Map currently - supports the use of up to 2 processors. Based on the the user options and - machine load, Map will use 2 processors during this run. -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part -'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -WARNING:LIT:672 - FIFO18E1 symbol - "physical_group_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_ - out_int[0]_adc_data<15>/cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_if - ace/gen_adc_data_chains[0].gen_adc_data_chains_check.cmp_fmc_adc_data/cmp_adc - _data_async_fifo/gen_native.U_Native_FIFO/gen_fifo18.U_Wrapped_FIFO18" has - one or more pins of DI[16:31] or DIP[2:3] actively driven, however DATA_WIDTH - is 18. These connections will be dropped as they are not supported when - DATA_WIDTH is 18. -Running directed packing... -WARNING:Pack:1186 - One or more I/O components have conflicting property values. - For each occurrence, the system will use the property value attached to the - pad. Otherwise, the system will use the first property value read. To view - each occurrence, create a detailed map report (run map using the -detail - option). -Running delay-based LUT packing... -Updating timing models... -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_2500_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 98771418.8 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 246928547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 98771418.8 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 49385709.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_2500_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_2224_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2500_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_1390000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_222400000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_22240000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_2500_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_2780000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_55600000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_5560000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_1112_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_1390000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_22240000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_2224_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_2500_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_2780000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_5000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_55600000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_5560000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_556_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_2224_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 49385709.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 24692854.7 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 24692854.7 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_2224_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_2500_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" TO - TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" TO - TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_1390000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_22240000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_2224_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_2500_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_2780000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_35_cc71cef7_group" 155.440632 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_5000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_55600000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_5560000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 7 mins 2 secs -Total CPU time at the beginning of Placer: 7 mins 2 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:747ba0a3) REAL time: 7 mins 34 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:8c10af72) REAL time: 7 mins 44 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:30fe715c) REAL time: 7 mins 44 secs - -Phase 4.37 Local Placement Optimization -Phase 4.37 Local Placement Optimization (Checksum:30fe715c) REAL time: 7 mins 44 secs - -Phase 5.2 Initial Placement for Architecture Specific Features - -...... - - -There are 12 clock regions on the target FPGA device: -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 1 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 2 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: | -| 4 BUFRs available, 1 in use | 2 BUFRs available, 1 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 1 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 3 in use | 4 center BUFIOs available, 3 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 3 in use | 6 Regional Clock Spines, 1 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: | -| 4 BUFRs available, 2 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 4 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: | -| 4 BUFRs available, 2 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 4 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 0/4; bufrs - 2/4; regional-clock-spines - 4/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/ | 1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/ | 1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 0/4; bufrs - 2/4; regional-clock-spines - 4/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 3/4; bufrs - 1/4; regional-clock-spines - 1/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 0 | 0 | 0 | 40 | 0 | 1035 | 40 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/0; center-bufios - 3/4; bufrs - 1/2; regional-clock-spines - 1/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 108 | 0 | 0 | 40 | 40 | 24960 | 9920 | 15040 | 64 | 2 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 108 | 0 | 0 | 40 | 40 | 24000 | 9760 | 14240 | 64 | 0 | 0 | 1 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 108 | 0 | 0 | 40 | 40 | 24960 | 9920 | 15040 | 64 | 2 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 0 | 0 | 0 | 25 | 0 | 641 | 25 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 2/4; bufrs - 0/4; regional-clock-spines - 1/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - - - -###################################################################################### -# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT: -# -# Number of Regional Clocking Regions in the device: 12 (6 clock spines in each) -# Number of Regional Clock Networks used in this design: 15 (each network can be -# composed of up to 3 clock spines and cover up to 3 regional clock regions) -# -###################################################################################### - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" driven by "BUFIODQS_X1Y15" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt" -LOC = "BUFIODQS_X1Y15" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<7>" RANGE = CLOCKREGION_X0Y3; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" driven by "BUFIODQS_X1Y14" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_bufio_cpt" -LOC = "BUFIODQS_X1Y14" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<6>" RANGE = CLOCKREGION_X0Y3; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" driven by "BUFIODQS_X1Y12" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_bufio_cpt" -LOC = "BUFIODQS_X1Y12" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<5>" RANGE = CLOCKREGION_X0Y3; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" driven by "BUFIODQS_X1Y18" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_bufio_cpt" -LOC = "BUFIODQS_X1Y18" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<4>" RANGE = CLOCKREGION_X0Y4; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" driven by "BUFIODQS_X1Y17" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_bufio_cpt" -LOC = "BUFIODQS_X1Y17" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<3>" RANGE = CLOCKREGION_X0Y4; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" driven by "BUFIODQS_X2Y15" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_bufio_cpt" -LOC = "BUFIODQS_X2Y15" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<2>" RANGE = CLOCKREGION_X1Y3; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" driven by "BUFIODQS_X2Y12" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_bufio_cpt" -LOC = "BUFIODQS_X2Y12" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<0>" RANGE = CLOCKREGION_X1Y3; - - -# IO-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" driven by "BUFIODQS_X2Y14" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_bufio_cpt" -LOC = "BUFIODQS_X2Y14" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_cpt<1>" RANGE = CLOCKREGION_X1Y3; - - -# Regional-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" driven by "BUFR_X1Y6" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" -LOC = "BUFR_X1Y6" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" RANGE = -CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y2; - - -# Regional-Clock "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" driven by "BUFR_X2Y6" -INST -"cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" -LOC = "BUFR_X2Y6" ; -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" TNM_NET = -"TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" AREA_GROUP = -"CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" RANGE = -CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y2; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" driven -by "BUFR_X0Y3" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[3].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y3" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" driven -by "BUFR_X1Y1" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[2].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y1" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" driven -by "BUFR_X0Y0" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y0" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" driven -by "BUFR_X1Y3" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y3" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -Phase 5.2 Initial Placement for Architecture Specific Features (Checksum:7187d043) REAL time: 8 mins 58 secs - -Phase 6.36 Local Placement Optimization -Phase 6.36 Local Placement Optimization (Checksum:7187d043) REAL time: 8 mins 58 secs - -................................... -...................................................................................................................... -Phase 7.30 Global Clock Region Assignment - - -###################################################################################### -# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT: -# -# Number of Global Clock Regions : 12 -# Number of Global Clock Networks: 16 -# -# Clock Region Assignment: SUCCESSFUL - -# Location of Clock Components -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/drp_clk_bufg_i" LOC = "BUFGCTRL_X0Y31" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_ref_clk.cmp_adc2x_out_bufg" LOC = "BUFGCTRL_X0Y0" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/GEN1_LINK.pipe_clk_bufg" LOC = "BUFGCTRL_X0Y30" ; -INST "cmp_sys_pll_inst/cmp_clkout0_buf" LOC = "BUFGCTRL_X0Y7" ; -INST "cmp_sys_pll_inst/cmp_clkout1_buf" LOC = "BUFGCTRL_X0Y4" ; -INST "cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/u_bufg_clk0" LOC = "BUFGCTRL_X0Y26" ; -INST "cmp_chipscope_icon_13/U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG/U_BUFG" LOC = "BUFGCTRL_X0Y24" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_ref_clk.cmp_adc_out_bufg" LOC = "BUFGCTRL_X0Y1" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/sys_clk_bufg_i" LOC = "BUFGCTRL_X0Y27" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/clkfbin_bufg_i" LOC = "BUFGCTRL_X0Y28" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/x4_GEN1_125_00.user_clk_bufg" LOC = "BUFGCTRL_X0Y29" ; -INST "cmp_sys_pll_inst/cmp_clkf_bufg" LOC = "BUFGCTRL_X0Y6" ; -INST "cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/u_bufg_clk_ref" LOC = "BUFGCTRL_X0Y5" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_ref_clk.cmp_adc_clk_fb_bufg" LOC = "BUFGCTRL_X0Y2" ; -INST "cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/u_bufg_clkdiv0" LOC = "BUFGCTRL_X0Y25" ; -INST "cmp_clk_gen/cmp_bufg_clk_gen" LOC = "BUFGCTRL_X0Y3" ; -INST "sys_clk_p_i" LOC = "J9" ; -INST "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X2Y6" ; -INST "cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" LOC = "BUFR_X1Y6" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y0" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y3" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[2].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y1" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[3].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y3" ; -INST "cmp_bpm_pcie_ml605/pcieclk_ibuf" LOC = "IBUFDS_GTXE1_X0Y6" ; -INST "cmp_sys_pll_inst/cmp_mmcm" LOC = "MMCM_ADV_X0Y0" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_adv_i" LOC = "MMCM_ADV_X0Y7" ; -INST "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_ref_clk.cmp_mmcm_adc_clk" LOC = "MMCM_ADV_X0Y1" ; -INST "cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/u_mmcm_adv" LOC = "MMCM_ADV_X0Y8" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX" LOC = "GTXE1_X0Y15" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX" LOC = "GTXE1_X0Y14" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX" LOC = "GTXE1_X0Y13" ; -INST "cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX" LOC = "GTXE1_X0Y12" ; - -# cmp_bpm_pcie_ml605/pcie_core_i/drp_clk driven by BUFGCTRL_X0Y31 -NET "cmp_bpm_pcie_ml605/pcie_core_i/drp_clk" TNM_NET = "TN_cmp_bpm_pcie_ml605/pcie_core_i/drp_clk" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/pcie_core_i/drp_clk" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/drp_clk" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/drp_clk" RANGE = CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# fmc_130m_4ch_clk2x<1> driven by BUFGCTRL_X0Y0 -NET "fmc_130m_4ch_clk2x<1>" TNM_NET = "TN_fmc_130m_4ch_clk2x<1>" ; -TIMEGRP "TN_fmc_130m_4ch_clk2x<1>" AREA_GROUP = "CLKAG_fmc_130m_4ch_clk2x<1>" ; -AREA_GROUP "CLKAG_fmc_130m_4ch_clk2x<1>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk driven by BUFGCTRL_X0Y30 -NET "cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk" TNM_NET = "TN_cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk" RANGE = CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# clk_sys driven by BUFGCTRL_X0Y7 -NET "clk_sys" TNM_NET = "TN_clk_sys" ; -TIMEGRP "TN_clk_sys" AREA_GROUP = "CLKAG_clk_sys" ; -AREA_GROUP "CLKAG_clk_sys" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# clk_200mhz driven by BUFGCTRL_X0Y4 -NET "clk_200mhz" TNM_NET = "TN_clk_200mhz" ; -TIMEGRP "TN_clk_200mhz" AREA_GROUP = "CLKAG_clk_200mhz" ; -AREA_GROUP "CLKAG_clk_200mhz" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_bpm_pcie_ml605/u_ddr_core/clk_mem driven by BUFGCTRL_X0Y26 -NET "cmp_bpm_pcie_ml605/u_ddr_core/clk_mem" TNM_NET = "TN_cmp_bpm_pcie_ml605/u_ddr_core/clk_mem" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/clk_mem" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/clk_mem" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/clk_mem" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# CONTROL0<0> driven by BUFGCTRL_X0Y24 -NET "CONTROL0<0>" TNM_NET = "TN_CONTROL0<0>" ; -TIMEGRP "TN_CONTROL0<0>" AREA_GROUP = "CLKAG_CONTROL0<0>" ; -AREA_GROUP "CLKAG_CONTROL0<0>" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk driven by BUFGCTRL_X0Y1 -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk" TNM_NET = "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk" AREA_GROUP = "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg driven by BUFGCTRL_X0Y27 -NET "cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg" TNM_NET = "TN_cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg" RANGE = CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_clkfbin driven by BUFGCTRL_X0Y28 -NET "cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_clkfbin" TNM_NET = "TN_cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_clkfbin" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_clkfbin" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_clkfbin" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/pcie_core_i/pcie_clocking_i/mmcm_clkfbin" RANGE = CLOCKREGION_X0Y3, CLOCKREGION_X1Y3 ; - -# cmp_bpm_pcie_ml605/user_clk driven by BUFGCTRL_X0Y29 -NET "cmp_bpm_pcie_ml605/user_clk" TNM_NET = "TN_cmp_bpm_pcie_ml605/user_clk" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/user_clk" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/user_clk" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/user_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_sys_pll_inst/s_mmcm_fbin driven by BUFGCTRL_X0Y6 -NET "cmp_sys_pll_inst/s_mmcm_fbin" TNM_NET = "TN_cmp_sys_pll_inst/s_mmcm_fbin" ; -TIMEGRP "TN_cmp_sys_pll_inst/s_mmcm_fbin" AREA_GROUP = "CLKAG_cmp_sys_pll_inst/s_mmcm_fbin" ; -AREA_GROUP "CLKAG_cmp_sys_pll_inst/s_mmcm_fbin" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0 ; - -# cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg driven by BUFGCTRL_X0Y5 -NET "cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg" TNM_NET = "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg" ; -TIMEGRP "TN_cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg" AREA_GROUP = "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg" ; -AREA_GROUP "CLKAG_cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_fbin driven by BUFGCTRL_X0Y2 -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_fbin" TNM_NET = "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_fbin" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_fbin" AREA_GROUP = "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_fbin" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_fbin" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0 ; - -# memc_ui_clk driven by BUFGCTRL_X0Y25 -NET "memc_ui_clk" TNM_NET = "TN_memc_ui_clk" ; -TIMEGRP "TN_memc_ui_clk" AREA_GROUP = "CLKAG_memc_ui_clk" ; -AREA_GROUP "CLKAG_memc_ui_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ; - -# sys_clk_gen_bufg driven by BUFGCTRL_X0Y3 -NET "sys_clk_gen_bufg" TNM_NET = "TN_sys_clk_gen_bufg" ; -TIMEGRP "TN_sys_clk_gen_bufg" AREA_GROUP = "CLKAG_sys_clk_gen_bufg" ; -AREA_GROUP "CLKAG_sys_clk_gen_bufg" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2 ; - -# NOTE: -# This report is provided to help reproduce successful clock-region -# assignments. The report provides range constraints for all global -# clock networks, in a format that is directly usable in ucf files. -# -#END of Global Clock Net Distribution UCF Constraints -###################################################################################### - - -###################################################################################### -GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT: - -Number of Global Clock Regions : 12 -Number of Global Clock Networks: 24 - -Clock Region Assignment: SUCCESSFUL - -Clock-Region: - key resource utilizations (used/available): global-clocks - 6/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 96 | 2 | 0 | 80 | 80 | 80 | 64 | 0 | 0 | 0 | 2 | 9600 | 26880 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 1344 |CONTROL0<0> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |clk_200mhz - 21 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 18 | 3040 |clk_sys - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |cmp_bpm_pcie_ml605/user_clk - 7 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 48 | 341 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 628 |fmc_130m_4ch_clk2x<1> ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 31 | 0 | 0 | 0 | 0 | 8 | 4 | 0 | 0 | 0 | 1 | 93 | 5354 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 4/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 120 | 0 | 4 | 40 | 40 | 40 | 64 | 0 | 0 | 0 | 1 | 9920 | 24960 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 72 | 241 |CONTROL0<0> - 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 536 |clk_sys - 19 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 130 | 503 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 793 | 6860 |fmc_130m_4ch_clk2x<1> ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 38 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 999 | 8140 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 7/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 96 | 2 | 0 | 80 | 80 | 80 | 64 | 0 | 0 | 0 | 2 | 9600 | 26880 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 177 | 58 |CONTROL0<0> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 |clk_200mhz - 14 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 12 | 1820 |clk_sys - 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 139 |cmp_bpm_pcie_ml605/user_clk - 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 144 | 718 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 1 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 660 | 5308 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 344 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 42 | 0 | 0 | 0 | 0 | 9 | 14 | 0 | 0 | 0 | 2 | 993 | 8387 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 5/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 108 | 0 | 4 | 40 | 40 | 40 | 64 | 0 | 0 | 1 | 1 | 9760 | 24000 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 467 | 204 |CONTROL0<0> - 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 505 |clk_sys - 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 451 | 1350 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 5 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 470 | 8114 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 |sys_clk_gen_bufg ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 34 | 0 | 0 | 0 | 0 | 2 | 15 | 0 | 0 | 0 | 0 | 1388 | 10184 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 7/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 96 | 2 | 0 | 80 | 80 | 80 | 64 | 16 | 0 | 0 | 2 | 9600 | 23040 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 277 | 140 |CONTROL0<0> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |clk_200mhz - 2 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clk_sys - 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2585 |cmp_bpm_pcie_ml605/user_clk - 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 422 | 1216 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 3 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 3993 | 6511 |fmc_130m_4ch_clk2x<1> - 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 589 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 42 | 0 | 0 | 0 | 0 | 8 | 22 | 0 | 0 | 0 | 1 | 4692 | 11041 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 7/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 108 | 0 | 4 | 40 | 40 | 40 | 64 | 0 | 2 | 0 | 1 | 9920 | 24960 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 823 | 196 |CONTROL0<0> - 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 2 |clk_sys - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 38 |cmp_bpm_pcie_ml605/user_clk - 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 823 | 3576 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 14 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 493 | 8127 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 54 | 0 | 0 | 0 | 0 | 2 | 11 | 0 | 0 | 0 | 0 | 2139 | 11951 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 8/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 96 | 2 | 0 | 80 | 80 | 80 | 64 | 16 | 0 | 0 | 2 | 9600 | 23040 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 205 | 60 |CONTROL0<0> - 0 | 0 | 0 | 0 | 24 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_mem - 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_rd_base - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg - 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 254 | 1033 |cmp_bpm_pcie_ml605/user_clk - 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 211 | 686 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 2 | 0 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | 0 | 2489 | 3353 |fmc_130m_4ch_clk2x<1> - 4 | 0 | 0 | 0 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | 766 | 4204 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 24 | 0 | 0 | 0 | 24 | 78 | 49 | 0 | 0 | 0 | 1 | 3925 | 9336 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 12/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 108 | 0 | 4 | 40 | 40 | 40 | 64 | 0 | 0 | 1 | 1 | 9760 | 24000 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 211 | 125 |CONTROL0<0> - 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |clk_sys - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 |cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk_bufg - 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 |cmp_bpm_pcie_ml605/pcie_core_i/drp_clk - 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 8 | 399 |cmp_bpm_pcie_ml605/pcie_core_i/pipe_clk - 0 | 0 | 0 | 0 | 25 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_mem - 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_rd_base - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 12 |cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg - 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 24 | 2968 |cmp_bpm_pcie_ml605/user_clk - 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 211 | 715 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 6 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 3476 | 4363 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | 120 | 187 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 36 | 0 | 8 | 0 | 26 | 78 | 15 | 0 | 0 | 2 | 1 | 4050 | 8812 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 7/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 96 | 2 | 0 | 80 | 80 | 80 | 64 | 0 | 0 | 0 | 2 | 9600 | 26880 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 |CONTROL0<0> - 0 | 0 | 0 | 0 | 16 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_mem - 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_rd_base - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 3 |cmp_bpm_pcie_ml605/u_ddr_core/u_iodelay_ctrl/clk_ref_bufg - 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 910 |cmp_bpm_pcie_ml605/user_clk - 2 | 0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | 0 | 4127 | 3872 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | 216 | 1543 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 3 | 0 | 0 | 0 | 16 | 50 | 25 | 0 | 0 | 0 | 1 | 4351 | 6328 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 6/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 108 | 0 | 4 | 40 | 40 | 40 | 64 | 0 | 2 | 0 | 1 | 9920 | 24960 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |CONTROL0<0> - 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |cmp_bpm_pcie_ml605/u_ddr_core/clk_mem - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 666 |cmp_bpm_pcie_ml605/user_clk - 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 |cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/adc_out[0]_adc_clk - 3 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 4052 | 3906 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 120 | 769 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 6 | 0 | 0 | 0 | 0 | 49 | 14 | 0 | 0 | 0 | 0 | 4174 | 5350 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 3/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 96 | 2 | 0 | 80 | 80 | 80 | 64 | 0 | 0 | 0 | 2 | 9600 | 26880 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 |cmp_bpm_pcie_ml605/user_clk - 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 2129 | 2813 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 250 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 2 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 2129 | 3109 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): global-clocks - 2/12 ; ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - BRAM | MMCM | GT | IOB | ILOGIC | OLOGIC | MULT | BUFG | TEMAC | PCIE | IDLYCT | LUTRAM | FF | <- (Types of Resources in this Region) - FIFO | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 120 | 0 | 4 | 40 | 40 | 40 | 64 | 0 | 0 | 0 | 1 | 9920 | 24960 | <- (Available Resources in this Region) ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - | | | | | | | | | | | | | ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 827 | 2929 |fmc_130m_4ch_clk2x<1> - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 40 |memc_ui_clk ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 829 | 2969 | Total ---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+---------------------------------------- - -NOTE: -The above detailed report is the initial placement of the logic after the clock region assignment. The final placement -may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks -maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated. - - -# END of Global Clock Net Loads Distribution Report: -###################################################################################### - - -Phase 7.30 Global Clock Region Assignment (Checksum:7187d043) REAL time: 17 mins 10 secs - -Phase 8.3 Local Placement Optimization -Phase 8.3 Local Placement Optimization (Checksum:7187d043) REAL time: 17 mins 11 secs - -Phase 9.5 Local Placement Optimization -Phase 9.5 Local Placement Optimization (Checksum:7187d043) REAL time: 17 mins 14 secs - -Phase 10.8 Global Placement -................................. -....................................................................................................................................................... -........................................................................................................................................................................................... -.................................................................................................................................................................................... -................................. -Phase 10.8 Global Placement (Checksum:1df4ace2) REAL time: 25 mins 34 secs - -Phase 11.5 Local Placement Optimization -Phase 11.5 Local Placement Optimization (Checksum:1df4ace2) REAL time: 25 mins 41 secs - -Phase 12.18 Placement Optimization -Phase 12.18 Placement Optimization (Checksum:5f5defef) REAL time: 29 mins 18 secs - -Phase 13.5 Local Placement Optimization -Phase 13.5 Local Placement Optimization (Checksum:5f5defef) REAL time: 29 mins 21 secs - -Phase 14.34 Placement Validation -Phase 14.34 Placement Validation (Checksum:e0cd0fba) REAL time: 29 mins 24 secs - -Total REAL time to Placer completion: 29 mins 33 secs -Total CPU time to Placer completion: 31 mins 33 secs -Running physical synthesis... -................................................................................................................................... -Physical synthesis completed. -Running post-placement packing... -Writing output files... - -Design Summary: -Number of errors: 0 -Number of warnings: 814 -Slice Logic Utilization: - Number of Slice Registers: 95,814 out of 301,440 31% - Number used as Flip Flops: 95,796 - Number used as Latches: 15 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 3 - Number of Slice LUTs: 80,988 out of 150,720 53% - Number used as logic: 58,715 out of 150,720 38% - Number using O6 output only: 42,101 - Number using O5 output only: 2,286 - Number using O5 and O6: 14,328 - Number used as ROM: 0 - Number used as Memory: 14,922 out of 58,400 25% - Number used as Dual Port RAM: 1,340 - Number using O6 output only: 56 - Number using O5 output only: 8 - Number using O5 and O6: 1,276 - Number used as Single Port RAM: 628 - Number using O6 output only: 624 - Number using O5 output only: 0 - Number using O5 and O6: 4 - Number used as Shift Register: 12,954 - Number using O6 output only: 8,520 - Number using O5 output only: 2,401 - Number using O5 and O6: 2,033 - Number used exclusively as route-thrus: 7,351 - Number with same-slice register load: 6,884 - Number with same-slice carry load: 467 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 30,293 out of 37,680 80% - Number of LUT Flip Flop pairs used: 101,319 - Number with an unused Flip Flop: 19,096 out of 101,319 18% - Number with an unused LUT: 20,331 out of 101,319 20% - Number of fully used LUT-FF pairs: 61,892 out of 101,319 61% - Number of unique control sets: 2,747 - Number of slice register sites lost - to control set restrictions: 9,762 out of 301,440 3% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 253 out of 600 42% - Number of LOCed IOBs: 253 out of 253 100% - IOB Flip Flops: 38 - IOB Master Pads: 10 - IOB Slave Pads: 10 - Number of bonded IPADs: 10 - Number of LOCed IPADs: 2 out of 10 20% - Number of bonded OPADs: 8 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 172 out of 416 41% - Number using RAMB36E1 only: 164 - Number using FIFO36E1 only: 8 - Number of RAMB18E1/FIFO18E1s: 30 out of 832 3% - Number using RAMB18E1 only: 24 - Number using FIFO18E1 only: 6 - Number of BUFG/BUFGCTRLs: 16 out of 32 50% - Number used as BUFGs: 16 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 67 out of 720 9% - Number used as ILOGICE1s: 2 - Number used as ISERDESE1s: 65 - Number of OLOGICE1/OSERDESE1s: 159 out of 720 22% - Number used as OLOGICE1s: 37 - Number used as OSERDESE1s: 122 - Number of BSCANs: 1 out of 4 25% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 8 out of 72 11% - Number of BUFRs: 6 out of 36 16% - Number of LOCed BUFRs: 2 out of 6 33% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 208 out of 768 27% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 4 out of 20 20% - Number of LOCed GTXE1s: 4 out of 4 100% - Number of IBUFDS_GTXE1s: 1 out of 12 8% - Number of LOCed IBUFDS_GTXE1s: 1 out of 1 100% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 7 out of 18 38% - Number of IODELAYE1s: 158 out of 720 21% - Number of LOCed IODELAYE1s: 10 out of 158 6% - Number of MMCM_ADVs: 4 out of 12 33% - Number of LOCed MMCM_ADVs: 2 out of 4 50% - Number of PCIE_2_0s: 1 out of 2 50% - Number of LOCed PCIE_2_0s: 1 out of 1 100% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - Number of RPM macros: 143 -Average Fanout of Non-Clock Nets: 3.20 - -Peak Memory Usage: 4748 MB -Total REAL time to MAP completion: 1 hrs 19 mins 59 secs -Total CPU time to MAP completion (all processors): 1 hrs 21 mins 58 secs - -Mapping completed. -See MAP report file "dbe_bpm_dsp_map.mrp" for details. - -Process "Map" completed successfully - -Started : "Place & Route". -Running par... -Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_dsp_map.ncd dbe_bpm_dsp.ncd dbe_bpm_dsp.pcf - - - -Constraints file: dbe_bpm_dsp.pcf. -Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_dsp" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRODUCTION 1.17 2012-01-07". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 95,814 out of 301,440 31% - Number used as Flip Flops: 95,796 - Number used as Latches: 15 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 3 - Number of Slice LUTs: 80,988 out of 150,720 53% - Number used as logic: 58,715 out of 150,720 38% - Number using O6 output only: 42,101 - Number using O5 output only: 2,286 - Number using O5 and O6: 14,328 - Number used as ROM: 0 - Number used as Memory: 14,922 out of 58,400 25% - Number used as Dual Port RAM: 1,340 - Number using O6 output only: 56 - Number using O5 output only: 8 - Number using O5 and O6: 1,276 - Number used as Single Port RAM: 628 - Number using O6 output only: 624 - Number using O5 output only: 0 - Number using O5 and O6: 4 - Number used as Shift Register: 12,954 - Number using O6 output only: 8,520 - Number using O5 output only: 2,401 - Number using O5 and O6: 2,033 - Number used exclusively as route-thrus: 7,351 - Number with same-slice register load: 6,884 - Number with same-slice carry load: 467 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 30,293 out of 37,680 80% - Number of LUT Flip Flop pairs used: 101,319 - Number with an unused Flip Flop: 19,096 out of 101,319 18% - Number with an unused LUT: 20,331 out of 101,319 20% - Number of fully used LUT-FF pairs: 61,892 out of 101,319 61% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 253 out of 600 42% - Number of LOCed IOBs: 253 out of 253 100% - IOB Flip Flops: 38 - IOB Master Pads: 10 - IOB Slave Pads: 10 - Number of bonded IPADs: 10 - Number of LOCed IPADs: 2 out of 10 20% - Number of bonded OPADs: 8 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 172 out of 416 41% - Number using RAMB36E1 only: 164 - Number using FIFO36E1 only: 8 - Number of RAMB18E1/FIFO18E1s: 30 out of 832 3% - Number using RAMB18E1 only: 24 - Number using FIFO18E1 only: 6 - Number of BUFG/BUFGCTRLs: 16 out of 32 50% - Number used as BUFGs: 16 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 67 out of 720 9% - Number used as ILOGICE1s: 2 - Number used as ISERDESE1s: 65 - Number of OLOGICE1/OSERDESE1s: 159 out of 720 22% - Number used as OLOGICE1s: 37 - Number used as OSERDESE1s: 122 - Number of BSCANs: 1 out of 4 25% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 8 out of 72 11% - Number of BUFRs: 6 out of 36 16% - Number of LOCed BUFRs: 2 out of 6 33% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 208 out of 768 27% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 4 out of 20 20% - Number of LOCed GTXE1s: 4 out of 4 100% - Number of IBUFDS_GTXE1s: 1 out of 12 8% - Number of LOCed IBUFDS_GTXE1s: 1 out of 1 100% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 7 out of 18 38% - Number of IODELAYE1s: 158 out of 720 21% - Number of LOCed IODELAYE1s: 10 out of 158 6% - Number of MMCM_ADVs: 4 out of 12 33% - Number of LOCed MMCM_ADVs: 2 out of 4 50% - Number of PCIE_2_0s: 1 out of 2 50% - Number of LOCed PCIE_2_0s: 1 out of 1 100% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -INFO:Timing:2802 - Read 230 constraints. If you are experiencing memory or runtime issues it may help to consolidate some of these - constraints. For more details please do a search for "timing:2802" at http://www.xilinx.com/support. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 98771418.8 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 246928547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_222400000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_222400000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 98771418.8 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 49385709.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2500_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_2_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 49385709.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_55600000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_55600000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 11102.9023 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_222400000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_222400000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2500_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2500_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 155.440632 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_55600000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_55600000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx - Command Line Tools User Guide for information on generating a TSI report. -Starting initial Timing Analysis. REAL time: 3 mins 50 secs -Finished initial Timing Analysis. REAL time: 3 mins 55 secs - -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iobuf_dqs/OB has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc0_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc1_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc2_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc3_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<164> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<165> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<166> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<167> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<52> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<53> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<54> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<55> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<184> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<185> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<186> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<187> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<172> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<173> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<174> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<175> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<168> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<169> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<170> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<171> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<12> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<13> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<14> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<15> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<44> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<45> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<46> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<47> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<180> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<181> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<182> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<183> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<8> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<9> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<10> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<11> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<56> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<57> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<58> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<59> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<48> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<49> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<50> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<51> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<160> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<161> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<162> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<163> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<188> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<189> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<190> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<191> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<16> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<17> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<18> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<19> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<4> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<5> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<6> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<7> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<41> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<42> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<43> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<156> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<157> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<158> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<159> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<20> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<21> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<22> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<23> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<192> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<193> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<194> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<195> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<176> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<177> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<178> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<179> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<60> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<61> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<62> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<63> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<152> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<153> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<154> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<155> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfi - fo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<0> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<1> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<2> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<3> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<196> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<197> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<198> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<199> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<24> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<25> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<26> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<27> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<252> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<253> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<254> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<255> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<148> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<149> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<150> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<151> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gco - nvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gco - nvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gco - nvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gco - nvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<64> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<65> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<66> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<67> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<248> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<249> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<250> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<251> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<200> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<201> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<202> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<203> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<28> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<29> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<30> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<31> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<244> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<245> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<246> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<247> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<144> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<145> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<146> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<147> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<68> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<69> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<70> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<71> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconv - fifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<204> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<205> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<206> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<207> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<240> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<241> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<242> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<243> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/reset_f_edge/iDOUT<1> has no load. PAR will not attempt to route - this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<32> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<33> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<34> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<35> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/reset_f_edge/iDOUT<1> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<236> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<237> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<238> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<239> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<140> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<141> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<142> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<143> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<148> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<149> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<150> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<151> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<232> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<233> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<234> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<235> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<208> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<209> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<210> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<211> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<144> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<145> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<146> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<147> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<72> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<73> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<74> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<75> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<228> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<229> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<230> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<231> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<140> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<141> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<142> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<143> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<152> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<153> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<154> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<155> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<228> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<229> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<230> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<231> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<36> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<37> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<38> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<39> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<137> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<138> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<136> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<139> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<212> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<213> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<214> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<215> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<216> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<217> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<218> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<219> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<224> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<225> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<226> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<227> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<156> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<157> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<158> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<159> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<160> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<161> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<162> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<163> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<184> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<185> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<186> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<187> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<176> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<177> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<178> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<179> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<76> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<77> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<78> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<79> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<220> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<221> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<222> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<223> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<136> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<137> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<138> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<139> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<164> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<165> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<166> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<167> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<188> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<189> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<190> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<191> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<168> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<169> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<170> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<171> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<180> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<172> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<181> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<173> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<182> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<174> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<183> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<175> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<224> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<225> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<226> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<227> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<220> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<221> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<222> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<223> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<80> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<81> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<82> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<83> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<197> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<198> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<196> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<199> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<192> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<193> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<194> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<195> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<216> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<217> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<218> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<219> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<208> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<209> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<210> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<211> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<132> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<133> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<134> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<135> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<232> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<233> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<234> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<235> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<204> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<205> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<206> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<207> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<84> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<85> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<86> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<87> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<212> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<213> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<214> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<215> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[0].RAM32M0_RAMA_D1_DPO has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[0].RAM32M0_RAMD_D1_O has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[1].RAM32M0_RAMA_D1_DPO has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/rams[1].RAM32M0_RAMD_D1_O has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<200> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<201> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<202> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<203> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<40> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<41> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<42> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<43> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[37].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_wr_data0/wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[38].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gcon - vfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gcon - vfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gcon - vfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[36].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gcon - vfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[39].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[30].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[29].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[25].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[26].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<128> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<129> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<130> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<131> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[40].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[27].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<88> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<89> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<90> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<91> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<132> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<133> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<134> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<135> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[41].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[42].RAM32M0_RAMA_D1_DPO - has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[42].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[4].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[3].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[28].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[16].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<236> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<237> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<238> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<239> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[6].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[24].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[9].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[15].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[23].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[8].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[5].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[22].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[31].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[20].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[21].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[19].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_xwb_position_calc_core/cmp_wb_position_calc_core/cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvf - ifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<124> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<125> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<126> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<127> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[35].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[34].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[7].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[33].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[32].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[2].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[11].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[12].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[17].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[0].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[1].RAM32M0_RAMA_D1_DPO has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[1].RAM32M0_RAMB_D1_DPO has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/fifo_ram[1].RAM32M0_RAMD_D1_O has no - load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[0].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[18].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[10].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[1].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[14].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.rd_buffer_ram[13].RAM32M0_RAMD_D1_O has - no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.RAM32M0_RAMB_D1_DPO has no load. PAR - will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/xhdl3.RAM32M0_RAMD_D1_O has no load. PAR will - not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<44> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<45> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<46> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<47> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<240> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<241> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<242> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<243> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<128> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<129> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<130> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<131> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<120> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<121> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<122> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<123> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<112> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<113> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<114> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<115> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<116> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<117> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<118> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<119> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<244> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<245> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<246> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<247> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<92> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<93> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<94> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<95> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<252> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<248> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<253> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<249> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<254> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<250> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<255> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<251> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<96> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<92> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<97> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<93> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<98> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<94> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<99> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<95> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<124> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<125> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<126> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<127> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<88> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<89> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<90> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<91> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<84> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<85> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<86> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<87> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<48> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<49> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<50> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<51> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<108> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<109> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<110> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<111> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<100> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<101> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<102> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<103> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<104> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<105> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<106> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<107> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<80> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<81> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<82> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<83> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<112> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<113> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<114> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<115> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<116> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<117> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<118> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<119> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<120> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<121> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<122> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<123> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<52> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<53> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<54> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<55> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<104> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<105> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<106> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<107> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<100> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<96> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<101> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<97> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<102> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<98> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<103> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256/U0/I_VIO/UPDATE<99> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<76> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<77> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<78> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<79> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<108> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<109> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<110> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<111> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<56> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<57> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<58> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<59> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<72> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<73> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<74> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<75> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<60> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<61> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<62> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<63> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<68> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<69> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<70> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<71> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<64> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<65> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<66> has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_chipscope_vio_256_dsp_config/U0/I_VIO/UPDATE<67> has no load. PAR will not attempt to route this signal. -Starting Router - - -Phase 1 : 545379 unrouted; REAL time: 4 mins 4 secs - -Phase 2 : 386219 unrouted; REAL time: 4 mins 40 secs - -Phase 3 : 135550 unrouted; REAL time: 6 mins 22 secs - -Phase 4 : 135700 unrouted; (Setup:132342, Hold:75335, Component Switching Limit:0) REAL time: 7 mins 7 secs - -Updating file: dbe_bpm_dsp.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:128905, Hold:63853, Component Switching Limit:0) REAL time: 10 mins 55 secs - -Phase 6 : 0 unrouted; (Setup:128628, Hold:63853, Component Switching Limit:0) REAL time: 11 mins 22 secs - -Updating file: dbe_bpm_dsp.ncd with current fully routed design. - -Phase 7 : 0 unrouted; (Setup:128628, Hold:63853, Component Switching Limit:0) REAL time: 13 mins 10 secs - -Phase 8 : 0 unrouted; (Setup:128628, Hold:63853, Component Switching Limit:0) REAL time: 13 mins 10 secs - -Phase 9 : 0 unrouted; (Setup:128628, Hold:0, Component Switching Limit:0) REAL time: 13 mins 22 secs - -Phase 10 : 0 unrouted; (Setup:128050, Hold:0, Component Switching Limit:0) REAL time: 13 mins 57 secs -Total REAL time to Router completion: 13 mins 58 secs -Total CPU time to Router completion: 14 mins 46 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -| ser_clk |BUFGCTRL_X0Y29| No | 2476 | 0.326 | 1.940 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_sys | BUFGCTRL_X0Y7| No | 2186 | 0.446 | 2.048 | -+---------------------+--------------+------+------+------------+-------------+ -| memc_ui_clk |BUFGCTRL_X0Y25| No | 2719 | 0.351 | 1.953 | -+---------------------+--------------+------+------+------------+-------------+ -|fmc_130m_4ch_clk2x<1 | | | | | | -| > | BUFGCTRL_X0Y0| No |16897 | 0.440 | 2.020 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/a | | | | | | -| dc_out[0]_adc_clk | BUFGCTRL_X0Y1| No | 2655 | 0.460 | 2.046 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<0> |BUFGCTRL_X0Y24| No | 1204 | 0.447 | 2.045 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/p | | | | | | -| cie_core_i/pipe_clk |BUFGCTRL_X0Y30| No | 164 | 0.394 | 2.046 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_rsync<1> | Regional Clk|Yes | 437 | 0.219 | 1.062 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_rsync<0> | Regional Clk|Yes | 288 | 0.176 | 1.014 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/p | | | | | | -| cie_core_i/drp_clk |BUFGCTRL_X0Y31| No | 14 | 0.386 | 2.046 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[3]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 14 | 0.223 | 1.073 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[2]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 7 | 0.205 | 1.056 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[1]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 8 | 0.300 | 1.207 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[0]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 8 | 0.203 | 1.056 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_gen_bufg | BUFGCTRL_X0Y3| No | 5 | 0.006 | 1.823 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/p | | | | | | -|cie_core_i/TxOutClk_ | | | | | | -| bufg |BUFGCTRL_X0Y27| No | 6 | 0.023 | 1.633 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_iodelay_ | | | | | | -| ctrl/clk_ref_bufg | BUFGCTRL_X0Y5| No | 6 | 0.123 | 1.711 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -| _ddr_core/clk_mem |BUFGCTRL_X0Y26| No | 187 | 0.164 | 1.901 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_200mhz | BUFGCTRL_X0Y4| No | 6 | 0.260 | 1.826 | -+---------------------+--------------+------+------+------------+-------------+ -| mtx_clk_pad_i_IBUF | Local| | 92 | 5.003 | 5.972 | -+---------------------+--------------+------+------+------------+-------------+ -| mrx_clk_pad_i_IBUF | Local| | 96 | 3.969 | 5.184 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL6<13> | Local| | 5 | 0.000 | 0.654 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_2883_ML_N | | | | | | -| EW_CLK | Local| | 3 | 0.465 | 0.829 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_2875_ML_N | | | | | | -| EW_CLK | Local| | 3 | 0.242 | 0.756 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/p | | | | | | -|cie_core_i/pcie_cloc | | | | | | -|king_i/mmcm_adv_i_ML | | | | | | -| _NEW_OUT | Local| | 2 | 0.000 | 0.236 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_infrastr | | | | | | -|ucture/u_mmcm_adv_ML | | | | | | -| _NEW_OUT | Local| | 2 | 0.000 | 0.351 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_2891_ML_N | | | | | | -| EW_CLK | Local| | 3 | 0.437 | 0.791 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_2899_ML_N | | | | | | -| EW_CLK | Local| | 3 | 0.132 | 0.601 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/gen | | | | | | -|_clock_chains[1].gen | | | | | | -|_clock_chains_check. | | | | | | -|cmp_fmc_adc_clk/gen_ | | | | | | -|with_ref_clk.cmp_mmc | | | | | | -|m_adc_clk_ML_NEW_OUT | | | | | | -| | Local| | 2 | 0.000 | 0.235 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_OUT | Local| | 2 | 0.000 | 0.355 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL3<13> | Local| | 5 | 0.000 | 0.543 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_chipscope_icon_1 | | | | | | -| 3/U0/iUPDATE_OUT | Local| | 1 | 0.000 | 2.332 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<13> | Local| | 5 | 0.000 | 0.683 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_I1 | Local| | 3 | 0.000 | 1.285 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/p | | | | | | -|cie_core_i/pcie_cloc | | | | | | -|king_i/mmcm_adv_i_ML | | | | | | -| _NEW_I1 | Local| | 3 | 0.000 | 2.425 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_infrastr | | | | | | -|ucture/u_mmcm_adv_ML | | | | | | -| _NEW_I1 | Local| | 3 | 0.000 | 0.877 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/gen | | | | | | -|_clock_chains[1].gen | | | | | | -|_clock_chains_check. | | | | | | -|cmp_fmc_adc_clk/gen_ | | | | | | -|with_ref_clk.cmp_mmc | | | | | | -| m_adc_clk_ML_NEW_I1 | Local| | 3 | 0.000 | 0.809 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL7<13> | Local| | 5 | 0.000 | 0.354 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL4<13> | Local| | 5 | 0.000 | 0.630 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL1<13> | Local| | 5 | 0.000 | 0.366 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL2<13> | Local| | 4 | 0.000 | 0.229 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL5<13> | Local| | 5 | 0.000 | 1.203 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL8<13> | Local| | 4 | 0.000 | 0.367 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL9<13> | Local| | 5 | 0.000 | 0.367 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL10<13> | Local| | 5 | 0.000 | 0.363 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<7> | Local| | 16 | 0.011 | 1.310 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/clk_rd_bas | | | | | | -| e | Local| | 10 | 0.271 | 1.428 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<6> | Local| | 16 | 0.000 | 1.288 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<5> | Local| | 16 | 0.011 | 1.310 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<4> | Local| | 16 | 0.011 | 1.310 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<3> | Local| | 16 | 0.000 | 1.288 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<2> | Local| | 16 | 0.011 | 1.310 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<0> | Local| | 18 | 0.011 | 1.310 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/u | | | | | | -|_ddr_core/u_memc_ui_ | | | | | | -|top/u_mem_intfc/phy_ | | | | | | -| top0/clk_cpt<1> | Local| | 16 | 0.000 | 1.288 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_bpm_pcie_ml605/s | | | | | | -| ys_clk_c | Local| | 8 | 0.000 | 1.600 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -* The fanout is the number of component pins not the individual BEL loads, -for example SLICE loads not FF loads. - -Timing Score: 128050 (Setup: 128050, Hold: 0, Component Switching Limit: 0) - -WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. - - Review the timing report using Timing Analyzer (In ISE select "Post-Place & - Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. - - Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options - are set in the tools for timing closure. - - Use the Xilinx "SmartXplorer" script to try special combinations of - options known to produce very good results. - - Visit the Xilinx technical support web at http://support.xilinx.com and go to - either "Troubleshoot->Tech Tips->Timing & Constraints" or " - TechXclusives->Timing Closure" for tips and suggestions for meeting timing - in your design. - -Number of Timing Constraints that were not applied: 187 - -Asterisk (*) preceding a constraint indicates it was not met. - This may be due to a setup or hold violation. - ----------------------------------------------------------------------------------------------------------- - Constraint | Check | Worst Case | Best Case | Timing | Timing - | | Slack | Achievable | Errors | Score ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0. | SETUP | -3.337ns| 2.637ns| 16| 41117 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 8.211ns| | 0| 0 - c_adc0_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0. | SETUP | -2.628ns| 1.928ns| 16| 26675 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 5.790ns| | 0| 0 - c_adc1_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0. | SETUP | -2.596ns| 1.896ns| 16| 31196 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 7.675ns| | 0| 0 - c_adc3_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0. | SETUP | -1.865ns| 1.165ns| 16| 25261 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 7.798ns| | 0| 0 - c_adc2_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TS_cmp_bpm_pcie_ml605_u_ddr_core_u_infras | SETUP | -0.285ns| 5.285ns| 7| 696 - tructure_clk_pll_1 = PERIOD TIMEGRP | HOLD | 0.022ns| | 0| 0 - "cmp_bpm_pcie_ml605_u_ddr_core_u_infra | | | | | - structure_clk_pll_1" TS_cmp_sys_p | | | | | - ll_inst_s_clk1 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- -* TS_cmp_xwb_fmc130m_4ch_cmp_wb_fmc130m_4ch | SETUP | -0.162ns| 4.602ns| 35| 3105 - _cmp_fmc_adc_iface_gen_clock_chains_1__ge | HOLD | 0.008ns| | 0| 0 - n_clock_chains_check_cmp_fmc_adc_clk_adc_ | | | | | - clk2x_mmcm_out = PERIOD TIMEGRP | | | | | - "cmp_xwb_fmc130m_4ch_cmp_wb_fmc130 | | | | | - m_4ch_cmp_fmc_adc_iface_gen_clock_chains_ | | | | | - 1__gen_clock_chains_check_cmp_fmc_adc_clk | | | | | - _adc_clk2x_mmcm_out" TS_fmc_adc1_ | | | | | - clk_i / 2 HIGH 50% INPUT_JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc130m_4ch_cmp_wb_fmc130m_4ch | SETUP | 0.002ns| 8.878ns| 0| 0 - _cmp_fmc_adc_iface_gen_clock_chains_1__ge | HOLD | 0.011ns| | 0| 0 - n_clock_chains_check_cmp_fmc_adc_clk_adc_ | | | | | - clk_mmcm_out = PERIOD TIMEGRP | | | | | - "cmp_xwb_fmc130m_4ch_cmp_wb_fmc130m_ | | | | | - 4ch_cmp_fmc_adc_iface_gen_clock_chains_1_ | | | | | - _gen_clock_chains_check_cmp_fmc_adc_clk_a | | | | | - dc_clk_mmcm_out" TS_fmc_adc1_clk_ | | | | | - i HIGH 50% INPUT_JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_sys_pll_inst_s_clk0 = PERIOD TIMEG | SETUP | 0.054ns| 9.946ns| 0| 0 - RP "cmp_sys_pll_inst_s_clk0" TS_s | HOLD | 0.017ns| | 0| 0 - ys_clk_group / 0.5 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_clk_sys_to_ddr3_ui_clk = MAXDELAY FROM | SETUP | 0.112ns| 9.888ns| 0| 0 - TIMEGRP "TNM_clk_sys_group_ffs" TO | HOLD | 0.130ns| | 0| 0 - TIMEGRP "TNM_ddr_sys_clk" 10 ns DATAPA | | | | | - THONLY | | | | | ----------------------------------------------------------------------------------------------------------- - TS_clk_rsync = PERIOD TIMEGRP "TNM_clk_rs | SETUP | 0.118ns| 4.882ns| 0| 0 - ync" 5 ns HIGH 50% | HOLD | 0.081ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | 0.191ns| 7.809ns| 0| 0 - SYSCLK * 1.25 HIGH 50% PRIORITY 1 | HOLD | 0.011ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_sys_clk200_group = PERIOD TIMEGRP "sys | MINPERIOD | 0.239ns| 4.761ns| 0| 0 - _clk200_group" 5 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_200mhz_sys_clk = PERIOD TIMEGRP "TNM_2 | MINPERIOD | 0.239ns| 4.761ns| 0| 0 - 00mhz_sys_clk" 5 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_sys_pll_inst_s_clk1 = PERIOD TIMEG | SETUP | 0.763ns| 4.237ns| 0| 0 - RP "cmp_sys_pll_inst_s_clk1" TS_s | HOLD | 0.112ns| | 0| 0 - ys_clk_group HIGH 50% | MINPERIOD | 0.239ns| 4.761ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - Pin to Pin Skew Constraint | MAXDELAY | 0.262ns| 0.450ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_clk_cc71cef7 = PERIOD TIMEGRP "clk_cc7 | MINPERIOD | 0.636ns| 3.805ns| 0| 0 - 1cef7" 4.44116092 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2_cc71cef | SETUP | 0.764ns| 8.118ns| 0| 0 - 7_group = MAXDELAY FROM TIMEGRP " | HOLD | 0.331ns| | 0| 0 - ce_2224_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_u_infras | MINPERIOD | 1.071ns| 1.429ns| 0| 0 - tructure_clk_mem_pll = PERIOD TIMEGRP | | | | | - "cmp_bpm_pcie_ml605_u_ddr_core_u_inf | | | | | - rastructure_clk_mem_pll" TS_sys_c | | | | | - lk200_group / 2 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_u_infras | MINPERIOD | 1.071ns| 1.429ns| 0| 0 - tructure_clk_mem_pll_1 = PERIOD T | | | | | - IMEGRP "cmp_bpm_pcie_ml605_u_ddr_core_u_i | | | | | - nfrastructure_clk_mem_pll_1" TS_c | | | | | - mp_sys_pll_inst_s_clk1 / 2 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_u_infras | MINPERIOD | 1.071ns| 1.429ns| 0| 0 - tructure_clk_mem_pll_0 = PERIOD T | | | | | - IMEGRP "cmp_bpm_pcie_ml605_u_ddr_core_u_i | | | | | - nfrastructure_clk_mem_pll_0" TS_2 | | | | | - 00mhz_sys_clk / 2 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_2_cc7 | SETUP | 2.057ns| 6.825ns| 0| 0 - 1cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.228ns| | 0| 0 - "ce_22240000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_2_cc71cef7_group" 8.8823218 | | | | | - 4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_sys_clk_group = PERIOD TIMEGRP "sys_cl | SETUP | 2.269ns| 2.731ns| 0| 0 - k_group" 5 ns HIGH 50% | HOLD | 0.160ns| | 0| 0 - | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_u_infras | MINPERIOD | 2.500ns| 2.500ns| 0| 0 - tructure_clk_pll = PERIOD TIMEGRP | | | | | - "cmp_bpm_pcie_ml605_u_ddr_core_u_infrast | | | | | - ructure_clk_pll" TS_sys_clk200_gr | | | | | - oup HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_u_infras | MINPERIOD | 2.500ns| 2.500ns| 0| 0 - tructure_clk_pll_0 = PERIOD TIMEGRP | | | | | - "cmp_bpm_pcie_ml605_u_ddr_core_u_infra | | | | | - structure_clk_pll_0" TS_200mhz_sy | | | | | - s_clk HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ddr_sys_clk = PERIOD TIMEGRP "TNM_ddr_ | MINPERIOD | 2.500ns| 2.500ns| 0| 0 - sys_clk" 5 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc1_clk_i = PERIOD TIMEGRP "fmc_a | MINLOWPULSE | 4.880ns| 4.000ns| 0| 0 - dc1_clk_i" 8.88 ns HIGH 50% INPUT | | | | | - _JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_2_cc | SETUP | 3.116ns| 5.766ns| 0| 0 - 71cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.183ns| | 0| 0 - "ce_222400000_cc71cef7_group" TO TIME | | | | | - GRP "ce_2_cc71cef7_group" 8.88232 | | | | | - 184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2_cc71cef7_ | SETUP | 3.676ns| 5.206ns| 0| 0 - group = MAXDELAY FROM TIMEGRP "ce | HOLD | 0.182ns| | 0| 0 - _70_cc71cef7_group" TO TIMEGRP "ce_2_cc71 | | | | | - cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2224_cc71cef | SETUP | 4.126ns| 4.756ns| 0| 0 - 7_group = MAXDELAY FROM TIMEGRP " | HOLD | 0.967ns| | 0| 0 - ce_2_cc71cef7_group" TO TIMEGRP "ce_2224_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2_cc71cef7_g | SETUP | 4.846ns| 4.036ns| 0| 0 - roup = MAXDELAY FROM TIMEGRP "ce_ | HOLD | 0.019ns| | 0| 0 - 2_cc71cef7_group" TO TIMEGRP "ce_2_cc71ce | | | | | - f7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc3_clk_i = PERIOD TIMEGRP "fmc_a | MINPERIOD | 5.548ns| 3.332ns| 0| 0 - dc3_clk_i" 8.88 ns HIGH 50% INPUT | | | | | - _JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc2_clk_i = PERIOD TIMEGRP "fmc_a | MINPERIOD | 5.548ns| 3.332ns| 0| 0 - dc2_clk_i" 8.88 ns HIGH 50% INPUT | | | | | - _JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc0_clk_i = PERIOD TIMEGRP "fmc_a | MINPERIOD | 5.548ns| 3.332ns| 0| 0 - dc0_clk_i" 8.88 ns HIGH 50% INPUT | | | | | - _JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_5000_cc71cef | SETUP | 5.673ns| 3.209ns| 0| 0 - 7_group = MAXDELAY FROM TIMEGRP " | HOLD | 0.688ns| | 0| 0 - ce_2_cc71cef7_group" TO TIMEGRP "ce_5000_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_TXOUTCLKBUFG = PERIOD TIMEGRP "TXOUTCL | SETUP | 6.151ns| 3.849ns| 0| 0 - KBUFG" 100 MHz HIGH 50% PRIORITY 100 | HOLD | 0.143ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_70_cc71cef7_ | SETUP | 6.517ns| 2.365ns| 0| 0 - group = MAXDELAY FROM TIMEGRP "ce | HOLD | 0.374ns| | 0| 0 - _2_cc71cef7_group" TO TIMEGRP "ce_70_cc71 | | | | | - cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_clk_sys_group = PERIOD TIMEGRP "clk_sy | MINPERIOD | 7.500ns| 2.500ns| 0| 0 - s_group" 10 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_SYSCLK = PERIOD TIMEGRP "SYSCLK" 100 M | MINPERIOD | 8.462ns| 1.538ns| 0| 0 - Hz HIGH 50% PRIORITY 100 | | | | | ----------------------------------------------------------------------------------------------------------- - TS_clk_rsync_rise_to_fall = MAXDELAY FROM | SETUP | 16.769ns| 3.231ns| 0| 0 - TIMEGRP "TG_clk_rsync_rise" TO T | HOLD | 0.278ns| | 0| 0 - IMEGRP "TG_clk_rsync_fall" TS_ddr_sys_clk | | | | | - * 4 | | | | | ----------------------------------------------------------------------------------------------------------- - TS_MC_PHY_INIT_SEL = MAXDELAY FROM TIMEGR | SETUP | 33.405ns| 6.595ns| 0| 0 - P "TNM_PHY_INIT_SEL" TO TIMEGRP "FFS" | HOLD | 0.296ns| | 0| 0 - TS_ddr_sys_clk * 8 | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_35_cc71cef7 | SETUP | 149.451ns| 5.989ns| 0| 0 - _group = MAXDELAY FROM TIMEGRP "c | HOLD | 0.066ns| | 0| 0 - e_35_cc71cef7_group" TO TIMEGRP "ce_35_cc | | | | | - 71cef7_group" 155.440632 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_70_cc71cef7 | SETUP | 151.800ns| 3.640ns| 0| 0 - _group = MAXDELAY FROM TIMEGRP "c | HOLD | 0.073ns| | 0| 0 - e_35_cc71cef7_group" TO TIMEGRP "ce_70_cc | | | | | - 71cef7_group" 155.440632 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_70_cc71cef7 | SETUP | 307.011ns| 3.870ns| 0| 0 - _group = MAXDELAY FROM TIMEGRP "c | HOLD | 0.049ns| | 0| 0 - e_70_cc71cef7_group" TO TIMEGRP "ce_70_cc | | | | | - 71cef7_group" 310.881264 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_556_cc71ce | SETUP | 2466.378ns| 2.907ns| 0| 0 - f7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.187ns| | 0| 0 - "ce_556_cc71cef7_group" TO TIMEGRP "ce_55 | | | | | - 6_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_556_cc71c | SETUP | 2467.129ns| 2.156ns| 0| 0 - ef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.116ns| | 0| 0 - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_1112_cc71 | SETUP | 4932.445ns| 6.125ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.022ns| | 0| 0 - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 4938.57094 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2224_cc71 | SETUP | 4936.042ns| 2.528ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.167ns| | 0| 0 - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 4938.57094 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2224_cc71 | SETUP | 9872.308ns| 4.833ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.052ns| | 0| 0 - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 9877.14188 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_2500_ | SETUP | 11097.497ns| 5.405ns| 0| 0 - cc71cef7_group = MAXDELAY FROM TI | HOLD | 0.142ns| | 0| 0 - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_2500_cc71cef7_group" 111 | | | | | - 02.9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_5560000_c | SETUP | 11101.765ns| 1.137ns| 0| 0 - c71cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.071ns| | 0| 0 - "ce_2500_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 11102 | | | | | - .9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_22240000_ | SETUP | 22201.206ns| 4.598ns| 0| 0 - cc71cef7_group = MAXDELAY FROM TI | HOLD | 0.088ns| | 0| 0 - MEGRP "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 222 | | | | | - 05.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_139000 | SETUP | 2147476.292ns| 7.356ns| 0| 0 - 0_cc71cef7_group = MAXDELAY FROM | HOLD | 0.319ns| | 0| 0 - TIMEGRP "ce_1390000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_1390000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_556000 | SETUP | 2147478.466ns| 5.182ns| 0| 0 - 0_cc71cef7_group = MAXDELAY FROM | HOLD | 0.085ns| | 0| 0 - TIMEGRP "ce_5560000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_5560000_cc71cef7_group" | | | | | - 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_22240 | SETUP | 2147479.808ns| 3.840ns| 0| 0 - 000_cc71cef7_group = MAXDELAY FROM | HOLD | 0.033ns| | 0| 0 - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_22240000_cc71cef7_gr | | | | | - oup" 98771418.8 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_278000 | SETUP | 2147480.298ns| 3.350ns| 0| 0 - 0_cc71cef7_group = MAXDELAY FROM | HOLD | 0.104ns| | 0| 0 - TIMEGRP "ce_2780000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_2780000_cc71cef7_group" | | | | | - 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_22240 | SETUP | 2147480.383ns| 3.265ns| 0| 0 - 0000_cc71cef7_group = MAXDELAY FROM | HOLD | 0.088ns| | 0| 0 - TIMEGRP "ce_55600000_cc71cef7_group" T | | | | | - O TIMEGRP "ce_222400000_cc71cef7_ | | | | | - group" 246928547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_55600 | SETUP | 2147480.479ns| 3.169ns| 0| 0 - 000_cc71cef7_group = MAXDELAY FROM | HOLD | 0.107ns| | 0| 0 - TIMEGRP "ce_55600000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_55600000_cc71cef7_gr | | | | | - oup" 246928547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_2224 | SETUP | 2147481.345ns| 2.303ns| 0| 0 - 00000_cc71cef7_group = MAXDELAY FROM | HOLD | 0.696ns| | 0| 0 - TIMEGRP "ce_222400000_cc71cef7_group" | | | | | - TO TIMEGRP "ce_222400000_cc71cef | | | | | - 7_group" 987714188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_222400 | SETUP | 2147482.213ns| 1.435ns| 0| 0 - 00_cc71cef7_group = MAXDELAY FROM | HOLD | 0.069ns| | 0| 0 - TIMEGRP "ce_5560000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_22240000_cc71cef7_grou | | | | | - p" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 44.4116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_1112_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_55600000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_1112_cc71cef7_group" 493 | | | | | - 8.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_13900 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_55600000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_1390000_cc71cef7_grou | | | | | - p" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_22240 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_55600000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_22240000_cc71cef7_gr | | | | | - oup" 49385709.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_2224_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_55600000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_2224_cc71cef7_group" 987 | | | | | - 7.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_222400000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "c | | | | | - e_222400000_cc71cef7_group" 22.20 | | | | | - 58046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_2500_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_55600000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_2500_cc71cef7_group" 111 | | | | | - 02.9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_27800 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_55600000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_2780000_cc71cef7_grou | | | | | - p" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_2_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_2_cc71cef7_group" 8.8823218 | | | | | - 4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_35_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_35_cc71cef7_group" 22.2058 | | | | | - 046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_5000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_55600000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_5000_cc71cef7_group" 222 | | | | | - 05.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_55600 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_55600000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_5560000_cc71cef7_grou | | | | | - p" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_556_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" TO TIME | | | | | - GRP "ce_556_cc71cef7_group" 2469. | | | | | - 28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_55600000_cc71cef7_group_to_ce_70_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_70_cc71cef7_group" 44.4116 | | | | | - 092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_1112_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_1112_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_139000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_5560000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_1390000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2780000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 2780000_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_ | N/A | N/A| N/A| N/A| N/A - group = MAXDELAY FROM TIMEGRP "ce | | | | | - _35_cc71cef7_group" TO TIMEGRP "ce_2_cc71 | | | | | - cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_22240000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce | | | | | - _22240000_cc71cef7_group" 22.2058 | | | | | - 046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_5000_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_500 | | | | | - 0_cc71cef7_group" 22.2058046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_55600000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce | | | | | - _55600000_cc71cef7_group" 22.2058 | | | | | - 046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_5560000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 5560000_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_556_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_35_cc71cef7_group" TO TIMEGRP "ce_556_ | | | | | - cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_1112_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_222400000 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_5000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_222400000_cc71cef7_group" 2 | | | | | - 2205.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2500_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_250 | | | | | - 0_cc71cef7_group" 22.2058046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2224_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2500_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2500_cc71cef7_group" 11102.9023 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_5000_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 22.2058046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_55600000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" 222 | | | | | - 05.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_5560000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2224_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_222 | | | | | - 4_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_556_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 17.7646437 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_5560000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "c | | | | | - e_5560000_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_70_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_556_cc71cef7_group" TO TIMEGRP "ce_70_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_1112_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_111 | | | | | - 2_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_1390000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 1390000_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_222400000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "c | | | | | - e_222400000_cc71cef7_group" 44.41 | | | | | - 16092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_22240000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce | | | | | - _22240000_cc71cef7_group" 44.4116 | | | | | - 092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2224_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_222 | | | | | - 4_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2500_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_250 | | | | | - 0_cc71cef7_group" 44.4116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2780000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 2780000_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_222400000 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_1112_cc71cef7_group" TO TIMEGR | | | | | - P "ce_222400000_cc71cef7_group" 4 | | | | | - 938.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7 | N/A | N/A| N/A| N/A| N/A - _group = MAXDELAY FROM TIMEGRP "c | | | | | - e_70_cc71cef7_group" TO TIMEGRP "ce_35_cc | | | | | - 71cef7_group" 155.440632 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_5000_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_500 | | | | | - 0_cc71cef7_group" 44.4116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_55600000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce | | | | | - _55600000_cc71cef7_group" 44.4116 | | | | | - 092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_5560000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 5560000_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_556_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_70_cc71cef7_group" TO TIMEGRP "ce_556_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_clk_rd_b | N/A | N/A| N/A| N/A| N/A - ase = PERIOD TIMEGRP "cmp_bpm_pci | | | | | - e_ml605_u_ddr_core_clk_rd_base" TS_sys_cl | | | | | - k200_group / 2 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_5000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 22205.8046 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_clk_rd_b | N/A | N/A| N/A| N/A| N/A - ase_0 = PERIOD TIMEGRP "cmp_bpm_p | | | | | - cie_ml605_u_ddr_core_clk_rd_base_0" TS_20 | | | | | - 0mhz_sys_clk / 2 HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_2500_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2500_cc71cef7_group" 11102.9023 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_bpm_pcie_ml605_u_ddr_core_clk_rd_b | N/A | N/A| N/A| N/A| N/A - ase_1 = PERIOD TIMEGRP "cmp_bpm_p | | | | | - cie_ml605_u_ddr_core_clk_rd_base_1" | | | | | - TS_cmp_sys_pll_inst_s_clk1 / 2 HIGH 50 | | | | | - % | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_5560000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_222400000_cc71cef7_gr | | | | | - oup" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_2224_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2224_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_2500_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2500_cc71cef7_group" 11102 | | | | | - .9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_278000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_5560000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_2780000_cc71cef7_group" | | | | | - 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_2_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_35_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_35_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_5000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_5000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_5560000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_55600000_cc71cef7_grou | | | | | - p" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_556_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_556_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_70_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_70_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_1112_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1 | | | | | - 112_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_1390000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "c | | | | | - e_1390000_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_222400000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_556_cc71cef7_group" TO TIMEGRP | | | | | - "ce_222400000_cc71cef7_group" 246 | | | | | - 9.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_22240000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP " | | | | | - ce_22240000_cc71cef7_group" 2469. | | | | | - 28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2224_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2 | | | | | - 224_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2500_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2 | | | | | - 500_cc71cef7_group" 17.7646437 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2780000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "c | | | | | - e_2780000_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7 | N/A | N/A| N/A| N/A| N/A - _group = MAXDELAY FROM TIMEGRP "c | | | | | - e_556_cc71cef7_group" TO TIMEGRP "ce_2_cc | | | | | - 71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_35_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_556_cc71cef7_group" TO TIMEGRP "ce_35_ | | | | | - cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_5000_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5 | | | | | - 000_cc71cef7_group" 17.7646437 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_55600000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP " | | | | | - ce_55600000_cc71cef7_group" 2469. | | | | | - 28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_35_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_222400000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_35_cc71cef7_group" 22.20 | | | | | - 58046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_5000 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_222400000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_5000_cc71cef7_group" 2 | | | | | - 2205.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_5560 | N/A | N/A| N/A| N/A| N/A - 0000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_222400000_cc71cef7_group" | | | | | - TO TIMEGRP "ce_55600000_cc71cef7_ | | | | | - group" 246928547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_5560 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_222400000_cc71cef7_group" T | | | | | - O TIMEGRP "ce_5560000_cc71cef7_gr | | | | | - oup" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_556_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_222400000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_556_cc71cef7_group" 246 | | | | | - 9.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_70_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_222400000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_70_cc71cef7_group" 44.41 | | | | | - 16092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_1112_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_1112_cc71cef7_group" 493 | | | | | - 8.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_13900 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_1390000_cc71cef7_grou | | | | | - p" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_22240 | N/A | N/A| N/A| N/A| N/A - 0000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" T | | | | | - O TIMEGRP "ce_222400000_cc71cef7_ | | | | | - group" 98771418.8 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_2224_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_2224_cc71cef7_group" 987 | | | | | - 7.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_27800 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_2780000_cc71cef7_grou | | | | | - p" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_1112_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_35_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_35_cc71cef7_group" 22.2058 | | | | | - 046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_5000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_5000_cc71cef7_group" 222 | | | | | - 05.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_55600 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_55600000_cc71cef7_gr | | | | | - oup" 49385709.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_55600 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_5560000_cc71cef7_grou | | | | | - p" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_556_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" TO TIME | | | | | - GRP "ce_556_cc71cef7_group" 2469. | | | | | - 28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_70_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_70_cc71cef7_group" 44.4116 | | | | | - 092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_1112_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 4938.57094 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_222400000 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_2224_cc71cef7_group" TO TIMEGR | | | | | - P "ce_222400000_cc71cef7_group" 9 | | | | | - 877.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_22240000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 987 | | | | | - 7.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_5000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_55600000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" 493 | | | | | - 8.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_5560000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_556_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_1112_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_1112_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_222400000_cc71cef7_gr | | | | | - oup" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_22240000_cc71cef7_grou | | | | | - p" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_2224_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2224_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_2500_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2500_cc71cef7_group" 11102 | | | | | - .9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_278000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_2780000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_2_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_35_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_35_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_5000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_5000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_55600000_cc71cef7_grou | | | | | - p" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_5560000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_556_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_556_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_70_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_70_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_1112 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_222400000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_1112_cc71cef7_group" 4 | | | | | - 938.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_1390 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_222400000_cc71cef7_group" T | | | | | - O TIMEGRP "ce_1390000_cc71cef7_gr | | | | | - oup" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_2224 | N/A | N/A| N/A| N/A| N/A - 0000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_222400000_cc71cef7_group" | | | | | - TO TIMEGRP "ce_22240000_cc71cef7_ | | | | | - group" 98771418.8 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_2224 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_222400000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_2224_cc71cef7_group" 9 | | | | | - 877.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_2500 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_222400000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_2500_cc71cef7_group" 1 | | | | | - 1102.9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_222400000_cc71cef7_group_to_ce_2780 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_222400000_cc71cef7_group" T | | | | | - O TIMEGRP "ce_2780000_cc71cef7_gr | | | | | - oup" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_2224_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2224_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_2500_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2500_cc71cef7_group" 11102 | | | | | - .9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_2_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_35_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_35_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_5000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_5000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_55600000_cc71cef7_grou | | | | | - p" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_5560000_cc71cef7_group" | | | | | - 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_556_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_556_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_70_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_70_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_2_cc71cef7_group" TO TIMEGRP "ce_1112_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_1390000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_13 | | | | | - 90000_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_222400000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 222400000_cc71cef7_group" 8.88232 | | | | | - 184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_22240000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_2 | | | | | - 2240000_cc71cef7_group" 8.8823218 | | | | | - 4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2500_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2500_cc71cef7_group" 17.7646437 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2500_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_2_cc71cef7_group" TO TIMEGRP "ce_2500_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2780000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_27 | | | | | - 80000_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_ | N/A | N/A| N/A| N/A| N/A - group = MAXDELAY FROM TIMEGRP "ce | | | | | - _2_cc71cef7_group" TO TIMEGRP "ce_35_cc71 | | | | | - cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_55600000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_5 | | | | | - 5600000_cc71cef7_group" 8.8823218 | | | | | - 4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_5560000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_55 | | | | | - 60000_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7 | N/A | N/A| N/A| N/A| N/A - _group = MAXDELAY FROM TIMEGRP "c | | | | | - e_2_cc71cef7_group" TO TIMEGRP "ce_556_cc | | | | | - 71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_22240000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 493 | | | | | - 8.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_1112_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_111 | | | | | - 2_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_1390000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 1390000_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2500_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2500_cc71cef7_group" 17.7646437 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_5000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_55600000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" 987 | | | | | - 7.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_5560000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_1112_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 17.7646437 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 11102 | | | | | - .9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_222400000 | N/A | N/A| N/A| N/A| N/A - _cc71cef7_group = MAXDELAY FROM T | | | | | - IMEGRP "ce_2500_cc71cef7_group" TO TIMEGR | | | | | - P "ce_222400000_cc71cef7_group" 1 | | | | | - 1102.9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_22240000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_2500_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 111 | | | | | - 02.9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_2224_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 17.7646437 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 11102 | | | | | - .9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_2_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_2500_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 22.2058046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_5000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 11102.9023 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_55600000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_2500_cc71cef7_group" TO TIMEGRP | | | | | - "ce_55600000_cc71cef7_group" 111 | | | | | - 02.9023 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_556_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 17.7646437 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2500_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2500_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 44.4116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_1112_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_1112_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_139000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_1390000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 000_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_222400000_cc71cef7_gr | | | | | - oup" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_22240000_cc71cef7_grou | | | | | - p" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - - -Derived Constraint Report -Review Timing Report for more details on the following derived constraints. -To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" -or "Run Timing Analysis" from Timing Analyzer (timingan). -Derived Constraints for TS_sys_clk200_group -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_sys_clk200_group | 5.000ns| 4.761ns| 2.858ns| 0| 0| 0| 0| -| TS_cmp_bpm_pcie_ml605_u_ddr_co| 5.000ns| 2.500ns| N/A| 0| 0| 0| 0| -| re_u_infrastructure_clk_pll | | | | | | | | -| TS_cmp_bpm_pcie_ml605_u_ddr_co| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| -| re_u_infrastructure_clk_mem_pl| | | | | | | | -| l | | | | | | | | -| TS_cmp_bpm_pcie_ml605_u_ddr_co| 2.500ns| N/A| N/A| 0| 0| 0| 0| -| re_clk_rd_base | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_sys_clk_group -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_sys_clk_group | 5.000ns| 2.800ns| 5.285ns| 0| 7| 165| 2718668| -| TS_cmp_sys_pll_inst_s_clk1 | 5.000ns| 4.761ns| 5.285ns| 0| 7| 164| 123136| -| TS_cmp_bpm_pcie_ml605_u_ddr_c| 5.000ns| 5.285ns| N/A| 7| 0| 123136| 0| -| ore_u_infrastructure_clk_pll_| | | | | | | | -| 1 | | | | | | | | -| TS_cmp_bpm_pcie_ml605_u_ddr_c| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| -| ore_u_infrastructure_clk_mem_| | | | | | | | -| pll_1 | | | | | | | | -| TS_cmp_bpm_pcie_ml605_u_ddr_c| 2.500ns| N/A| N/A| 0| 0| 0| 0| -| ore_clk_rd_base_1 | | | | | | | | -| TS_cmp_sys_pll_inst_s_clk0 | 10.000ns| 9.946ns| N/A| 0| 0| 2595368| 0| -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_200mhz_sys_clk -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_200mhz_sys_clk | 5.000ns| 4.761ns| 2.858ns| 0| 0| 0| 0| -| TS_cmp_bpm_pcie_ml605_u_ddr_co| 5.000ns| 2.500ns| N/A| 0| 0| 0| 0| -| re_u_infrastructure_clk_pll_0 | | | | | | | | -| TS_cmp_bpm_pcie_ml605_u_ddr_co| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| -| re_u_infrastructure_clk_mem_pl| | | | | | | | -| l_0 | | | | | | | | -| TS_cmp_bpm_pcie_ml605_u_ddr_co| 2.500ns| N/A| N/A| 0| 0| 0| 0| -| re_clk_rd_base_0 | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_ddr_sys_clk -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_ddr_sys_clk | 5.000ns| 2.500ns| 0.824ns| 0| 0| 0| 914| -| TS_clk_rsync_rise_to_fall | 20.000ns| 3.231ns| N/A| 0| 0| 389| 0| -| TS_MC_PHY_INIT_SEL | 40.000ns| 6.595ns| N/A| 0| 0| 525| 0| -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_fmc_adc1_clk_i -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_fmc_adc1_clk_i | 8.880ns| 4.000ns| 9.204ns| 0| 35| 0| 1096416| -| TS_cmp_xwb_fmc130m_4ch_cmp_wb_| 4.440ns| 4.602ns| N/A| 35| 0| 757949| 0| -| fmc130m_4ch_cmp_fmc_adc_iface_| | | | | | | | -| gen_clock_chains_1__gen_clock_| | | | | | | | -| chains_check_cmp_fmc_adc_clk_a| | | | | | | | -| dc_clk2x_mmcm_out | | | | | | | | -| TS_cmp_xwb_fmc130m_4ch_cmp_wb_| 8.880ns| 8.878ns| N/A| 0| 0| 338467| 0| -| fmc130m_4ch_cmp_fmc_adc_iface_| | | | | | | | -| gen_clock_chains_1__gen_clock_| | | | | | | | -| chains_check_cmp_fmc_adc_clk_a| | | | | | | | -| dc_clk_mmcm_out | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_SYSCLK -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_SYSCLK | 10.000ns| 1.538ns| 9.761ns| 0| 0| 0| 220495| -| TS_CLK_125 | 8.000ns| 7.809ns| N/A| 0| 0| 220495| 0| -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -6 constraints not met. -INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the - constraint is not analyzed due to the following: No paths covered by this - constraint; Other constraints intersect with this constraint; or This - constraint was disabled by a Path Tracing Control. Please run the Timespec - Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. - - -Generating Pad Report. - -All signals are completely routed. - -WARNING:Par:283 - There are 635 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - -Total REAL time to PAR completion: 14 mins 25 secs -Total CPU time to PAR completion: 15 mins 13 secs - -Peak Memory Usage: 3852 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - 106 errors found. - -Number of error messages: 0 -Number of warning messages: 807 -Number of info messages: 2 - -Writing design to file dbe_bpm_dsp.ncd - - - -PAR done! - -Process "Place & Route" completed successfully - -Started : "Generate Programming File". -Running bitgen... -Command Line: bitgen -intstyle ise -f dbe_bpm_dsp.ut dbe_bpm_dsp.ncd -INFO:Bitgen:40 - Replacing "Auto" with "2" for option "Match_cycle". Most - commonly, bitgen has determined and will use a specific value instead of the - generic command-line value of "Auto". Alternately, this message appears if - the same option is specified multiple times on the command-line. In this - case, the option listed last will be used. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL6<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL3<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL7<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL4<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL2<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL5<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL8<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL9<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL10<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load pins in - the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load pins in the - design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load pins in - the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load pins in the - design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive - any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal - does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load - pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any - load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load pins in the - design. -WARNING:PhysDesignRules:367 - The signal - is incomplete. The signal does not drive any load pins in the - design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The signal does - not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - > is incomplete. The - signal does not drive any load pins in the design. -INFO:PhysDesignRules:2172 - Issue with pin connections and/or configuration on - block::. When FIFO18E1 attribute DO_REG is set to - 0, REGCE should be tied to GND to save power. -INFO:PhysDesignRules:2172 - Issue with pin connections and/or configuration on - block::. When FIFO18E1 attribute DO_REG is set to - 0, REGCE should be tied to GND to save power. -WARNING:PhysDesignRules:2045 - The MMCM_ADV block - has CLKOUT pins - that do not drive the same kind of BUFFER loINFO:TclTasksC:1850 - process run : Generate Programming File is done. -ad. Routing from the different - buffer types will not be phase aligned. - -Process "Generate Programming File" completed successfully - -real 113m29.603s -user 115m24.055s -sys 0m16.841s -Sex Fev 28 23:50:26 BRT 2014 diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc516/Manifest.py b/hdl/syn/ml605/dbe_bpm_dsp_fmc516/Manifest.py deleted file mode 100755 index 8482842c..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc516/Manifest.py +++ /dev/null @@ -1,10 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_dsp" -syn_project = "dbe_bpm_dsp.xise" - -modules = { "local" : [ "../../../top/ml_605/dbe_bpm_dsp_fmc516" ] }; diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.xise b/hdl/syn/ml605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.xise deleted file mode 100644 index 832350d0..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.xise +++ /dev/null @@ -1,1614 +0,0 @@ - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_dsp_fmc516/make_output b/hdl/syn/ml605/dbe_bpm_dsp_fmc516/make_output deleted file mode 100644 index a79ad4ba..00000000 --- a/hdl/syn/ml605/dbe_bpm_dsp_fmc516/make_output +++ /dev/null @@ -1,27346 +0,0 @@ -echo "project open dbe_bpm_dsp.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_dsp/dbe_bpm_dsp.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_dsp/dbe_bpm_dsp.syr" -Reading design: dbe_bpm_dsp.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_clockgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_receivecontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 94. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_cop.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" included at line 64. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 65. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 165. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 166. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 87. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_crc.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 74. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" into library work -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 317: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 318: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 322: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 323: Macro is redefined. -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxaddrcheck.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 67. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 42. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_random.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 80. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_maccontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_macstatus.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 112. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xilinx_dist_ram_16x32.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_spram_256x32.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 74. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 83. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 240. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 241. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_outputcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_transmitcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 82. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/dsp_cores_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_common/custom_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xwb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_wfifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_239e4f614ba09ab1.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_26986301a9f671cd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_8b0747970e52f130.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_3ac902fec2d60a4a.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_59fbd17f7e62a7fe.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_d31b0f3a494d423b.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/cmpy_v5_0_fc1d91881e8e8ae6.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/cntr_11_0_3166d4cc5b09c744.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/crdc_v5_0_19fb63dead3076ad.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/dds_cmplr_v5_0_ca0550aac85c1501.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/dv_gn_v4_0_7887f22978e0003d.vhd" into library work -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/dv_gn_v4_0_fc1ee041a30564f8.vhd" into library work -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/fifo_generator_virtex6_8_4_784d0e5148f6dbe1.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_0c61ac74cf3e5cc7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_95e3c24666ebc2c9.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_ef8269b30b0e0deb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_fe47fe6ccabc2305.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/mult_11_2_6d8e463c710483da.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/nonleaf_results.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/perl_results.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "Wishbone slave device #1 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." -Warning: "Wishbone slave device #0 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x3ffe0000]" -Note: "Mapping slave #1[0x10000000/0x3ffe0000]" -Note: "Mapping slave #2[0x20000000/0x3fffc000]" -Note: "Mapping slave #3[0x30004000/0x3fffffe0]" -Note: "Mapping slave #4[0x30005000/0x3ffffe00]" -Note: "Mapping slave #5[0x30006000/0x3fffff00]" -Note: "Mapping slave #6[0x30007000/0x3fffff00]" -Note: "Mapping slave #7[0x30010000/0x3ffff000]" -Note: "Mapping slave #8[0x30020000/0x3ffff000]" -Note: "Mapping slave #9[0x30000000/0x3ffffc00]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE. -Going to verilog side to elaborate module lm32_top_medium_icache_debug - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -Going to vhdl side to elaborate module lm32_ram - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 146: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 147: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 187: Comparison between arrays of unequal length always returns FALSE. -Back to verilog to continue elaboration -Going to vhdl side to elaborate module lm32_ram - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Back to verilog to continue elaboration -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 66223: Assignment to pc_w ignored, since the identifier is never used - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 66289: Assignment to x_result_sel_logic_d ignored, since the identifier is never used - -Elaborating module . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 69491. $display Data bus error. Address: 0 -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 69639. $display Warning: Non-aligned halfword access. Address: 0x0 Time: $time . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 69641. $display Warning: Non-aligned word access. Address: 0x0 Time: $time . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -Going to vhdl side to elaborate module lm32_dp_ram - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 146: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 147: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 187: Comparison between arrays of unequal length always returns FALSE. -Back to verilog to continue elaboration -Going to vhdl side to elaborate module lm32_dp_ram -Back to verilog to continue elaboration - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 64280: Assignment to jrstn ignored, since the identifier is never used -Back to vhdl to continue elaboration -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 123: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 71: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 73: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module ethmac - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" Line 883: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used -"/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted - -Elaborating module . -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" Line 248: Using initial value "00000000000000000000000000000000" for zero_din_width since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -WARNING:UtilitiesC:159 - Message file "usenglish/ip.msg" wasn't found. -INFO:ip - 0: (0,0) : 36x1024 u:32 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 36x1024 u:32 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Assignment ignored -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 509: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 428: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 432: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 168: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 169: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xf00]" -Note: "Mapping slave #1[0x100/0xf00]" -Note: "Mapping slave #2[0x200/0xf00]" -Note: "Mapping slave #3[0x300/0xf00]" -Note: "Mapping slave #4[0x400/0xf00]" -Note: "Mapping slave #5[0x500/0xf00]" -Note: "Mapping slave #6[0x600/0xf00]" -Note: "Mapping slave #7[0x800/0xe00]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 208: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 209: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 210: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 211: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 212: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -Note: "[ map vector(0) = 1 ]" -Note: "[ map vector(1) = 0 ]" -Note: "[ map vector(2) = 0 ]" -Note: "[ map vector(3) = 1 ]" -Note: "[ intercon(0) = 1 ]" -Note: "[ intercon(1) = 0 ]" -Note: "[ intercon(2) = 0 ]" -Note: "[ intercon(3) = 1 ]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd" Line 162: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd" Line 96: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd" Line 97: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" Line 178: Assignment to sys_rst ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" Line 214: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -INFO:ip - 0: (0,0) : 18x1024 u:16 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 18x1024 u:16 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 2776: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 2776: Assignment ignored - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" Line 141: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" Line 90: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_top - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" Line 250: Assignment to three_mode ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" Line 67: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_top - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" Line 250: Assignment to three_mode ignored, since the identifier is never used - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" Line 67: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module sockit_owm - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 192: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 194: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 196: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 199: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 201: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 204: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 206: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 208: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 305: Result of 32-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 392: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 393: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 156: Net does not have a driver. -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" Line 97: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" Line 420: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 1107: Assignment to fmc516_fs_rst_n ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 78612: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 78623: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 78375: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 78387: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82068: Using initial value false for op_mem_22_20_front_din since it is never assigned -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82074: Assignment to op_mem_22_20_back ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82321: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82339: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82340: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82433: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82451: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 82452: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 79514: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 80557: Assignment to internal_core_ce ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 80559: Assignment to nd ignored, since the identifier is never used - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . -WARNING:HDLCompiler:758 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 76823: Replacing existing netlist mult_11_2_6d8e463c710483da() - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 81617: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 81710: Assignment to rst_limit_join_44_1 ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" Line 81821: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture <>) from library . -WARNING:HDLCompiler:758 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/fifo_generator_virtex6_8_4_784d0e5148f6dbe1.vhd" Line 43: Replacing existing netlist fifo_generator_virtex6_8_4_784d0e5148f6dbe1() - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . - -Elaborating entity (architecture <>) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 1245: Assignment to dsp_sysce ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 1246: Assignment to dsp_sysce_clr ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x700]" -Note: "Mapping slave #1[0x100/0x700]" -Note: "Mapping slave #2[0x200/0x700]" -Note: "Mapping slave #3[0x300/0x7f0]" -Note: "Mapping slave #4[0x400/0x600]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" Line 65: Net does not have a driver. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 611: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 624: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 635: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 510: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 511: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 512: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 513: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 517: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 518: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 519: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 520: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 524: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 525: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 526: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 527: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 531: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 532: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 533: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 534: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 538: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 539: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 540: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 541: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 545: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 546: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 547: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" Line 548: Net does not have a driver. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 694: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 694: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 803: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 803: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 803: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 803: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 803: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 803: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 942: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1263: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1263: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.vhd" line 1263: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit tristate buffer for signal created at line 878 - Summary: - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 1 - g_logdelay = 10 - g_syncdepth = 3 - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 14 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 9 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000000000000001100000000001000000100000000000000000000000000000000000000000000110000000000100000000000000000000000000000000000000000000000000011000000000010000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000011000000000001000010000000000000000000000000000000000000000000001100000000000100000000000000000000000000000000000000000000000000110000000000010000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000110000000000000111000000000000000000000000000000000000000000000011000000000000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000001100000000000001100000000000000000000000000000000000000000000000110000000000000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000110000000000000101000000000000000000000000000000000000000000000011000000000000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000110000000000000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010101111 -10011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000001111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_sdb_addr = "00110000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000000000000001100000000001000000100000000000000000000000000000000000000000000110000000000100000000000000000000000000000000000000000000000000011000000000010000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000011000000000001000010000000000000000000000000000000000000000000001100000000000100000000000000000000000000000000000000000000000000110000000000010000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000110000000000000111000000000000000000000000000000000000000000000011000000000000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000001100000000000001100000000000000000000000000000000000000000000000110000000000000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000110000000000000101000000000000000000000000000000000000000000000011000000000000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000110000000000000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010101111 -10011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000001111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000111111111111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value. - Found 256x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 10 - g_registered = true - g_address = ("00110000000000000000000000000000","00110000000000100000000000000000","00110000000000010000000000000000","00110000000000000111000000000000","00110000000000000110000000000000","00110000000000000101000000000000","00110000000000000100000000000000","00100000000000000000000000000000","00010000000000000000000000000000","00000000000000000000000000000000") - g_mask = ("00111111111111111111110000000000","00111111111111111111000000000000","00111111111111111111000000000000","00111111111111111111111100000000","00111111111111111111111100000000","00111111111111111111111000000000","00111111111111111111111111100000","00111111111111111100000000000000","00111111111111100000000000000000","00111111111111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 89 D-type flip-flop(s). - inferred 88 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd". - g_profile = "medium_icache_debug" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. - Found 3-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 688. - Found 32-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 3-bit subtractor for signal > created at line 650. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 70 D-type flip-flop(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 64271: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - eba_reset = 32'b00000000000000000000000000000000 - deba_reset = 32'b00010000000000000000000000000000 - icache_associativity = 1 - icache_sets = 256 - icache_bytes_per_line = 16 - icache_base_address = 32'b00000000000000000000000000000000 - icache_limit = 32'b01111111111111111111111111111111 - dcache_associativity = 1 - dcache_sets = 512 - dcache_bytes_per_line = 16 - dcache_base_address = 0 - dcache_limit = 0 - watchpoints = 32'b00000000000000000000000000000100 - breakpoints = 0 - interrupts = 32 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 66159: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 66269: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 23-bit register for signal . - Found 23-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 29-bit adder for signal created at line 66956. - Found 32-bit 3-to-1 multiplexer for signal created at line 66967. - Found 1-bit 8-to-1 multiplexer for signal created at line 67004. - Found 5-bit comparator equal for signal created at line 66707 - Found 5-bit comparator equal for signal created at line 66713 - Found 5-bit comparator equal for signal created at line 66894 - Found 5-bit comparator equal for signal created at line 66895 - Found 5-bit comparator equal for signal created at line 66896 - Found 5-bit comparator equal for signal created at line 66897 - Found 5-bit comparator equal for signal created at line 66898 - Found 5-bit comparator equal for signal created at line 66899 - Found 32-bit comparator equal for signal created at line 66998 - Found 1-bit comparator equal for signal created at line 67011 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 441 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - eba_reset = 32'b00000000000000000000000000000000 - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 29-bit adder for signal created at line 74164. - Found 2-bit adder for signal created at line 74394. - Found 8-bit 4-to-1 multiplexer for signal created at line 74326. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 314 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 18 | - | Inputs | 11 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit subtractor for signal created at line 71585. - Found 2-bit adder for signal created at line 71662. - Found 20-bit comparator equal for signal created at line 71467 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 41 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 8 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd". - data_width = 32 - address_width = 10 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 1024 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 1024 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 1024 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1024x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 10-bit comparator equal for signal <_n0022> created at line 58 - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd". - data_width = 20 - address_width = 8 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 20-bit register for signal . - Summary: - inferred 21 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 20 - g_size = 256 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 20 - g_size = 256 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 20 - g_size = 256 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 256x20-bit dual-port RAM for signal . - Found 20-bit register for signal . - Found 20-bit register for signal . - Found 8-bit comparator equal for signal <_n0022> created at line 58 - Summary: - inferred 1 RAM(s). - inferred 40 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 512 - bytes_per_line = 16 - base_address = 0 - limit = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 69246. - Summary: - inferred 180 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v". - Found 33-bit subtractor for signal created at line 69. - Found 33-bit subtractor for signal created at line 69. - Found 33-bit adder for signal created at line 68. - Found 33-bit adder for signal created at line 68. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v". - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Summary: - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 64-bit shifter logical right for signal created at line 104 - Summary: - inferred 33 D-type flip-flop(s). - inferred 3 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v". - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 115. - Found 16-bit adder for signal created at line 115. - Found 16x16-bit multiplier for signal created at line 109. - Found 16x16-bit multiplier for signal created at line 110. - Found 16x16-bit multiplier for signal created at line 111. - Summary: - inferred 3 Multiplier(s). - inferred 2 Adder/Subtractor(s). - inferred 160 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - interrupts = 32 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 75866. - Summary: - inferred 78 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 36 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 75285. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 80 D-type flip-flop(s). - inferred 13 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - breakpoints = 0 - watchpoints = 32'b00000000000000000000000000000100 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal <31>>. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 36 | - | Inputs | 8 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit comparator equal for signal created at line 73093 - Found 32-bit comparator equal for signal created at line 73093 - Found 32-bit comparator equal for signal created at line 73093 - Found 32-bit comparator equal for signal created at line 73093 - Summary: - inferred 138 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 35 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd". - addr_width = 5 - addr_depth = 32 - data_width = 32 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 32 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 32 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 32 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 5-bit comparator equal for signal <_n0022> created at line 58 - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v". - Found 11-bit register for signal . - Found 11-bit register for signal . - Summary: - inferred 22 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v". - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16x32-bit dual-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 32-bit adder for signal created at line 197. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 213. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 180. - Found 4-bit comparator equal for signal created at line 224 - Found 5-bit comparator not equal for signal created at line 236 - Found 5-bit comparator not equal for signal created at line 237 - Found 5-bit comparator not equal for signal created at line 238 - Summary: - inferred 1 RAM(s). - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 175 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 22528 - g_init_file = "../../../embedded-sw/dbe.ram" - g_must_have_init_file = true - g_slave1_interface_mode = pipelined - g_slave2_interface_mode = pipelined - g_slave1_granularity = byte - g_slave2_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../embedded-sw/dbe.ram" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../embedded-sw/dbe.ram" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. - Found 22528x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 4096 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = byte - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 4096 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 4096 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4096x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xwb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 54 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 409. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_clockgen.v". - Tp = 1 - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 92. - Found 8-bit subtractor for signal created at line 107. - Found 8-bit comparator greater for signal created at line 91 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v". - Tp = 1 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 25 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_outputcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit comparator greater for signal created at line 100 - Found 7-bit comparator greater for signal created at line 101 - Found 7-bit comparator greater for signal created at line 138 - Summary: - inferred 6 D-type flip-flop(s). - inferred 3 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861. - Found 32-bit comparator lessequal for signal created at line 388 - Found 32-bit comparator greater for signal created at line 907 - Found 32-bit comparator greater for signal created at line 908 - Summary: - inferred 21 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b10100000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 1'b0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0000000 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0010010 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0001100 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000110 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 6 - RESET_VALUE = 6'b111111 - Found 6-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 4 - RESET_VALUE = 4'b1111 - Found 4-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 3 - RESET_VALUE = 3'b000 - Found 3-bit register for signal . - Summary: - inferred 3 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01100100 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 5 - RESET_VALUE = 5'b00000 - Found 5-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 16 - RESET_VALUE = 16'b0000000000000000 - Found 16-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_maccontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_receivecontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 16-bit subtractor for signal created at line 356. - Found 3-bit adder for signal created at line 304. - Found 5-bit adder for signal created at line 323. - Found 6-bit adder for signal created at line 417. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 72 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_transmitcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 6-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 255. - Found 6-bit adder for signal created at line 274. - Found 6-bit adder for signal created at line 277. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 20 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v". - Tp = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 344. - Found 6-bit comparator equal for signal created at line 249 - Found 4-bit comparator equal for signal created at line 349 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v". - Tp = 1 - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 17-bit subtractor for signal created at line 170. - Found 32-bit subtractor for signal created at line 170. - Found 16-bit adder for signal created at line 162. - Found 16-bit adder for signal created at line 194. - Found 3-bit adder for signal created at line 215. - Found 32-bit comparator lessequal for signal created at line 170 - Found 16-bit comparator equal for signal created at line 199 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 35 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txstatem.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 187 - Found 7-bit comparator not equal for signal created at line 187 - Summary: - inferred 12 D-type flip-flop(s). - inferred 4 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_crc.v". - Tp = 1 - Found 32-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_random.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 4-bit comparator greater for signal created at line 114 - Found 4-bit comparator greater for signal created at line 115 - Found 4-bit comparator greater for signal created at line 116 - Found 4-bit comparator greater for signal created at line 117 - Found 4-bit comparator greater for signal created at line 118 - Found 4-bit comparator greater for signal created at line 119 - Found 4-bit comparator greater for signal created at line 120 - Found 4-bit comparator greater for signal created at line 121 - Found 4-bit comparator greater for signal created at line 122 - Found 10-bit comparator equal for signal created at line 139 - Summary: - inferred 20 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxethmac.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit comparator greater for signal created at line 213 - Found 4-bit comparator lessequal for signal created at line 314 - Summary: - inferred 40 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxstatem.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxcounters.v". - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 116. - Found 16-bit adder for signal created at line 120. - Found 5-bit adder for signal created at line 151. - Found 4-bit adder for signal created at line 173. - Found 16-bit comparator greater for signal created at line 131 - Found 16-bit comparator greater for signal created at line 132 - Found 16-bit comparator equal for signal created at line 134 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxaddrcheck.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v". -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 7-bit register for signal . - Found 7-bit register for signal . - Found 2-bit register for signal . - Found 24-bit register for signal . - Found 9-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 773. - Found 16-bit subtractor for signal created at line 777. - Found 16-bit subtractor for signal created at line 781. - Found 16-bit subtractor for signal created at line 785. - Found 30-bit adder for signal created at line 821. - Found 3-bit adder for signal created at line 960. - Found 30-bit adder for signal created at line 964. - Found 3-bit adder for signal created at line 996. - Found 8-bit adder for signal created at line 1395. - Found 8-bit adder for signal created at line 1398. - Found 2-bit adder for signal created at line 1745. - Found 30-bit adder for signal created at line 2001. - Found 2-bit adder for signal created at line 2098. - Found 2-bit adder for signal created at line 2117. - Found 4x2-bit Read Only RAM for signal - Found 4x6-bit Read Only RAM for signal <_n1580> - Found 1-bit 4-to-1 multiplexer for signal created at line 1630. - Found 8-bit 4-to-1 multiplexer for signal created at line 1648. - Found 8-bit 4-to-1 multiplexer for signal created at line 1660. - Found 16-bit 4-to-1 multiplexer for signal created at line 776. - Found 16-bit comparator greater for signal created at line 627 - Found 16-bit comparator greater for signal created at line 803 - Found 16-bit comparator lessequal for signal created at line 898 - Found 8-bit comparator greater for signal created at line 1062 - Found 16-bit comparator greater for signal created at line 1062 - Found 8-bit comparator lessequal for signal created at line 2417 - Found 1-bit comparator equal for signal created at line 2422 - Found 8-bit comparator greater for signal created at line 2423 - Summary: - inferred 2 RAM(s). - inferred 11 Adder/Subtractor(s). - inferred 461 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_spram_256x32.v". - we_width = 1 - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v". - DATA_WIDTH = 32 - DEPTH = 256 - CNT_WIDTH = 8 - Set property "syn_ramstyle = no_rw_check" for signal . - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 83. - Found 8-bit adder for signal created at line 114. - Found 8-bit adder for signal created at line 122. - Found 8-bit subtractor for signal > created at line 81. - Summary: - inferred 1 RAM(s). - inferred 3 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_macstatus.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 16-bit comparator greater for signal created at line 236 - Found 16-bit comparator greater for signal created at line 236 - Found 6-bit comparator equal for signal created at line 310 - Summary: - inferred 18 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 3 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_851_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_851_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 299. - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 320. - Found 16-bit adder for signal created at line 1241. - Found 32-bit 7-to-1 multiplexer for signal <_n0442> created at line 206. - Found 32-bit comparator greater for signal created at line 299 - Found 16-bit comparator greater for signal created at line 320 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 254 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 2 - g_adr_width_B = 32 - g_dat_width_A = 16 - g_dat_width_B = 32 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 32 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 32 - g_adr_width_B = 2 - g_dat_width_A = 32 - g_dat_width_B = 16 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 32 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 15-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 13-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 160-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 11-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 12 | - | Transitions | 41 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | _n0498 (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 11-bit adder for signal created at line 222. - Found 6-bit adder for signal created at line 464. - Found 7-bit adder for signal created at line 472. - Found 16-bit adder for signal created at line 1241. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit 3-to-1 multiplexer for signal created at line 242. - Found 1-bit 3-to-1 multiplexer for signal created at line 242. - Found 11-bit comparator equal for signal created at line 456 - Found 11-bit comparator equal for signal created at line 464 - Found 11-bit comparator equal for signal created at line 472 - Found 11-bit comparator greater for signal created at line 482 - Found 16-bit comparator equal for signal created at line 485 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 499 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 86 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 96 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 106 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd". - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 1 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_867_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 28-bit adder for signal created at line 91. - Found 28-bit adder for signal created at line 102. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 61 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 160 - g_width_OUT = 16 - g_protected = 0 - Found 9-bit register for signal . - Found 160-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 170 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 15-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 29 | - | Inputs | 10 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_927_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State ipv4_chksum is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 15 | - | Transitions | 34 | - | Inputs | 13 | - | Outputs | 12 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_parser_reset_OR_12293_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | eth | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 14-bit subtractor for signal created at line 426. - Found 11-bit adder for signal created at line 291. - Found 12-bit adder for signal created at line 405. - Found 12-bit adder for signal created at line 426. - Found 13-bit adder for signal created at line 426. - Found 17-bit adder for signal created at line 504. - Found 15-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 504. - Found 11-bit comparator equal for signal created at line 347 - Found 12-bit comparator equal for signal created at line 405 - Found 12-bit comparator greater for signal created at line 420 - Found 14-bit comparator equal for signal created at line 426 - Found 16-bit comparator equal for signal created at line 447 - Found 11-bit comparator greater for signal created at line 520 - Found 11-bit comparator equal for signal created at line 529 - Summary: - inferred 8 Adder/Subtractor(s). - inferred 244 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 14 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 160 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 160-bit register for signal . - Found 4-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 166 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 15-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . -INFO:Xst:1799 - State zero_pad_wait is never reached in FSM . -INFO:Xst:1799 - State error is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 716 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_1014_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 19 | - | Transitions | 145 | - | Inputs | 19 | - | Outputs | 16 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_1014_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit subtractor for signal > created at line 1308. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 4-bit comparator greater for signal created at line 363 - Found 16-bit comparator greater for signal created at line 504 - Found 8-bit comparator greater for signal created at line 584 - Found 8-bit comparator greater for signal created at line 619 - Found 16-bit comparator equal for signal created at line 659 - Found 4-bit comparator greater for signal created at line 716 - Found 8-bit comparator greater for signal created at line 986 - Summary: - inferred 13 Adder/Subtractor(s). - inferred 359 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 65 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 32 - g_size = 16 - g_show_ahead = true - g_with_empty = true - g_with_full = true - g_with_almost_empty = true - g_with_almost_full = true - g_with_count = true - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 1 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 32 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 0 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_PROG_FULL_TYPE = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 1 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd". - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_WR_RST_MAXFAN = 2 - C_RD_RST_MAXFAN = 3 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Summary: - inferred 15 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 1 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 32 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 4 - C_WRITE_WIDTH_A = 32 - C_WRITE_WIDTH_A_CORE = 32 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 4 - C_WRITE_WIDTH_B = 32 - C_WRITE_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 4 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 32 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 4 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 32 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_1', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_READ_WIDTH_B = 32 - C_READ_WIDTH_A_CORE = 32 - C_READ_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_USE_EMBEDDED_REG = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic_1', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_1', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd". - C_HAS_ALMOST_EMPTY = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY_FB', unconnected in block 'rd_status_flags_ss', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd". - C_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd". - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 210. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd". - C_RD_PNTR_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd". - C_COUNTER_RESET_VAL = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 126. - Found 4-bit subtractor for signal > created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 4 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_FULL_FLAGS_RST_VAL = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 1 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 151. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_EMPTY_TYPE = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss', is tied to its initial value (1). -WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd". - C_HAS_RST = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_FULL_FLAGS_RST_VAL = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 243. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd". - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 1 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 8-to-1 multiplexer for signal <_n0255> created at line 168. - Found 32-bit 8-to-1 multiplexer for signal <_n0277> created at line 137. - Summary: - inferred 328 D-type flip-flop(s). - inferred 22 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (0.0,0.0,8.882,8.882) - g_use_clk_chains = "0011" - g_use_data_chains = "1111" - g_map_clk_data_chains = (1,0,0,1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (0.0,0.0,8.882,8.882) - g_use_clk_chains = "0011" - g_use_data_chains = "1111" - g_map_clk_data_chains = (1,0,0,1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 632: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 669: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 712: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 999: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1162: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1208: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1208: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1247: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1247: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1322: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1322: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd" line 1357: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 1-bit tristate buffer for signal created at line 1146 - Found 1-bit tristate buffer for signal created at line 1149 - Found 1-bit tristate buffer for signal created at line 1187 - Found 1-bit tristate buffer for signal created at line 1271 - Found 1-bit tristate buffer for signal created at line 1273 - Found 1-bit tristate buffer for signal created at line 1310 - Found 1-bit tristate buffer for signal created at line 1343 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 120 D-type flip-flop(s). - inferred 16 Multiplexer(s). - inferred 7 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_common/reset_synch/reset_synch.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 7 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001101111111100010000000000000000000000000000010011100010110000000101111001010101001001011111101110110000100100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111100110001010111110101011101001001010100100100010100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000101000000000000000000000000000000000000000000000000000000000000010111111111000100000000000000000000000000000100111000101100000001011110010101010010010111111011101100001001000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111001100010101111101010111010010010101001001000101001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100010000000000000000000000000000010011100010110000000101111001011001011110110110001100100011110100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101001001001100100100001101011111010011010100000101010011010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000100000000000000000000000000000100111000101100000001011110010101000000001010000110010000010111000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010100110101000001001001001000000010000000100000001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010011110111001010100110100000100000000000000000000000000000001001000000001001000010001001001000100110001001110010011000101001101011111010001100100110101000011001101010011000100110110010111110101001001000101010001110101001100100000001000000010000000000001") - g_sdb_addr = "00000000000000000000100000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001101111111100010000000000000000000000000000010011100010110000000101111001010101001001011111101110110000100100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111100110001010111110101011101001001010100100100010100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000101000000000000000000000000000000000000000000000000000000000000010111111111000100000000000000000000000000000100111000101100000001011110010101010010010111111011101100001001000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111001100010101111101010111010010010101001001000101001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100010000000000000000000000000000010011100010110000000101111001011001011110110110001100100011110100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101001001001100100100001101011111010011010100000101010011010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000100000000000000000000000000000100111000101100000001011110010101000000001010000110010000010111000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010100110101000001001001001000000010000000100000001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010011110111001010100110100000100000000000000000000000000000001001000000001001000010001001001000100110001001110010011000101001101011111010001100100110101000011001101010011000100110110010111110101001001000101010001110101001100100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 8 - g_registered = true - g_address = ("00000000000000000000100000000000","00000000000000000000011000000000","00000000000000000000010100000000","00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000111000000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 10 D-type flip-flop(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32-bit register for signal . - Found 27-bit register for signal . - Found 30-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 22-bit register for signal . - Found 22-bit register for signal . - Found 22-bit register for signal . - Found 22-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 506 D-type flip-flop(s). - inferred 145 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_buf.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clk_period_values = (0.0,0.0,8.882,8.882) - g_use_clk_chains = "0011" - g_clk_default_dly = (5,5,5,5) - g_use_data_chains = "1111" - g_map_clk_data_chains = (1,0,0,1) - g_data_default_dly = (9,9,9,9) - g_ref_clk = 1 - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd" line 277: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.882 - g_default_adc_clk_delay = 5 - g_with_ref_clk = false - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.882 - g_default_adc_clk_delay = 5 - g_with_ref_clk = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd". - g_delay_type = "VAR_LOADABLE" - g_default_adc_data_delay = 9 - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd" line 337: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Summary: - inferred 97 D-type flip-flop(s). - inferred 26 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 16 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 0 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 16 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 16 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 0 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 2 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_PROG_FULL_TYPE = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 0 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 0 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 0 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 0 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 0 - C_HAS_SRST = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 16 - C_READ_WIDTH_B = 16 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 16 - C_READ_WIDTH_B = 16 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 2 - C_WRITE_WIDTH_A = 16 - C_WRITE_WIDTH_A_CORE = 16 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 2 - C_WRITE_WIDTH_B = 16 - C_WRITE_WIDTH_B_CORE = 16 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(18,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 2 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 16 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 16 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 2 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 16 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 16 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 18 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 16 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 18 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 16 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 18 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 18 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 18 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 18 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_2', is tied to its initial value (000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_READ_WIDTH_B = 16 - C_READ_WIDTH_A_CORE = 16 - C_READ_WIDTH_B_CORE = 16 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_MSGON_VAL = 1 - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 0 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_USE_EMBEDDED_REG = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 241: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'DATA_COUNT', unconnected in block 'rd_logic_2', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_2', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY', unconnected in block 'rd_status_flags_as', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_FULL_FLAGS_RST_VAL = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 243: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 0 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 270. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_almost_full_i', unconnected in block 'wr_status_flags_as', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 0 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_OVERFLOW = 0 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 64 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd". - ARST_LVL = '0' -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit 8-to-1 multiplexer for signal created at line 191. - Summary: - inferred 54 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 26 | - | Inputs | 9 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | st_idle | - | Power Up State | st_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 3-bit subtractor for signal > created at line 1308. - Found 4-bit 6-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 34 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 14-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 64 | - | Inputs | 6 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit subtractor for signal > created at line 1308. - Found 14-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 57 D-type flip-flop(s). - inferred 26 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd". - g_three_wire_mode = 1 - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd". - g_three_wire_mode = 1 - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v". - g_three_wire_mode = 1 - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 7-to-1 multiplexer for signal created at line 123. - Summary: - inferred 75 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v". - Tp = 1 - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 80. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v". - g_three_wire_mode = 1 - Tp = 1 - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 99. - Found 8-bit adder for signal created at line 99. - Found 1-bit 128-to-1 multiplexer for signal created at line 147. - Found 1-bit 128-to-1 multiplexer for signal created at line 260. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 138 D-type flip-flop(s). - inferred 141 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd". - g_three_wire_mode = 0 - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd". - g_three_wire_mode = 0 - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v". - g_three_wire_mode = 0 - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 7-to-1 multiplexer for signal created at line 123. - Summary: - inferred 74 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v". - g_three_wire_mode = 0 - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 99. - Found 8-bit adder for signal created at line 99. - Found 1-bit 128-to-1 multiplexer for signal created at line 147. - Found 1-bit 128-to-1 multiplexer for signal created at line 260. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 138 D-type flip-flop(s). - inferred 141 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_ports = 1 - g_ow_btp_normal = "5.0" - g_ow_btp_overdrive = "1.0" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_ports = 1 - g_ow_btp_normal = "5.0" - g_ow_btp_overdrive = "1.0" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v". - OVD_E = 1 - CDR_E = 1 - BDW = 32 - OWN = 1 - BAW = 1 - BTP_N = "5.0" - BTP_O = "1.0" - T_RSTH_N = 96 - T_RSTL_N = 96 - T_RSTP_N = 15 - T_DAT0_N = 12 - T_DAT1_N = 1 - T_BITS_N = 3 - T_RCVR_N = 1 - T_IDLE_N = 200 - T_RSTH_O = 48 - T_RSTL_O = 48 - T_RSTP_O = 10 - T_DAT0_O = 6 - T_DAT1_O = 1 - T_BITS_O = 2 - T_RCVR_O = 2 - T_IDLE_O = 96 - CDR_N = 4 - CDR_O = 0 -WARNING:Xst:2935 - Signal 'owr_sel', unconnected in block 'sockit_owm', is tied to its initial value (0). - Found 16-bit register for signal . - Found 16-bit register for signal
. - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 17-bit adder for signal created at line 305. - Found 8-bit subtractor for signal > created at line 392. - Found 8-bit subtractor for signal > created at line 393. - Found 1-bit shifter logical left for signal created at line 100 - Found 16-bit comparator equal for signal created at line 309 - Found 8-bit comparator equal for signal created at line 399 - Found 8-bit comparator equal for signal created at line 400 - Found 8-bit comparator equal for signal created at line 409 - Found 8-bit comparator equal for signal created at line 410 - Found 8-bit comparator not equal for signal created at line 411 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 65 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 11 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_source_gen.vhd". - g_wbs_interface_width = narrow2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd". - g_data_width = 25 - g_size = 32 - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 25-bit register for signal >. - Found 5-bit adder for signal created at line 142. - Found 5-bit subtractor for signal > created at line 144. -INFO:Xst:3019 - HDL ADVISOR - 800 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 25-bit 32-to-1 multiplexer for signal created at line 109. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 806 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd". - g_min_pulse_width = 1 - g_clk_frequency = 100 - g_output_polarity = '0' - g_output_retrig = false - g_output_length = 1 - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 20000000 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" line 144: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - Set property "syn_noprune = true". - Set property "optimize_primitives = false". - Set property "dont_touch = true". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 508: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 523: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 523: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 537: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 552: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 567: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 567: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 581: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 581: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 610: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 610: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 624: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 624: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 638: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 653: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 653: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 667: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 667: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 1 - log_2_period = 1 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd" line 254: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 1112 - log_2_period = 11 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 11-bit register for signal . - Found 11-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 11 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 1390000 - log_2_period = 21 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 21-bit register for signal . - Found 21-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 21 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 2 - log_2_period = 2 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 1-bit register for signal . - Found 1-bit adder for signal > created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 1 - init_value = "0000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 1 - init_value = "0000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 2224 - log_2_period = 12 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 12-bit register for signal . - Found 12-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 22240000 - log_2_period = 25 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 25-bit register for signal . - Found 25-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 2780000 - log_2_period = 22 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 22-bit register for signal . - Found 22-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 22 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 35 - log_2_period = 6 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 6-bit register for signal . - Found 6-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 5000 - log_2_period = 13 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 13-bit register for signal . - Found 13-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 13 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 556 - log_2_period = 10 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 10-bit register for signal . - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 10 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 5560000 - log_2_period = 23 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 23-bit register for signal . - Found 23-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 23 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - period = 70 - log_2_period = 7 - pipeline_regs = 5 - use_bufg = 0 - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Set property "MAX_FANOUT = REDUCE" for signal >. - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "syn_black_box = true" for instance . - Set property "syn_noprune = true" for instance . - Set property "optimize_primitives = false" for instance . - Set property "dont_touch = true" for instance . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "MAX_FANOUT = REDUCE" for signal . - Set property "syn_keep = true" for signal . - Set property "KEEP = TRUE" for signal . -WARNING:Xst:37 - Detected unknown constraint/property "preserve_signal". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 82849: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 24 - init_value = "000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - init_index = 2 - init_value = "000000000000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - init_index = 2 - init_value = "000000000000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90126: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90158: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90190: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90312: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90344: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90376: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90446: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90478: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90510: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 90964: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - core_name0 = "addsb_11_0_26986301a9f671cd" - a_width = 24 - a_bin_pt = 22 - a_arith = 2 - c_in_width = 16 - c_in_bin_pt = 4 - c_in_arith = 1 - c_out_width = 16 - c_out_bin_pt = 4 - c_out_arith = 1 - b_width = 24 - b_bin_pt = 22 - b_arith = 2 - s_width = 25 - s_bin_pt = 22 - s_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - full_s_width = 25 - full_s_arith = 2 - mode = 1 - extra_registers = 0 - latency = 0 - quantization = 1 - overflow = 1 - c_latency = 0 - c_output_width = 25 - c_has_c_in = 0 - c_has_c_out = 0 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 1 - dout_width = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 25 - dout_width = 25 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 26 - din_bin_pt = 22 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 21 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 26 - din_bin_pt = 22 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 21 - dout_arith = 2 - quantization = 2 - overflow = 2 - Found 27-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - latency = 25 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - latency = 25 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - latency = 17 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - latency = 8 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - core_name0 = "addsb_11_0_8b0747970e52f130" - a_width = 25 - a_bin_pt = 22 - a_arith = 2 - c_in_width = 16 - c_in_bin_pt = 4 - c_in_arith = 1 - c_out_width = 16 - c_out_bin_pt = 4 - c_out_arith = 1 - b_width = 25 - b_bin_pt = 22 - b_arith = 2 - s_width = 26 - s_bin_pt = 22 - s_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - full_s_width = 26 - full_s_arith = 2 - mode = 1 - extra_registers = 0 - latency = 0 - quantization = 1 - overflow = 1 - c_latency = 0 - c_output_width = 26 - c_has_c_in = 0 - c_has_c_out = 0 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 1112 - phase = 1111 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 1112 - phase = 1111 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 1112 - phase = 1111 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 1 - init_value = "0" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 2 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - init_index = 2 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_dividend_tdata_net<31:26>', unconnected in block 'xldivider_generator_7b92d2b3a8529d55359a27d09fb2c5d6', is tied to its initial value (000000). -WARNING:Xst:2935 - Signal 's_axis_divisor_tdata_net<31:26>', unconnected in block 'xldivider_generator_7b92d2b3a8529d55359a27d09fb2c5d6', is tied to its initial value (000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - init_value = "0000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - init_index = 2 - init_value = "0000000000000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - init_index = 2 - init_value = "0000000000000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 26 - init_value = "00000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - init_index = 2 - init_value = "00000000000000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 26 - init_index = 2 - init_value = "00000000000000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 26-bit comparator greater for signal created at line 82404 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - core_name0 = "addsb_11_0_239e4f614ba09ab1" - a_width = 25 - a_bin_pt = 22 - a_arith = 2 - c_in_width = 16 - c_in_bin_pt = 4 - c_in_arith = 1 - c_out_width = 16 - c_out_bin_pt = 4 - c_out_arith = 1 - b_width = 25 - b_bin_pt = 22 - b_arith = 2 - s_width = 26 - s_bin_pt = 22 - s_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - full_s_width = 26 - full_s_arith = 2 - mode = 1 - extra_registers = 0 - latency = 0 - quantization = 1 - overflow = 1 - c_latency = 0 - c_output_width = 26 - c_has_c_in = 0 - c_has_c_out = 0 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 50 - din_bin_pt = 24 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 24 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 1 - overflow = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 50 - din_bin_pt = 24 - din_arith = 2 - dout_width = 25 - dout_bin_pt = 24 - dout_arith = 2 - quantization = 1 - overflow = 2 - Summary: - inferred 27 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_dividend_tdata_net<31:26>', unconnected in block 'xldivider_generator_9bc6b5677974555f6235feeceb7f929f', is tied to its initial value (000000). -WARNING:Xst:2935 - Signal 's_axis_divisor_tdata_net<31:26>', unconnected in block 'xldivider_generator_9bc6b5677974555f6235feeceb7f929f', is tied to its initial value (000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 91740: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 91772: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 91804: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 91926: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 91958: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 91990: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 92060: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 92092: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 92124: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 92510: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4448 - phase = 4447 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2500 - phase = 2499 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 92981: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93013: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93045: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93199: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93231: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93301: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93333: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93365: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 93819: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 26 - d_bin_pt = 22 - d_arith = 2 - q_width = 26 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 35 - phase = 34 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 24 - d_arith = 2 - q_width = 25 - q_bin_pt = 24 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 35 - phase = 34 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 25 - d_bin_pt = 21 - d_arith = 2 - q_width = 25 - q_bin_pt = 21 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 35 - phase = 34 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83707: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83707: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83707: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83707: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83707: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83722: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83722: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83722: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83722: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83722: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - latency = 4 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - latency = 4 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - latency = 4 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 2 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 2 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 2 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - latency = 2 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - latency = 2 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 25 - latency = 2 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 2-bit register for signal . - Found 2-bit comparator equal for signal created at line 79878 - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 23 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 23 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 26-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 2 - phase = 1 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit comparator equal for signal created at line 79472 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 83304: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:2935 - Signal 's_axis_cartesian_tdata_net<63:57>', unconnected in block 'xlcordic_67422259e33cafe86cb2beaf1e4ed91a', is tied to its initial value (0000000). -WARNING:Xst:2935 - Signal 's_axis_cartesian_tdata_net<31:25>', unconnected in block 'xlcordic_67422259e33cafe86cb2beaf1e4ed91a', is tied to its initial value (0000000). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84292: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 84149: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - new_msb = 49 - new_lsb = 24 - x_width = 50 - y_width = 26 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - core_name0 = "mult_11_2_6d8e463c710483da" - a_width = 25 - a_bin_pt = 21 - a_arith = 2 - b_width = 25 - b_bin_pt = 23 - b_arith = 2 - p_width = 50 - p_bin_pt = 44 - p_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - quantization = 1 - overflow = 1 - extra_registers = 0 - c_a_width = 25 - c_b_width = 25 - c_type = 0 - c_a_type = 0 - c_b_type = 0 - c_pipelined = 1 - c_baat = 25 - multsign = 2 - c_output_width = 50 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - core_name0 = "mult_11_2_6d8e463c710483da" - a_width = 25 - a_bin_pt = 24 - a_arith = 2 - b_width = 25 - b_bin_pt = 0 - b_arith = 2 - p_width = 50 - p_bin_pt = 24 - p_arith = 2 - rst_width = 1 - rst_bin_pt = 0 - rst_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - quantization = 1 - overflow = 1 - extra_registers = 0 - c_a_width = 25 - c_b_width = 25 - c_type = 0 - c_a_type = 0 - c_b_type = 0 - c_pipelined = 1 - c_baat = 25 - multsign = 2 - c_output_width = 50 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 24 - din_bin_pt = 19 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 1 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 24 - din_bin_pt = 19 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 1 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 2-bit comparator equal for signal created at line 80727 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 86890: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 86910: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 86910: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 86910: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 86910: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 86928: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 21 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - bool_conversion = 0 - latency = 0 - quantization = 2 - overflow = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - din_width = 25 - din_bin_pt = 21 - din_arith = 2 - dout_width = 24 - dout_bin_pt = 22 - dout_arith = 2 - quantization = 2 - overflow = 1 - Found 28-bit adder for signal created at line 735. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 3 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 3 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 3 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 2 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 2 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 2 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 3 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 3 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 3 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - init_index = 0 - init_value = "0" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - init_index = 0 - init_value = "0" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 2 - init_value = "00" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - init_index = 2 - init_value = "00" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - init_index = 2 - init_value = "00" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 3-bit register for signal . - Found 2-bit comparator equal for signal created at line 80900 - Summary: - inferred 3 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 4 - phase = 3 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 2-bit comparator equal for signal created at line 80849 - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 16 - init_value = "0000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 16 - init_index = 2 - init_value = "0000000000000000" - latency = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 16 - init_index = 2 - init_value = "0000000000000000" - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 87467: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 88010: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 7 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 7 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 24 - latency = 7 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - latency = 7 - reg_retiming = 0 - reset = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - latency = 7 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 1 - latency = 7 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - new_msb = 24 - new_lsb = 1 - x_width = 25 - y_width = 24 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 88281: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 88622: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 24 - q_width = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit adder for signal > created at line 81705. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 24 - d_bin_pt = 22 - d_arith = 2 - q_width = 24 - q_bin_pt = 22 - q_arith = 2 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - sampling_ratio = 2 - latency = 0 - copy_samples = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd" line 81835: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - d_width = 2 - d_bin_pt = 0 - d_arith = 1 - q_width = 2 - q_bin_pt = 0 - q_arith = 1 - en_width = 1 - en_bin_pt = 0 - en_arith = 1 - ds_ratio = 556 - phase = 555 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - width = 2 - latency = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 24-bit 4-to-1 multiplexer for signal created at line 81934. - Summary: - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066.vhd". - core_name0 = "cntr_11_0_3166d4cc5b09c744" - op_width = 2 - op_arith = 1 - Set property "syn_black_box = true" for instance . -WARNING:Xst:37 - Detected unknown constraint/property "fpga_dont_touch". This constraint/property is not supported by the current software release and will be ignored. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 84: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 119: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 158: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 4 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_sdb_addr = "00000000000000000000010000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000011111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_3', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_address = ("00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000011000000000","00000000000000000000011111110000","00000000000000000000011100000000","00000000000000000000011100000000","00000000000000000000011100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 46 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1535_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1545_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 24-bit register for signal . - Found 24-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 90 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 18 - 1024x32-bit dual-port RAM : 1 - 128x32-bit single-port Read Only RAM : 2 - 16x32-bit dual-port RAM : 1 - 22528x32-bit dual-port RAM : 1 - 256x20-bit dual-port RAM : 1 - 256x32-bit dual-port RAM : 4 - 256x32-bit single-port Read Only RAM : 1 - 32x32-bit dual-port RAM : 2 - 4096x32-bit dual-port RAM : 1 - 4x2-bit single-port Read Only RAM : 1 - 4x6-bit single-port Read Only RAM : 1 - 8x1-bit single-port Read Only RAM : 2 -# Multipliers : 3 - 16x16-bit multiplier : 3 -# Adders/Subtractors : 191 - 1-bit adder : 4 - 10-bit adder : 3 - 11-bit adder : 4 - 11-bit subtractor : 1 - 12-bit adder : 4 - 13-bit adder : 3 - 14-bit subtractor : 3 - 15-bit subtractor : 3 - 16-bit adder : 15 - 16-bit subtractor : 7 - 17-bit adder : 4 - 17-bit subtractor : 1 - 2-bit adder : 8 - 2-bit addsub : 1 - 2-bit subtractor : 2 - 21-bit adder : 2 - 22-bit adder : 2 - 23-bit adder : 2 - 24-bit adder : 1 - 25-bit adder : 2 - 26-bit adder : 5 - 27-bit adder : 3 - 28-bit adder : 3 - 29-bit adder : 2 - 3-bit adder : 4 - 3-bit subtractor : 3 - 30-bit adder : 3 - 32-bit adder : 8 - 32-bit subtractor : 6 - 33-bit adder : 2 - 33-bit subtractor : 2 - 4-bit adder : 18 - 4-bit addsub : 2 - 5-bit adder : 10 - 5-bit addsub : 4 - 6-bit adder : 5 - 7-bit adder : 4 - 8-bit adder : 12 - 8-bit addsub : 3 - 8-bit subtractor : 14 - 9-bit subtractor : 6 -# Registers : 2101 - 1-bit register : 1399 - 10-bit register : 5 - 11-bit register : 17 - 12-bit register : 2 - 13-bit register : 2 - 14-bit register : 2 - 15-bit register : 3 - 16-bit register : 79 - 160-bit register : 3 - 17-bit register : 1 - 2-bit register : 51 - 20-bit register : 3 - 21-bit register : 2 - 22-bit register : 6 - 23-bit register : 4 - 24-bit register : 2 - 25-bit register : 130 - 27-bit register : 1 - 28-bit register : 1 - 29-bit register : 9 - 3-bit register : 24 - 30-bit register : 4 - 32-bit register : 93 - 4-bit register : 99 - 48-bit register : 4 - 5-bit register : 25 - 6-bit register : 20 - 64-bit register : 2 - 7-bit register : 11 - 8-bit register : 88 - 9-bit register : 8 - 96-bit register : 1 -# Comparators : 163 - 1-bit comparator equal : 36 - 10-bit comparator equal : 2 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 7 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 2-bit comparator equal : 17 - 20-bit comparator equal : 1 - 26-bit comparator greater : 3 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator equal : 10 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 21 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 1 - 8-bit comparator not equal : 2 -# Multiplexers : 2231 - 1-bit 128-to-1 multiplexer : 4 - 1-bit 2-to-1 multiplexer : 1618 - 1-bit 3-to-1 multiplexer : 5 - 1-bit 4-to-1 multiplexer : 41 - 1-bit 8-to-1 multiplexer : 3 - 11-bit 2-to-1 multiplexer : 10 - 14-bit 2-to-1 multiplexer : 4 - 15-bit 2-to-1 multiplexer : 3 - 16-bit 2-to-1 multiplexer : 50 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 29 - 20-bit 2-to-1 multiplexer : 3 - 23-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 8 - 24-bit 4-to-1 multiplexer : 1 - 25-bit 2-to-1 multiplexer : 12 - 25-bit 32-to-1 multiplexer : 4 - 28-bit 2-to-1 multiplexer : 4 - 29-bit 2-to-1 multiplexer : 8 - 3-bit 2-to-1 multiplexer : 21 - 30-bit 2-to-1 multiplexer : 4 - 32-bit 2-to-1 multiplexer : 141 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 4 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 76 - 4-bit 6-to-1 multiplexer : 2 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 16 - 6-bit 2-to-1 multiplexer : 4 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 116 - 8-bit 4-to-1 multiplexer : 3 - 8-bit 8-to-1 multiplexer : 2 - 9-bit 2-to-1 multiplexer : 9 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 3 - 1-bit shifter logical left : 2 - 64-bit shifter logical right : 1 -# Tristates : 10 - 1-bit tristate buffer : 8 - 8-bit tristate buffer : 2 -# FSMs : 17 -# Xors : 625 - 1-bit xor2 : 504 - 1-bit xor3 : 18 - 1-bit xor4 : 10 - 32-bit xor2 : 93 - -========================================================================= -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. -WARNING:Xst:638 - in unit xlclockdriver_2 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_3 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_4 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_5 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_6 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_7 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_8 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_9 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_10 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_11 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. -WARNING:Xst:638 - in unit xlclockdriver_12 Conflict on KEEP property on signal ce_vec_logic<5> and ce_vec<5> ce_vec<5> signal will be lost. - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Reading core <../../platform/virtex6/chipscope/ila/chipscope_ila.ngc>. -Reading core <../../platform/virtex6/chipscope/ila/chipscope_ila_8192.ngc>. -Reading core <../../platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/xlpersistentdff.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fifo_generator_virtex6_8_4_784d0e5148f6dbe1.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_26986301a9f671cd.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/dv_gn_v4_0_7887f22978e0003d.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/dv_gn_v4_0_fc1ee041a30564f8.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_8b0747970e52f130.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_239e4f614ba09ab1.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/mult_11_2_6d8e463c710483da.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_ef8269b30b0e0deb.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_d31b0f3a494d423b.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_59fbd17f7e62a7fe.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/crdc_v5_0_19fb63dead3076ad.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cmpy_v5_0_fc1d91881e8e8ae6.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_0c61ac74cf3e5cc7.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_3ac902fec2d60a4a.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_95e3c24666ebc2c9.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_fe47fe6ccabc2305.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cntr_11_0_3166d4cc5b09c744.ngc>. -Reading core <../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/dds_cmplr_v5_0_ca0550aac85c1501.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance blk00000229 in unit blk00000229 of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000022a in unit blk0000022a of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000022b in unit blk0000022b of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000022c in unit blk0000022c of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance blk0000022d in unit blk0000022d of type DSP48E has been replaced by DSP48E1 -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk00000229 in unit blk00000229 is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000022a in unit blk0000022a is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000022b in unit blk0000022b is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000022c in unit blk0000022c is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance blk0000022d in unit blk0000022d is not supported -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -INFO:Xst:1901 - Instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive of type DSP48E has been replaced by DSP48E1 -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_upper_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_quotient_collector/i_typical_case.i_addsub/i_vx5_sp3.i_casc_dsp48.i_lower_addsub/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_multadd/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_mult/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_extra_digits.i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[0].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[1].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -WARNING:Xst:1902 - Value 0 for attribute AUTORESET_PATDET of instance U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive in unit U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_iterative_unit/i_splice[2].i_add/i_synth_option.i_synth_model/opt_vx5.i_uniwrap/i_primitive is not supported -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 14 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 12 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 34 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 6-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 1024-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 1024-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4096-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 4096-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal > | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal > | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block , in block . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block . - Found pipelined multiplier on signal : - - 1 pipeline level(s) found in a register connected to the multiplier macro output. - Pushing register(s) into the multiplier macro. -INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s). -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | addrB | connected to signal > | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 18 - 1024x32-bit dual-port block RAM : 1 - 128x32-bit single-port block Read Only RAM : 2 - 16x32-bit dual-port distributed RAM : 1 - 22528x32-bit dual-port block RAM : 1 - 256x20-bit dual-port block RAM : 1 - 256x32-bit dual-port block RAM : 3 - 256x32-bit single-port block RAM : 1 - 256x32-bit single-port block Read Only RAM : 1 - 32x32-bit dual-port block RAM : 2 - 4096x32-bit dual-port block RAM : 1 - 4x2-bit single-port distributed Read Only RAM : 1 - 4x6-bit single-port distributed Read Only RAM : 1 - 8x1-bit single-port distributed Read Only RAM : 2 -# MACs : 2 - 16x16-to-16-bit MAC : 2 -# Multipliers : 1 - 16x16-bit registered multiplier : 1 -# Adders/Subtractors : 99 - 1-bit subtractor : 1 - 11-bit adder : 1 - 11-bit subtractor : 1 - 12-bit adder : 2 - 14-bit adder : 1 - 14-bit subtractor : 2 - 16-bit adder : 6 - 16-bit subtractor : 2 - 17-bit adder : 3 - 17-bit subtractor : 1 - 2-bit adder : 6 - 24-bit adder : 7 - 27-bit adder : 3 - 28-bit adder : 1 - 29-bit adder : 2 - 3-bit adder : 2 - 3-bit subtractor : 3 - 30-bit adder : 1 - 32-bit adder : 7 - 32-bit subtractor : 2 - 33-bit adder carry in : 1 - 33-bit subtractor borrow in : 1 - 4-bit adder : 14 - 5-bit adder : 8 - 6-bit adder : 1 - 7-bit adder : 4 - 7-bit subtractor : 4 - 8-bit adder : 4 - 8-bit subtractor : 6 - 9-bit subtractor : 2 -# Counters : 88 - 1-bit up counter : 4 - 10-bit up counter : 3 - 11-bit up counter : 2 - 12-bit up counter : 2 - 13-bit up counter : 2 - 15-bit down counter : 3 - 16-bit down counter : 5 - 16-bit up counter : 7 - 2-bit down counter : 1 - 2-bit up counter : 2 - 2-bit updown counter : 1 - 21-bit up counter : 2 - 22-bit up counter : 2 - 23-bit up counter : 2 - 24-bit up counter : 1 - 25-bit up counter : 2 - 3-bit up counter : 2 - 30-bit up counter : 2 - 32-bit down counter : 4 - 32-bit up counter : 1 - 4-bit up counter : 4 - 4-bit updown counter : 2 - 5-bit up counter : 6 - 5-bit updown counter : 4 - 6-bit up counter : 3 - 7-bit up counter : 2 - 8-bit down counter : 4 - 8-bit up counter : 6 - 8-bit updown counter : 3 - 9-bit down counter : 4 -# Accumulators : 3 - 11-bit up accumulator : 2 - 6-bit up loadable accumulator : 1 -# Registers : 14552 - Flip-Flops : 14552 -# Shift Registers : 100 - 32-bit dynamic shift register : 100 -# Comparators : 159 - 1-bit comparator equal : 36 - 10-bit comparator equal : 1 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 7 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 2-bit comparator equal : 17 - 20-bit comparator equal : 1 - 26-bit comparator greater : 3 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator equal : 8 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 20 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 1 - 8-bit comparator not equal : 2 -# Multiplexers : 2634 - 1-bit 128-to-1 multiplexer : 4 - 1-bit 2-to-1 multiplexer : 2046 - 1-bit 3-to-1 multiplexer : 5 - 1-bit 4-to-1 multiplexer : 41 - 1-bit 7-to-1 multiplexer : 64 - 1-bit 8-to-1 multiplexer : 19 - 11-bit 2-to-1 multiplexer : 9 - 14-bit 2-to-1 multiplexer : 4 - 16-bit 2-to-1 multiplexer : 35 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 24 - 20-bit 2-to-1 multiplexer : 1 - 23-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 7 - 24-bit 4-to-1 multiplexer : 1 - 25-bit 2-to-1 multiplexer : 12 - 28-bit 2-to-1 multiplexer : 4 - 29-bit 2-to-1 multiplexer : 8 - 3-bit 2-to-1 multiplexer : 18 - 30-bit 2-to-1 multiplexer : 2 - 32-bit 2-to-1 multiplexer : 120 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 70 - 4-bit 6-to-1 multiplexer : 2 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 14 - 6-bit 2-to-1 multiplexer : 1 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 88 - 8-bit 4-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 4 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 3 - 1-bit shifter logical left : 2 - 64-bit shifter logical right : 1 -# FSMs : 17 -# Xors : 625 - 1-bit xor2 : 504 - 1-bit xor3 : 18 - 1-bit xor4 : 10 - 32-bit xor2 : 93 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - st_idle | 000 - st_start | 001 - st_read | 010 - st_write | 011 - st_ack | 100 - st_stop | 101 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 00000 - start_a | 00001 - start_b | 00010 - start_c | 00011 - start_d | 00100 - start_e | 00101 - stop_a | 00110 - stop_b | 00111 - stop_c | 01000 - stop_d | 01001 - rd_a | 01010 - rd_b | 01011 - rd_c | 01100 - rd_d | 01101 - wr_a | 01110 - wr_b | 01111 - wr_c | 10000 - wr_d | 10001 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - eth | 0001 - eth_capture | 0010 - eth_chk | 0011 - ipv4 | 0100 - ipv4_capture | 0101 - ipv4_chksum | unreached - ipv4_opt | 0111 - udp | 1000 - udp_fetch_buf | 1001 - udp_capture | 1010 - chk | 1011 - done | 1100 - errors | 1101 - waits | 1110 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 000 - header | 001 - payload | 010 - padding | 011 - done | 100 - errors | 101 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------ - State | Encoding ------------------------------------ - idle | 00000 - eb_hdr_rec | 00001 - eb_hdr_proc | 00010 - eb_hdr_probe_id | 00011 - eb_hdr_probe_rdy | 00100 - cyc_hdr_rec | 00101 - cyc_hdr_read_proc | 00110 - cyc_hdr_read_get_adr | 00111 - wb_read_rdy | 01000 - wb_read | 01001 - cyc_hdr_write_proc | 01010 - cyc_hdr_write_get_adr | 01011 - wb_write_rdy | 01100 - wb_write | 01101 - wb_write_done | 01110 - cyc_done | 01111 - eb_done | 10000 - error | 10001 - error_wait | 10010 ------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------- - State | Encoding -------------------------------------- - idle | 000000000001 - eb_hdr_init | 000000000100 - eb_hdr_probe_id | 001000000000 - eb_hdr_probe_wait | 000010000000 - packet_hdr_send | 000001000000 - eb_hdr_send | 000100000000 - rdy | 000000000010 - cyc_hdr_init | 000000001000 - cyc_hdr_send | 010000000000 - base_write_adr_send | 000000010000 - data_send | 100000000000 - zero_pad_write | 000000100000 - zero_pad_wait | unreached - error | unreached -------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - calc_chksum | 0001 - wait_send_req | 0010 - prep_eth | 0011 - eth | 0100 - ipv4 | 0101 - udp | 0110 - hdr_send | 0111 - payload_send | 1000 - padding | 1001 - wait_ifgap | 1010 - error | 1011 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - addup | 001 - carries | 010 - finalise | 011 - output | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ----------------------- - State | Encoding ----------------------- - idle | 00 - init | 01 - transfer | 11 - waiting | unreached - done | 10 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - init | 001 - transfer | 010 - waiting | unreached - done | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0110 | 0010 - 0101 | 0011 - 0010 | 0100 - 0011 | 0101 - 0100 | 0110 - 0111 | 0111 - 1000 | 1000 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0001 | 00 - 0010 | 01 - 0100 | 11 - 1000 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 011 | 011 - 100 | 100 -------------------- -WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL. - You should achieve better results by setting this init to 1. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:1901 - Instance gen_clock_chains[1].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc_clk_bufio in unit fmc516_adc_iface of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_clock_chains[0].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc_clk_bufio in unit fmc516_adc_iface of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_adc_data[0].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[1].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[2].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[3].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[4].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[5].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[6].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[7].cmp_iddr in unit fmc516_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:638 - in unit dbe_bpm_dsp Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_dsp Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_dsp Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : - -Mapping all equations... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -Building and optimizing final netlist ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_dsp, actual ratio is 19. -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 122 FFs/Latches : - - - - - - - - - - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 122 FFs/Latches : - - - - - - - - - - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 122 FFs/Latches : - - - - - - - - - - - - - - - - - -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 13 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Final Macro Processing ... - -Processing Unit : - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -Processing Unit : - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 14772 - Flip-Flops : 14772 -# Shift Registers : 13 - 2-bit shift register : 4 - 3-bit shift register : 1 - 5-bit shift register : 8 - -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- ------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -sys_clk_p_i | IBUFGDS+BUFG | 11 | -cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc516_adc_clk/adc_clk_ibufgds_dly| MMCM_ADV:CLKOUT1 | 65317 | -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 6450 | -cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc516_adc_clk/adc_clk_ibufgds_dly| MMCM_ADV:CLKOUT0 | 1363 | -mrx_clk_pad_i | BUFGP | 287 | -mtx_clk_pad_i | BUFGP | 225 | -cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc516_adc_clk/adc_clk_ibufgds_dly| BUFR | 267 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtag_cores/jtag_tap/update_delay)| 23 | -cmp_chipscope_icon_7_port/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 1475 | -cmp_chipscope_icon_7_port/CONTROL0<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/CONTROL6<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[6].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/CONTROL5<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[5].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/CONTROL4<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[4].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/CONTROL3<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/CONTROL2<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/CONTROL1<13>(cmp_chipscope_icon_7_port/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_7_port/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_7_port/U0/U_ICON/U_iDATA_CMD) | 1 | ------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -(*) These 7 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -FindSrcOfAsyncThruGates : 100 (1) -FindSrcOfAsyncThruGates : 200 (1) -FindSrcOfAsyncThruGates : 300 (1) -FindSrcOfAsyncThruGates : 400 (1) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_8192_bpf_mix/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 136 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_8192_fofb_amp/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 136 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_8192_fofb_pos/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 136 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_8192_monit_pos/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 136 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_8192_tbt_amp/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 136 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_8192_tbt_pos/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 136 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_compiler_5_0/dds_cmplr_v5_0_ca0550aac85c1501_instance/sig00000001(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_compiler_5_0/dds_cmplr_v5_0_ca0550aac85c1501_instance/blk00000001:P) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_compiler_5_0/dds_cmplr_v5_0_ca0550aac85c1501_instance/blk00000213) | 62 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/sig0000037e(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk0000014a:P) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk0000014b) | 62 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instance/blk00000152/sig000003a0(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instance/blk00000152/blk00000154:P) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instance/blk00000152/blk00000155) | 62 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/sig00002209(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031a:P)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 62 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/sig00002301(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000385:P)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 62 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/sig00002209(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031a:P)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 62 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/sig00002301(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000385:P)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 62 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0_fmc516_adc/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 56 | -cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G) | NONE(cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram) | 48 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_compiler_5_0/dds_cmplr_v5_0_ca0550aac85c1501_instance/sig000001a0(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_compiler_5_0/dds_cmplr_v5_0_ca0550aac85c1501_instance/blk00000002:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/dds_compiler_5_0/dds_cmplr_v5_0_ca0550aac85c1501_instance/blk00000213) | 38 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/sig0000037d(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk00000149:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instance/blk00000148/blk0000014b) | 36 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instance/blk00000152/sig0000039f(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instance/blk00000152/blk00000153:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instance/blk00000152/blk00000155) | 36 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/sig00002208(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk00000319:G)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 36 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/sig00002300(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000384:G)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp0_88b1c45f0e/tbt_poly_decim_4477ec06c2/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 36 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/sig00002208(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk00000319:G)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk000002d5/blk00000318/blk0000031b) | 36 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/sig00002300(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000384:G)| NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb0c/tbt_amp1_6e98f85f9f/tbt_poly_decim_bb6f6b5b6a/tbt_poly/fr_cmplr_v6_3_fe47fe6ccabc2305_instance/blk00000001/blk00000340/blk00000383/blk00000386) | 36 | -cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_0_fmc516_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_8192_bpf_mix/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_8192_fofb_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_8192_fofb_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_8192_monit_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_8192_tbt_amp/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_8192_tbt_pos/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1) | 6 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_10922_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_10922_o1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo) | 4 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/q_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/q_divider/dv_gn_v4_0_7887f22978e0003d_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/q_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/y_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/y_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_fofb_ee61e649ea/y_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/q_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/q_divider/dv_gn_v4_0_7887f22978e0003d_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/q_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/y_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/y_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_monit_a8f8b81626/y_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/q_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/q_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/q_divider/dv_gn_v4_0_fc1ee041a30564f8_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/x_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/y_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/del_addr_offset(1)(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/y_divider/dv_gn_v4_0_7887f22978e0003d_instance/XST_GND:G) | NONE(cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/delta_sigma_tbt_bbfa8a8a69/y_divider/dv_gn_v4_0_7887f22978e0003d_instance/U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_radix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim) | 2 | -wbs_fmc516_in_array[3]_ack(XST_VCC:P) | NONE(cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc_clk_bufr) | 2 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 18.338ns (Maximum Frequency: 54.532MHz) - Minimum input arrival time before clock: 4.798ns - Maximum output required time after clock: 1.801ns - Maximum combinational path delay: 0.896ns - -========================================================================= - -Process "Synthesize - XST" completed successfully - -Started : "Translate". -Running ngdbuild... -Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope/icon_4_port -sd ../../platform/virtex6/chipscope/icon_7_port -sd ../../platform/virtex6/chipscope/icon_8_port -sd ../../platform/virtex6/chipscope/ila -sd ../../modules/custom_wishbone/wb_fmc150/netlist -sd ../../ip_cores/dsp-cores/hdl/modules/position_calc/generated -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf -uc /home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/ddc_bpm_476_066_cw.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_dsp.ngc dbe_bpm_dsp.ngd - -Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle -ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd -../../platform/virtex6/chipscope/icon_2_port -sd -../../platform/virtex6/chipscope/icon_4_port -sd -../../platform/virtex6/chipscope/icon_7_port -sd -../../platform/virtex6/chipscope/icon_8_port -sd -../../platform/virtex6/chipscope/ila -sd -../../modules/custom_wishbone/wb_fmc150/netlist -sd -../../ip_cores/dsp-cores/hdl/modules/position_calc/generated -nt timestamp -uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf -uc -/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/gener -ated/ddc_bpm_476_066_cw.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_dsp.ngc -dbe_bpm_dsp.ngd - -Reading NGO file "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_dsp/dbe_bpm_dsp.ngc" -... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_2698630 -1a9f671cd.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/dv_gn_v4_0_7887f22 -978e0003d.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/dv_gn_v4_0_fc1ee04 -1a30564f8.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_8b07479 -70e52f130.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/addsb_11_0_239e4f6 -14ba09ab1.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/mult_11_2_6d8e463c -710483da.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_ef82 -69b30b0e0deb.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_d31b -0f3a494d423b.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_59fb -d17f7e62a7fe.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/crdc_v5_0_19fb63de -ad3076ad.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cmpy_v5_0_fc1d9188 -1e8e8ae6.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_0c61 -ac74cf3e5cc7.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cc_cmplr_v3_0_3ac9 -02fec2d60a4a.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_95e3 -c24666ebc2c9.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fr_cmplr_v6_3_fe47 -fe6ccabc2305.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/cntr_11_0_3166d4cc -5b09c744.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/dds_cmplr_v5_0_ca0 -550aac85c1501.ngc"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/xlpersistentdff.ng -c"... -Loading design module -"../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/fifo_generator_vir -tex6_8_4_784d0e5148f6dbe1.ngc"... -Loading design module -"../../platform/virtex6/chipscope/ila/chipscope_ila.ngc"... -Loading design module -"../../platform/virtex6/chipscope/ila/chipscope_ila_8192.ngc"... -Loading design module -"../../platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.ngc"... - /dbe_bpm_dsp/dbe_bpm_dsp - /dbe_bpm_dsp/cmp_chipscope_ila_0_fmc516_adc - /dbe_bpm_dsp/cmp_chipscope_ila_8192_monit_pos - /dbe_bpm_dsp/cmp_chipscope_ila_8192_fofb_pos - /dbe_bpm_dsp/cmp_chipscope_ila_8192_fofb_amp - /dbe_bpm_dsp/cmp_chipscope_ila_8192_tbt_pos - /dbe_bpm_dsp/cmp_chipscope_ila_8192_tbt_amp - /dbe_bpm_dsp/cmp_chipscope_ila_8192_bpf_mix - ------------------------------------------------ -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - ------------------------------------------------ - ------------------------------------------------ -Gathering constraint information from source properties... -Done. - -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf" ... -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/gene -rated/ddc_bpm_476_066_cw.ucf" ... -Resolving constraint associations... -Checking Constraint Associations... -WARNING:ConstraintSystem:137 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(138)]: - No appropriate instances for the TNM constraint are driven by "adc_clk2_p_i". - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(139)]: - Unable to find an active 'TNM' or 'TimeGrp' constraint named 'adc_clk2_p_i'. - -WARNING:ConstraintSystem:137 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(143)]: - No appropriate instances for the TNM constraint are driven by "adc_clk3_p_i". - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(144)]: - Unable to find an active 'TNM' or 'TimeGrp' constraint named 'adc_clk3_p_i'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(203)]: - Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named - 'TNM_ADC_DATA_2'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(204)]: - Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named - 'TNM_ADC_DATA_2'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(208)]: - Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named - 'TNM_ADC_DATA_3'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(209)]: - Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named - 'TNM_ADC_DATA_3'. - - - -WARNING:ConstraintSystem:191 - The TNM 'adc_clk2_p_i', does not directly or - indirectly drive any flip-flops, latches and/or RAMS and cannot be actively - used by the referencing Period constraint 'TS_adc_clk2_p_i'. If clock manager - blocks are directly or indirectly driven, a new TNM constraint will not be - derived even though the referencing constraint is a PERIOD constraint unless - an output of the clock manager drives flip-flops, latches or RAMs. This TNM - is used in the following user PERIOD specification: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(139)] - -WARNING:ConstraintSystem:197 - The following specification is invalid because - the referenced TNM constraint was removed: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(139)] - -WARNING:ConstraintSystem:191 - The TNM 'adc_clk3_p_i', does not directly or - indirectly drive any flip-flops, latches and/or RAMS and cannot be actively - used by the referencing Period constraint 'TS_adc_clk3_p_i'. If clock manager - blocks are directly or indirectly driven, a new TNM constraint will not be - derived even though the referencing constraint is a PERIOD constraint unless - an output of the clock manager drives flip-flops, latches or RAMs. This TNM - is used in the following user PERIOD specification: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(144)] - -WARNING:ConstraintSystem:197 - The following specification is invalid because - the referenced TNM constraint was removed: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp/dbe_bpm_dsp.ucf(144)] - -Done... - -Checking expanded design ... -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_default_clock_driver/xlclockdriver_1/clr_reg/latency_g - t_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected - output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/default_clock_driver_x0/xlclockdriv - er_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre - _comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/default_clock_driver_x0/xlclockdriv - er_2/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre - _comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_i/m - _axis_data_tuser_chan_sync_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg - _comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_i/m - _axis_data_tlast_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_p - rim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/m - _axis_data_tuser_chan_out_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_ - comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/m - _axis_data_tuser_chan_sync_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg - _comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/m - _axis_data_tlast_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_p - rim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_i/m - _axis_data_tlast_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_p - rim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_i/m - _axis_data_tuser_chan_sync_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg - _comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/m - _axis_data_tlast_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_p - rim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/m - _axis_data_tuser_chan_sync_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg - _comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/m - _axis_data_tuser_chan_out_ps_net_synchronizer_1/latency_gt_0.fd_array[1].reg_ - comp/fd_prim_array[0].bit_is_0.fdre_comp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/m_axis_data_tdata_ps_net_synchronizer/ - latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp' has - unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/m_axis_data_tdata_ps_net_synchronizer/ - latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp' has - unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/m_axis_data_tdata_ps_net_synchronizer/ - latency_gt_0.fd_array[1].reg_comp/fd_prim_array[23].bit_is_0.fdre_comp' has - unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/m_axis_data_tdata_ps_net_synchronizer/ - latency_gt_0.fd_array[1].reg_comp/fd_prim_array[24].bit_is_0.fdre_comp' has - unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cic/m_axis_data_tuser_chan_sync_ps_net_sync - hronizer_1/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_c - omp' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cic/m_axis_data_tlast_ps_net_synchronizer_1 - /latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp' has - unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6 - e8/tdm_mix_ch0_1_b9bb73dd5f/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6 - e8/tdm_mix_ch0_1_b9bb73dd5f/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6 - e8/tdm_mix_ch1_2_5f72ff242b/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_mix_54ce67e6 - e8/tdm_mix_ch1_2_5f72ff242b/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e3829 - 2ecb/up_sample_ch0/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e3829 - 2ecb/up_sample_ch1/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e3829 - 2ecb/up_sample_ch2/sel_gen' has unconnected output pin -WARNING:NgdBuild:443 - SFF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tdm_monit_6e3829 - 2ecb/up_sample_ch3/sel_gen' has unconnected output pin -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "U0/i_synth/i_nonzero_fract.i_synth/opt_high_radix.i_nonzero_fract.i_high_rad - ix/i_estimator/i_lut/i_synth_opt.i_synth/i_not_sandia.i_prim" of type - "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:440 - FF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_i/c - c_cmplr_v3_0_d31b0f3a494d423b_instance/U0/i_synth/decimator.decimation_filter - /int/gen_stages[2].gen_unfolded.int_comb_stage/gen_split_accum[1].gen_sum_str - uct.gen_sum/gen_structural.gen_no_dsp48.gen_adder[0].split_adder_n/gen_adders - [6].gen_reg_carry.i_reg' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_i/c - c_cmplr_v3_0_59fbd17f7e62a7fe_instance/U0/i_synth/decimator.decimation_filter - /int/gen_stages[2].gen_unfolded.int_comb_stage/gen_split_accum[1].gen_sum_str - uct.gen_sum/gen_structural.gen_no_dsp48.gen_adder[0].split_adder_n/gen_adders - [6].gen_reg_carry.i_reg' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_amp_f70fcc8ed9/cic_fofb_579902476d/cic_fofb_q/c - c_cmplr_v3_0_59fbd17f7e62a7fe_instance/U0/i_synth/decimator.decimation_filter - /int/gen_stages[2].gen_unfolded.int_comb_stage/gen_split_accum[1].gen_sum_str - uct.gen_sum/gen_structural.gen_no_dsp48.gen_adder[0].split_adder_n/gen_adders - [6].gen_reg_carry.i_reg' has unconnected output pin -WARNING:NgdBuild:440 - FF primitive - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_amp_078cdb1842/cic_fofb_2ed6a6e00c/cic_fofb_q/c - c_cmplr_v3_0_59fbd17f7e62a7fe_instance/U0/i_synth/decimator.decimation_filter - /int/gen_stages[2].gen_unfolded.int_comb_stage/gen_split_accum[1].gen_sum_str - uct.gen_sum/gen_structural.gen_no_dsp48.gen_adder[0].split_adder_n/gen_adders - [6].gen_reg_carry.i_reg' has unconnected output pin -WARNING:NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol - "blk00000214" of type "RAMB16". This attribute will be ignored. -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4c/sig00002578' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4c/sig00002579' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4c/sig0000257a' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4c/sig0000257c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4c/sig0000257d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4c/sig0000257e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4d/sig00002584' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4d/sig00002585' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4d/sig00002586' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4d/sig00002588' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4d/sig00002589' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4e/sig00002590' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4e/sig00002591' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4e/sig00002592' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4e/sig00002594' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4e/sig00002595' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4f/sig0000259c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4f/sig0000259d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4f/sig0000259e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4f/sig000025a0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c4f/sig000025a1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c50/sig000025a8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c50/sig000025a9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c50/sig000025aa' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c50/sig000025ac' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c50/sig000025ad' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c51/sig000025b4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c51/sig000025b5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c51/sig000025b6' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c51/sig000025b8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c51/sig000025b9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c52/sig000025c0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c52/sig000025c1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c52/sig000025c2' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c52/sig000025c4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c52/sig000025c5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c53/sig000025cc' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c53/sig000025cd' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c53/sig000025ce' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c53/sig000025d0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c53/sig000025d1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c54/sig000025d8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c54/sig000025d9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c54/sig000025da' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c54/sig000025dc' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c54/sig000025dd' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c55/sig000025e4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c55/sig000025e5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c55/sig000025e6' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c55/sig000025e8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c55/sig000025e9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c56/sig000025f0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c56/sig000025f1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c56/sig000025f2' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c56/sig000025f4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c56/sig000025f5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c56/sig000025f6' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c57/sig000025fc' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c57/sig000025fd' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c57/sig000025fe' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c57/sig00002600' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c57/sig00002601' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c58/sig00002608' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c58/sig00002609' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c58/sig0000260a' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c58/sig0000260c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c58/sig0000260d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c59/sig00002614' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c59/sig00002615' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c59/sig00002616' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c59/sig00002618' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c59/sig00002619' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5a/sig00002620' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5a/sig00002621' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5a/sig00002622' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5a/sig00002624' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5a/sig00002625' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5b/sig0000262c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5b/sig0000262d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5b/sig0000262e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5b/sig00002630' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5b/sig00002631' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5c/sig00002638' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5c/sig00002639' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5c/sig0000263a' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5c/sig0000263c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5c/sig0000263d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5d/sig00002644' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5d/sig00002645' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5d/sig00002646' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5d/sig00002648' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5d/sig00002649' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5e/sig00002650' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5e/sig00002651' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5e/sig00002652' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5e/sig00002654' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5e/sig00002655' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5f/sig0000265c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5f/sig0000265d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5f/sig0000265e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5f/sig00002660' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c5f/sig00002661' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c60/sig00002668' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c60/sig00002669' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c60/sig0000266a' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c60/sig0000266c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c60/sig0000266d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c60/sig0000266e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c61/sig00002674' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c61/sig00002675' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c61/sig00002676' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c61/sig00002678' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c61/sig00002679' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c62/sig00002680' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c62/sig00002681' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c62/sig00002682' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c62/sig00002684' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c62/sig00002685' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c63/sig0000268c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c63/sig0000268d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c63/sig0000268e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c63/sig00002690' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c63/sig00002691' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c64/sig00002698' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c64/sig00002699' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c64/sig0000269a' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c64/sig0000269c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c64/sig0000269d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c65/sig000026a4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c65/sig000026a5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c65/sig000026a6' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c65/sig000026a8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c65/sig000026a9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c66/sig000026b0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c66/sig000026b1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c66/sig000026b2' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c66/sig000026b4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c66/sig000026b5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c67/sig000026bc' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c67/sig000026bd' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c67/sig000026be' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c67/sig000026c0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c67/sig000026c1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c68/sig000026c8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c68/sig000026c9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c68/sig000026ca' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c68/sig000026cc' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c68/sig000026cd' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c69/sig000026d4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c69/sig000026d5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c69/sig000026d6' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c69/sig000026d8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c69/sig000026d9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6a/sig000026e0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6a/sig000026e1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6a/sig000026e2' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6a/sig000026e4' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6a/sig000026e5' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6a/sig000026e6' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6b/sig000026ec' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6b/sig000026ed' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6b/sig000026ee' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6b/sig000026f0' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6b/sig000026f1' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6c/sig000026f8' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6c/sig000026f9' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6c/sig000026fa' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6c/sig000026fc' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6c/sig000026fd' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6d/sig00002704' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6d/sig00002705' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6d/sig00002706' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6d/sig00002708' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6d/sig00002709' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6e/sig00002710' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6e/sig00002711' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6e/sig00002712' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6e/sig00002714' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6e/sig00002715' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6f/sig0000271c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6f/sig0000271d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6f/sig0000271e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6f/sig00002720' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c6f/sig00002721' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c70/sig00002728' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c70/sig00002729' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c70/sig0000272a' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c70/sig0000272c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c70/sig0000272d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c71/sig00002734' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c71/sig00002735' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c71/sig00002736' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c71/sig00002738' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c71/sig00002739' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c72/sig00002740' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c72/sig00002741' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c72/sig00002742' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c72/sig00002744' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c72/sig00002745' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c73/sig0000274c' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c73/sig0000274d' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c73/sig0000274e' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c73/sig00002750' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/bpf_d31c4af409/b - pf_fpga/fr_cmplr_v6_3_ef8269b30b0e0deb_instance/blk00000c73/sig00002751' has - no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp1_6e98f85f9f/tbt_cordic_9dc3371de2/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/tbt_amp_cbd277bb - 0c/tbt_amp0_88b1c45f0e/tbt_cordic_232cb2e43e/rect2pol/crdc_v5_0_19fb63dead307 - 6ad_instance/blk00001bd4/sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp1_a049562dde/fofb_cordic_e4c0810ec7/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000257f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002580' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002581' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002582' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002583' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002584' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002585' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002586' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002587' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002588' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002589' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258a' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258b' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258c' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258d' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258e' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig0000258f' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002590' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002591' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002592' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002593' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002594' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002595' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002596' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002597' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002598' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/fofb_amp_8b25d4b - 0b6/fofb_amp0_95b23bfc2c/fofb_cordic_fad57e49ce/rect2pol/crdc_v5_0_19fb63dead - 3076ad_instance/blk00001bd4/sig00002599' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instanc - e/blk0000017d/sig000003bc' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instanc - e/blk0000017d/sig000003bd' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instanc - e/blk0000017d/sig000003bf' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instanc - e/blk0000017d/sig000003c0' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instanc - e/blk0000017d/sig000003c1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_cfir/fr_cmplr_v6_3_0c61ac74cf3e5cc7_instanc - e/sig000001a1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instanc - e/blk00000188/sig000003e1' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instanc - e/blk00000188/sig000003e2' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instanc - e/blk00000188/sig000003e4' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instanc - e/blk00000188/sig000003e5' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instanc - e/blk00000188/sig000003e6' has no driver -WARNING:NgdBuild:452 - logical net - 'cmp_position_calc/cmp_ddc_bpm_476_066_cw/ddc_bpm_476_066_x0/monit_amp_44da74 - e268/monit_amp_c_c83793ea71/monit_pfir/fr_cmplr_v6_3_95e3c24666ebc2c9_instanc - e/sig000001ad' has no driver - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 377 - -Writing NGD file "dbe_bpm_dsp.ngd" ... -Total REAL time to NGDBUILD completion: 2 min 55 sec -Total CPU time to NGDBUILD completion: 2 min 53 sec - -Writing NGDBUILD log file "dbe_bpm_dsp.bld"... - -NGDBUILD done. - -Process "Translate" completed successfully - -Started : "Map". -Running map... -Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_dsp_map.ncd dbe_bpm_dsp.ngd dbe_bpm_dsp.pcf -Using target part "6vlx240tff1156-1". -INFO:Map:284 - Map is running with the multi-threading option on. Map currently - supports the use of up to 2 processors. Based on the the user options and - machine load, Map will use 2 processors during this run. -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part -'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -WARNING:MapLib:701 - Signal adc_clk3_p_i connected to top level port - adc_clk3_p_i has been removed. -WARNING:MapLib:701 - Signal adc_clk3_n_i connected to top level port - adc_clk3_n_i has been removed. -WARNING:MapLib:701 - Signal adc_clk2_p_i connected to top level port - adc_clk2_p_i has been removed. -WARNING:MapLib:701 - Signal adc_clk2_n_i connected to top level port - adc_clk2_n_i has been removed. -Running directed packing... -WARNING:Pack:1186 - One or more I/O components have conflicting property values. - For each occurrence, the system will use the property value attached to the - pad. Otherwise, the system will use the first property value read. To view - each occurrence, create a detailed map report (run map using the -detail - option). -Running delay-based LUT packing... -Updating timing models... -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_1112_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2224_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_1390000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_22240000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_2780000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_5560000_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" TO - TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_1112_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_1390000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_22240000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_2224_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_2780000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_5000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_5560000_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" TO - TIMEGRP "ce_556_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_2224_cc71cef7_group" 35.5292874 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_5000_cc71cef7_group" - TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_1112_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_2224_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" TO - TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" TO - TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" - TO TIMEGRP "ce_5000_cc71cef7_group" 17.7646437 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 2469.28547 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_556_cc71cef7_group" TO - TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_1390000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_22240000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_2224_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_2780000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_35_cc71cef7_group" 155.440632 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_5000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" - TO TIMEGRP "ce_5560000_cc71cef7_group" 44.4116092 ns ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_70_cc71cef7_group" TO - TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns ignored during timing analysis. -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 8 mins 42 secs -Total CPU time at the beginning of Placer: 5 mins 59 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:5ed76986) REAL time: 10 mins 27 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:5ed76986) REAL time: 10 mins 43 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:33f2f6db) REAL time: 10 mins 43 secs - -Phase 4.37 Local Placement Optimization -Phase 4.37 Local Placement Optimization (Checksum:33f2f6db) REAL time: 10 mins 43 secs - -Phase 5.2 Initial Placement for Architecture Specific Features - -...... - - -There are 12 clock regions on the target FPGA device: -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: | -| 4 BUFRs available, 1 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 2 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 1 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 1 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: | -| 4 BUFRs available, 1 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 2 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 1 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 1 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 1/4; bufrs - 1/4; regional-clock-spines - 2/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | Upper/ | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/ | 2 | 0 | 0 | 0 | 0 | 218 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 1/4; center-bufios - 0/4; bufrs - 1/4; regional-clock-spines - 2/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | Lower | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 2 | 0 | 0 | 0 | 0 | 218 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - - - -###################################################################################### -# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT: -# -# Number of Regional Clocking Regions in the device: 12 (6 clock spines in each) -# Number of Regional Clock Networks used in this design: 4 (each network can be -# composed of up to 3 clock spines and cover up to 3 regional clock regions) -# -###################################################################################### - -# IO-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" driven by "BUFIODQS_X0Y6" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc -_clk_bufio" LOC = "BUFIODQS_X0Y6" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y0; - - -# IO-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" driven by "BUFIODQS_X1Y2" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc -_clk_bufio" LOC = "BUFIODQS_X1Y2" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# Regional-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" driven by "BUFR_X0Y2" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc -_clk_bufr" LOC = "BUFR_X0Y2" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[1]_adc_clk_bufr" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -# Regional-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" driven by "BUFR_X1Y0" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc516_adc_clk/cmp_adc -_clk_bufr" LOC = "BUFR_X1Y0" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain[0]_adc_clk_bufr" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -Phase 5.2 Initial Placement for Architecture Specific Features (Checksum:d8786eb6) REAL time: 12 mins 30 secs - -Phase 6.36 Local Placement Optimization -Phase 6.36 Local Placement Optimization (Checksum:d8786eb6) REAL time: 12 mins 30 secs - -Phase 7.30 Global Clock Region Assignment -Phase 7.30 Global Clock Region Assignment (Checksum:d8786eb6) REAL time: 12 mins 30 secs - -Phase 8.3 Local Placement Optimization -Phase 8.3 Local Placement Optimization (Checksum:d8786eb6) REAL time: 12 mins 33 secs - -Phase 9.5 Local Placement Optimization -Phase 9.5 Local Placement Optimization (Checksum:d8786eb6) REAL time: 12 mins 34 secs - -Phase 10.8 Global Placement -.................................... -.................................................................................................................... -......................................................................................................................... -................................................................................................ -........................................ -Phase 10.8 Global Placement (Checksum:308d1cc8) REAL time: 22 mins 15 secs - -Phase 11.5 Local Placement Optimization -Phase 11.5 Local Placement Optimization (Checksum:308d1cc8) REAL time: 22 mins 20 secs - -Phase 12.18 Placement Optimization -Phase 12.18 Placement Optimization (Checksum:b1623fd) REAL time: 25 mins 22 secs - -Phase 13.5 Local Placement Optimization -Phase 13.5 Local Placement Optimization (Checksum:b1623fd) REAL time: 25 mins 23 secs - -Phase 14.34 Placement Validation -Phase 14.34 Placement Validation (Checksum:a3b40784) REAL time: 25 mins 27 secs - -Total REAL time to Placer completion: 25 mins 45 secs -Total CPU time to Placer completion: 19 mins 43 secs -Running post-placement packing... -Writing output files... - -Design Summary: -Number of errors: 0 -Number of warnings: 163 -Slice Logic Utilization: - Number of Slice Registers: 54,304 out of 301,440 18% - Number used as Flip Flops: 54,294 - Number used as Latches: 9 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 53,010 out of 150,720 35% - Number used as logic: 35,887 out of 150,720 23% - Number using O6 output only: 26,609 - Number using O5 output only: 1,344 - Number using O5 and O6: 7,934 - Number used as ROM: 0 - Number used as Memory: 13,734 out of 58,400 23% - Number used as Dual Port RAM: 472 - Number using O6 output only: 52 - Number using O5 output only: 10 - Number using O5 and O6: 410 - Number used as Single Port RAM: 624 - Number using O6 output only: 624 - Number using O5 output only: 0 - Number using O5 and O6: 0 - Number used as Shift Register: 12,638 - Number using O6 output only: 8,792 - Number using O5 output only: 2,341 - Number using O5 and O6: 1,505 - Number used exclusively as route-thrus: 3,389 - Number with same-slice register load: 2,874 - Number with same-slice carry load: 515 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 18,800 out of 37,680 49% - Number of LUT Flip Flop pairs used: 61,969 - Number with an unused Flip Flop: 14,986 out of 61,969 24% - Number with an unused LUT: 8,959 out of 61,969 14% - Number of fully used LUT-FF pairs: 38,024 out of 61,969 61% - Number of unique control sets: 1,111 - Number of slice register sites lost - to control set restrictions: 3,624 out of 301,440 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 140 out of 600 23% - Number of LOCed IOBs: 140 out of 140 100% - IOB Flip Flops: 32 - IOB Master Pads: 2 - IOB Slave Pads: 2 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 257 out of 416 61% - Number using RAMB36E1 only: 257 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 28 out of 832 3% - Number using RAMB18E1 only: 28 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 11 out of 32 34% - Number used as BUFGs: 11 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 32 out of 720 4% - Number used as ILOGICE1s: 32 - Number used as ISERDESE1s: 0 - Number of OLOGICE1/OSERDESE1s: 4 out of 720 1% - Number used as OLOGICE1s: 4 - Number used as OSERDESE1s: 0 - Number of BSCANs: 2 out of 4 50% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 2 out of 72 2% - Number of BUFRs: 2 out of 36 5% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 260 out of 768 33% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 4 out of 18 22% - Number of IODELAYE1s: 34 out of 720 4% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - Number of RPM macros: 90 -Average Fanout of Non-Clock Nets: 3.29 - -Peak Memory Usage: 3116 MB -Total REAL time to MAP completion: 30 mins 18 secs -Total CPU time to MAP completion (all processors): 20 mins 38 secs - -Mapping completed. -See MAP report file "dbe_bpm_dsp_map.mrp" for details. - -Process "Map" completed successfully - -Started : "Place & Route". -Running par... -Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_dsp_map.ncd dbe_bpm_dsp.ncd dbe_bpm_dsp.pcf - - - -Constraints file: dbe_bpm_dsp.pcf. -Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_dsp" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRODUCTION 1.17 2012-01-07". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 54,304 out of 301,440 18% - Number used as Flip Flops: 54,294 - Number used as Latches: 9 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 53,010 out of 150,720 35% - Number used as logic: 35,887 out of 150,720 23% - Number using O6 output only: 26,609 - Number using O5 output only: 1,344 - Number using O5 and O6: 7,934 - Number used as ROM: 0 - Number used as Memory: 13,734 out of 58,400 23% - Number used as Dual Port RAM: 472 - Number using O6 output only: 52 - Number using O5 output only: 10 - Number using O5 and O6: 410 - Number used as Single Port RAM: 624 - Number using O6 output only: 624 - Number using O5 output only: 0 - Number using O5 and O6: 0 - Number used as Shift Register: 12,638 - Number using O6 output only: 8,792 - Number using O5 output only: 2,341 - Number using O5 and O6: 1,505 - Number used exclusively as route-thrus: 3,389 - Number with same-slice register load: 2,874 - Number with same-slice carry load: 515 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 18,800 out of 37,680 49% - Number of LUT Flip Flop pairs used: 61,969 - Number with an unused Flip Flop: 14,986 out of 61,969 24% - Number with an unused LUT: 8,959 out of 61,969 14% - Number of fully used LUT-FF pairs: 38,024 out of 61,969 61% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 140 out of 600 23% - Number of LOCed IOBs: 140 out of 140 100% - IOB Flip Flops: 32 - IOB Master Pads: 2 - IOB Slave Pads: 2 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 257 out of 416 61% - Number using RAMB36E1 only: 257 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 28 out of 832 3% - Number using RAMB18E1 only: 28 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 11 out of 32 34% - Number used as BUFGs: 11 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 32 out of 720 4% - Number used as ILOGICE1s: 32 - Number used as ISERDESE1s: 0 - Number of OLOGICE1/OSERDESE1s: 4 out of 720 1% - Number used as OLOGICE1s: 4 - Number used as OSERDESE1s: 0 - Number of BSCANs: 2 out of 4 50% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 2 out of 72 2% - Number of BUFRs: 2 out of 36 5% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 260 out of 768 33% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 4 out of 18 22% - Number of IODELAYE1s: 34 out of 720 4% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -INFO:Timing:2802 - Read 132 constraints. If you are experiencing memory or runtime issues it may help to consolidate some of these - constraints. For more details please do a search for "timing:2802" at http://www.xilinx.com/support. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1112_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_1390000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_22240000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2224_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2780000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_2_cc71cef7_group" - TO TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP "ce_35_cc71cef7_group" - TO TIMEGRP "ce_2_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_35_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_5560000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 17.7646437 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_556_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 155.440632 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint TS_ce_70_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 8.88232184 ns; ignored during timing analysis. -INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx - Command Line Tools User Guide for information on generating a TSI report. -Starting initial Timing Analysis. REAL time: 2 mins 52 secs -Finished initial Timing Analysis. REAL time: 2 mins 56 secs - -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM - 1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM - 3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM - 4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM - 2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_fofb_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_ - RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RA - M1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RA - M4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_tbt_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_R - AMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RA - M3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_sum/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RA - M2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_q/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_x/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal - cmp_position_calc/cmp_ddc_bpm_476_066_cw/fifo_monit_ds_y/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4 - _RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring5_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -Starting Router - - -Phase 1 : 397032 unrouted; REAL time: 3 mins 4 secs - -Phase 2 : 243047 unrouted; REAL time: 3 mins 32 secs - -Phase 3 : 73389 unrouted; REAL time: 4 mins 56 secs - -Phase 4 : 73333 unrouted; (Setup:78024, Hold:27190, Component Switching Limit:0) REAL time: 5 mins 40 secs - -Updating file: dbe_bpm_dsp.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:60019, Hold:22763, Component Switching Limit:0) REAL time: 8 mins 58 secs - -Phase 6 : 0 unrouted; (Setup:52804, Hold:22763, Component Switching Limit:0) REAL time: 9 mins 44 secs - -Updating file: dbe_bpm_dsp.ncd with current fully routed design. - -Phase 7 : 0 unrouted; (Setup:52784, Hold:22763, Component Switching Limit:0) REAL time: 11 mins 29 secs - -Phase 8 : 0 unrouted; (Setup:52784, Hold:22763, Component Switching Limit:0) REAL time: 11 mins 29 secs - -Phase 9 : 0 unrouted; (Setup:52784, Hold:1244, Component Switching Limit:0) REAL time: 11 mins 35 secs - -Phase 10 : 0 unrouted; (Setup:52616, Hold:1244, Component Switching Limit:0) REAL time: 12 mins 1 secs -Total REAL time to Router completion: 12 mins 2 secs -Total CPU time to Router completion: 11 mins 49 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain[1]_adc_clk2x_buf | | | | | | -| g | BUFGCTRL_X0Y0| No |13848 | 0.468 | 2.048 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_sys | BUFGCTRL_X0Y6| No | 2310 | 0.347 | 1.952 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -| ain[1]_adc_clk_bufg | BUFGCTRL_X0Y1| No | 299 | 0.422 | 2.019 | -+---------------------+--------------+------+------+------------+-------------+ -| mrx_clk_pad_i_BUFGP | BUFGCTRL_X0Y3| No | 100 | 0.227 | 1.903 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -| ain[1]_adc_clk_bufr | Regional Clk| No | 67 | 0.323 | 1.210 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -| ain[0]_adc_clk_bufr | Regional Clk| No | 69 | 0.260 | 1.107 | -+---------------------+--------------+------+------+------------+-------------+ -| mtx_clk_pad_i_BUFGP | BUFGCTRL_X0Y4| No | 95 | 0.143 | 1.899 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<0> |BUFGCTRL_X0Y29| No | 848 | 0.468 | 2.048 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_gen |BUFGCTRL_X0Y31| No | 5 | 0.004 | 1.824 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_200mhz | BUFGCTRL_X0Y7| No | 4 | 0.145 | 1.826 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_chipscope_icon_7 | | | | | | -|_port/U0/iUPDATE_OUT | | | | | | -| | Local| | 1 | 0.000 | 1.014 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL1<13> | Local| | 5 | 0.000 | 0.886 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/gen_clock_ | | | | | | -|chains[1].gen_clock_ | | | | | | -|chains_check.cmp_fmc | | | | | | -|516_adc_clk/gen_with | | | | | | -|_ref_clk.cmp_mmcm_ad | | | | | | -| c_clk_ML_NEW_I1 | Local| | 3 | 0.000 | 1.451 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_I1 | Local| | 3 | 0.000 | 1.349 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_lm32/gen_profile | | | | | | -|_medium_icache_debug | | | | | | -|.U_Wrapped_LM32/jtck | | | | | | -| | Local| | 7 | 0.803 | 2.764 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL2<13> | Local| | 5 | 0.000 | 1.933 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL3<13> | Local| | 5 | 0.000 | 1.251 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL4<13> | Local| | 5 | 0.000 | 1.106 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL5<13> | Local| | 5 | 0.000 | 1.189 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL6<13> | Local| | 5 | 0.000 | 1.224 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<13> | Local| | 5 | 0.000 | 0.864 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain[1]_adc_clk_bufio | | | | | | -| | Local| | 32 | 0.211 | 1.499 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain[0]_adc_clk_bufio | | | | | | -| | Local| | 32 | 0.211 | 1.499 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_OUT | Local| | 2 | 0.000 | 0.359 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/gen_clock_ | | | | | | -|chains[1].gen_clock_ | | | | | | -|chains_check.cmp_fmc | | | | | | -|516_adc_clk/gen_with | | | | | | -|_ref_clk.cmp_mmcm_ad | | | | | | -| c_clk_ML_NEW_OUT | Local| | 2 | 0.000 | 0.481 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_2575_ML_N | | | | | | -| EW_CLK | Local| | 3 | 0.000 | 0.354 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_2567_ML_N | | | | | | -| EW_CLK | Local| | 3 | 0.132 | 0.361 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -* The fanout is the number of component pins not the individual BEL loads, -for example SLICE loads not FF loads. - -Timing Score: 53860 (Setup: 52616, Hold: 1244, Component Switching Limit: 0) - -WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. - - Review the timing report using Timing Analyzer (In ISE select "Post-Place & - Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. - - Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options - are set in the tools for timing closure. - - Use the Xilinx "SmartXplorer" script to try special combinations of - options known to produce very good results. - - Visit the Xilinx technical support web at http://support.xilinx.com and go to - either "Troubleshoot->Tech Tips->Timing & Constraints" or " - TechXclusives->Timing Closure" for tips and suggestions for meeting timing - in your design. - -Number of Timing Constraints that were not applied: 100 - -Asterisk (*) preceding a constraint indicates it was not met. - This may be due to a setup or hold violation. - ----------------------------------------------------------------------------------------------------------- - Constraint | Check | Worst Case | Best Case | Timing | Timing - | | Slack | Achievable | Errors | Score ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -0.2 | SETUP | -1.557ns| 1.357ns| 16| 23872 - ns VALID 1.2 ns BEFORE COMP "adc | HOLD | 1.029ns| | 0| 0 - _clk1_p_i" "FALLING" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -0.2 | SETUP | -1.556ns| 1.356ns| 16| 23856 - ns VALID 1.2 ns BEFORE COMP "adc | HOLD | 1.026ns| | 0| 0 - _clk1_p_i" "RISING" | | | | | ----------------------------------------------------------------------------------------------------------- -* TS_cmp_xwb_fmc516_cmp_wb_fmc516_cmp_fmc51 | SETUP | -0.476ns| 4.917ns| 27| 2173 - 6_adc_iface_gen_clock_chains_1__gen_clock | HOLD | 0.007ns| | 0| 0 - _chains_check_cmp_fmc516_adc_clk_adc_clk2 | | | | | - x_mmcm_out = PERIOD TIMEGRP | | | | | - "cmp_xwb_fmc516_cmp_wb_fmc516_cmp_fmc5 | | | | | - 16_adc_iface_gen_clock_chains_1__gen_cloc | | | | | - k_chains_check_cmp_fmc516_adc_clk_adc_clk | | | | | - 2x_mmcm_out" TS_adc_clk1_p_i / 2 | | | | | - HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -0.2 | SETUP | -0.137ns| -0.063ns| 15| 1365 - ns VALID 1.2 ns BEFORE COMP "adc | HOLD | -0.103ns| | 8| 610 - _clk0_p_i" "FALLING" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -0.2 | SETUP | -0.136ns| -0.064ns| 15| 1350 - ns VALID 1.2 ns BEFORE COMP "adc | HOLD | -0.106ns| | 8| 634 - _clk0_p_i" "RISING" | | | | | ----------------------------------------------------------------------------------------------------------- - TS_sys_clk_group = PERIOD TIMEGRP "sys_cl | SETUP | 0.023ns| 9.977ns| 0| 0 - k_group" 10 ns HIGH 50% | HOLD | 0.016ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_sys_clk200_group = PERIOD TIMEGRP "sys | MINPERIOD | 0.239ns| 4.761ns| 0| 0 - _clk200_group" 5 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2_cc71cef7_g | SETUP | 0.275ns| 8.607ns| 0| 0 - roup = MAXDELAY FROM TIMEGRP "ce_ | HOLD | 0.015ns| | 0| 0 - 2_cc71cef7_group" TO TIMEGRP "ce_2_cc71ce | | | | | - f7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc516_cmp_wb_fmc516_cmp_fmc51 | SETUP | 0.431ns| 8.451ns| 0| 0 - 6_adc_iface_gen_clock_chains_1__gen_clock | HOLD | 0.006ns| | 0| 0 - _chains_check_cmp_fmc516_adc_clk_adc_clk_ | | | | | - mmcm_out = PERIOD TIMEGRP | | | | | - "cmp_xwb_fmc516_cmp_wb_fmc516_cmp_fmc516 | | | | | - _adc_iface_gen_clock_chains_1__gen_clock_ | | | | | - chains_check_cmp_fmc516_adc_clk_adc_clk_m | | | | | - mcm_out" TS_adc_clk1_p_i HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_clk_cc71cef7 = PERIOD TIMEGRP "clk_cc7 | MINPERIOD | 0.636ns| 3.805ns| 0| 0 - 1cef7" 4.44116092 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_adc_clk1_p_i = PERIOD TIMEGRP "adc_clk | SETUP | 1.760ns| 7.122ns| 0| 0 - 1_p_i" 8.882 ns HIGH 50% | HOLD | 0.078ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_2_cc7 | SETUP | 4.479ns| 4.403ns| 0| 0 - 1cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.130ns| | 0| 0 - "ce_22240000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_2_cc71cef7_group" 8.8823218 | | | | | - 4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_adc_clk0_p_i = PERIOD TIMEGRP "adc_clk | SETUP | 4.867ns| 4.015ns| 0| 0 - 0_p_i" 8.882 ns HIGH 50% | HOLD | 0.025ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2_cc71cef | SETUP | 5.377ns| 3.505ns| 0| 0 - 7_group = MAXDELAY FROM TIMEGRP " | HOLD | 0.141ns| | 0| 0 - ce_2224_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2_cc71cef7_ | SETUP | 5.434ns| 3.448ns| 0| 0 - group = MAXDELAY FROM TIMEGRP "ce | HOLD | 0.140ns| | 0| 0 - _70_cc71cef7_group" TO TIMEGRP "ce_2_cc71 | | | | | - cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_70_cc71cef7_ | SETUP | 6.549ns| 2.333ns| 0| 0 - group = MAXDELAY FROM TIMEGRP "ce | HOLD | 0.068ns| | 0| 0 - _2_cc71cef7_group" TO TIMEGRP "ce_70_cc71 | | | | | - cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2224_cc71cef | MAXDELAY | 6.892ns| 1.990ns| 0| 0 - 7_group = MAXDELAY FROM TIMEGRP " | HOLD | 0.072ns| | 0| 0 - ce_2_cc71cef7_group" TO TIMEGRP "ce_2224_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_5000_cc71cef | SETUP | 7.456ns| 1.426ns| 0| 0 - 7_group = MAXDELAY FROM TIMEGRP " | HOLD | 0.301ns| | 0| 0 - ce_2_cc71cef7_group" TO TIMEGRP "ce_5000_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_35_cc71cef7 | SETUP | 149.218ns| 6.222ns| 0| 0 - _group = MAXDELAY FROM TIMEGRP "c | HOLD | 0.054ns| | 0| 0 - e_35_cc71cef7_group" TO TIMEGRP "ce_35_cc | | | | | - 71cef7_group" 155.440632 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_70_cc71cef7 | SETUP | 152.783ns| 2.657ns| 0| 0 - _group = MAXDELAY FROM TIMEGRP "c | HOLD | 0.152ns| | 0| 0 - e_35_cc71cef7_group" TO TIMEGRP "ce_70_cc | | | | | - 71cef7_group" 155.440632 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_70_cc71cef7 | SETUP | 306.978ns| 3.903ns| 0| 0 - _group = MAXDELAY FROM TIMEGRP "c | HOLD | 0.085ns| | 0| 0 - e_70_cc71cef7_group" TO TIMEGRP "ce_70_cc | | | | | - 71cef7_group" 310.881264 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_556_cc71ce | SETUP | 2465.088ns| 4.197ns| 0| 0 - f7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.080ns| | 0| 0 - "ce_556_cc71cef7_group" TO TIMEGRP "ce_55 | | | | | - 6_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_556_cc71c | SETUP | 2467.331ns| 1.954ns| 0| 0 - ef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.169ns| | 0| 0 - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_1112_cc71 | SETUP | 4932.029ns| 6.541ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.063ns| | 0| 0 - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 4938.57094 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2224_cc71 | SETUP | 4936.502ns| 2.068ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.104ns| | 0| 0 - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 4938.57094 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2224_cc71 | SETUP | 9873.074ns| 4.067ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.085ns| | 0| 0 - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 9877.14188 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_5000_cc71 | SETUP | 22193.399ns| 12.405ns| 0| 0 - cef7_group = MAXDELAY FROM TIMEGRP | HOLD | 0.030ns| | 0| 0 - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 22205.8046 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_22240000_ | SETUP | 22202.296ns| 3.508ns| 0| 0 - cc71cef7_group = MAXDELAY FROM TI | HOLD | 0.153ns| | 0| 0 - MEGRP "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 222 | | | | | - 05.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_5000_ | SETUP | 22203.442ns| 2.362ns| 0| 0 - cc71cef7_group = MAXDELAY FROM TI | HOLD | 0.321ns| | 0| 0 - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_5000_cc71cef7_group" 222 | | | | | - 05.8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_278000 | SETUP | 2147479.659ns| 3.989ns| 0| 0 - 0_cc71cef7_group = MAXDELAY FROM | HOLD | 0.289ns| | 0| 0 - TIMEGRP "ce_2780000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_2780000_cc71cef7_group" | | | | | - 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_556000 | SETUP | 2147480.090ns| 3.558ns| 0| 0 - 0_cc71cef7_group = MAXDELAY FROM | HOLD | 0.074ns| | 0| 0 - TIMEGRP "ce_5560000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_5560000_cc71cef7_group" | | | | | - 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_22240 | SETUP | 2147480.348ns| 3.300ns| 0| 0 - 000_cc71cef7_group = MAXDELAY FROM | HOLD | 0.086ns| | 0| 0 - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_22240000_cc71cef7_gr | | | | | - oup" 98771418.8 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_139000 | SETUP | 2147481.033ns| 2.615ns| 0| 0 - 0_cc71cef7_group = MAXDELAY FROM | HOLD | 0.147ns| | 0| 0 - TIMEGRP "ce_1390000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_1390000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_222400 | SETUP | 2147481.485ns| 2.163ns| 0| 0 - 00_cc71cef7_group = MAXDELAY FROM | HOLD | 0.007ns| | 0| 0 - TIMEGRP "ce_5560000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_22240000_cc71cef7_grou | | | | | - p" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_278000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_5560000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_2780000_cc71cef7_group" | | | | | - 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_2224_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2224_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_2_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_139000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_5560000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_1390000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_1112_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_1112_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 44.4116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_556_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 17.7646437 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_5560000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 22.2058046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_5000_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_2224_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _2224_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5000_cc71cef7_group_to_ce_1112_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5000_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_556_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_35_cc71cef7_group" TO TIMEGRP "ce_556_ | | | | | - cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_5560000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 5560000_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_5000_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_500 | | | | | - 0_cc71cef7_group" 22.2058046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_ | N/A | N/A| N/A| N/A| N/A - group = MAXDELAY FROM TIMEGRP "ce | | | | | - _35_cc71cef7_group" TO TIMEGRP "ce_2_cc71 | | | | | - cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2780000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 2780000_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_2224_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_222 | | | | | - 4_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_556_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_70_cc71cef7_group" TO TIMEGRP "ce_556_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_5560000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 5560000_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_5000_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_500 | | | | | - 0_cc71cef7_group" 44.4116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7 | N/A | N/A| N/A| N/A| N/A - _group = MAXDELAY FROM TIMEGRP "c | | | | | - e_70_cc71cef7_group" TO TIMEGRP "ce_35_cc | | | | | - 71cef7_group" 155.440632 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2780000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 2780000_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_2224_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_222 | | | | | - 4_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_22240000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce | | | | | - _22240000_cc71cef7_group" 44.4116 | | | | | - 092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_1390000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 1390000_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_70_cc71cef7_group_to_ce_1112_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_70_cc71cef7_group" TO TIMEGRP "ce_111 | | | | | - 2_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_70_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_556_cc71cef7_group" TO TIMEGRP "ce_70_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_5560000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "c | | | | | - e_5560000_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_5000_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5 | | | | | - 000_cc71cef7_group" 17.7646437 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_35_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_556_cc71cef7_group" TO TIMEGRP "ce_35_ | | | | | - cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7 | N/A | N/A| N/A| N/A| N/A - _group = MAXDELAY FROM TIMEGRP "c | | | | | - e_556_cc71cef7_group" TO TIMEGRP "ce_2_cc | | | | | - 71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2780000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "c | | | | | - e_2780000_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_2224_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2 | | | | | - 224_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_22240000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP " | | | | | - ce_22240000_cc71cef7_group" 2469. | | | | | - 28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_1390000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "c | | | | | - e_1390000_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_556_cc71cef7_group_to_ce_1112_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1 | | | | | - 112_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_70_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_70_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_556_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_556_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_5000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_5000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_5560000_cc71cef7_group_to_ce_35_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_35_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_22240000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 493 | | | | | - 8.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_2780000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_22240000_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" 987 | | | | | - 7.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_1112_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _1112_cc71cef7_group" 4938.57094 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_70_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_70_cc71cef7_group" 44.4116 | | | | | - 092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_556_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" TO TIME | | | | | - GRP "ce_556_cc71cef7_group" 2469. | | | | | - 28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_55600 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_5560000_cc71cef7_grou | | | | | - p" 24692854.7 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_35_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_22240000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_35_cc71cef7_group" 22.2058 | | | | | - 046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_5560000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_27800 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_2780000_cc71cef7_grou | | | | | - p" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_2224_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_2224_cc71cef7_group" 987 | | | | | - 7.14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_13900 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_22240000_cc71cef7_group" TO | | | | | - TIMEGRP "ce_1390000_cc71cef7_grou | | | | | - p" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_22240000_cc71cef7_group_to_ce_1112_ | N/A | N/A| N/A| N/A| N/A - cc71cef7_group = MAXDELAY FROM TI | | | | | - MEGRP "ce_22240000_cc71cef7_group" TO TIM | | | | | - EGRP "ce_1112_cc71cef7_group" 493 | | | | | - 8.57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_70_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_70_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_556_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_556_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_5560000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_5000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_5000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_35_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_35_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_2_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_278000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_2780000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_2224_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2224_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_1390000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_22240000_cc71cef7_grou | | | | | - p" 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1390000_cc71cef7_group_to_ce_1112_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_1112_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_556_cc71c | N/A | N/A| N/A| N/A| N/A - ef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 556_cc71cef7_group" 2469.28547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_22240000_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce | | | | | - _22240000_cc71cef7_group" 22.2058 | | | | | - 046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_1390000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_ | | | | | - 1390000_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_35_cc71cef7_group_to_ce_1112_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_35_cc71cef7_group" TO TIMEGRP "ce_111 | | | | | - 2_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_1112_cc71cef7_group" TO TIMEGRP "ce_2_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7 | N/A | N/A| N/A| N/A| N/A - _group = MAXDELAY FROM TIMEGRP "c | | | | | - e_2_cc71cef7_group" TO TIMEGRP "ce_556_cc | | | | | - 71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_5560000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_55 | | | | | - 60000_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_35_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_3 | | | | | - 5_cc71cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_ | N/A | N/A| N/A| N/A| N/A - group = MAXDELAY FROM TIMEGRP "ce | | | | | - _2_cc71cef7_group" TO TIMEGRP "ce_35_cc71 | | | | | - cef7_group" 4.44116092 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_2780000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_27 | | | | | - 80000_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_1390000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP | | | | | - "ce_1390000_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_22240000_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_2 | | | | | - 2240000_cc71cef7_group" 8.8823218 | | | | | - 4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_1390000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2_cc71cef7_group" TO TIMEGRP "ce_13 | | | | | - 90000_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef | N/A | N/A| N/A| N/A| N/A - 7_group = MAXDELAY FROM TIMEGRP " | | | | | - ce_2_cc71cef7_group" TO TIMEGRP "ce_1112_ | | | | | - cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_70_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_70_cc71cef7_group" 44.411609 | | | | | - 2 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_556_cc | N/A | N/A| N/A| N/A| N/A - 71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGR | | | | | - P "ce_556_cc71cef7_group" 2469.28 | | | | | - 547 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_556000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_5560000_cc71cef7_group" | | | | | - 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_5000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_5000_cc71cef7_group" 22205 | | | | | - .8046 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_35_cc7 | N/A | N/A| N/A| N/A| N/A - 1cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_35_cc71cef7_group" 22.205804 | | | | | - 6 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_2_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEGRP | | | | | - "ce_2_cc71cef7_group" 8.88232184 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_2224_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_2224_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_222400 | N/A | N/A| N/A| N/A| N/A - 00_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO T | | | | | - IMEGRP "ce_22240000_cc71cef7_grou | | | | | - p" 12346427.4 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_139000 | N/A | N/A| N/A| N/A| N/A - 0_cc71cef7_group = MAXDELAY FROM | | | | | - TIMEGRP "ce_2780000_cc71cef7_group" TO TI | | | | | - MEGRP "ce_1390000_cc71cef7_group" | | | | | - 6173213.68 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2780000_cc71cef7_group_to_ce_1112_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2780000_cc71cef7_group" TO TIMEG | | | | | - RP "ce_1112_cc71cef7_group" 4938. | | | | | - 57094 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_70_cc71ce | N/A | N/A| N/A| N/A| N/A - f7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_7 | | | | | - 0_cc71cef7_group" 8.88232184 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_1112_cc71cef7_group_to_ce_5000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_1112_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_5560000_c | N/A | N/A| N/A| N/A| N/A - c71cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP | | | | | - "ce_5560000_cc71cef7_group" 9877. | | | | | - 14188 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_ce_2224_cc71cef7_group_to_ce_5000_cc71 | N/A | N/A| N/A| N/A| N/A - cef7_group = MAXDELAY FROM TIMEGRP | | | | | - "ce_2224_cc71cef7_group" TO TIMEGRP "ce | | | | | - _5000_cc71cef7_group" 35.5292874 | | | | | - ns | | | | | ----------------------------------------------------------------------------------------------------------- - - -Derived Constraint Report -Review Timing Report for more details on the following derived constraints. -To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" -or "Run Timing Analysis" from Timing Analyzer (timingan). -Derived Constraints for TS_adc_clk1_p_i -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_adc_clk1_p_i | 8.882ns| 7.122ns| 9.834ns| 0| 27| 991| 144547| -| TS_cmp_xwb_fmc516_cmp_wb_fmc51| 4.441ns| 4.917ns| N/A| 27| 0| 134068| 0| -| 6_cmp_fmc516_adc_iface_gen_clo| | | | | | | | -| ck_chains_1__gen_clock_chains_| | | | | | | | -| check_cmp_fmc516_adc_clk_adc_c| | | | | | | | -| lk2x_mmcm_out | | | | | | | | -| TS_cmp_xwb_fmc516_cmp_wb_fmc51| 8.882ns| 8.451ns| N/A| 0| 0| 10479| 0| -| 6_cmp_fmc516_adc_iface_gen_clo| | | | | | | | -| ck_chains_1__gen_clock_chains_| | | | | | | | -| check_cmp_fmc516_adc_clk_adc_c| | | | | | | | -| lk_mmcm_out | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -5 constraints not met. -INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the - constraint is not analyzed due to the following: No paths covered by this - constraint; Other constraints intersect with this constraint; or This - constraint was disabled by a Path Tracing Control. Please run the Timespec - Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. - - -Generating Pad Report. - -All signals are completely routed. - -WARNING:Par:283 - There are 53 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - -Total REAL time to PAR completion: 12 mins 30 secs -Total CPU time to PAR completion: 12 mins 10 secs - -Peak Memory Usage: 3023 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - 105 errors found. - -Number of error messages: 0 -Number of warning messages: 154 -Number of info messages: 2 - -Writing design to file dbe_bpm_dsp.ncd - - - -PAR done! - -Process "Place & Route" completed successfully - -Started : "Generate Post-Place & Route Static Timing". -Running trce... -Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_dsp.twx dbe_bpm_dsp.ncd -o dbe_bpm_dsp.twr dbe_bpm_dsp.pcf -Loading device for application Rf_Device from file '6vlx240t.nph' in environment -/opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_dsp" is an NCD, version 3.2, device xc6vlx240t, package ff1156, -speed -1 -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1112_cc71cef7_group" TO TIMEGRP - "ce_1390000_cc71cef7_group" 4938.57094 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1112_cc71cef7_group" TO TIMEGRP - "ce_22240000_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1112_cc71cef7_group" TO TIMEGRP - "ce_2780000_cc71cef7_group" 4938.57094 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" - 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1112_cc71cef7_group" TO TIMEGRP - "ce_5560000_cc71cef7_group" 4938.57094 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 2469.28547 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1112_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1112_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1390000_cc71cef7_group" TO TIMEGRP - "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1390000_cc71cef7_group" TO TIMEGRP - "ce_22240000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1390000_cc71cef7_group" TO TIMEGRP - "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1390000_cc71cef7_group" TO TIMEGRP - "ce_2780000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1390000_cc71cef7_group" TO TIMEGRP - "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_1390000_cc71cef7_group" TO TIMEGRP - "ce_5560000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" - 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_1390000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_1390000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_22240000_cc71cef7_group" TO TIMEGRP - "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_22240000_cc71cef7_group" TO TIMEGRP - "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_22240000_cc71cef7_group" TO TIMEGRP - "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_22240000_cc71cef7_group" TO TIMEGRP - "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_22240000_cc71cef7_group" TO TIMEGRP - "ce_5560000_cc71cef7_group" 24692854.7 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_22240000_cc71cef7_group" TO TIMEGRP - "ce_556_cc71cef7_group" 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_22240000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_22240000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" - 4938.57094 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2224_cc71cef7_group" TO TIMEGRP - "ce_1390000_cc71cef7_group" 9877.14188 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2224_cc71cef7_group" TO TIMEGRP - "ce_22240000_cc71cef7_group" 9877.14188 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2224_cc71cef7_group" TO TIMEGRP - "ce_2780000_cc71cef7_group" 9877.14188 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" - 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2224_cc71cef7_group" TO TIMEGRP - "ce_5560000_cc71cef7_group" 9877.14188 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2224_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2224_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2780000_cc71cef7_group" TO TIMEGRP - "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2780000_cc71cef7_group" TO TIMEGRP - "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2780000_cc71cef7_group" TO TIMEGRP - "ce_22240000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2780000_cc71cef7_group" TO TIMEGRP - "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2780000_cc71cef7_group" TO TIMEGRP - "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_2780000_cc71cef7_group" TO TIMEGRP - "ce_5560000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" - 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2780000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2780000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 ns; - ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_2_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 4.44116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 4.44116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 4.44116092 ns; - ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 22.2058046 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_35_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_35_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 4.44116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" - 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5000_cc71cef7_group" TO TIMEGRP - "ce_1390000_cc71cef7_group" 22205.8046 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" - 35.5292874 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5000_cc71cef7_group" TO TIMEGRP - "ce_2780000_cc71cef7_group" 22205.8046 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 22.2058046 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5000_cc71cef7_group" TO TIMEGRP - "ce_5560000_cc71cef7_group" 22205.8046 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 17.7646437 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 44.4116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5560000_cc71cef7_group" TO TIMEGRP - "ce_1112_cc71cef7_group" 4938.57094 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5560000_cc71cef7_group" TO TIMEGRP - "ce_1390000_cc71cef7_group" 6173213.68 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5560000_cc71cef7_group" TO TIMEGRP - "ce_2224_cc71cef7_group" 9877.14188 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5560000_cc71cef7_group" TO TIMEGRP - "ce_2780000_cc71cef7_group" 12346427.4 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" - 8.88232184 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" - 22.2058046 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_5560000_cc71cef7_group" TO TIMEGRP - "ce_5000_cc71cef7_group" 22205.8046 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" - 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_5560000_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_5560000_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 2469.28547 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" - 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM - TIMEGRP "ce_556_cc71cef7_group" TO TIMEGRP - "ce_22240000_cc71cef7_group" 2469.28547 ns; ignored during timing - analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 2469.28547 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" - 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_2_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 4.44116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 17.7646437 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" - 2469.28547 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_556_cc71cef7_group_to_ce_70_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_556_cc71cef7_group" TO TIMEGRP "ce_70_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_1112_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_1112_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_1390000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_1390000_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_22240000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_22240000_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_2224_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2224_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_2780000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_2780000_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_35_cc71cef7_group" 155.440632 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_5000_cc71cef7_group" 44.4116092 - ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_5560000_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_5560000_cc71cef7_group" - 44.4116092 ns; ignored during timing analysis. -WARNING:Timing:3223 - Timing constraint - TS_ce_70_cc71cef7_group_to_ce_556_cc71cef7_group = MAXDELAY FROM TIMEGRP - "ce_70_cc71cef7_group" TO TIMEGRP "ce_556_cc71cef7_group" 8.88232184 - ns; ignored during timing analysis. - -Analysis completed Wed Jul 3 10:55:07 2013 --------------------------------------------------------------------------------- - -Generating Report ... - -Number of warnings: 98 -Total time: 3 mins 33 secs - -Process "Generate Post-Place & Route Static Timing" completed successfully - -Started : "Generate Programming File". -Running bitgen... -Command Line: bitgen -intstyle ise -f dbe_bpm_dsp.ut dbe_bpm_dsp.ncd -INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most - commonly, bitgen has determined and will use a specific value instead of the - generic command-line value of "Auto". Alternately, this message appears if - the same option is specified multiple times on the command-line. In this - case, the option listed last will be used. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL2<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL3<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL4<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL5<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL6<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. - -Process "Generate Programming File" completed successfully diff --git a/hdl/syn/ml605/dbe_bpm_ebone/Manifest.py b/hdl/syn/ml605/dbe_bpm_ebone/Manifest.py deleted file mode 100755 index 1da0fe4b..00000000 --- a/hdl/syn/ml605/dbe_bpm_ebone/Manifest.py +++ /dev/null @@ -1,10 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_ebone" -syn_project = "dbe_bpm_ebone.xise" - -modules = { "local" : [ "../../../top/ml_605/dbe_bpm_ebone" ] }; diff --git a/hdl/syn/ml605/dbe_bpm_ebone/dbe_bpm_ebone.xise b/hdl/syn/ml605/dbe_bpm_ebone/dbe_bpm_ebone.xise deleted file mode 100644 index eb42a212..00000000 --- a/hdl/syn/ml605/dbe_bpm_ebone/dbe_bpm_ebone.xise +++ /dev/null @@ -1,1606 +0,0 @@ - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_ebone/make_output b/hdl/syn/ml605/dbe_bpm_ebone/make_output deleted file mode 100644 index 501054e1..00000000 --- a/hdl/syn/ml605/dbe_bpm_ebone/make_output +++ /dev/null @@ -1,7588 +0,0 @@ -echo "project open dbe_bpm_ebone.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.syr" -Reading design: dbe_bpm_ebone.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_clockgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_receivecontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 94. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_cop.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" included at line 64. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 65. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 165. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 166. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 87. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_crc.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 74. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" into library work -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 317: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 318: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 322: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 323: Macro is redefined. -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxaddrcheck.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 67. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 42. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_random.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 80. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_maccontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_macstatus.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 112. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xilinx_dist_ram_16x32.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_spram_256x32.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 74. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 83. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 240. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 241. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_outputcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_transmitcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 82. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 34. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xwb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_clk.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_wfifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" Line 50: Range is empty (null range) - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xfffe0000]" -Note: "Mapping slave #1[0x10000000/0xfffe0000]" -Note: "Mapping slave #2[0x20000000/0xffff0000]" -Note: "Mapping slave #3[0x60000000/0xffffffe0]" -Note: "Mapping slave #4[0x70000000/0xff000000]" -Note: "Mapping slave #5[0x80000000/0xffffff00]" -Note: "Mapping slave #6[0x90000000/0xffffff00]" -Note: "Mapping slave #7[0xa0000000/0xffffff00]" -Note: "Mapping slave #8[0xb0000000/0xffffff00]" -Note: "Mapping slave #9[0xc0000000/0xffffff00]" -Note: "Mapping slave #10[0x30000000/0xfffffc00]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE. -Going to verilog side to elaborate module lm32_top_medium_icache_debug - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 49056: Result of 30-bit expression is truncated to fit in 29-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 41108: Assignment to pc_w ignored, since the identifier is never used - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45380: Assignment to op_user ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45414: Assignment to multiply ignored, since the identifier is never used -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45624: Result of 32-bit expression is truncated to fit in 29-bit target. - -Elaborating module . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44387. $display Data bus error. Address: 0 -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44535. $display Warning: Non-aligned halfword access. Address: 0x0 Time: $time . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44537. $display Warning: Non-aligned word access. Address: 0x0 Time: $time . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" Line 128: Result of 64-bit expression is truncated to fit in 32-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Result of 3-bit expression is truncated to fit in 1-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Assignment to ie_csr_read_data ignored, since the identifier is never used -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Result of 32-bit expression is truncated to fit in 1-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Assignment to ip_csr_read_data ignored, since the identifier is never used -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Result of 32-bit expression is truncated to fit in 1-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Assignment to im_csr_read_data ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 47797: Net does not have a driver. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 42753: Assignment to x_result_sel_logic_x ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 39170: Assignment to jrstn ignored, since the identifier is never used -Back to vhdl to continue elaboration -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 72: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 74: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module ethmac - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" Line 883: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used -"/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted - -Elaborating module . -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" Line 248: Using initial value "00000000000000000000000000000000" for zero_din_width since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -WARNING:UtilitiesC:159 - Message file "usenglish/ip.msg" wasn't found. -INFO:ip - 0: (0,0) : 36x1024 u:32 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 36x1024 u:32 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Assignment ignored -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 509: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 428: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 432: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 168: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 169: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" Line 325: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" Line 335: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" Line 281: Net does not have a driver. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 365: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 393: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 393: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 641: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 656: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 656: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 682: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 682: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 682: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit tristate buffer for signal created at line 577 - Summary: - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 1 - g_logdelay = 10 - g_syncdepth = 3 - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 14 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 10 - g_registered = true - g_wraparound = false - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001100000000000000000000001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000101100000000000000000000000000000000000000000000000000000000000010110000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000001010000000000000000000001111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000010010000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000101101000001000000010101100100010000000000000000000000000000000010010000000010010000010010001001001000111010100110100100101011111010001010101010001001000010001010101001001000010010011110100111001000101010111110100001101000110010001110010000000100 -00000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010111111111001101000101000111000000000000000000000000000000001001000000001001100000111000000010100010101010100010010000100110101000001010000110101111101000001010001000100000101010000010101000100010101010010001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000001110000111111111111111111111111000100000000000000000000000000000100111000101100000001011110010111111000110011111110101100010110000000000000000000000000000000010010000000010010000100100001001001001111010000110100111101010010010001010101001101011111010001010101010001001000010011010100000101000011001000000010000000100000001000000010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000000000000000000000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000001111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001 -00000001000000010000000000001") - g_sdb_addr = "00110000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001100000000000000000000001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000101100000000000000000000000000000000000000000000000000000000000010110000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000001010000000000000000000001111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000010010000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000101101000001000000010101100100010000000000000000000000000000000010010000000010010000010010001001001000111010100110100100101011111010001010101010001001000010001010101001001000010010011110100111001000101010111110100001101000110010001110010000000100 -00000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010111111111001101000101000111000000000000000000000000000000001001000000001001100000111000000010100010101010100010010000100110101000001010000110101111101000001010001000100000101010000010101000100010101010010001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000001110000111111111111111111111111000100000000000000000000000000000100111000101100000001011110010111111000110011111110101100010110000000000000000000000000000000010010000000010010000100100001001001001111010000110100111101010010010001010101001101011111010001010101010001001000010011010100000101000011001000000010000000100000001000000010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000000000000000000000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000001111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001 -00000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000011111111111111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom', is tied to its initial value. - Found 256x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 11 - g_registered = true - g_address = ("00110000000000000000000000000000","11000000000000000000000000000000","10110000000000000000000000000000","10100000000000000000000000000000","10010000000000000000000000000000","10000000000000000000000000000000","01110000000000000000000000000000","01100000000000000000000000000000","00100000000000000000000000000000","00010000000000000000000000000000","00000000000000000000000000000000") - g_mask = ("11111111111111111111110000000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111000000000000000000000000","11111111111111111111111111100000","11111111111111110000000000000000","11111111111111100000000000000000","11111111111111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 97 D-type flip-flop(s). - inferred 96 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd". - g_profile = "medium_icache_debug" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. - Found 3-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 688. - Found 32-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 3-bit subtractor for signal > created at line 650. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 70 D-type flip-flop(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 39161: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - eba_reset = 32'b00000000000000000000000000000000 - deba_reset = 32'b00010000000000000000000000000000 - icache_associativity = 1 - icache_sets = 256 - icache_bytes_per_line = 16 - icache_base_address = 32'b00000000000000000000000000000000 - icache_limit = 32'b01111111111111111111111111111111 - dcache_associativity = 1 - dcache_sets = 512 - dcache_bytes_per_line = 16 - dcache_base_address = 0 - dcache_limit = 0 - watchpoints = 32'b00000000000000000000000000000100 - breakpoints = 0 - interrupts = 32 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41044: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41154: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 23-bit register for signal . - Found 23-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 29-bit adder for signal created at line 41841. - Found 32-bit 3-to-1 multiplexer for signal created at line 41852. - Found 1-bit 8-to-1 multiplexer for signal created at line 41889. - Found 5-bit comparator equal for signal created at line 41592 - Found 5-bit comparator equal for signal created at line 41598 - Found 5-bit comparator equal for signal created at line 41779 - Found 5-bit comparator equal for signal created at line 41780 - Found 5-bit comparator equal for signal created at line 41781 - Found 5-bit comparator equal for signal created at line 41782 - Found 5-bit comparator equal for signal created at line 41783 - Found 5-bit comparator equal for signal created at line 41784 - Found 32-bit comparator equal for signal created at line 41883 - Found 1-bit comparator equal for signal created at line 41896 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 441 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 29-bit adder for signal created at line 48969. - Found 2-bit adder for signal created at line 49199. - Found 8-bit 4-to-1 multiplexer for signal created at line 49131. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 314 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 18 | - | Inputs | 11 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit subtractor for signal created at line 46392. - Found 2-bit adder for signal created at line 46469. - Found 20-bit comparator equal for signal created at line 46274 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 41 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 8 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v". - data_width = 32 - address_width = 10 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1024x32-bit dual-port RAM for signal . - Found 10-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 10 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v". - data_width = 20 - address_width = 8 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 256x20-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 512 - bytes_per_line = 16 - base_address = 0 - limit = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 44142. - Summary: - inferred 180 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v". - Found 33-bit subtractor for signal created at line 69. - Found 33-bit subtractor for signal created at line 69. - Found 33-bit adder for signal created at line 68. - Found 33-bit adder for signal created at line 68. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v". - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Summary: - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 64-bit shifter logical right for signal created at line 128 - Summary: - inferred 33 D-type flip-flop(s). - inferred 3 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v". - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 115. - Found 16-bit adder for signal created at line 115. - Found 16x16-bit multiplier for signal created at line 109. - Found 16x16-bit multiplier for signal created at line 110. - Found 16x16-bit multiplier for signal created at line 111. - Summary: - inferred 3 Multiplier(s). - inferred 2 Adder/Subtractor(s). - inferred 160 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - interrupts = 32 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 50671. - Summary: - inferred 78 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 36 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 50090. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 80 D-type flip-flop(s). - inferred 13 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - breakpoints = 0 - watchpoints = 32'b00000000000000000000000000000100 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal <31>>. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 36 | - | Inputs | 8 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit comparator equal for signal created at line 47900 - Found 32-bit comparator equal for signal created at line 47900 - Found 32-bit comparator equal for signal created at line 47900 - Found 32-bit comparator equal for signal created at line 47900 - Summary: - inferred 138 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 35 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v". - addr_width = 5 - addr_depth = 32 - data_width = 32 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32x32-bit dual-port RAM for signal . - Found 5-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v". - Found 11-bit register for signal . - Found 11-bit register for signal . - Summary: - inferred 22 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v". - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16x32-bit dual-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 32-bit adder for signal created at line 197. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 213. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 180. - Found 4-bit comparator equal for signal created at line 224 - Found 5-bit comparator not equal for signal created at line 236 - Found 5-bit comparator not equal for signal created at line 237 - Found 5-bit comparator not equal for signal created at line 238 - Summary: - inferred 1 RAM(s). - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 175 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 32768 - g_init_file = "../../../embedded-sw/dbe.ram" - g_init_value = "" - g_must_have_init_file = true - g_slave1_interface_mode = pipelined - g_slave2_interface_mode = pipelined - g_slave1_granularity = byte - g_slave2_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 32768 - g_with_byte_enable = true - g_addr_conflict_resolution = "read_first" - g_init_file = "../../../embedded-sw/dbe.ram" - g_init_value = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 32768 - g_with_byte_enable = true - g_addr_conflict_resolution = "read_first" - g_init_file = "../../../embedded-sw/dbe.ram" - g_init_value = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32768x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 16384 - g_init_file = "" - g_init_value = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = byte - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "read_first" - g_init_file = "" - g_init_value = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "read_first" - g_init_file = "" - g_init_value = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16384x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xwb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 54 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 409. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_clockgen.v". - Tp = 1 - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 92. - Found 8-bit subtractor for signal created at line 107. - Found 8-bit comparator greater for signal created at line 91 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v". - Tp = 1 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 25 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_outputcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit comparator greater for signal created at line 100 - Found 7-bit comparator greater for signal created at line 101 - Found 7-bit comparator greater for signal created at line 138 - Summary: - inferred 6 D-type flip-flop(s). - inferred 3 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861. - Found 32-bit comparator lessequal for signal created at line 388 - Found 32-bit comparator greater for signal created at line 907 - Found 32-bit comparator greater for signal created at line 908 - Summary: - inferred 21 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b10100000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 1'b0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0000000 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0010010 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0001100 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000110 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 6 - RESET_VALUE = 6'b111111 - Found 6-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 4 - RESET_VALUE = 4'b1111 - Found 4-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 3 - RESET_VALUE = 3'b000 - Found 3-bit register for signal . - Summary: - inferred 3 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01100100 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 5 - RESET_VALUE = 5'b00000 - Found 5-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v". - WIDTH = 16 - RESET_VALUE = 16'b0000000000000000 - Found 16-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_maccontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_receivecontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 16-bit subtractor for signal created at line 356. - Found 3-bit adder for signal created at line 304. - Found 5-bit adder for signal created at line 323. - Found 6-bit adder for signal created at line 417. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 72 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_transmitcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 6-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 255. - Found 6-bit adder for signal created at line 274. - Found 6-bit adder for signal created at line 277. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 20 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v". - Tp = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 344. - Found 6-bit comparator equal for signal created at line 249 - Found 4-bit comparator equal for signal created at line 349 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v". - Tp = 1 - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 17-bit subtractor for signal created at line 170. - Found 32-bit subtractor for signal created at line 170. - Found 16-bit adder for signal created at line 162. - Found 16-bit adder for signal created at line 194. - Found 3-bit adder for signal created at line 215. - Found 32-bit comparator lessequal for signal created at line 170 - Found 16-bit comparator equal for signal created at line 199 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 35 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txstatem.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 187 - Found 7-bit comparator not equal for signal created at line 187 - Summary: - inferred 12 D-type flip-flop(s). - inferred 4 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_crc.v". - Tp = 1 - Found 32-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_random.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 4-bit comparator greater for signal created at line 114 - Found 4-bit comparator greater for signal created at line 115 - Found 4-bit comparator greater for signal created at line 116 - Found 4-bit comparator greater for signal created at line 117 - Found 4-bit comparator greater for signal created at line 118 - Found 4-bit comparator greater for signal created at line 119 - Found 4-bit comparator greater for signal created at line 120 - Found 4-bit comparator greater for signal created at line 121 - Found 4-bit comparator greater for signal created at line 122 - Found 10-bit comparator equal for signal created at line 139 - Summary: - inferred 20 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxethmac.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit comparator greater for signal created at line 213 - Found 4-bit comparator lessequal for signal created at line 314 - Summary: - inferred 40 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxstatem.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxcounters.v". - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 116. - Found 16-bit adder for signal created at line 120. - Found 5-bit adder for signal created at line 151. - Found 4-bit adder for signal created at line 173. - Found 16-bit comparator greater for signal created at line 131 - Found 16-bit comparator greater for signal created at line 132 - Found 16-bit comparator equal for signal created at line 134 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxaddrcheck.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v". -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 7-bit register for signal . - Found 7-bit register for signal . - Found 2-bit register for signal . - Found 24-bit register for signal . - Found 9-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 773. - Found 16-bit subtractor for signal created at line 777. - Found 16-bit subtractor for signal created at line 781. - Found 16-bit subtractor for signal created at line 785. - Found 30-bit adder for signal created at line 821. - Found 3-bit adder for signal created at line 960. - Found 30-bit adder for signal created at line 964. - Found 3-bit adder for signal created at line 996. - Found 8-bit adder for signal created at line 1395. - Found 8-bit adder for signal created at line 1398. - Found 2-bit adder for signal created at line 1745. - Found 30-bit adder for signal created at line 2001. - Found 2-bit adder for signal created at line 2098. - Found 2-bit adder for signal created at line 2117. - Found 4x2-bit Read Only RAM for signal - Found 4x6-bit Read Only RAM for signal <_n1569> - Found 1-bit 4-to-1 multiplexer for signal created at line 1630. - Found 8-bit 4-to-1 multiplexer for signal created at line 1648. - Found 8-bit 4-to-1 multiplexer for signal created at line 1660. - Found 16-bit 4-to-1 multiplexer for signal created at line 776. - Found 16-bit comparator greater for signal created at line 627 - Found 16-bit comparator greater for signal created at line 803 - Found 16-bit comparator lessequal for signal created at line 898 - Found 8-bit comparator greater for signal created at line 1062 - Found 16-bit comparator greater for signal created at line 1062 - Found 8-bit comparator lessequal for signal created at line 2417 - Found 1-bit comparator equal for signal created at line 2422 - Found 8-bit comparator greater for signal created at line 2423 - Summary: - inferred 2 RAM(s). - inferred 11 Adder/Subtractor(s). - inferred 461 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_spram_256x32.v". - we_width = 1 - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v". - DATA_WIDTH = 32 - DEPTH = 256 - CNT_WIDTH = 8 - Set property "syn_ramstyle = no_rw_check" for signal . - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 83. - Found 8-bit adder for signal created at line 114. - Found 8-bit adder for signal created at line 122. - Found 8-bit subtractor for signal > created at line 81. - Summary: - inferred 1 RAM(s). - inferred 3 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_macstatus.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 16-bit comparator greater for signal created at line 236 - Found 16-bit comparator greater for signal created at line 236 - Found 6-bit comparator equal for signal created at line 310 - Summary: - inferred 18 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 3 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_862_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_862_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 299. - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 320. - Found 16-bit adder for signal created at line 1241. - Found 32-bit 7-to-1 multiplexer for signal <_n0442> created at line 206. - Found 32-bit comparator greater for signal created at line 299 - Found 16-bit comparator greater for signal created at line 320 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 254 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 2 - g_adr_width_B = 32 - g_dat_width_A = 16 - g_dat_width_B = 32 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 32 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 32 - g_adr_width_B = 2 - g_dat_width_A = 32 - g_dat_width_B = 16 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 32 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 15-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 13-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 160-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 11-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 12 | - | Transitions | 41 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | _n0498 (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 11-bit adder for signal created at line 222. - Found 6-bit adder for signal created at line 464. - Found 7-bit adder for signal created at line 472. - Found 16-bit adder for signal created at line 1241. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit 3-to-1 multiplexer for signal created at line 242. - Found 1-bit 3-to-1 multiplexer for signal created at line 242. - Found 11-bit comparator equal for signal created at line 456 - Found 11-bit comparator equal for signal created at line 464 - Found 11-bit comparator equal for signal created at line 472 - Found 11-bit comparator greater for signal created at line 482 - Found 16-bit comparator equal for signal created at line 485 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 499 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 86 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 96 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 106 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd". - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 1 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_878_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 28-bit adder for signal created at line 91. - Found 28-bit adder for signal created at line 102. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 61 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 160 - g_width_OUT = 16 - g_protected = 0 - Found 9-bit register for signal . - Found 160-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 170 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 15-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 29 | - | Inputs | 10 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_938_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State ipv4_chksum is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 15 | - | Transitions | 34 | - | Inputs | 13 | - | Outputs | 12 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_parser_reset_OR_13374_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | eth | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 14-bit subtractor for signal created at line 426. - Found 11-bit adder for signal created at line 291. - Found 12-bit adder for signal created at line 405. - Found 12-bit adder for signal created at line 426. - Found 13-bit adder for signal created at line 426. - Found 17-bit adder for signal created at line 504. - Found 15-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 504. - Found 11-bit comparator equal for signal created at line 347 - Found 12-bit comparator equal for signal created at line 405 - Found 12-bit comparator greater for signal created at line 420 - Found 14-bit comparator equal for signal created at line 426 - Found 16-bit comparator equal for signal created at line 447 - Found 11-bit comparator greater for signal created at line 520 - Found 11-bit comparator equal for signal created at line 529 - Summary: - inferred 8 Adder/Subtractor(s). - inferred 244 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 14 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 160 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 160-bit register for signal . - Found 4-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 166 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 15-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . -INFO:Xst:1799 - State zero_pad_wait is never reached in FSM . -INFO:Xst:1799 - State error is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 716 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_1025_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 19 | - | Transitions | 145 | - | Inputs | 19 | - | Outputs | 16 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_1025_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit subtractor for signal > created at line 1308. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 4-bit comparator greater for signal created at line 363 - Found 16-bit comparator greater for signal created at line 504 - Found 8-bit comparator greater for signal created at line 584 - Found 8-bit comparator greater for signal created at line 619 - Found 16-bit comparator equal for signal created at line 659 - Found 4-bit comparator greater for signal created at line 716 - Found 8-bit comparator greater for signal created at line 986 - Summary: - inferred 13 Adder/Subtractor(s). - inferred 359 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 65 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 32 - g_size = 16 - g_show_ahead = true - g_with_empty = true - g_with_full = true - g_with_almost_empty = true - g_with_almost_full = true - g_with_count = true - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 1 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 32 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 0 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_PROG_FULL_TYPE = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 1 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd". - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_WR_RST_MAXFAN = 2 - C_RD_RST_MAXFAN = 3 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Summary: - inferred 15 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 1 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 32 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 4 - C_WRITE_WIDTH_A = 32 - C_WRITE_WIDTH_A_CORE = 32 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 4 - C_WRITE_WIDTH_B = 32 - C_WRITE_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 4 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 32 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 4 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 32 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_READ_WIDTH_B = 32 - C_READ_WIDTH_A_CORE = 32 - C_READ_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_USE_EMBEDDED_REG = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd". - C_HAS_ALMOST_EMPTY = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY_FB', unconnected in block 'rd_status_flags_ss', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd". - C_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd". - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 210. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd". - C_RD_PNTR_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd". - C_COUNTER_RESET_VAL = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 126. - Found 4-bit subtractor for signal > created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 4 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_FULL_FLAGS_RST_VAL = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 1 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 151. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_EMPTY_TYPE = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss', is tied to its initial value (1). -WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd". - C_HAS_RST = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_FULL_FLAGS_RST_VAL = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 243. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd". - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 1 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 8-to-1 multiplexer for signal <_n0259> created at line 137. - Found 32-bit 8-to-1 multiplexer for signal <_n0277> created at line 168. - Summary: - inferred 328 D-type flip-flop(s). - inferred 22 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 47 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1074_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1084_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = classic - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = classic - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 16 - 1024x32-bit dual-port RAM : 1 - 16384x32-bit dual-port RAM : 1 - 16x32-bit dual-port RAM : 1 - 256x20-bit dual-port RAM : 1 - 256x32-bit dual-port RAM : 4 - 256x32-bit single-port Read Only RAM : 1 - 32768x32-bit dual-port RAM : 1 - 32x32-bit dual-port RAM : 2 - 4x2-bit single-port Read Only RAM : 1 - 4x6-bit single-port Read Only RAM : 1 - 8x1-bit single-port Read Only RAM : 2 -# Multipliers : 3 - 16x16-bit multiplier : 3 -# Adders/Subtractors : 114 - 10-bit adder : 1 - 11-bit adder : 2 - 11-bit subtractor : 1 - 12-bit adder : 2 - 13-bit adder : 1 - 14-bit subtractor : 1 - 15-bit subtractor : 3 - 16-bit adder : 11 - 16-bit subtractor : 3 - 17-bit adder : 2 - 17-bit subtractor : 1 - 2-bit adder : 7 - 2-bit addsub : 1 - 2-bit subtractor : 1 - 28-bit adder : 1 - 29-bit adder : 2 - 3-bit adder : 4 - 3-bit subtractor : 1 - 30-bit adder : 3 - 32-bit adder : 7 - 32-bit subtractor : 3 - 33-bit adder : 2 - 33-bit subtractor : 2 - 4-bit adder : 10 - 4-bit addsub : 2 - 5-bit adder : 10 - 6-bit adder : 3 - 7-bit adder : 2 - 8-bit adder : 10 - 8-bit addsub : 3 - 8-bit subtractor : 6 - 9-bit subtractor : 6 -# Registers : 986 - 1-bit register : 638 - 10-bit register : 4 - 11-bit register : 7 - 12-bit register : 8 - 15-bit register : 3 - 16-bit register : 37 - 160-bit register : 3 - 17-bit register : 1 - 2-bit register : 22 - 23-bit register : 2 - 24-bit register : 1 - 28-bit register : 1 - 29-bit register : 9 - 3-bit register : 13 - 30-bit register : 3 - 32-bit register : 76 - 4-bit register : 45 - 48-bit register : 4 - 5-bit register : 15 - 6-bit register : 4 - 64-bit register : 2 - 7-bit register : 7 - 8-bit register : 72 - 9-bit register : 8 - 96-bit register : 1 -# Comparators : 93 - 1-bit comparator equal : 2 - 10-bit comparator equal : 1 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 5 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 20-bit comparator equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator equal : 8 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 12 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 1 -# Multiplexers : 1150 - 1-bit 2-to-1 multiplexer : 731 - 1-bit 3-to-1 multiplexer : 1 - 1-bit 4-to-1 multiplexer : 41 - 1-bit 8-to-1 multiplexer : 3 - 11-bit 2-to-1 multiplexer : 2 - 12-bit 2-to-1 multiplexer : 8 - 15-bit 2-to-1 multiplexer : 3 - 16-bit 2-to-1 multiplexer : 22 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 23 - 23-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 5 - 28-bit 2-to-1 multiplexer : 4 - 29-bit 2-to-1 multiplexer : 7 - 3-bit 2-to-1 multiplexer : 13 - 30-bit 2-to-1 multiplexer : 4 - 32-bit 2-to-1 multiplexer : 105 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 34 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 16 - 6-bit 2-to-1 multiplexer : 3 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 86 - 8-bit 4-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 8 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 1 - 64-bit shifter logical right : 1 -# Tristates : 3 - 1-bit tristate buffer : 1 - 8-bit tristate buffer : 2 -# FSMs : 13 -# Xors : 275 - 1-bit xor2 : 175 - 1-bit xor3 : 10 - 1-bit xor4 : 2 - 32-bit xor2 : 88 - -========================================================================= -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Reading core <../../platform/virtex6/chipscope/chipscope_ila.ngc>. -Reading core <../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 14 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 12 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 34 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 6-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32768-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32768-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 1024-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal <(refill_address<11:4>,refill_offset)> | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 1024-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal > | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block , in block . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block . - Found pipelined multiplier on signal : - - 1 pipeline level(s) found in a register connected to the multiplier macro output. - Pushing register(s) into the multiplier macro. -INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s). -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | addrB | connected to signal > | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 16 - 1024x32-bit dual-port block RAM : 1 - 16384x32-bit dual-port block RAM : 1 - 16x32-bit dual-port distributed RAM : 1 - 256x20-bit dual-port block RAM : 1 - 256x32-bit dual-port block RAM : 3 - 256x32-bit single-port block RAM : 1 - 256x32-bit single-port block Read Only RAM : 1 - 32768x32-bit dual-port block RAM : 1 - 32x32-bit dual-port block RAM : 2 - 4x2-bit single-port distributed Read Only RAM : 1 - 4x6-bit single-port distributed Read Only RAM : 1 - 8x1-bit single-port distributed Read Only RAM : 2 -# MACs : 2 - 16x16-to-16-bit MAC : 2 -# Multipliers : 1 - 16x16-bit registered multiplier : 1 -# Adders/Subtractors : 65 - 1-bit subtractor : 1 - 11-bit adder : 1 - 11-bit subtractor : 1 - 12-bit adder : 2 - 14-bit adder : 1 - 16-bit adder : 6 - 16-bit subtractor : 2 - 17-bit adder : 1 - 17-bit subtractor : 1 - 2-bit adder : 6 - 28-bit adder : 1 - 29-bit adder : 2 - 3-bit adder : 2 - 3-bit subtractor : 1 - 30-bit adder : 1 - 32-bit adder : 7 - 32-bit subtractor : 2 - 33-bit adder carry in : 1 - 33-bit subtractor borrow in : 1 - 4-bit adder : 6 - 5-bit adder : 8 - 6-bit adder : 1 - 7-bit adder : 4 - 8-bit adder : 2 - 8-bit subtractor : 2 - 9-bit subtractor : 2 -# Counters : 45 - 10-bit up counter : 1 - 15-bit down counter : 3 - 16-bit down counter : 1 - 16-bit up counter : 3 - 2-bit up counter : 1 - 2-bit updown counter : 1 - 3-bit up counter : 2 - 30-bit up counter : 2 - 32-bit down counter : 1 - 4-bit up counter : 4 - 4-bit updown counter : 2 - 5-bit up counter : 6 - 6-bit up counter : 1 - 8-bit down counter : 4 - 8-bit up counter : 6 - 8-bit updown counter : 3 - 9-bit down counter : 4 -# Accumulators : 3 - 11-bit up accumulator : 2 - 6-bit up loadable accumulator : 1 -# Registers : 5612 - Flip-Flops : 5612 -# Comparators : 93 - 1-bit comparator equal : 2 - 10-bit comparator equal : 1 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 5 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 20-bit comparator equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator equal : 8 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 12 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 1 -# Multiplexers : 1345 - 1-bit 2-to-1 multiplexer : 993 - 1-bit 3-to-1 multiplexer : 1 - 1-bit 4-to-1 multiplexer : 41 - 1-bit 8-to-1 multiplexer : 3 - 11-bit 2-to-1 multiplexer : 1 - 12-bit 2-to-1 multiplexer : 8 - 16-bit 2-to-1 multiplexer : 17 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 20 - 23-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 5 - 28-bit 2-to-1 multiplexer : 4 - 29-bit 2-to-1 multiplexer : 7 - 3-bit 2-to-1 multiplexer : 10 - 30-bit 2-to-1 multiplexer : 2 - 32-bit 2-to-1 multiplexer : 95 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 28 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 14 - 6-bit 2-to-1 multiplexer : 1 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 60 - 8-bit 4-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 4 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 1 - 64-bit shifter logical right : 1 -# FSMs : 13 -# Xors : 275 - 1-bit xor2 : 175 - 1-bit xor3 : 10 - 1-bit xor4 : 2 - 32-bit xor2 : 88 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - eth | 0001 - eth_capture | 0010 - eth_chk | 0011 - ipv4 | 0100 - ipv4_capture | 0101 - ipv4_chksum | unreached - ipv4_opt | 0111 - udp | 1000 - udp_fetch_buf | 1001 - udp_capture | 1010 - chk | 1011 - done | 1100 - errors | 1101 - waits | 1110 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 000 - header | 001 - payload | 010 - padding | 011 - done | 100 - errors | 101 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------ - State | Encoding ------------------------------------ - idle | 00000 - eb_hdr_rec | 00001 - eb_hdr_proc | 00010 - eb_hdr_probe_id | 00011 - eb_hdr_probe_rdy | 00100 - cyc_hdr_rec | 00101 - cyc_hdr_read_proc | 00110 - cyc_hdr_read_get_adr | 00111 - wb_read_rdy | 01000 - wb_read | 01001 - cyc_hdr_write_proc | 01010 - cyc_hdr_write_get_adr | 01011 - wb_write_rdy | 01100 - wb_write | 01101 - wb_write_done | 01110 - cyc_done | 01111 - eb_done | 10000 - error | 10001 - error_wait | 10010 ------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------- - State | Encoding -------------------------------------- - idle | 000000000001 - eb_hdr_init | 000000000100 - eb_hdr_probe_id | 001000000000 - eb_hdr_probe_wait | 000010000000 - packet_hdr_send | 000001000000 - eb_hdr_send | 000100000000 - rdy | 000000000010 - cyc_hdr_init | 000000001000 - cyc_hdr_send | 010000000000 - base_write_adr_send | 000000010000 - data_send | 100000000000 - zero_pad_write | 000000100000 - zero_pad_wait | unreached - error | unreached -------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - calc_chksum | 0001 - wait_send_req | 0010 - prep_eth | 0011 - eth | 0100 - ipv4 | 0101 - udp | 0110 - hdr_send | 0111 - payload_send | 1000 - padding | 1001 - wait_ifgap | 1010 - error | 1011 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - addup | 001 - carries | 010 - finalise | 011 - output | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ----------------------- - State | Encoding ----------------------- - idle | 00 - init | 01 - transfer | 11 - waiting | unreached - done | 10 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - init | 001 - transfer | 010 - waiting | unreached - done | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0110 | 0010 - 0101 | 0011 - 0010 | 0100 - 0011 | 0101 - 0100 | 0110 - 0111 | 0111 - 1000 | 1000 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0001 | 00 - 0010 | 01 - 0100 | 11 - 1000 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 011 | 011 - 100 | 100 -------------------- -WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL. - You should achieve better results by setting this init to 1. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:638 - in unit dbe_bpm_ebone Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_ebone Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_ebone Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_ebone, actual ratio is 9. - -Final Macro Processing ... - -Processing Unit : - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 5437 - Flip-Flops : 5437 -# Shift Registers : 12 - 2-bit shift register : 3 - 3-bit shift register : 1 - 5-bit shift register : 8 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- -------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -sys_clk_p_i | IBUFGDS+BUFG | 11 | -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 6554 | -mrx_clk_pad_i | BUFGP | 1068 | -mtx_clk_pad_i | BUFGP | 1006 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtag_cores/jtag_tap/update_delay)| 23 | -cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 731 | -cmp_chipscope_icon_0/CONTROL3<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL2<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD) | 1 | -------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -(*) These 4 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -FindSrcOfAsyncThruGates : 100 (1) -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0_ethmac/XST_VCC:P) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_ethmac_miim/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_ethmac_rx/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_ethmac_tx/XST_VCC:P) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 56 | -cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G) | NONE(cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram) | 10 | -cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w1:O) | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram) | 8 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1) | 6 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_12454_o(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_12454_o1:O) | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_11801_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_11801_o1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo) | 4 | -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 6.577ns (Maximum Frequency: 152.045MHz) - Minimum input arrival time before clock: 4.777ns - Maximum output required time after clock: 1.820ns - Maximum combinational path delay: No path found - -========================================================================= - -Process "Synthesize - XST" completed successfully - -Started : "Translate". -Running ngdbuild... -Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope/icon_4_port -sd ../../platform/virtex6/chipscope -sd ../../modules/dbe_wishbone/wb_fmc150/netlist -sd ../../modules/dbe_wishbone/wb_fmc516/coregen -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_ebone.ngc dbe_bpm_ebone.ngd - -Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle -ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd -../../platform/virtex6/chipscope/icon_2_port -sd -../../platform/virtex6/chipscope/icon_4_port -sd -../../platform/virtex6/chipscope -sd -../../modules/dbe_wishbone/wb_fmc150/netlist -sd -../../modules/dbe_wishbone/wb_fmc516/coregen -nt timestamp -uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf -p -xc6vlx240t-ff1156-1 dbe_bpm_ebone.ngc dbe_bpm_ebone.ngd - -Reading NGO file -"/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.ngc" ... -Loading design module "../../platform/virtex6/chipscope/chipscope_ila.ngc"... -Loading design module -"../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc"... - /dbe_bpm_ebone/dbe_bpm_ebone - /dbe_bpm_ebone/cmp_chipscope_ila_1_ethmac_miim - /dbe_bpm_ebone/cmp_chipscope_ila_0_ethmac - /dbe_bpm_ebone/cmp_chipscope_ila_1_ethmac_rx - /dbe_bpm_ebone/cmp_chipscope_ila_1_ethmac_tx - ------------------------------------------------ -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - ------------------------------------------------ - ------------------------------------------------ -Gathering constraint information from source properties... -Done. - -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf" ... -Resolving constraint associations... -Checking Constraint Associations... -Done... - -Checking expanded design ... - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 0 - -Writing NGD file "dbe_bpm_ebone.ngd" ... -Total REAL time to NGDBUILD completion: 21 sec -Total CPU time to NGDBUILD completion: 20 sec - -Writing NGDBUILD log file "dbe_bpm_ebone.bld"... - -NGDBUILD done. - -Process "Translate" completed successfully - -Started : "Map". -Running map... -Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_ebone_map.ncd dbe_bpm_ebone.ngd dbe_bpm_ebone.pcf -Using target part "6vlx240tff1156-1". -INFO:Map:284 - Map is running with the multi-threading option on. Map currently - supports the use of up to 2 processors. Based on the the user options and - machine load, Map will use 2 processors during this run. -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part -'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -Running directed packing... -Running delay-based LUT packing... -Updating timing models... -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 46 secs -Total CPU time at the beginning of Placer: 45 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:8c1ca42e) REAL time: 57 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:8c1ca42e) REAL time: 58 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:fe0c584d) REAL time: 58 secs - -Phase 4.37 Local Placement Optimization -Phase 4.37 Local Placement Optimization (Checksum:fe0c584d) REAL time: 58 secs - -Phase 5.2 Initial Placement for Architecture Specific Features - -Phase 5.2 Initial Placement for Architecture Specific Features -(Checksum:d06d9c09) REAL time: 1 mins 4 secs - -Phase 6.36 Local Placement Optimization -Phase 6.36 Local Placement Optimization (Checksum:d06d9c09) REAL time: 1 mins 4 secs - -Phase 7.30 Global Clock Region Assignment -Phase 7.30 Global Clock Region Assignment (Checksum:d06d9c09) REAL time: 1 mins 4 secs - -Phase 8.3 Local Placement Optimization -Phase 8.3 Local Placement Optimization (Checksum:d06d9c09) REAL time: 1 mins 4 secs - -Phase 9.5 Local Placement Optimization -Phase 9.5 Local Placement Optimization (Checksum:d06d9c09) REAL time: 1 mins 4 secs - -Phase 10.8 Global Placement -........................................ -...................................................................................................................................................................................... -............................................................................ -...................... -Phase 10.8 Global Placement (Checksum:76d2473e) REAL time: 1 mins 30 secs - -Phase 11.5 Local Placement Optimization -Phase 11.5 Local Placement Optimization (Checksum:76d2473e) REAL time: 1 mins 30 secs - -Phase 12.18 Placement Optimization -Phase 12.18 Placement Optimization (Checksum:5085956) REAL time: 1 mins 56 secs - -Phase 13.5 Local Placement Optimization -Phase 13.5 Local Placement Optimization (Checksum:5085956) REAL time: 1 mins 56 secs - -Phase 14.34 Placement Validation -Phase 14.34 Placement Validation (Checksum:ddc915e9) REAL time: 1 mins 57 secs - -Total REAL time to Placer completion: 1 mins 57 secs -Total CPU time to Placer completion: 2 mins 6 secs -Running post-placement packing... -Writing output files... - -Design Summary: -Number of errors: 0 -Number of warnings: 9 -Slice Logic Utilization: - Number of Slice Registers: 8,298 out of 301,440 2% - Number used as Flip Flops: 8,292 - Number used as Latches: 5 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 10,984 out of 150,720 7% - Number used as logic: 9,634 out of 150,720 6% - Number using O6 output only: 7,562 - Number using O5 output only: 430 - Number using O5 and O6: 1,642 - Number used as ROM: 0 - Number used as Memory: 712 out of 58,400 1% - Number used as Dual Port RAM: 24 - Number using O6 output only: 4 - Number using O5 output only: 0 - Number using O5 and O6: 20 - Number used as Single Port RAM: 0 - Number used as Shift Register: 688 - Number using O6 output only: 460 - Number using O5 output only: 0 - Number using O5 and O6: 228 - Number used exclusively as route-thrus: 638 - Number with same-slice register load: 602 - Number with same-slice carry load: 36 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 3,901 out of 37,680 10% - Number of LUT Flip Flop pairs used: 12,676 - Number with an unused Flip Flop: 5,808 out of 12,676 45% - Number with an unused LUT: 1,692 out of 12,676 13% - Number of fully used LUT-FF pairs: 5,176 out of 12,676 40% - Number of unique control sets: 428 - Number of slice register sites lost - to control set restrictions: 1,343 out of 301,440 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 40 out of 600 6% - Number of LOCed IOBs: 40 out of 40 100% - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 107 out of 416 25% - Number using RAMB36E1 only: 107 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 12 out of 832 1% - Number using RAMB18E1 only: 12 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 7 out of 32 21% - Number used as BUFGs: 7 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 0 out of 720 0% - Number of OLOGICE1/OSERDESE1s: 1 out of 720 1% - Number used as OLOGICE1s: 1 - Number used as OSERDESE1s: 0 - Number of BSCANs: 2 out of 4 50% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 0 out of 36 0% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 3 out of 768 1% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 0 out of 18 0% - Number of IODELAYE1s: 0 out of 720 0% - Number of MMCM_ADVs: 1 out of 12 8% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - Number of RPM macros: 48 -Average Fanout of Non-Clock Nets: 3.87 - -Peak Memory Usage: 1348 MB -Total REAL time to MAP completion: 2 mins 8 secs -Total CPU time to MAP completion (all processors): 2 mins 16 secs - -Mapping completed. -See MAP report file "dbe_bpm_ebone_map.mrp" for details. - -Process "Map" completed successfully - -Started : "Place & Route". -Running par... -Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_ebone_map.ncd dbe_bpm_ebone.ncd dbe_bpm_ebone.pcf - - - -Constraints file: dbe_bpm_ebone.pcf. -Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_ebone" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRODUCTION 1.17 2012-01-07". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 8,298 out of 301,440 2% - Number used as Flip Flops: 8,292 - Number used as Latches: 5 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 10,984 out of 150,720 7% - Number used as logic: 9,634 out of 150,720 6% - Number using O6 output only: 7,562 - Number using O5 output only: 430 - Number using O5 and O6: 1,642 - Number used as ROM: 0 - Number used as Memory: 712 out of 58,400 1% - Number used as Dual Port RAM: 24 - Number using O6 output only: 4 - Number using O5 output only: 0 - Number using O5 and O6: 20 - Number used as Single Port RAM: 0 - Number used as Shift Register: 688 - Number using O6 output only: 460 - Number using O5 output only: 0 - Number using O5 and O6: 228 - Number used exclusively as route-thrus: 638 - Number with same-slice register load: 602 - Number with same-slice carry load: 36 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 3,901 out of 37,680 10% - Number of LUT Flip Flop pairs used: 12,676 - Number with an unused Flip Flop: 5,808 out of 12,676 45% - Number with an unused LUT: 1,692 out of 12,676 13% - Number of fully used LUT-FF pairs: 5,176 out of 12,676 40% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 40 out of 600 6% - Number of LOCed IOBs: 40 out of 40 100% - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 107 out of 416 25% - Number using RAMB36E1 only: 107 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 12 out of 832 1% - Number using RAMB18E1 only: 12 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 7 out of 32 21% - Number used as BUFGs: 7 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 0 out of 720 0% - Number of OLOGICE1/OSERDESE1s: 1 out of 720 1% - Number used as OLOGICE1s: 1 - Number used as OSERDESE1s: 0 - Number of BSCANs: 2 out of 4 50% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 0 out of 36 0% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 3 out of 768 1% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 0 out of 18 0% - Number of IODELAYE1s: 0 out of 720 0% - Number of MMCM_ADVs: 1 out of 12 8% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -Starting initial Timing Analysis. REAL time: 14 secs -Finished initial Timing Analysis. REAL time: 14 secs - -WARNING:Par:288 - The signal cmp_dma/Mram_ring5_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -Starting Router - - -Phase 1 : 92673 unrouted; REAL time: 18 secs - -Phase 2 : 71706 unrouted; REAL time: 24 secs - -Phase 3 : 30721 unrouted; REAL time: 1 mins 1 secs - -Phase 4 : 30721 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 8 secs - -Updating file: dbe_bpm_ebone.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs - -Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs - -Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs - -Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs - -Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs - -Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 26 secs -Total REAL time to Router completion: 1 mins 26 secs -Total CPU time to Router completion: 1 mins 26 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<0> |BUFGCTRL_X0Y29| No | 321 | 0.428 | 2.020 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_sys | BUFGCTRL_X0Y3| No | 2075 | 0.321 | 1.905 | -+---------------------+--------------+------+------+------------+-------------+ -| mrx_clk_pad_i_BUFGP | BUFGCTRL_X0Y1| No | 267 | 0.361 | 2.007 | -+---------------------+--------------+------+------+------------+-------------+ -| mtx_clk_pad_i_BUFGP | BUFGCTRL_X0Y0| No | 265 | 0.335 | 2.019 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_gen |BUFGCTRL_X0Y31| No | 5 | 0.003 | 1.826 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_chipscope_icon_0 | | | | | | -| /U0/iUPDATE_OUT | Local| | 1 | 0.000 | 1.959 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_lm32/gen_profile | | | | | | -|_medium_icache_debug | | | | | | -|.U_Wrapped_LM32/jtck | | | | | | -| | Local| | 7 | 0.955 | 2.149 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<13> | Local| | 4 | 0.000 | 0.578 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_60_ML_NEW | | | | | | -| _CLK | Local| | 3 | 0.255 | 0.609 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_I1 | Local| | 3 | 0.000 | 1.495 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_OUT | Local| | 2 | 0.000 | 0.562 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL1<13> | Local| | 4 | 0.000 | 0.624 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL2<13> | Local| | 4 | 0.000 | 0.496 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL3<13> | Local| | 4 | 0.000 | 0.365 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -* The fanout is the number of component pins not the individual BEL loads, -for example SLICE loads not FF loads. - -Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) - - - -Generating Pad Report. - -All signals are completely routed. - -WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - -Total REAL time to PAR completion: 1 mins 33 secs -Total CPU time to PAR completion: 1 mins 32 secs - -Peak Memory Usage: 1227 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - No errors found. - -Number of error messages: 0 -Number of warning meINFO:TclTasksC:1850 - process run : Generate Programming File is done. -ssages: 7 -Number of info messages: 0 - -Writing design to file dbe_bpm_ebone.ncd - - - -PAR done! - -Process "Place & Route" completed successfully - -Started : "Generate Post-Place & Route Static Timing". -Running trce... -Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_ebone.twx dbe_bpm_ebone.ncd -o dbe_bpm_ebone.twr dbe_bpm_ebone.pcf -Loading device for application Rf_Device from file '6vlx240t.nph' in environment -/opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_ebone" is an NCD, version 3.2, device xc6vlx240t, package ff1156, -speed -1 - -Analysis completed Mon Feb 25 09:32:38 2013 --------------------------------------------------------------------------------- - -Generating Report ... - -Number of warnings: 0 -Total time: 26 secs - -Process "Generate Post-Place & Route Static Timing" completed successfully - -Started : "Generate Programming File". -Running bitgen... -Command Line: bitgen -intstyle ise -f dbe_bpm_ebone.ut dbe_bpm_ebone.ncd -INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most - commonly, bitgen has determined and will use a specific value instead of the - generic command-line value of "Auto". Alternately, this message appears if - the same option is specified multiple times on the command-line. In this - case, the option listed last will be used. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL2<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL3<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. - -Process "Generate Programming File" completed successfully diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/Manifest.py b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/Manifest.py deleted file mode 100755 index 68b1da23..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/Manifest.py +++ /dev/null @@ -1,10 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_fmc130m_4ch" -syn_project = "dbe_bpm_fmc130m_4ch.xise" - -modules = { "local" : [ "../../../top/ml_605/dbe_bpm_fmc130m_4ch" ] }; diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.xise b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.xise deleted file mode 100644 index f07fb03c..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.xise +++ /dev/null @@ -1,1610 +0,0 @@ - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/make_output b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/make_output deleted file mode 100644 index a99d36de..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch/make_output +++ /dev/null @@ -1,12270 +0,0 @@ -echo "project open dbe_bpm_fmc130m_4ch.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.syr" -Reading design: dbe_bpm_fmc130m_4ch.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 94. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_cop.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" included at line 64. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 65. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 165. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 166. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 87. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 74. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" into library work -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 317: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 318: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 322: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 323: Macro is redefined. -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 67. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 42. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 80. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 112. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xilinx_dist_ram_16x32.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 74. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 83. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 240. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 241. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 82. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" into library work -Parsing module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 133: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 159: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" into library work -Parsing package . -Parsing package body . -WARNING:HDLCompiler:797 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 704: Subprogram does not conform with its declaration. -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 251. f_num_adc_pins is declared here -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_private_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x3ffe0000]" -Note: "Mapping slave #1[0x10000000/0x3ffe0000]" -Note: "Mapping slave #2[0x20000000/0x3fff0000]" -Note: "Mapping slave #3[0x30004000/0x3fffffe0]" -Note: "Mapping slave #4[0x30005000/0x3ffffe00]" -Note: "Mapping slave #5[0x30006000/0x3fffff00]" -Note: "Mapping slave #6[0x30007000/0x3fffff00]" -Note: "Mapping slave #7[0x30010000/0x3ffff000]" -Note: "Mapping slave #8[0x30020000/0x3ffff000]" -Note: "Mapping slave #9[0x30000000/0x3ffffc00]" -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" Line 607: Assignment to lm32_rstn ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" Line 630: Assignment to lm32_interrupt ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module rs232_syscon_top_1_0 - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 322: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 357: Result of 17-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 363: Result of 17-bit expression is truncated to fit in 16-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 656: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 668: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 539: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 472: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 524: Result of 6-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1066: Result of 32-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1067: Result of 6-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1096: Result of 32-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1168: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1176: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1186: Result of 17-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:552 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" Line 30: Input port master_adr_i[31] is not connected on this instance -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 146: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 164: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 123: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 71: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 73: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module ethmac - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 883: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used -"/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted - -Elaborating module . -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" Line 248: Using initial value "00000000000000000000000000000000" for zero_din_width since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -WARNING:UtilitiesC:159 - Message file "usenglish/ip.msg" wasn't found. -INFO:ip - 0: (0,0) : 36x1024 u:32 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 36x1024 u:32 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Assignment ignored -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 509: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 428: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 432: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 168: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 169: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 286: Using initial value (('0','0',"00000000"),('0','0',"00000000"),('0','0',"00000000"),('0','0',"00000000")) for adc_in_dummy since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 311: Using initial value ("UUUU","UUUU","UUUU","UUUU") for adc_cs_dly_in since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 451: Using initial value '0' for dummy_bit_low since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 452: Using initial value "0000000000000000" for dummy_adc_vector_low since it is never assigned - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xf00]" -Note: "Mapping slave #1[0x100/0xf00]" -Note: "Mapping slave #2[0x200/0xf00]" -Note: "Mapping slave #3[0x300/0xf00]" -Note: "Mapping slave #4[0x400/0xf00]" -Note: "Mapping slave #5[0x800/0xe00]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 114: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 115: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 116: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 117: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 118: Assignment to allzeros ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 812: Assignment to adc_rst ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "[ map vector(0) = -1 ]" -Note: "[ map vector(1) = -1 ]" -Note: "[ map vector(2) = -1 ]" -Note: "[ map vector(3) = -1 ]" -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 601: Range is empty (null range) -Note: "[ intercon(0) = 0 ]" -Note: "[ intercon(1) = 1 ]" -Note: "[ intercon(2) = 2 ]" -Note: "[ intercon(3) = 3 ]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" Line 161: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" Line 207: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -INFO:ip - 0: (0,0) : 18x1024 u:16 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 18x1024 u:16 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 2776: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 2776: Assignment ignored - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" Line 141: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -INFO:ip - 0: (0,0) : 36x1024 u:36 -INFO:ip - 1: (36,0) : 36x1024 u:28 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 36x1024 u:36 -INFO:ip - 1: (36,0) : 36x1024 u:28 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" Line 90: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_bidir_top - -Elaborating module . - -Elaborating module . - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" Line 65: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 308: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x700]" -Note: "Mapping slave #1[0x100/0x700]" -Note: "Mapping slave #2[0x200/0x700]" -Note: "Mapping slave #3[0x300/0x7f0]" -Note: "Mapping slave #4[0x400/0x600]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" Line 65: Net does not have a driver. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" Line 474: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" Line 484: remains a black-box since it has no binding entity. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 562: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 562: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 675: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 713: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 735: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 797: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 797: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 852: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 1011: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 1011: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 1011: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd" line 1011: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit tristate buffer for signal created at line 788 - Summary: - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 1 - g_logdelay = 10 - g_syncdepth = 3 - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 14 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 7 - g_num_slaves = 9 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000000000000001100000000001000000100000000000000000000000000000000000000000000110000000000100000000000000000000000000000000000000000000000000011000000000010000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000011000000000001000010000000000000000000000000000000000000000000001100000000000100000000000000000000000000000000000000000000000000110000000000010000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000110000000000000111000000000000000000000000000000000000000000000011000000000000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000001100000000000001100000000000000000000000000000000000000000000000110000000000000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000110000000000000101000000000000000000000000000000000000000000000011000000000000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000110000000000000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010101111 -10011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_sdb_addr = "00110000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000000000000001100000000001000000100000000000000000000000000000000000000000000110000000000100000000000000000000000000000000000000000000000000011000000000010000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000011000000000001000010000000000000000000000000000000000000000000001100000000000100000000000000000000000000000000000000000000000000110000000000010000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000110000000000000111000000000000000000000000000000000000000000000011000000000000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000001100000000000001100000000000000000000000000000000000000000000000110000000000000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000110000000000000101000000000000000000000000000000000000000000000011000000000000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000110000000000000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010101111 -10011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000111111111111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value. - Found 256x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 7 - g_num_slaves = 10 - g_registered = true - g_address = ("00110000000000000000000000000000","00110000000000100000000000000000","00110000000000010000000000000000","00110000000000000111000000000000","00110000000000000110000000000000","00110000000000000101000000000000","00110000000000000100000000000000","00100000000000000000000000000000","00010000000000000000000000000000","00000000000000000000000000000000") - g_mask = ("00111111111111111111110000000000","00111111111111111111000000000000","00111111111111111111000000000000","00111111111111111111111100000000","00111111111111111111111100000000","00111111111111111111111000000000","00111111111111111111111111100000","00111111111111110000000000000000","00111111111111100000000000000000","00111111111111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 78 D-type flip-flop(s). - inferred 77 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd". - g_ma_interface_mode = pipelined - g_ma_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd". - g_ma_interface_mode = pipelined - g_ma_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = false - g_master_mode = pipelined - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v". -WARNING:Xst:2898 - Port 'master_adr_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. -WARNING:Xst:2898 - Port 'master_stb_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. -WARNING:Xst:2898 - Port 'master_we_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v". - ADR_DIGITS_PP = 8 - DAT_DIGITS_PP = 8 - QTY_DIGITS_PP = 2 - CMD_BUFFER_SIZE_PP = 64 - CMD_PTR_BITS_PP = 5 - WATCHDOG_TIMER_VALUE_PP = 65000 - WATCHDOG_TIMER_BITS_PP = 16 - RD_FIELDS_PP = 8 - RD_FIELD_COUNT_BITS_PP = 4 - RD_DIGIT_COUNT_BITS_PP = 4 - m1_initial_state = 5'b00000 - m1_send_ok = 5'b00001 - m1_send_prompt = 5'b00010 - m1_check_received_char = 5'b00011 - m1_send_crlf = 5'b00100 - m1_parse_error_indicator_crlf = 5'b00101 - m1_parse_error_indicator = 5'b00110 - m1_ack_error_indicator = 5'b00111 - m1_bg_error_indicator = 5'b01000 - m1_cmd_error_indicator = 5'b01001 - m1_adr_error_indicator = 5'b01010 - m1_dat_error_indicator = 5'b01011 - m1_qty_error_indicator = 5'b01100 - m1_scan_command = 5'b10000 - m1_scan_adr_whitespace = 5'b10001 - m1_get_adr_field = 5'b10010 - m1_scan_dat_whitespace = 5'b10011 - m1_get_dat_field = 5'b10100 - m1_scan_qty_whitespace = 5'b10101 - m1_get_qty_field = 5'b10110 - m1_start_execution = 5'b10111 - m1_request_bus = 5'b11000 - m1_bus_granted = 5'b11001 - m1_execute = 5'b11010 - m1_rd_send_adr_sr = 5'b11011 - m1_rd_send_separator = 5'b11100 - m1_rd_send_dat_sr = 5'b11101 - m1_rd_send_space = 5'b11110 - m1_rd_send_crlf = 5'b11111 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" line 371: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:3015 - Contents of array may be accessed with an index that does not cover the full array size or with a negative index. The RAM size is reduced to the index upper access or for only positive index values. - Found 32x8-bit single-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . -INFO:Xst:1799 - State 00101 is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 29 | - | Transitions | 90 | - | Inputs | 24 | - | Outputs | 21 | - | Clock | clk_i (rising_edge) | - | Reset | reset_i (positive) | - | Reset type | synchronous | - | Reset State | 00000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 472. - Found 32-bit adder for signal created at line 475. - Found 5-bit adder for signal created at line 524. - Found 5-bit adder for signal created at line 526. - Found 5-bit adder for signal created at line 1067. - Found 5-bit adder for signal created at line 1096. - Found 4-bit adder for signal created at line 1168. - Found 4-bit adder for signal created at line 1176. - Found 16-bit adder for signal created at line 1186. - Found 5-bit subtractor for signal > created at line 1066. - Found 32x8-bit Read Only RAM for signal - Found 4x2-bit Read Only RAM for signal <_n0785> - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 8-bit comparator equal for signal created at line 939 - Found 8-bit comparator lessequal for signal created at line 1089 - Found 8-bit comparator lessequal for signal created at line 1089 - Found 8-bit comparator lessequal for signal created at line 1090 - Found 8-bit comparator lessequal for signal created at line 1090 - Summary: - inferred 3 RAM(s). - inferred 9 Adder/Subtractor(s). - inferred 148 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 93 Multiplexer(s). - inferred 32 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v". - CLOCK_FACTOR_PP = 8 - LOG2_MAX_COUNT_PP = 16 - m1_idle = 4'b0000 - m1_measure_0 = 4'b0001 - m1_measure_1 = 4'b0010 - m1_measure_2 = 4'b0011 - m1_measure_3 = 4'b0100 - m1_measure_4 = 4'b0101 - m1_verify_0 = 4'b1000 - m1_verify_1 = 4'b1001 - m1_run = 4'b0110 - m1_verify_failed = 4'b0111 - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 24 | - | Inputs | 6 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | reset_i (positive) | - | Reset type | asynchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 322. - Found 16-bit adder for signal created at line 363. - Found 16-bit comparator equal for signal created at line 423 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 46 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 6 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v". - START_BITS_PP = 1 - DATA_BITS_PP = 8 - STOP_BITS_PP = 1 - CLOCK_FACTOR_PP = 8 - TX_BIT_COUNT_BITS_PP = 4 - m1_idle = 0 - m1_waiting = 1 - m1_sending = 3 - m1_sending_last_bit = 2 - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 10-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 12 | - | Inputs | 4 | - | Outputs | 1 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 00 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 656. - Found 4-bit adder for signal created at line 668. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v". - START_BITS_PP = 1 - DATA_BITS_PP = 8 - STOP_BITS_PP = 1 - CLOCK_FACTOR_PP = 8 - m1_idle = 0 - m1_start = 1 - m1_shift = 3 - m1_over_run = 2 - m1_under_run = 4 - m1_all_low = 5 - m1_extra_1 = 6 - m1_extra_2 = 7 - m2_data_ready_flag = 1 - m2_data_ready_ack = 0 - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 10-bit register for signal . - Found 8-bit register for signal . - Found 3-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 16 | - | Inputs | 7 | - | Outputs | 5 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 539. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 23 D-type flip-flop(s). - inferred 2 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 224. - Found 32-bit adder for signal created at line 228. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 214. - Found 4-bit comparator equal for signal created at line 165 - Found 5-bit comparator not equal for signal created at line 233 - Found 5-bit comparator not equal for signal created at line 234 - Found 5-bit comparator not equal for signal created at line 235 - Summary: - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 174 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 32768 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = pipelined - g_slave2_interface_mode = pipelined - g_slave1_granularity = byte - g_slave2_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 32768 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 32768 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32768x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 16384 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = byte - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16384x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 54 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 409. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v". - Tp = 1 - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 92. - Found 8-bit subtractor for signal created at line 107. - Found 8-bit comparator greater for signal created at line 91 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v". - Tp = 1 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 25 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit comparator greater for signal created at line 100 - Found 7-bit comparator greater for signal created at line 101 - Found 7-bit comparator greater for signal created at line 138 - Summary: - inferred 6 D-type flip-flop(s). - inferred 3 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861. - Found 32-bit comparator lessequal for signal created at line 388 - Found 32-bit comparator greater for signal created at line 907 - Found 32-bit comparator greater for signal created at line 908 - Summary: - inferred 21 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b10100000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 1'b0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0000000 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0010010 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0001100 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000110 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 6 - RESET_VALUE = 6'b111111 - Found 6-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 4 - RESET_VALUE = 4'b1111 - Found 4-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 3 - RESET_VALUE = 3'b000 - Found 3-bit register for signal . - Summary: - inferred 3 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01100100 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 5 - RESET_VALUE = 5'b00000 - Found 5-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 16 - RESET_VALUE = 16'b0000000000000000 - Found 16-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 16-bit subtractor for signal created at line 356. - Found 3-bit adder for signal created at line 304. - Found 5-bit adder for signal created at line 323. - Found 6-bit adder for signal created at line 417. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 72 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 6-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 255. - Found 6-bit adder for signal created at line 274. - Found 6-bit adder for signal created at line 277. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 20 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v". - Tp = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 344. - Found 6-bit comparator equal for signal created at line 249 - Found 4-bit comparator equal for signal created at line 349 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v". - Tp = 1 - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 17-bit subtractor for signal created at line 170. - Found 32-bit subtractor for signal created at line 170. - Found 16-bit adder for signal created at line 162. - Found 16-bit adder for signal created at line 194. - Found 3-bit adder for signal created at line 215. - Found 32-bit comparator lessequal for signal created at line 170 - Found 16-bit comparator equal for signal created at line 199 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 35 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 187 - Found 7-bit comparator not equal for signal created at line 187 - Summary: - inferred 12 D-type flip-flop(s). - inferred 4 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v". - Tp = 1 - Found 32-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 4-bit comparator greater for signal created at line 114 - Found 4-bit comparator greater for signal created at line 115 - Found 4-bit comparator greater for signal created at line 116 - Found 4-bit comparator greater for signal created at line 117 - Found 4-bit comparator greater for signal created at line 118 - Found 4-bit comparator greater for signal created at line 119 - Found 4-bit comparator greater for signal created at line 120 - Found 4-bit comparator greater for signal created at line 121 - Found 4-bit comparator greater for signal created at line 122 - Found 10-bit comparator equal for signal created at line 139 - Summary: - inferred 20 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit comparator greater for signal created at line 213 - Found 4-bit comparator lessequal for signal created at line 314 - Summary: - inferred 40 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v". - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 116. - Found 16-bit adder for signal created at line 120. - Found 5-bit adder for signal created at line 151. - Found 4-bit adder for signal created at line 173. - Found 16-bit comparator greater for signal created at line 131 - Found 16-bit comparator greater for signal created at line 132 - Found 16-bit comparator equal for signal created at line 134 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v". -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 7-bit register for signal . - Found 7-bit register for signal . - Found 2-bit register for signal . - Found 24-bit register for signal . - Found 9-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 773. - Found 16-bit subtractor for signal created at line 777. - Found 16-bit subtractor for signal created at line 781. - Found 16-bit subtractor for signal created at line 785. - Found 30-bit adder for signal created at line 821. - Found 3-bit adder for signal created at line 960. - Found 30-bit adder for signal created at line 964. - Found 3-bit adder for signal created at line 996. - Found 8-bit adder for signal created at line 1395. - Found 8-bit adder for signal created at line 1398. - Found 2-bit adder for signal created at line 1745. - Found 30-bit adder for signal created at line 2001. - Found 2-bit adder for signal created at line 2098. - Found 2-bit adder for signal created at line 2117. - Found 4x2-bit Read Only RAM for signal - Found 4x6-bit Read Only RAM for signal <_n1544> - Found 1-bit 4-to-1 multiplexer for signal created at line 1630. - Found 8-bit 4-to-1 multiplexer for signal created at line 1648. - Found 8-bit 4-to-1 multiplexer for signal created at line 1660. - Found 16-bit 4-to-1 multiplexer for signal created at line 776. - Found 16-bit comparator greater for signal created at line 627 - Found 16-bit comparator greater for signal created at line 803 - Found 16-bit comparator lessequal for signal created at line 898 - Found 8-bit comparator greater for signal created at line 1062 - Found 16-bit comparator greater for signal created at line 1062 - Found 8-bit comparator lessequal for signal created at line 2417 - Found 1-bit comparator equal for signal created at line 2422 - Found 8-bit comparator greater for signal created at line 2423 - Summary: - inferred 2 RAM(s). - inferred 11 Adder/Subtractor(s). - inferred 461 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v". - we_width = 1 - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v". - DATA_WIDTH = 32 - DEPTH = 256 - CNT_WIDTH = 8 - Set property "syn_ramstyle = no_rw_check" for signal . - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 83. - Found 8-bit adder for signal created at line 114. - Found 8-bit adder for signal created at line 122. - Found 8-bit subtractor for signal > created at line 81. - Summary: - inferred 1 RAM(s). - inferred 3 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 16-bit comparator greater for signal created at line 236 - Found 16-bit comparator greater for signal created at line 236 - Found 6-bit comparator equal for signal created at line 310 - Summary: - inferred 18 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 3 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_779_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_779_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 299. - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 320. - Found 16-bit adder for signal created at line 1241. - Found 32-bit 7-to-1 multiplexer for signal <_n0440> created at line 206. - Found 32-bit comparator greater for signal created at line 299 - Found 16-bit comparator greater for signal created at line 320 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 254 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 2 - g_adr_width_B = 32 - g_dat_width_A = 16 - g_dat_width_B = 32 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 32 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 32 - g_adr_width_B = 2 - g_dat_width_A = 32 - g_dat_width_B = 16 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 32 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 15-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 13-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 160-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 11-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 12 | - | Transitions | 41 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | _n0498 (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 11-bit adder for signal created at line 222. - Found 6-bit adder for signal created at line 464. - Found 7-bit adder for signal created at line 472. - Found 16-bit adder for signal created at line 1241. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit 3-to-1 multiplexer for signal created at line 242. - Found 1-bit 3-to-1 multiplexer for signal created at line 242. - Found 11-bit comparator equal for signal created at line 456 - Found 11-bit comparator equal for signal created at line 464 - Found 11-bit comparator equal for signal created at line 472 - Found 11-bit comparator greater for signal created at line 482 - Found 16-bit comparator equal for signal created at line 485 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 499 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 86 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 96 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 106 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd". - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 1 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_795_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 28-bit adder for signal created at line 91. - Found 28-bit adder for signal created at line 102. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 61 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 160 - g_width_OUT = 16 - g_protected = 0 - Found 9-bit register for signal . - Found 160-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 170 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 15-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 29 | - | Inputs | 10 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_855_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State ipv4_chksum is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 15 | - | Transitions | 34 | - | Inputs | 13 | - | Outputs | 12 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_parser_reset_OR_10592_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | eth | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 14-bit subtractor for signal created at line 426. - Found 11-bit adder for signal created at line 291. - Found 12-bit adder for signal created at line 405. - Found 12-bit adder for signal created at line 426. - Found 13-bit adder for signal created at line 426. - Found 17-bit adder for signal created at line 504. - Found 15-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 504. - Found 11-bit comparator equal for signal created at line 347 - Found 12-bit comparator equal for signal created at line 405 - Found 12-bit comparator greater for signal created at line 420 - Found 14-bit comparator equal for signal created at line 426 - Found 16-bit comparator equal for signal created at line 447 - Found 11-bit comparator greater for signal created at line 520 - Found 11-bit comparator equal for signal created at line 529 - Summary: - inferred 8 Adder/Subtractor(s). - inferred 244 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 14 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 160 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 160-bit register for signal . - Found 4-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 166 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 15-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . -INFO:Xst:1799 - State zero_pad_wait is never reached in FSM . -INFO:Xst:1799 - State error is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 716 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_946_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 19 | - | Transitions | 145 | - | Inputs | 19 | - | Outputs | 16 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_946_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit subtractor for signal > created at line 1308. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 4-bit comparator greater for signal created at line 363 - Found 16-bit comparator greater for signal created at line 504 - Found 8-bit comparator greater for signal created at line 584 - Found 8-bit comparator greater for signal created at line 619 - Found 16-bit comparator equal for signal created at line 659 - Found 4-bit comparator greater for signal created at line 716 - Found 8-bit comparator greater for signal created at line 986 - Summary: - inferred 13 Adder/Subtractor(s). - inferred 359 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 65 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 32 - g_size = 16 - g_show_ahead = true - g_with_empty = true - g_with_full = true - g_with_almost_empty = true - g_with_almost_full = true - g_with_count = true - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 1 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 32 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 0 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_PROG_FULL_TYPE = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 1 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd". - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_WR_RST_MAXFAN = 2 - C_RD_RST_MAXFAN = 3 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Summary: - inferred 15 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 1 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 32 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 4 - C_WRITE_WIDTH_A = 32 - C_WRITE_WIDTH_A_CORE = 32 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 4 - C_WRITE_WIDTH_B = 32 - C_WRITE_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 4 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 32 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 4 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 32 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_1', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_READ_WIDTH_B = 32 - C_READ_WIDTH_A_CORE = 32 - C_READ_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_USE_EMBEDDED_REG = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic_1', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_1', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd". - C_HAS_ALMOST_EMPTY = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY_FB', unconnected in block 'rd_status_flags_ss', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd". - C_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd". - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 210. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd". - C_RD_PNTR_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd". - C_COUNTER_RESET_VAL = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 126. - Found 4-bit subtractor for signal > created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 4 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_FULL_FLAGS_RST_VAL = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 1 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 151. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_EMPTY_TYPE = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss_1', is tied to its initial value (1). -WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss_1', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd". - C_HAS_RST = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_FULL_FLAGS_RST_VAL = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 243. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd". - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 1 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 8-to-1 multiplexer for signal <_n0259> created at line 168. - Found 32-bit 8-to-1 multiplexer for signal <_n0277> created at line 137. - Summary: - inferred 328 D-type flip-flop(s). - inferred 22 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (8.47,8.47,8.47,8.47) - g_use_clk_chains = "1111" - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (8.47,8.47,8.47,8.47) - g_use_clk_chains = "1111" - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 533: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 570: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 612: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 612: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 612: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 612: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 612: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 924: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1044: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1044: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1079: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1115: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1153: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 1-bit tristate buffer for signal created at line 1028 - Found 1-bit tristate buffer for signal created at line 1031 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1103 - Found 1-bit tristate buffer for signal created at line 1136 - Found 1-bit tristate buffer for signal created at line 1139 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 6 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100010000000000000000000000000000010011100010110000000101111001011001011110110110001100100011110100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101001001001100100100001101011111010011010100000101010011010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010111000010000101111011110001010100000000000000000000000000000001001000000001001100100000000010000100110001001110010011000101001101011111010001100100110101000011001100010011001100110000010011010101111101010010010001010100011101010011001000000010000000000001") - g_sdb_addr = "00000000000000000000100000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100010000000000000000000000000000010011100010110000000101111001011001011110110110001100100011110100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101001001001100100100001101011111010011010100000101010011010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010111000010000101111011110001010100000000000000000000000000000001001000000001001100100000000010000100110001001110010011000101001101011111010001100100110101000011001100010011001100110000010011010101111101010010010001010100011101010011001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 6 - g_registered = true - g_address = ("00000000000000000000100000000000","00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000111000000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 7-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 7 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 297 D-type flip-flop(s). - inferred 35 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd". - g_with_var_loadable = true - g_with_variable = false - g_with_fn_dly_select = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Summary: - inferred 12 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd". - g_with_clk_single_ended = true - g_with_data_single_ended = true - g_with_data_sdr = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clk_period_values = (8.47,8.47,8.47,8.47) - g_use_clk_chains = "1111" - g_clk_default_dly = (5,5,5,5) - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_data_default_dly = (9,9,9,9) - g_ref_clk = 1 - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_with_data_sdr = true - g_with_fn_dly_select = true - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.47 - g_default_adc_clk_delay = 5 - g_with_ref_clk = false - g_with_fn_dly_select = true - g_with_bufio = false - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.47 - g_default_adc_clk_delay = 5 - g_with_ref_clk = true - g_with_fn_dly_select = true - g_with_bufio = false - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd". - g_delay_type = "VAR_LOADABLE" - g_default_adc_data_delay = 9 - g_with_data_sdr = true - g_with_fn_dly_select = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Summary: - inferred 81 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 16 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 0 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 16 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 16 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 0 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 2 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_PROG_FULL_TYPE = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 0 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 0 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 0 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 0 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 0 - C_HAS_SRST = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 16 - C_READ_WIDTH_B = 16 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 16 - C_READ_WIDTH_B = 16 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 2 - C_WRITE_WIDTH_A = 16 - C_WRITE_WIDTH_A_CORE = 16 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 2 - C_WRITE_WIDTH_B = 16 - C_WRITE_WIDTH_B_CORE = 16 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(18,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 2 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 16 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 16 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 2 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 16 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 16 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 18 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 16 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 18 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 16 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 18 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 18 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 18 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 18 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_2', is tied to its initial value (000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_READ_WIDTH_B = 16 - C_READ_WIDTH_A_CORE = 16 - C_READ_WIDTH_B_CORE = 16 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_MSGON_VAL = 1 - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 0 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_USE_EMBEDDED_REG = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 241: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'DATA_COUNT', unconnected in block 'rd_logic_2', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_2', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY', unconnected in block 'rd_status_flags_as', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_FULL_FLAGS_RST_VAL = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 243: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 0 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 270. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_almost_full_i', unconnected in block 'wr_status_flags_as', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 0 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_OVERFLOW = 0 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 64 - g_size = 16 - g_show_ahead = false - g_with_empty = true - g_with_full = true - g_with_almost_empty = false - g_with_almost_full = false - g_with_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 1 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 64 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 64 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 0 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_PROG_FULL_TYPE = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 0 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 1 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 64 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 64 - C_READ_WIDTH_A = 64 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 64 - C_READ_WIDTH_B = 64 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 64 - C_READ_WIDTH_A = 64 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 64 - C_READ_WIDTH_B = 64 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 8 - C_WRITE_WIDTH_A = 64 - C_WRITE_WIDTH_A_CORE = 64 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 8 - C_WRITE_WIDTH_B = 64 - C_WRITE_WIDTH_B_CORE = 64 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 2 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(36,36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(36,28,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 8 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 64 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 64 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 8 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 64 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 64 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 36 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "000000000000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "000000000000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 36 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_3', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 36 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 28 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<35:34>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dina_pad<26:25>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dina_pad<17:16>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dina_pad<8:7>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<35:34>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<26:25>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<17:16>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<8:7>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 36 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 28 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_4', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 64 - C_READ_WIDTH_A = 64 - C_READ_WIDTH_B = 64 - C_READ_WIDTH_A_CORE = 64 - C_READ_WIDTH_B_CORE = 64 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_USE_EMBEDDED_REG = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic_3', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_3', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_FULL_FLAGS_RST_VAL = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 1 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 151. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_EMPTY_TYPE = 0 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss_2', is tied to its initial value (1). -WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss_2', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 1 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd". - ARST_LVL = '0' -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit 8-to-1 multiplexer for signal created at line 191. - Summary: - inferred 54 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 26 | - | Inputs | 9 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | st_idle | - | Power Up State | st_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 3-bit subtractor for signal > created at line 1308. - Found 4-bit 6-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 34 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 14-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 64 | - | Inputs | 6 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit subtractor for signal > created at line 1308. - Found 14-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 57 D-type flip-flop(s). - inferred 26 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 12-to-1 multiplexer for signal created at line 126. - Summary: - inferred 80 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v". - Tp = 1 - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 80. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v". - Tp = 1 - Found 12-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 91. - Found 8-bit subtractor for signal created at line 91. - Found 8-bit subtractor for signal created at line 92. - Found 8-bit adder for signal created at line 92. - Found 12-bit adder for signal created at line 116. - Found 1-bit 128-to-1 multiplexer for signal created at line 164. - Found 1-bit 128-to-1 multiplexer for signal created at line 293. - Found 1-bit 128-to-1 multiplexer for signal created at line 294. - Found 12-bit comparator lessequal for signal created at line 137 - Found 12-bit comparator greater for signal created at line 139 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 407 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 146 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd". - g_wbs_interface_width = narrow2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd". - g_data_width = 25 - g_size = 32 - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 25-bit register for signal >. - Found 5-bit adder for signal created at line 142. - Found 5-bit subtractor for signal > created at line 144. -INFO:Xst:3019 - HDL ADVISOR - 800 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 25-bit 32-to-1 multiplexer for signal created at line 109. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 806 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd". - g_min_pulse_width = 1 - g_clk_frequency = 130 - g_output_polarity = '0' - g_output_retrig = false - g_output_length = 1 - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 20000000 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 84: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 119: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 158: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 4 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_sdb_addr = "00000000000000000000010000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000011111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_3', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_address = ("00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000011000000000","00000000000000000000011111110000","00000000000000000000011100000000","00000000000000000000011100000000","00000000000000000000011100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 46 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1263_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1273_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 5 | - | Inputs | 1 | - | Outputs | 1 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1273_o (positive) | - | Reset type | synchronous | - | Reset State | 00 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 24-bit register for signal . - Found 24-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 90 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 17 - 128x32-bit single-port Read Only RAM : 2 - 16384x32-bit dual-port RAM : 1 - 16x32-bit dual-port RAM : 1 - 256x32-bit dual-port RAM : 4 - 256x32-bit single-port Read Only RAM : 1 - 32768x32-bit dual-port RAM : 1 - 32x8-bit single-port RAM : 1 - 32x8-bit single-port Read Only RAM : 1 - 4x2-bit single-port Read Only RAM : 2 - 4x6-bit single-port Read Only RAM : 1 - 8x1-bit single-port Read Only RAM : 2 -# Adders/Subtractors : 150 - 10-bit adder : 1 - 11-bit adder : 2 - 11-bit subtractor : 1 - 12-bit adder : 3 - 13-bit adder : 1 - 14-bit subtractor : 4 - 15-bit subtractor : 3 - 16-bit adder : 14 - 16-bit subtractor : 7 - 17-bit adder : 2 - 17-bit subtractor : 1 - 2-bit adder : 6 - 2-bit addsub : 1 - 2-bit subtractor : 1 - 24-bit adder : 1 - 28-bit adder : 1 - 3-bit adder : 4 - 3-bit subtractor : 3 - 30-bit adder : 3 - 32-bit adder : 7 - 32-bit subtractor : 4 - 4-bit adder : 26 - 4-bit addsub : 2 - 5-bit adder : 13 - 5-bit addsub : 5 - 6-bit adder : 3 - 7-bit adder : 2 - 8-bit adder : 12 - 8-bit addsub : 3 - 8-bit subtractor : 8 - 9-bit subtractor : 6 -# Registers : 1798 - 1-bit register : 1206 - 10-bit register : 5 - 11-bit register : 11 - 12-bit register : 1 - 14-bit register : 3 - 15-bit register : 3 - 16-bit register : 66 - 160-bit register : 3 - 17-bit register : 5 - 2-bit register : 32 - 24-bit register : 2 - 25-bit register : 128 - 28-bit register : 1 - 3-bit register : 24 - 30-bit register : 3 - 32-bit register : 62 - 4-bit register : 105 - 48-bit register : 4 - 5-bit register : 23 - 6-bit register : 5 - 64-bit register : 2 - 7-bit register : 10 - 8-bit register : 84 - 9-bit register : 9 - 96-bit register : 1 -# Comparators : 86 - 1-bit comparator equal : 1 - 10-bit comparator equal : 1 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 2 - 12-bit comparator lessequal : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 6 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 13 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 5 -# Multiplexers : 1454 - 1-bit 128-to-1 multiplexer : 3 - 1-bit 2-to-1 multiplexer : 963 - 1-bit 3-to-1 multiplexer : 7 - 1-bit 4-to-1 multiplexer : 9 - 1-bit 8-to-1 multiplexer : 2 - 10-bit 2-to-1 multiplexer : 1 - 11-bit 2-to-1 multiplexer : 7 - 12-bit 2-to-1 multiplexer : 1 - 14-bit 2-to-1 multiplexer : 6 - 15-bit 2-to-1 multiplexer : 3 - 16-bit 2-to-1 multiplexer : 51 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 27 - 24-bit 2-to-1 multiplexer : 6 - 25-bit 32-to-1 multiplexer : 4 - 28-bit 2-to-1 multiplexer : 4 - 3-bit 2-to-1 multiplexer : 19 - 30-bit 2-to-1 multiplexer : 4 - 32-bit 12-to-1 multiplexer : 1 - 32-bit 2-to-1 multiplexer : 69 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 93 - 4-bit 6-to-1 multiplexer : 3 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 19 - 6-bit 2-to-1 multiplexer : 4 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 7 - 8-bit 2-to-1 multiplexer : 110 - 8-bit 4-to-1 multiplexer : 2 - 8-bit 8-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 9 - 96-bit 2-to-1 multiplexer : 1 -# Tristates : 41 - 1-bit tristate buffer : 39 - 8-bit tristate buffer : 2 -# FSMs : 21 -# Xors : 335 - 1-bit xor2 : 226 - 1-bit xor3 : 18 - 1-bit xor4 : 10 - 32-bit xor2 : 81 - -========================================================================= -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Reading core <../../platform/virtex6/chipscope/chipscope_ila.ngc>. -Reading core <../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 14 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 12 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 34 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 6-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32768-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32768-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 8-bit | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 8-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 17 - 128x32-bit single-port block Read Only RAM : 2 - 16384x32-bit dual-port block RAM : 1 - 16x32-bit dual-port block RAM : 1 - 256x32-bit dual-port block RAM : 3 - 256x32-bit single-port block RAM : 1 - 256x32-bit single-port block Read Only RAM : 1 - 32768x32-bit dual-port block RAM : 1 - 32x8-bit single-port distributed RAM : 1 - 32x8-bit single-port distributed Read Only RAM : 1 - 4x2-bit single-port distributed Read Only RAM : 2 - 4x6-bit single-port distributed Read Only RAM : 1 - 8x1-bit single-port distributed Read Only RAM : 2 -# Adders/Subtractors : 79 - 11-bit adder : 1 - 11-bit subtractor : 1 - 12-bit adder : 2 - 14-bit adder : 1 - 14-bit subtractor : 3 - 16-bit adder : 6 - 16-bit subtractor : 2 - 17-bit adder : 1 - 17-bit subtractor : 1 - 2-bit adder : 4 - 28-bit adder : 1 - 3-bit adder : 2 - 3-bit subtractor : 3 - 30-bit adder : 1 - 32-bit adder : 6 - 32-bit subtractor : 2 - 4-bit adder : 17 - 5-bit adder : 10 - 6-bit adder : 1 - 7-bit adder : 4 - 7-bit subtractor : 2 - 8-bit adder : 3 - 8-bit subtractor : 3 - 9-bit subtractor : 2 -# Counters : 71 - 10-bit up counter : 1 - 12-bit up counter : 1 - 15-bit down counter : 3 - 16-bit down counter : 5 - 16-bit up counter : 8 - 2-bit down counter : 1 - 2-bit up counter : 2 - 2-bit updown counter : 1 - 24-bit up counter : 1 - 3-bit up counter : 2 - 30-bit up counter : 2 - 32-bit down counter : 2 - 32-bit up counter : 1 - 4-bit up counter : 9 - 4-bit updown counter : 2 - 5-bit up counter : 7 - 5-bit updown counter : 5 - 6-bit up counter : 1 - 8-bit down counter : 3 - 8-bit up counter : 7 - 8-bit updown counter : 3 - 9-bit down counter : 4 -# Accumulators : 3 - 11-bit up accumulator : 2 - 6-bit up loadable accumulator : 1 -# Registers : 6170 - Flip-Flops : 6170 -# Shift Registers : 100 - 32-bit dynamic shift register : 100 -# Comparators : 86 - 1-bit comparator equal : 1 - 10-bit comparator equal : 1 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 2 - 12-bit comparator lessequal : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 6 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 13 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 5 -# Multiplexers : 1509 - 1-bit 12-to-1 multiplexer : 32 - 1-bit 128-to-1 multiplexer : 3 - 1-bit 2-to-1 multiplexer : 1048 - 1-bit 3-to-1 multiplexer : 7 - 1-bit 4-to-1 multiplexer : 9 - 1-bit 8-to-1 multiplexer : 26 - 10-bit 2-to-1 multiplexer : 1 - 11-bit 2-to-1 multiplexer : 7 - 14-bit 2-to-1 multiplexer : 6 - 16-bit 2-to-1 multiplexer : 38 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 22 - 24-bit 2-to-1 multiplexer : 5 - 28-bit 2-to-1 multiplexer : 4 - 3-bit 2-to-1 multiplexer : 17 - 30-bit 2-to-1 multiplexer : 2 - 32-bit 2-to-1 multiplexer : 66 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 84 - 4-bit 6-to-1 multiplexer : 3 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 17 - 6-bit 2-to-1 multiplexer : 1 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 81 - 8-bit 4-to-1 multiplexer : 2 - 9-bit 2-to-1 multiplexer : 5 - 96-bit 2-to-1 multiplexer : 1 -# FSMs : 21 -# Xors : 335 - 1-bit xor2 : 226 - 1-bit xor3 : 18 - 1-bit xor4 : 10 - 32-bit xor2 : 81 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d1 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - st_idle | 000 - st_start | 001 - st_read | 010 - st_write | 011 - st_ack | 100 - st_stop | 101 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 00000 - start_a | 00001 - start_b | 00010 - start_c | 00011 - start_d | 00100 - start_e | 00101 - stop_a | 00110 - stop_b | 00111 - stop_c | 01000 - stop_d | 01001 - rd_a | 01010 - rd_b | 01011 - rd_c | 01100 - rd_d | 01101 - wr_a | 01110 - wr_b | 01111 - wr_c | 10000 - wr_d | 10001 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 00 | 00 - 01 | 01 - 11 | 11 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 00000 | 00000 - 00010 | 00001 - 00001 | 00011 - 00011 | 00010 - 00100 | 00110 - 10000 | 00111 - 00101 | unreached - 00110 | 00101 - 00111 | 00100 - 01000 | 01100 - 01001 | 01101 - 01010 | 01111 - 01011 | 01110 - 01100 | 01010 - 10111 | 01011 - 10001 | 01001 - 10010 | 01000 - 10011 | 11000 - 10100 | 11001 - 10101 | 11011 - 10110 | 11010 - 11000 | 11110 - 11001 | 11111 - 11010 | 11101 - 11101 | 11100 - 11011 | 10100 - 11100 | 10101 - 11110 | 10111 - 11111 | 10110 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0010 | 0010 - 0011 | 0011 - 0100 | 0100 - 0101 | 0101 - 1000 | 1000 - 0110 | 0110 - 1001 | 1001 - 0111 | 0111 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------- - State | Encoding -------------------- - 00 | 001 - 11 | 010 - 10 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 100 | 010 - 011 | 011 - 010 | 100 - 101 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - eth | 0001 - eth_capture | 0010 - eth_chk | 0011 - ipv4 | 0100 - ipv4_capture | 0101 - ipv4_chksum | unreached - ipv4_opt | 0111 - udp | 1000 - udp_fetch_buf | 1001 - udp_capture | 1010 - chk | 1011 - done | 1100 - errors | 1101 - waits | 1110 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 000 - header | 001 - payload | 010 - padding | 011 - done | 100 - errors | 101 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------ - State | Encoding ------------------------------------ - idle | 00000 - eb_hdr_rec | 00001 - eb_hdr_proc | 00010 - eb_hdr_probe_id | 00011 - eb_hdr_probe_rdy | 00100 - cyc_hdr_rec | 00101 - cyc_hdr_read_proc | 00110 - cyc_hdr_read_get_adr | 00111 - wb_read_rdy | 01000 - wb_read | 01001 - cyc_hdr_write_proc | 01010 - cyc_hdr_write_get_adr | 01011 - wb_write_rdy | 01100 - wb_write | 01101 - wb_write_done | 01110 - cyc_done | 01111 - eb_done | 10000 - error | 10001 - error_wait | 10010 ------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------- - State | Encoding -------------------------------------- - idle | 000000000001 - eb_hdr_init | 000000000100 - eb_hdr_probe_id | 001000000000 - eb_hdr_probe_wait | 000010000000 - packet_hdr_send | 000001000000 - eb_hdr_send | 000100000000 - rdy | 000000000010 - cyc_hdr_init | 000000001000 - cyc_hdr_send | 010000000000 - base_write_adr_send | 000000010000 - data_send | 100000000000 - zero_pad_write | 000000100000 - zero_pad_wait | unreached - error | unreached -------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - calc_chksum | 0001 - wait_send_req | 0010 - prep_eth | 0011 - eth | 0100 - ipv4 | 0101 - udp | 0110 - hdr_send | 0111 - payload_send | 1000 - padding | 1001 - wait_ifgap | 1010 - error | 1011 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - addup | 001 - carries | 010 - finalise | 011 - output | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ----------------------- - State | Encoding ----------------------- - idle | 00 - init | 01 - transfer | 11 - waiting | unreached - done | 10 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - init | 001 - transfer | 010 - waiting | unreached - done | 100 ----------------------- -WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL. - You should achieve better results by setting this init to 1. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit rs232_syscon: 32 internal tristates are replaced by logic (pull-up yes): data_out<0>, data_out<10>, data_out<11>, data_out<12>, data_out<13>, data_out<14>, data_out<15>, data_out<16>, data_out<17>, data_out<18>, data_out<19>, data_out<1>, data_out<20>, data_out<21>, data_out<22>, data_out<23>, data_out<24>, data_out<25>, data_out<26>, data_out<27>, data_out<28>, data_out<29>, data_out<2>, data_out<30>, data_out<31>, data_out<3>, data_out<4>, data_out<5>, data_out<6>, data_out<7>, data_out<8>, data_out<9>. -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:638 - in unit dbe_bpm_fmc130m_4ch Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_fmc130m_4ch Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_fmc130m_4ch Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_fmc130m_4ch, actual ratio is 10. - -Final Macro Processing ... - -Processing Unit : - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 5758 - Flip-Flops : 5758 -# Shift Registers : 76 - 2-bit shift register : 3 - 3-bit shift register : 65 - 5-bit shift register : 8 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- ----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+-------+ -sys_clk_p_i | IBUFGDS+BUFG | 11 | -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 5743 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| MMCM_ADV:CLKOUT0 | 1902 | -mrx_clk_pad_i | BUFGP | 287 | -mtx_clk_pad_i | BUFGP | 1006 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[3].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 69 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[2].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 69 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 70 | -cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 731 | -cmp_chipscope_icon_0/CONTROL3<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)| 1 | -cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL2<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD) | 1 | ----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+-------+ -(*) These 4 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -FindSrcOfAsyncThruGates : 100 (1) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G) | NONE(cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram) | 58 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0_fmc130m_4ch_clk0/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_fmc130m_4ch_clk1/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_2_ethmac_tx/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_3_fmc130m_4ch_periph/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1) | 6 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_9323_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_9323_o1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo) | 4 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/gen_wbs_interfaces[0].gen_wbs_interfaces_ch.cmp_wb_stream_source_gen/cmp_fifo/do_write(XST_VCC:P) | NONE(cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr) | 4 | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 6.577ns (Maximum Frequency: 152.045MHz) - Minimum input arrival time before clock: 4.777ns - Maximum output required time after clock: 2.850ns - Maximum combinational path delay: 0.425ns - -========================================================================= - -Process "Synthesize - XST" completed successfully - -Started : "Translate". -Running ngdbuild... -Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope/icon_4_port -sd ../../platform/virtex6/chipscope -sd ../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_fmc130m_4ch.ngc dbe_bpm_fmc130m_4ch.ngd - -Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle -ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd -../../platform/virtex6/chipscope/icon_2_port -sd -../../platform/virtex6/chipscope/icon_4_port -sd -../../platform/virtex6/chipscope -sd -../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch -.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_fmc130m_4ch.ngc dbe_bpm_fmc130m_4ch.ngd - -Reading NGO file -"/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.ngc" -... -Loading design module "../../platform/virtex6/chipscope/chipscope_ila.ngc"... -Loading design module -"../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc"... - /dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch - /dbe_bpm_fmc130m_4ch/cmp_chipscope_ila_3_fmc130m_4ch_periph - /dbe_bpm_fmc130m_4ch/cmp_chipscope_ila_1_fmc130m_4ch_clk1 - /dbe_bpm_fmc130m_4ch/cmp_chipscope_ila_0_fmc130m_4ch_clk0 - /dbe_bpm_fmc130m_4ch/cmp_chipscope_ila_2_ethmac_tx - ------------------------------------------------ -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - ------------------------------------------------ - ------------------------------------------------ -Gathering constraint information from source properties... -Done. - -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4c -h.ucf" ... -Resolving constraint associations... -Checking Constraint Associations... - - - -Done... - -WARNING:NgdBuild:1440 - User specified non-default attribute value (8.47) was - detected for the CLKIN1_PERIOD attribute on MMCM - "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1] - .gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_ref_clk.cmp_mmcm_adc_clk". - This does not match the PERIOD constraint value (112.583 MHz.). The - uncertainty calculation will use the PERIOD constraint value. This could - result in incorrect uncertainty calculated for MMCM output clocks. -Checking expanded design ... -WARNING:NgdBuild:452 - logical net 'N2078' has no driver - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 2 - -Writing NGD file "dbe_bpm_fmc130m_4ch.ngd" ... -Total REAL time to NGDBUILD completion: 24 sec -Total CPU time to NGDBUILD completion: 23 sec - -Writing NGDBUILD log file "dbe_bpm_fmc130m_4ch.bld"... - -NGDBUILD done. - -Process "Translate" completed successfully - -Started : "Map". -Running map... -Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_fmc130m_4ch_map.ncd dbe_bpm_fmc130m_4ch.ngd dbe_bpm_fmc130m_4ch.pcf -Using target part "6vlx240tff1156-1". -INFO:Map:284 - Map is running with the multi-threading option on. Map currently - supports the use of up to 2 processors. Based on the the user options and - machine load, Map will use 2 processors during this run. -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part -'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -Running directed packing... -WARNING:Pack:1186 - One or more I/O components have conflicting property values. - For each occurrence, the system will use the property value attached to the - pad. Otherwise, the system will use the first property value read. To view - each occurrence, create a detailed map report (run map using the -detail - option). -Running delay-based LUT packing... -Updating timing models... -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 1 mins 1 secs -Total CPU time at the beginning of Placer: 57 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:9980711a) REAL time: 1 mins 13 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:9980711a) REAL time: 1 mins 15 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:92fb8ac) REAL time: 1 mins 15 secs - -Phase 4.37 Local Placement Optimization -Phase 4.37 Local Placement Optimization (Checksum:92fb8ac) REAL time: 1 mins 15 secs - -Phase 5.2 Initial Placement for Architecture Specific Features - -...... - - -There are 12 clock regions on the target FPGA device: -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 2 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: | -| 4 BUFRs available, 2 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 4 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: | -| 4 BUFRs available, 2 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 4 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 0/4; bufrs - 2/4; regional-clock-spines - 4/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/ | 1 | 0 | 0 | 0 | 0 | 32 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/ | 1 | 0 | 0 | 0 | 0 | 33 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 0/4; bufrs - 2/4; regional-clock-spines - 4/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 1 | 0 | 0 | 0 | 0 | 32 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 1 | 0 | 0 | 0 | 0 | 33 | 16 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - - - -###################################################################################### -# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT: -# -# Number of Regional Clocking Regions in the device: 12 (6 clock spines in each) -# Number of Regional Clock Networks used in this design: 4 (each network can be -# composed of up to 3 clock spines and cover up to 3 regional clock regions) -# -###################################################################################### - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" driven -by "BUFR_X0Y3" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[3].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y3" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[3]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" driven -by "BUFR_X1Y0" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[2].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y0" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[2]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" driven -by "BUFR_X0Y1" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y1" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# Regional-Clock "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" driven -by "BUFR_X1Y3" -INST -"cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen -_with_bufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y3" ; -NET "cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -Phase 5.2 Initial Placement for Architecture Specific Features (Checksum:287077) REAL time: 1 mins 50 secs - -Phase 6.36 Local Placement Optimization -Phase 6.36 Local Placement Optimization (Checksum:287077) REAL time: 1 mins 50 secs - -Phase 7.30 Global Clock Region Assignment -Phase 7.30 Global Clock Region Assignment (Checksum:287077) REAL time: 1 mins 50 secs - -Phase 8.3 Local Placement Optimization -Phase 8.3 Local Placement Optimization (Checksum:287077) REAL time: 1 mins 51 secs - -Phase 9.5 Local Placement Optimization -Phase 9.5 Local Placement Optimization (Checksum:287077) REAL time: 1 mins 51 secs - -Phase 10.8 Global Placement -...................................................................................... -...................................................................................................................................... -......................................................................................................... -.................. -Phase 10.8 Global Placement (Checksum:e60e0a2d) REAL time: 2 mins 40 secs - -Phase 11.5 Local Placement Optimization -Phase 11.5 Local Placement Optimization (Checksum:e60e0a2d) REAL time: 2 mins 41 secs - -Phase 12.18 Placement Optimization -Phase 12.18 Placement Optimization (Checksum:27580be7) REAL time: 3 mins 30 secs - -Phase 13.5 Local Placement Optimization -Phase 13.5 Local Placement Optimization (Checksum:27580be7) REAL time: 3 mins 30 secs - -Phase 14.34 Placement Validation -Phase 14.34 Placement Validation (Checksum:5f1eaa9e) REAL time: 3 mins 31 secs - -Total REAL time to Placer completion: 3 mins 34 secs -Total CPU time to Placer completion: 3 mins 26 secs -Running post-placement packing... -Writing output files... - -Design Summary: -Number of errors: 0 -Number of warnings: 5 -Slice Logic Utilization: - Number of Slice Registers: 8,674 out of 301,440 2% - Number used as Flip Flops: 8,668 - Number used as Latches: 6 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 0 - Number of Slice LUTs: 10,811 out of 150,720 7% - Number used as logic: 9,711 out of 150,720 6% - Number using O6 output only: 7,574 - Number using O5 output only: 502 - Number using O5 and O6: 1,635 - Number used as ROM: 0 - Number used as Memory: 792 out of 58,400 1% - Number used as Dual Port RAM: 0 - Number used as Single Port RAM: 4 - Number using O6 output only: 0 - Number using O5 output only: 0 - Number using O5 and O6: 4 - Number used as Shift Register: 788 - Number using O6 output only: 560 - Number using O5 output only: 0 - Number using O5 and O6: 228 - Number used exclusively as route-thrus: 308 - Number with same-slice register load: 268 - Number with same-slice carry load: 40 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 5,272 out of 37,680 13% - Number of LUT Flip Flop pairs used: 13,957 - Number with an unused Flip Flop: 6,261 out of 13,957 44% - Number with an unused LUT: 3,146 out of 13,957 22% - Number of fully used LUT-FF pairs: 4,550 out of 13,957 32% - Number of unique control sets: 524 - Number of slice register sites lost - to control set restrictions: 1,574 out of 301,440 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 142 out of 600 23% - Number of LOCed IOBs: 142 out of 142 100% - IOB Master Pads: 1 - IOB Slave Pads: 1 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 109 out of 416 26% - Number using RAMB36E1 only: 109 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 15 out of 832 1% - Number using RAMB18E1 only: 15 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 9 out of 32 28% - Number used as BUFGs: 9 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 0 out of 720 0% - Number of OLOGICE1/OSERDESE1s: 2 out of 720 1% - Number used as OLOGICE1s: 2 - Number used as OSERDESE1s: 0 - Number of BSCANs: 1 out of 4 25% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 4 out of 36 11% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 0 out of 768 0% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 4 out of 18 22% - Number of IODELAYE1s: 68 out of 720 9% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - Number of RPM macros: 48 -Average Fanout of Non-Clock Nets: 3.84 - -Peak Memory Usage: 1474 MB -Total REAL time to MAP completion: 3 mins 48 secs -Total CPU time to MAP completion (all processors): 3 mins 38 secs - -Mapping completed. -See MAP report file "dbe_bpm_fmc130m_4ch_map.mrp" for details. - -Process "Map" completed successfully - -Started : "Place & Route". -Running par... -Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_fmc130m_4ch_map.ncd dbe_bpm_fmc130m_4ch.ncd dbe_bpm_fmc130m_4ch.pcf - - - -Constraints file: dbe_bpm_fmc130m_4ch.pcf. -Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_fmc130m_4ch" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRODUCTION 1.17 2012-01-07". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 8,674 out of 301,440 2% - Number used as Flip Flops: 8,668 - Number used as Latches: 6 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 0 - Number of Slice LUTs: 10,811 out of 150,720 7% - Number used as logic: 9,711 out of 150,720 6% - Number using O6 output only: 7,574 - Number using O5 output only: 502 - Number using O5 and O6: 1,635 - Number used as ROM: 0 - Number used as Memory: 792 out of 58,400 1% - Number used as Dual Port RAM: 0 - Number used as Single Port RAM: 4 - Number using O6 output only: 0 - Number using O5 output only: 0 - Number using O5 and O6: 4 - Number used as Shift Register: 788 - Number using O6 output only: 560 - Number using O5 output only: 0 - Number using O5 and O6: 228 - Number used exclusively as route-thrus: 308 - Number with same-slice register load: 268 - Number with same-slice carry load: 40 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 5,272 out of 37,680 13% - Number of LUT Flip Flop pairs used: 13,957 - Number with an unused Flip Flop: 6,261 out of 13,957 44% - Number with an unused LUT: 3,146 out of 13,957 22% - Number of fully used LUT-FF pairs: 4,550 out of 13,957 32% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 142 out of 600 23% - Number of LOCed IOBs: 142 out of 142 100% - IOB Master Pads: 1 - IOB Slave Pads: 1 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 109 out of 416 26% - Number using RAMB36E1 only: 109 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 15 out of 832 1% - Number using RAMB18E1 only: 15 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 9 out of 32 28% - Number used as BUFGs: 9 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 0 out of 720 0% - Number of OLOGICE1/OSERDESE1s: 2 out of 720 1% - Number used as OLOGICE1s: 2 - Number used as OSERDESE1s: 0 - Number of BSCANs: 1 out of 4 25% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 4 out of 36 11% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 0 out of 768 0% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 4 out of 18 22% - Number of IODELAYE1s: 68 out of 720 9% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx - Command Line Tools User Guide for information on generating a TSI report. -Starting initial Timing Analysis. REAL time: 24 secs -Finished initial Timing Analysis. REAL time: 25 secs - -WARNING:Par:288 - The signal fmc_adc0_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc1_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc2_of_i_IBUF has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal fmc_adc3_of_i_IBUF has no load. PAR will not attempt to route this signal. -Starting Router - - -Phase 1 : 94357 unrouted; REAL time: 29 secs - -Phase 2 : 72851 unrouted; REAL time: 36 secs - -Phase 3 : 25994 unrouted; REAL time: 1 mins 24 secs - -Phase 4 : 26017 unrouted; (Setup:52202, Hold:9209, Component Switching Limit:0) REAL time: 1 mins 36 secs - -Updating file: dbe_bpm_fmc130m_4ch.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:52258, Hold:8167, Component Switching Limit:0) REAL time: 2 mins 4 secs - -Phase 6 : 0 unrouted; (Setup:52258, Hold:8167, Component Switching Limit:0) REAL time: 2 mins 7 secs - -Phase 7 : 0 unrouted; (Setup:52258, Hold:8167, Component Switching Limit:0) REAL time: 2 mins 42 secs - -Phase 8 : 0 unrouted; (Setup:52258, Hold:8167, Component Switching Limit:0) REAL time: 2 mins 42 secs - -Phase 9 : 0 unrouted; (Setup:52258, Hold:0, Component Switching Limit:0) REAL time: 2 mins 45 secs - -Phase 10 : 0 unrouted; (Setup:52258, Hold:0, Component Switching Limit:0) REAL time: 2 mins 50 secs -Total REAL time to Router completion: 2 mins 51 secs -Total CPU time to Router completion: 2 mins 49 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -| clk_sys |BUFGCTRL_X0Y29| No | 2119 | 0.374 | 1.958 | -+---------------------+--------------+------+------+------------+-------------+ -| mrx_clk_pad_i_BUFGP | BUFGCTRL_X0Y3| No | 106 | 0.225 | 1.832 | -+---------------------+--------------+------+------+------------+-------------+ -| mtx_clk_pad_i_BUFGP | BUFGCTRL_X0Y2| No | 302 | 0.427 | 2.020 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[3]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 23 | 0.229 | 1.079 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[2]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 27 | 0.201 | 1.050 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[1]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 14 | 0.209 | 1.126 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/adc | | | | | | -|_clk_chain_priv[0]_a | | | | | | -| dc_clk_bufio | Regional Clk| No | 27 | 0.205 | 1.054 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<0> | BUFGCTRL_X0Y4| No | 323 | 0.428 | 2.019 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/a | | | | | | -| dc_out[0]_adc_clk | BUFGCTRL_X0Y1| No | 500 | 0.376 | 2.020 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_gen |BUFGCTRL_X0Y31| No | 5 | 0.004 | 1.817 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_200mhz |BUFGCTRL_X0Y28| No | 4 | 0.260 | 1.826 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_chipscope_icon_0 | | | | | | -| /U0/iUPDATE_OUT | Local| | 1 | 0.000 | 1.052 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<13> | Local| | 5 | 0.000 | 0.521 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/gen | | | | | | -|_clock_chains[1].gen | | | | | | -|_clock_chains_check. | | | | | | -|cmp_fmc_adc_clk/gen_ | | | | | | -|with_ref_clk.cmp_mmc | | | | | | -| m_adc_clk_ML_NEW_I1 | Local| | 3 | 0.000 | 2.410 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_96_ML_NEW | | | | | | -| _CLK | Local| | 3 | 0.010 | 0.350 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_I1 | Local| | 3 | 0.000 | 1.541 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_OUT | Local| | 2 | 0.000 | 0.497 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL1<13> | Local| | 5 | 0.000 | 0.624 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL2<13> | Local| | 4 | 0.000 | 0.803 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL3<13> | Local| | 5 | 0.000 | 0.505 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc130m_4ch/ | | | | | | -|cmp_wb_fmc130m_4ch/c | | | | | | -|mp_fmc_adc_iface/gen | | | | | | -|_clock_chains[1].gen | | | | | | -|_clock_chains_check. | | | | | | -|cmp_fmc_adc_clk/gen_ | | | | | | -|with_ref_clk.cmp_mmc | | | | | | -|m_adc_clk_ML_NEW_OUT | | | | | | -| | Local| | 2 | 0.000 | 0.236 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_104_ML_NE | | | | | | -| W_CLK | Local| | 3 | 0.118 | 0.737 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -* The fanout is the number of component pins not the individual BEL loads, -for example SLICE loads not FF loads. - -Timing Score: 52258 (Setup: 52258, Hold: 0, Component Switching Limit: 0) - -WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. - - Review the timing report using Timing Analyzer (In ISE select "Post-Place & - Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. - - Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options - are set in the tools for timing closure. - - Use the Xilinx "SmartXplorer" script to try special combinations of - options known to produce very good results. - - Visit the Xilinx technical support web at http://support.xilinx.com and go to - either "Troubleshoot->Tech Tips->Timing & Constraints" or " - TechXclusives->Timing Closure" for tips and suggestions for meeting timing - in your design. - -Number of Timing Constraints that were not applied: 1 - -Asterisk (*) preceding a constraint indicates it was not met. - This may be due to a setup or hold violation. - ----------------------------------------------------------------------------------------------------------- - Constraint | Check | Worst Case | Best Case | Timing | Timing - | | Slack | Achievable | Errors | Score ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0. | SETUP | -1.066ns| 0.366ns| 16| 16077 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 7.650ns| | 0| 0 - c_adc3_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0. | SETUP | -1.065ns| 0.365ns| 16| 16560 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 7.694ns| | 0| 0 - c_adc2_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0. | SETUP | -1.058ns| 0.358ns| 16| 16341 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 7.627ns| | 0| 0 - c_adc0_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- -* TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0. | SETUP | -0.376ns| -0.324ns| 13| 3280 - 7 ns VALID 7.6 ns BEFORE COMP "fm | HOLD | 5.059ns| | 0| 0 - c_adc1_clk_i" | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_sys_pll_inst_s_clk0 = PERIOD TIMEG | SETUP | 0.008ns| 9.992ns| 0| 0 - RP "cmp_sys_pll_inst_s_clk0" TS_s | HOLD | 0.011ns| | 0| 0 - ys_clk_p_i * 0.5 HIGH 50% INPUT_JITTER 0. | | | | | - 05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_sys_pll_inst_s_clk1 = PERIOD TIMEG | MINPERIOD | 0.239ns| 4.761ns| 0| 0 - RP "cmp_sys_pll_inst_s_clk1" TS_s | | | | | - ys_clk_p_i HIGH 50% INPUT_JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc130m_4ch_cmp_wb_fmc130m_4ch | SETUP | 0.956ns| 7.926ns| 0| 0 - _cmp_fmc_adc_iface_gen_clock_chains_1__ge | HOLD | 0.020ns| | 0| 0 - n_clock_chains_check_cmp_fmc_adc_clk_adc_ | | | | | - clk_mmcm_out = PERIOD TIMEGRP | | | | | - "cmp_xwb_fmc130m_4ch_cmp_wb_fmc130m_ | | | | | - 4ch_cmp_fmc_adc_iface_gen_clock_chains_1_ | | | | | - _gen_clock_chains_check_cmp_fmc_adc_clk_a | | | | | - dc_clk_mmcm_out" TS_fmc_adc1_clk_ | | | | | - i HIGH 50% INPUT_JITTER 0.05 ns | | | | | ----------------------------------------------------------------------------------------------------------- - TS_sys_clk_p_i = PERIOD TIMEGRP "sys_clk_ | SETUP | 2.844ns| 2.156ns| 0| 0 - p_i" 200 MHz HIGH 50% INPUT_JITTER | HOLD | 0.148ns| | 0| 0 - 0.05 ns | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc1_clk_i = PERIOD TIMEGRP "fmc_a | SETUP | 6.228ns| 2.654ns| 0| 0 - dc1_clk_i" 112.583 MHz HIGH 50% I | HOLD | 0.078ns| | 0| 0 - NPUT_JITTER 0.05 ns | MINLOWPULSE | 4.882ns| 4.000ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc0_clk_i = PERIOD TIMEGRP "fmc_a | SETUP | 6.199ns| 2.683ns| 0| 0 - dc0_clk_i" 112.583 MHz HIGH 50% I | HOLD | 0.101ns| | 0| 0 - NPUT_JITTER 0.05 ns | MINPERIOD | 5.550ns| 3.332ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc2_clk_i = PERIOD TIMEGRP "fmc_a | SETUP | 6.507ns| 2.375ns| 0| 0 - dc2_clk_i" 112.583 MHz HIGH 50% I | HOLD | 0.101ns| | 0| 0 - NPUT_JITTER 0.05 ns | MINPERIOD | 5.550ns| 3.332ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TS_fmc_adc3_clk_i = PERIOD TIMEGRP "fmc_a | SETUP | 6.454ns| 2.428ns| 0| 0 - dc3_clk_i" 112.583 MHz HIGH 50% I | HOLD | 0.101ns| | 0| 0 - NPUT_JITTER 0.05 ns | MINPERIOD | 5.550ns| 3.332ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - - -Derived Constraint Report -Review Timing Report for more details on the following derived constraints. -To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" -or "Run Timing Analysis" from Timing Analyzer (timingan). -Derived Constraints for TS_sys_clk_p_i -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_sys_clk_p_i | 5.000ns| 2.800ns| 4.996ns| 0| 0| 165| 2036865| -| TS_cmp_sys_pll_inst_s_clk1 | 5.000ns| 4.761ns| N/A| 0| 0| 0| 0| -| TS_cmp_sys_pll_inst_s_clk0 | 10.000ns| 9.992ns| N/A| 0| 0| 2036865| 0| -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_fmc_adc1_clk_i -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_fmc_adc1_clk_i | 8.882ns| 4.000ns| 7.926ns| 0| 0| 122| 11285| -| TS_cmp_xwb_fmc130m_4ch_cmp_wb_| 8.882ns| 7.926ns| N/A| 0| 0| 11285| 0| -| fmc130m_4ch_cmp_fmc_adc_iface_| | | | | | | | -| gen_clock_chains_1__gen_clock_| | | | | | | | -| chains_check_cmp_fmc_adc_clk_a| | | | | | | | -| dc_clk_mmcm_out | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -4 constraints not met. - - -Generating Pad Report. - -All signals are completely routed. - -WARNING:Par:283 - There are 4 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - -Total REAL time to PAR completion: 3 mins 1 secs -Total CPU time to PAR completion: 2 mins 59 secs - -Peak Memory Usage: 1478 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - 61 errors found. - -Number of error messages: 0 -Number of warning messages: 7 -Number of info messages: 1 - -Writing design to file dbe_bpm_fmc130m_4ch.ncd - - - -PAR done! - -Process "Place & Route" completed successfully - -Started : "Generate Post-Place & Route Static Timing". -Running trce... -Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_fmc130m_4ch.twx dbe_bpm_fmc130m_4ch.ncd -o dbe_bpm_fmc130m_4ch.twr dbe_bpm_fmc130m_4ch.pcf -Loading device for application Rf_Device from file '6vlx240t.nph' in environment -/opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_fmc130m_4ch" is an NCD, version 3.2, device xc6vlx240t, package -ff1156, speed -1 - -Analysis completed Thu Aug 29 14:37:04 2013 --------------------------------------------------------------------------------- - -Generating Report ... - -Number of warnings: 0 -Total time: 36 secs - -Process "Generate Post-Place & Route Static Timing" completed successfully - -Started : "Generate Programming File". -Running bitgen... -Command Line: bitgen -intstyle ise -f dbe_bpm_fmc130m_4ch.ut dbe_bpm_fmc130m_4ch.ncd -INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most - commonly, bitgen has determined and will use a specific value instead of the - generic command-line value of "Auto". Alternately, this message appears if - the same option is specified multiple times on the command-line. In this - case, the option listed last will be used. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL2<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL3<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. - -Process "Generate Programming File" completed successfully diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/Manifest.py b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/Manifest.py deleted file mode 100755 index ee77868c..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/Manifest.py +++ /dev/null @@ -1,13 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_fmc130m_4ch_pcie" -syn_project = "dbe_bpm_fmc130m_4ch_pcie.xise" -syn_tool = "ise" - -modules = { "local" : - ["../../../top/ml_605/dbe_bpm_fmc130m_4ch_pcie"] - }; diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/build_bitstream_local.sh b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/build_bitstream_local.sh deleted file mode 100755 index 58f80bf1..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/build_bitstream_local.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash - -COMMAND="(hdlmake-devel; make clean; time make; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/build_bitstream_remote.sh b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/build_bitstream_remote.sh deleted file mode 100755 index 30d0f3f9..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/build_bitstream_remote.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash - -COMMAND="(hdlmake-devel; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xise b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xise deleted file mode 100644 index ee46b075..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xise +++ /dev/null @@ -1,1714 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/make_output b/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/make_output deleted file mode 100644 index 18c0566b..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/make_output +++ /dev/null @@ -1,23946 +0,0 @@ -rm -f *.b dbe_bpm_fmc130m_4ch_pcie_summary.html *.tcl dbe_bpm_fmc130m_4ch_pcie.bld dbe_bpm_fmc130m_4ch_pcie.cmd_log *.drc dbe_bpm_fmc130m_4ch_pcie.lso *.ncd dbe_bpm_fmc130m_4ch_pcie.ngc dbe_bpm_fmc130m_4ch_pcie.ngd dbe_bpm_fmc130m_4ch_pcie.ngr dbe_bpm_fmc130m_4ch_pcie.pad dbe_bpm_fmc130m_4ch_pcie.par dbe_bpm_fmc130m_4ch_pcie.pcf dbe_bpm_fmc130m_4ch_pcie.prj dbe_bpm_fmc130m_4ch_pcie.ptwx dbe_bpm_fmc130m_4ch_pcie.stx dbe_bpm_fmc130m_4ch_pcie.syr dbe_bpm_fmc130m_4ch_pcie.twr dbe_bpm_fmc130m_4ch_pcie.twx dbe_bpm_fmc130m_4ch_pcie.gise dbe_bpm_fmc130m_4ch_pcie.unroutes dbe_bpm_fmc130m_4ch_pcie.ut dbe_bpm_fmc130m_4ch_pcie.xpi dbe_bpm_fmc130m_4ch_pcie.xst dbe_bpm_fmc130m_4ch_pcie_bitgen.xwbt dbe_bpm_fmc130m_4ch_pcie_envsettings.html dbe_bpm_fmc130m_4ch_pcie_guide.ncd dbe_bpm_fmc130m_4ch_pcie_map.map dbe_bpm_fmc130m_4ch_pcie_map.mrp dbe_bpm_fmc130m_4ch_pcie_map.ncd dbe_bpm_fmc130m_4ch_pcie_map.ngm dbe_bpm_fmc130m_4ch_pcie_map.xrpt dbe_bpm_fmc130m_4ch_pcie_ngdbuild.xrpt dbe_bpm_fmc130m_4ch_pcie_pad.csv dbe_bpm_fmc130m_4ch_pcie_pad.txt dbe_bpm_fmc130m_4ch_pcie_par.xrpt dbe_bpm_fmc130m_4ch_pcie_summary.xml dbe_bpm_fmc130m_4ch_pcie_usage.xml dbe_bpm_fmc130m_4ch_pcie_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl -rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo -echo "project open dbe_bpm_fmc130m_4ch_pcie.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/ml605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.syr" -Reading design: dbe_bpm_fmc130m_4ch_pcie.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/ip_cores/dds_adc_input.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 94. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_cop.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" included at line 64. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 65. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 165. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 166. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 87. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 74. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" into library work -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 317: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 318: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 322: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 323: Macro is redefined. -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 67. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 42. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 80. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 112. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xilinx_dist_ram_16x32.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 74. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 83. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 240. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 241. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 82. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" into library work -Parsing module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 133: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 159: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_gtx_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_drp_chanalign_fix_3752_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_tx_sync_rate_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_top.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_clocking_v6.v" into library work -Parsing module . -INFO:HDLCompiler:693 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_rx_valid_filter_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_pipeline.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_lane_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_misc_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_upconfig_fix_3451_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_pipeline.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_null_gen.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_thrtl_ctl.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_brams_v6.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_reset_delay_v6.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/v6abb64Package_efifo_elink.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/pcie/top_ml605.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_a7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_k7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_private_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_6_port/chipscope_icon_6_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/data_checker.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDR_Blinker.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_Calculate.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/FF_tagram64x36.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Registers.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/RxIn_Delays.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/bram_DDRs_Control_Loopback.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_Transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_mem.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_fifo_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/dsp_cores_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_u16x16_DSP.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_16x10_DSP.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/position_calc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_core_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/xwb_position_calc_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wb_position_calc_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_cdc_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_counters_single.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/position_calc_counters.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_position_calc/wbgen/wb_pos_calc_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wb_bpm_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/xwb_bpm_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/wbgen/wb_bpm_swap_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_239e4f614ba09ab1.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_26986301a9f671cd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_8b0747970e52f130.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_0f9a053cdbbdc75e.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_59fbd17f7e62a7fe.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cmpy_v5_0_fc1d91881e8e8ae6.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cntr_11_0_3166d4cc5b09c744.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/crdc_v5_0_19fb63dead3076ad.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dds_cmplr_v5_0_757016b8a434f5d8.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_e1825854b6ed410d.vhd" into library work -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_f359164f94f65852.vhd" into library work -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_0c61ac74cf3e5cc7.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_51c8a9a7f4af2b84.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_95e3c24666ebc2c9.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_d5f4b3c608d95215.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_ef8269b30b0e0deb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/mult_11_2_6d8e463c710483da.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/nonleaf_results.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/perl_results.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/un_cross_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/swap_cnt_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/rf_ch_swap.vhd" into library work -Parsing entity . -WARNING:HDLCompiler:685 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/rf_ch_swap.vhd" Line 34: Overwriting existing primary unit rf_ch_swap -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/inv_ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/delay_inv_ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/inv_chs_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/dsp-cores/hdl/modules/wb_un_cross/cross_uncross_core/dyn_mult_2chs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_mach.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_mach.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_merge_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_dec_fix.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr2_ddr3_chipscope.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/infrastructure.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/iodelay_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/clk_ibuf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rddata_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdctrl_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_ck_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/circ_buffer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_read.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_clock_io.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_wr_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" Line 756: Assignment to clk_200mhz_rst ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "Wishbone slave device #1 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." -Warning: "Wishbone slave device #0 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x3e0000]" -Note: "Mapping slave #1[0x100000/0x3e0000]" -Note: "Mapping slave #2[0x200000/0x3f0000]" -Note: "Mapping slave #3[0x304000/0x3fffe0]" -Note: "Mapping slave #4[0x305000/0x3ffe00]" -Note: "Mapping slave #5[0x306000/0x3fff00]" -Note: "Mapping slave #6[0x307000/0x3fff00]" -Note: "Mapping slave #7[0x310000/0x3ff000]" -Note: "Mapping slave #8[0x320000/0x3ff000]" -Note: "Mapping slave #9[0x330000/0x3ff000]" -Note: "Mapping slave #10[0x300000/0x3ffc00]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" Line 829: Assignment to cfg_mgmt_byte_en ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" Line 830: Assignment to cfg_mgmt_wr_en ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" Line 831: Assignment to cfg_mgmt_rd_en ignored, since the identifier is never used -Going to verilog side to elaborate module pcie_core - -Elaborating module -. - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_thrtl_ctl.v" Line 650: Assignment to reg_tlast ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" Line 788: Assignment to trn_tecrc_gen ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" Line 874: Assignment to block_clk ignored, since the identifier is never used - -Elaborating module -. - -Elaborating module -. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module -. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 475: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 489: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 490: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 498: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 499: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 565: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 566: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 591: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 608: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 609: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 614: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 615: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 621: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. - -Elaborating module . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 - -Elaborating module . -WARNING:HDLCompiler:1016 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" Line 1140: Assignment to rx_func_level_reset_n ignored, since the identifier is never used -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/RxIn_Delays.vhd" Line 808. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" Line 284. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" Line 119: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" Line 582. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" Line 343. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 493: Assignment to m_axis_rx_tvalid_r4 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 525: Assignment to m_axis_rx_tdata_little ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 527: Assignment to m_axis_rx_tdata_little_r2 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 528: Assignment to m_axis_rx_tdata_little_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 540: Assignment to dsp_tag_on_fifo_r4p ignored, since the identifier is never used -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 765. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" Line 1257: Assignment to tram_douta_r2 ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_Calculate.vhd" Line 572. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 369. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 751. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 791. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd" Line 895. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" Line 289: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" Line 664. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" Line 698: Assignment to ustlp_nempty_r1 ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" Line 318: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" Line 260. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" Line 94: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd" Line 97: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" Line 480. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" Line 712: Assignment to regs_write_mbuf_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" Line 795: Assignment to wb_fifo_rden_mask_rise_r2 ignored, since the identifier is never used -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" Line 310: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" Line 176. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" Line 269: prior_init_value should be on the sensitivity list of the process -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" Line 607: Assignment to maddr_ustlp ignored, since the identifier is never used -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd" Line 1156. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd" Line 300. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 258: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 101: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 116: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 874. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 176: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 241: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" Line 248: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" Line 70: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" Line 115: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd" Line 721: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd" Line 766: Assignment to wire39 ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" Line 279: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" Line 299: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 245: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 246: Range is empty (null range) -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 87: remains a black-box since it has no binding entity. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 434. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 451: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 505: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" Line 238: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" Line 170: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" Line 194: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd" Line 196: Range is empty (null range) - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 403: Assignment to rank_busy_ns_tmp ignored, since the identifier is never used -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 149: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 150: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd" Line 155: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 366: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 367: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 368: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd" Line 463: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 367: Range is empty (null range) -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 637: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 639: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd" Line 406: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd" Line 635: Assignment to tsta ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 571: Assignment to slot_0_read ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 580: Assignment to slot_0_dynamic_odt ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 581: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 234: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 265: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd" Line 304: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" Line 123: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" Line 237: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 347: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 348: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 357: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 359: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 368: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 377: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 303: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 1289: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 1305: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 239: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 809: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 892: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 901: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1249: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1527: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1546: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 1697: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2383: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2389: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2395: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2401: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 2447: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 3140: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd" Line 3296. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 169: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 160: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 447: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd" Line 457: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd" Line 126: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd" Line 130. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd" Line 162. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 116: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 172: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 208: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd" Line 272. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 131: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 284: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 313: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd" Line 377. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd" Line 231: Assignment to dqs_oe_r ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd" Line 365: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 212: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 242: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 303: Assignment to wrdata_en_r7 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 401: Comparison between arrays of unequal length always returns FALSE. -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 719. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 1370: Assignment to wrlvl_done_r3 ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 1541: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd" Line 1589: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 446: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 590: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 682: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 830: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 850: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd" Line 718: Assignment to wl_state_r1 ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" Line 395. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" Line 191: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd" Line 194: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 641. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 688: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 719: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1077: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1133: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1173: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1346: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1568: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1306: Assignment to found_two_edge_r ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 1963: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2093: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2124: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2196: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2225: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2290: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2325: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2340: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd" Line 2393: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 275: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 283: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 352: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 353: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 354: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 355: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 358: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 359: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 363: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 364: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 368: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 121: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 133: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 143: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 238: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd" Line 271: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 399: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 360: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 365: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 419: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd" Line 439: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" Line 547: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" Line 286: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" Line 352: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd" Line 179: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" Line 678: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 779: Assignment to dbg_ocb_mon_off ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 786: Assignment to dbg_pd_msb_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 787: Assignment to dbg_sel_idel_cpt ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 788: Assignment to dbg_sel_idel_rsync ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 789: Assignment to dbg_pd_byte_sel ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 791: Assignment to modify_enable_sel ignored, since the identifier is never used -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 794: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 459: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" Line 460: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" Line 926: Assignment to wb_ma_pcie_rstn ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module rs232_syscon_top_1_0 - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 322: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 357: Result of 17-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 363: Result of 17-bit expression is truncated to fit in 16-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 656: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 668: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" Line 539: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 472: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 524: Result of 6-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1066: Result of 32-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1067: Result of 6-bit expression is truncated to fit in 5-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1096: Result of 32-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1168: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1176: Result of 5-bit expression is truncated to fit in 4-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" Line 1186: Result of 17-bit expression is truncated to fit in 16-bit target. -WARNING:HDLCompiler:552 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" Line 30: Input port master_adr_i[31] is not connected on this instance -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 157: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 175: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 134: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 71: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 73: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module ethmac - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 883: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used -"/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted - -Elaborating module . -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "generic_sync_fifo[xilinx]: using FIFO18E1 primitive [dw=32]." -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 292: Using initial value (('0','0',"00000000"),('0','0',"00000000"),('0','0',"00000000"),('0','0',"00000000")) for adc_in_dummy since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 317: Using initial value ("UUUU","UUUU","UUUU","UUUU") for adc_cs_dly_in since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 457: Using initial value '0' for dummy_bit_low since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 458: Using initial value "0000000000000000" for dummy_adc_vector_low since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xf00]" -Note: "Mapping slave #1[0x100/0xf00]" -Note: "Mapping slave #2[0x200/0xf00]" -Note: "Mapping slave #3[0x300/0xf00]" -Note: "Mapping slave #4[0x400/0xf00]" -Note: "Mapping slave #5[0x800/0xe00]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 114: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 115: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 116: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 117: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" Line 118: Assignment to allzeros ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 826: Assignment to adc_rst ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "[ map vector(0) = -1 ]" -Note: "[ map vector(1) = -1 ]" -Note: "[ map vector(2) = -1 ]" -Note: "[ map vector(3) = -1 ]" -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 615: Range is empty (null range) -Note: "[ intercon(0) = 0 ]" -Note: "[ intercon(1) = 1 ]" -Note: "[ intercon(2) = 2 ]" -Note: "[ intercon(3) = 3 ]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" Line 164: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" Line 207: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "generic_sync_fifo[xilinx]: using FIFO18E1 primitive [dw=16]." -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" Line 76: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd" Line 77: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" Line 90: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_bidir_top - -Elaborating module . - -Elaborating module . - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" Line 65: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" Line 25: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" Line 314: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x700]" -Note: "Mapping slave #1[0x100/0x700]" -Note: "Mapping slave #2[0x200/0x700]" -Note: "Mapping slave #3[0x300/0x7f0]" -Note: "Mapping slave #4[0x400/0x600]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" Line 65: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 167: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 168: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 169: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 170: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd" Line 171: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd" Line 472. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd" Line 546. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 175: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 198: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" Line 217: Assignment to lmt_shots_nb ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -Note: "generic_async_fifo[xilinx]: using inferred BRAM-based FIFO." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" Line 656: Assignment to lmt_valid ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" Line 364: Assignment to valid_trans_app_d0 ignored, since the identifier is never used -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd" Line 619: Range is empty (null range) -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd" Line 621: Range is empty (null range) - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" Line 582: Net does not have a driver. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd". - g_pcieLanes = 4 - pcieLanes = 4 - DDR_DQ_WIDTH = 64 - DDR_PAYLOAD_WIDTH = 256 - DDR_DQS_WIDTH = 8 - DDR_DM_WIDTH = 8 - DDR_ROW_WIDTH = 14 - DDR_BANK_WIDTH = 3 - DDR_CK_WIDTH = 1 - DDR_CKE_WIDTH = 1 - DDR_ODT_WIDTH = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 716: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 760: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 760: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 835: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 835: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 835: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 928: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1015: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1057: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1057: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1057: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1057: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1057: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1057: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1079: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1141: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1141: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1196: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd" line 1444: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 16-bit adder for signal > created at line 1241. - Found 1-bit tristate buffer for signal created at line 1132 - Summary: - inferred 16 Adder/Subtractor(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 2 - g_logdelay = 10 - g_syncdepth = 3 - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 3-bit register for signal >. - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Set property "shreg_extract = no" for signal . - Set property "shreg_extract = no" for signal . - Set property "shreg_extract = no" for signal . - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 10 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001100110000000000000000000000000000000000000000000000000000000000110011000011111111111100010000000000000000000000000000000000000000000000010010000101010100010100011001101000001010110100000000000000000000000000000001001000000001001100010000000100010100110001001110010011000101001101011111010000100101000001001101010111110100000101000011010100010101111101000011010011110101001001000101001000000010000000000001","000000000000000000000000000000000000000000110010000001000000000000000000000000000000000000000000000000000011001000000000000000000000000000000000000000000000000000000000001100100000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000000000000000000000011000100001000000000000000000000000000000000000000000000000000001100010000000000000000000000000000000000000000000000000000000000110001000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000011000001110000000000000000000000000000000000000000000000000000001100000111000011111111000000000000000000000000000000000000000000000000000001100101000101101000001000000010101100100010000000000000000000000000000000010010000000010010000010010001001001000111010100110100100101011111010001010101010001001000010001010101001001000010010011110100111001000101010111110100001101000110010001110010000000100 -00000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000001100000110000000000000000000000000000000000000000000000000000000110000011000001111111100010000000000000000000000000000000000000000000000010010000101010010111111111001101000101000111000000000000000000000000000000001001000000001001100000111000000010100010101010100010010000100110101000001010000110101111101000001010001000100000101010000010101000100010101010010001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000000000000011000001010000000000000000000000000000000000000000000000000000001100000101000111111111000100000000000000000000000000000100111000101100000001011110010111111000110011111110101100010110000000000000000000000000000000010010000000010010000100100001001001001111010000110100111101010010010001010101001101011111010001010101010001001000010011010100000101000011001000000010000000100000001000000010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001100000100000000000000000000000000000000000000000000000000000000110000010000000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001 -00000001000000010000000000001") - g_sdb_addr = "00000000001100000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001100110000000000000000000000000000000000000000000000000000000000110011000011111111111100010000000000000000000000000000000000000000000000010010000101010100010100011001101000001010110100000000000000000000000000000001001000000001001100010000000100010100110001001110010011000101001101011111010000100101000001001101010111110100000101000011010100010101111101000011010011110101001001000101001000000010000000000001","000000000000000000000000000000000000000000110010000001000000000000000000000000000000000000000000000000000011001000000000000000000000000000000000000000000000000000000000001100100000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000000000000000000000011000100001000000000000000000000000000000000000000000000000000001100010000000000000000000000000000000000000000000000000000000000110001000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000000000000011000001110000000000000000000000000000000000000000000000000000001100000111000011111111000000000000000000000000000000000000000000000000000001100101000101101000001000000010101100100010000000000000000000000000000000010010000000010010000010010001001001000111010100110100100101011111010001010101010001001000010001010101001001000010010011110100111001000101010111110100001101000110010001110010000000100 -00000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000000000001100000110000000000000000000000000000000000000000000000000000000110000011000001111111100010000000000000000000000000000000000000000000000010010000101010010111111111001101000101000111000000000000000000000000000000001001000000001001100000111000000010100010101010100010010000100110101000001010000110101111101000001010001000100000101010000010101000100010101010010001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000000000000011000001010000000000000000000000000000000000000000000000000000001100000101000111111111000100000000000000000000000000000100111000101100000001011110010111111000110011111110101100010110000000000000000000000000000000010010000000010010000100100001001001001111010000110100111101010010010001010101001101011111010001010101010001001000010011010100000101000011001000000010000000100000001000000010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000001100000100000000000000000000000000000000000000000000000000000000110000010000000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001 -00000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000001111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value. - Found 256x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 11 - g_registered = true - g_address = ("00000000001100000000000000000000","00000000001100110000000000000000","00000000001100100000000000000000","00000000001100010000000000000000","00000000001100000111000000000000","00000000001100000110000000000000","00000000001100000101000000000000","00000000001100000100000000000000","00000000001000000000000000000000","00000000000100000000000000000000","00000000000000000000000000000000") - g_mask = ("00000000001111111111110000000000","00000000001111111111000000000000","00000000001111111111000000000000","00000000001111111111000000000000","00000000001111111111111100000000","00000000001111111111111100000000","00000000001111111111111000000000","00000000001111111111111111100000","00000000001111110000000000000000","00000000001111100000000000000000","00000000001111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 12-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 97 D-type flip-flop(s). - inferred 96 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd". - SIMULATION = "FALSE" - pcieLanes = 4 - PL_FAST_TRAIN = "FALSE" - PIPE_SIM_MODE = "FALSE" - DDR_DQ_WIDTH = 64 - DDR_PAYLOAD_WIDTH = 256 - DDR_DQS_WIDTH = 8 - DDR_DM_WIDTH = 8 - DDR_ROW_WIDTH = 14 - DDR_BANK_WIDTH = 3 - DDR_CK_WIDTH = 1 - DDR_CKE_WIDTH = 1 - DDR_ODT_WIDTH = 1 - SIM_BYPASS_INIT_CAL = "OFF" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 866: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1007: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/bpm_pcie_ml605.vhd" line 1261: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v". - ALLOW_X8_GEN2 = "FALSE" - BAR0 = -1012 - BAR1 = -1 - BAR2 = -1048564 - BAR3 = -1 - BAR4 = -524276 - BAR5 = -1 - CARDBUS_CIS_POINTER = 0 - CLASS_CODE = 327680 - CMD_INTX_IMPLEMENTED = "TRUE" - CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE" - CPL_TIMEOUT_RANGES_SUPPORTED = 2 - DEV_CAP_ENDPOINT_L0S_LATENCY = 0 - DEV_CAP_ENDPOINT_L1_LATENCY = 7 - DEV_CAP_EXT_TAG_SUPPORTED = "FALSE" - DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2 - DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0 - DEVICE_ID = 24596 - DISABLE_LANE_REVERSAL = "TRUE" - DISABLE_SCRAMBLING = "FALSE" - DSN_BASE_PTR = 256 - DSN_CAP_NEXTPTR = 0 - DSN_CAP_ON = "TRUE" - ENABLE_MSG_ROUTE = 0 - ENABLE_RX_TD_ECRC_TRIM = "TRUE" - EXPANSION_ROM = 0 - EXT_CFG_CAP_PTR = 63 - EXT_CFG_XP_CAP_PTR = 1023 - HEADER_TYPE = 0 - INTERRUPT_PIN = 1 - LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE" - LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE" - LINK_CAP_MAX_LINK_SPEED = 1 - LINK_CAP_MAX_LINK_WIDTH = 4 - LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE" - LINK_CTRL2_DEEMPHASIS = "FALSE" - LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE" - LINK_CTRL2_TARGET_LINK_SPEED = 0 - LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE" - LL_ACK_TIMEOUT = 0 - LL_ACK_TIMEOUT_EN = "FALSE" - LL_ACK_TIMEOUT_FUNC = 0 - LL_REPLAY_TIMEOUT = 38 - LL_REPLAY_TIMEOUT_EN = "TRUE" - LL_REPLAY_TIMEOUT_FUNC = 1 - LTSSM_MAX_LINK_WIDTH = 4 - MSI_CAP_MULTIMSGCAP = 0 - MSI_CAP_MULTIMSG_EXTENSION = 0 - MSI_CAP_ON = "TRUE" - MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE" - MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE" - MSIX_CAP_ON = "FALSE" - MSIX_CAP_PBA_BIR = 0 - MSIX_CAP_PBA_OFFSET = 0 - MSIX_CAP_TABLE_BIR = 0 - MSIX_CAP_TABLE_OFFSET = 0 - MSIX_CAP_TABLE_SIZE = 0 - PCIE_CAP_DEVICE_PORT_TYPE = 0 - PCIE_CAP_INT_MSG_NUM = 1 - PCIE_CAP_NEXTPTR = 0 - PCIE_DRP_ENABLE = "FALSE" - PIPE_PIPELINE_STAGES = 0 - PM_CAP_DSI = "FALSE" - PM_CAP_D1SUPPORT = "FALSE" - PM_CAP_D2SUPPORT = "FALSE" - PM_CAP_NEXTPTR = 72 - PM_CAP_PMESUPPORT = 15 - PM_CSR_NOSOFTRST = "TRUE" - PM_DATA_SCALE0 = 0 - PM_DATA_SCALE1 = 0 - PM_DATA_SCALE2 = 0 - PM_DATA_SCALE3 = 0 - PM_DATA_SCALE4 = 0 - PM_DATA_SCALE5 = 0 - PM_DATA_SCALE6 = 0 - PM_DATA_SCALE7 = 0 - PM_DATA0 = 0 - PM_DATA1 = 0 - PM_DATA2 = 0 - PM_DATA3 = 0 - PM_DATA4 = 0 - PM_DATA5 = 0 - PM_DATA6 = 0 - PM_DATA7 = 0 - REF_CLK_FREQ = 0 - REVISION_ID = 0 - SPARE_BIT0 = 0 - SUBSYSTEM_ID = 7 - SUBSYSTEM_VENDOR_ID = 4334 - TL_RX_RAM_RADDR_LATENCY = 1 - TL_RX_RAM_RDATA_LATENCY = 3 - TL_RX_RAM_WRITE_LATENCY = 1 - TL_TX_RAM_RADDR_LATENCY = 1 - TL_TX_RAM_RDATA_LATENCY = 3 - TL_TX_RAM_WRITE_LATENCY = 1 - UPCONFIG_CAPABLE = "TRUE" - USER_CLK_FREQ = 2 - VC_BASE_PTR = 0 - VC_CAP_NEXTPTR = 0 - VC_CAP_ON = "FALSE" - VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE" - VC0_CPL_INFINITE = "TRUE" - VC0_RX_RAM_LIMIT = 2047 - VC0_TOTAL_CREDITS_CD = 308 - VC0_TOTAL_CREDITS_CH = 36 - VC0_TOTAL_CREDITS_NPH = 12 - VC0_TOTAL_CREDITS_PD = 308 - VC0_TOTAL_CREDITS_PH = 32 - VC0_TX_LASTPACKET = 29 - VENDOR_ID = 4334 - VSEC_BASE_PTR = 0 - VSEC_CAP_NEXTPTR = 0 - VSEC_CAP_ON = "FALSE" - AER_BASE_PTR = 296 - AER_CAP_ECRC_CHECK_CAPABLE = "FALSE" - AER_CAP_ECRC_GEN_CAPABLE = "FALSE" - AER_CAP_ID = 1 - AER_CAP_INT_MSG_NUM_MSI = 10 - AER_CAP_INT_MSG_NUM_MSIX = 21 - AER_CAP_NEXTPTR = 352 - AER_CAP_ON = "FALSE" - AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE" - AER_CAP_VERSION = 1 - CAPABILITIES_PTR = 64 - CRM_MODULE_RSTS = 0 - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE" - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE" - DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE" - DEV_CAP_ROLE_BASED_ERROR = "TRUE" - DEV_CAP_RSVD_14_12 = 0 - DEV_CAP_RSVD_17_16 = 0 - DEV_CAP_RSVD_31_29 = 0 - DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE" - DISABLE_ASPM_L1_TIMER = "FALSE" - DISABLE_BAR_FILTERING = "FALSE" - DISABLE_ID_CHECK = "FALSE" - DISABLE_RX_TC_FILTER = "FALSE" - DNSTREAM_LINK_NUM = 0 - DSN_CAP_ID = 3 - DSN_CAP_VERSION = 1 - ENTER_RVRY_EI_L0 = "TRUE" - INFER_EI = 12 - IS_SWITCH = "FALSE" - LAST_CONFIG_DWORD = 1023 - LINK_CAP_ASPM_SUPPORT = 1 - LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE" - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_RSVD_23_22 = 0 - LINK_CONTROL_RCB = 0 - MSI_BASE_PTR = 72 - MSI_CAP_ID = 5 - MSI_CAP_NEXTPTR = 96 - MSIX_BASE_PTR = 156 - MSIX_CAP_ID = 17 - MSIX_CAP_NEXTPTR = 0 - N_FTS_COMCLK_GEN1 = 255 - N_FTS_COMCLK_GEN2 = 254 - N_FTS_GEN1 = 255 - N_FTS_GEN2 = 255 - PCIE_BASE_PTR = 96 - PCIE_CAP_CAPABILITY_ID = 16 - PCIE_CAP_CAPABILITY_VERSION = 2 - PCIE_CAP_ON = "TRUE" - PCIE_CAP_RSVD_15_14 = 0 - PCIE_CAP_SLOT_IMPLEMENTED = "FALSE" - PCIE_REVISION = 2 - PGL0_LANE = 0 - PGL1_LANE = 1 - PGL2_LANE = 2 - PGL3_LANE = 3 - PGL4_LANE = 4 - PGL5_LANE = 5 - PGL6_LANE = 6 - PGL7_LANE = 7 - PL_AUTO_CONFIG = 0 - PL_FAST_TRAIN = "FALSE" - PM_BASE_PTR = 64 - PM_CAP_AUXCURRENT = 0 - PM_CAP_ID = 1 - PM_CAP_ON = "TRUE" - PM_CAP_PME_CLOCK = "FALSE" - PM_CAP_RSVD_04 = 0 - PM_CAP_VERSION = 3 - PM_CSR_BPCCEN = "FALSE" - PM_CSR_B2B3 = "FALSE" - RECRC_CHK = 0 - RECRC_CHK_TRIM = "FALSE" - ROOT_CAP_CRS_SW_VISIBILITY = "FALSE" - SELECT_DLL_IF = "FALSE" - SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE" - SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE" - SLOT_CAP_HOTPLUG_CAPABLE = "FALSE" - SLOT_CAP_HOTPLUG_SURPRISE = "FALSE" - SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE" - SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE" - SLOT_CAP_PHYSICAL_SLOT_NUM = 0 - SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE" - SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0 - SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 0 - SPARE_BIT1 = 0 - SPARE_BIT2 = 0 - SPARE_BIT3 = 0 - SPARE_BIT4 = 0 - SPARE_BIT5 = 0 - SPARE_BIT6 = 0 - SPARE_BIT7 = 0 - SPARE_BIT8 = 0 - SPARE_BYTE0 = 0 - SPARE_BYTE1 = 0 - SPARE_BYTE2 = 0 - SPARE_BYTE3 = 0 - SPARE_WORD0 = 0 - SPARE_WORD1 = 0 - SPARE_WORD2 = 0 - SPARE_WORD3 = 0 - TL_RBYPASS = "FALSE" - TL_TFC_DISABLE = "FALSE" - TL_TX_CHECKS_DISABLE = "FALSE" - EXIT_LOOPBACK_ON_EI = "TRUE" - UPSTREAM_FACING = "TRUE" - UR_INV_REQ = "TRUE" - VC_CAP_ID = 2 - VC_CAP_VERSION = 1 - VSEC_CAP_HDR_ID = 4660 - VSEC_CAP_HDR_LENGTH = 24 - VSEC_CAP_HDR_REVISION = 1 - VSEC_CAP_ID = 11 - VSEC_CAP_IS_LINK_VISIBLE = "TRUE" - VSEC_CAP_VERSION = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 744: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 744: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 864: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_core.v" line 1125: Output port of the instance is unconnected or connected to loadless signal. - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_top.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_pipeline.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 22-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Summary: - inferred 180 D-type flip-flop(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_null_gen.v". - C_DATA_WIDTH = 64 - TCQ = 1 - KEEP_WIDTH = 8 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 12-bit register for signal . - Found 1-bit register for signal . - Found 12-bit subtractor for signal created at line 238. - Found 12-bit adder for signal created at line 233. - Found 12-bit comparator lessequal for signal created at line 239 - Found 12-bit comparator lessequal for signal created at line 374 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 13 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_pipeline.v". - C_DATA_WIDTH = 64 - C_PM_PRIORITY = "FALSE" - TCQ = 1 - REM_WIDTH = 1 - KEEP_WIDTH = 8 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 75 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_thrtl_ctl.v". - C_DATA_WIDTH = 64 - C_FAMILY = "V6" - C_ROOT_PORT = "FALSE" - TCQ = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit subtractor for signal created at line 302. - Found 2-bit subtractor for signal created at line 352. - Found 6-bit comparator lessequal for signal created at line 237 - Found 6-bit comparator lessequal for signal created at line 270 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_reset_delay_v6.v". - PL_FAST_TRAIN = "FALSE" - REF_CLK_FREQ = 0 - TCQ = 1 - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 99. - Found 8-bit adder for signal created at line 100. - Found 8-bit adder for signal created at line 101. - Summary: - inferred 3 Adder/Subtractor(s). - inferred 24 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_clocking_v6.v". - IS_ENDPOINT = "TRUE" - CAP_LINK_WIDTH = 4 - CAP_LINK_SPEED = 1 - REF_CLK_FREQ = 0 - USER_CLK_FREQ = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 2-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v". - TCQ = 1 - REF_CLK_FREQ = 0 - PIPE_PIPELINE_STAGES = 0 - AER_BASE_PTR = 296 - AER_CAP_ECRC_CHECK_CAPABLE = "FALSE" - AER_CAP_ECRC_GEN_CAPABLE = "FALSE" - AER_CAP_ID = 1 - AER_CAP_INT_MSG_NUM_MSI = 10 - AER_CAP_INT_MSG_NUM_MSIX = 21 - AER_CAP_NEXTPTR = 352 - AER_CAP_ON = "FALSE" - AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE" - AER_CAP_VERSION = 1 - ALLOW_X8_GEN2 = "FALSE" - BAR0 = -1012 - BAR1 = -1 - BAR2 = -1048564 - BAR3 = -1 - BAR4 = -524276 - BAR5 = -1 - CAPABILITIES_PTR = 64 - CARDBUS_CIS_POINTER = 0 - CLASS_CODE = 327680 - CMD_INTX_IMPLEMENTED = "TRUE" - CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE" - CPL_TIMEOUT_RANGES_SUPPORTED = 2 - CRM_MODULE_RSTS = 0 - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE" - DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE" - DEV_CAP_ENDPOINT_L0S_LATENCY = 0 - DEV_CAP_ENDPOINT_L1_LATENCY = 7 - DEV_CAP_EXT_TAG_SUPPORTED = "FALSE" - DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE" - DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2 - DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0 - DEV_CAP_ROLE_BASED_ERROR = "TRUE" - DEV_CAP_RSVD_14_12 = 0 - DEV_CAP_RSVD_17_16 = 0 - DEV_CAP_RSVD_31_29 = 0 - DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE" - DEVICE_ID = 24596 - DISABLE_ASPM_L1_TIMER = "FALSE" - DISABLE_BAR_FILTERING = "FALSE" - DISABLE_ID_CHECK = "FALSE" - DISABLE_LANE_REVERSAL = "TRUE" - DISABLE_RX_TC_FILTER = "FALSE" - DISABLE_SCRAMBLING = "FALSE" - DNSTREAM_LINK_NUM = 0 - DSN_BASE_PTR = 256 - DSN_CAP_ID = 3 - DSN_CAP_NEXTPTR = 0 - DSN_CAP_ON = "TRUE" - DSN_CAP_VERSION = 1 - ENABLE_MSG_ROUTE = 0 - ENABLE_RX_TD_ECRC_TRIM = "TRUE" - ENTER_RVRY_EI_L0 = "TRUE" - EXPANSION_ROM = 0 - EXT_CFG_CAP_PTR = 63 - EXT_CFG_XP_CAP_PTR = 1023 - HEADER_TYPE = 0 - INFER_EI = 12 - INTERRUPT_PIN = 1 - IS_SWITCH = "FALSE" - LAST_CONFIG_DWORD = 1023 - LINK_CAP_ASPM_SUPPORT = 1 - LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE" - LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE" - LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE" - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7 - LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7 - LINK_CAP_MAX_LINK_SPEED = 1 - LINK_CAP_MAX_LINK_WIDTH = 4 - LINK_CAP_RSVD_23_22 = 0 - LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE" - LINK_CONTROL_RCB = 0 - LINK_CTRL2_DEEMPHASIS = "FALSE" - LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE" - LINK_CTRL2_TARGET_LINK_SPEED = 0 - LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE" - LL_ACK_TIMEOUT = 0 - LL_ACK_TIMEOUT_EN = "FALSE" - LL_ACK_TIMEOUT_FUNC = 0 - LL_REPLAY_TIMEOUT = 38 - LL_REPLAY_TIMEOUT_EN = "TRUE" - LL_REPLAY_TIMEOUT_FUNC = 1 - LTSSM_MAX_LINK_WIDTH = 4 - MSI_BASE_PTR = 72 - MSI_CAP_ID = 5 - MSI_CAP_MULTIMSGCAP = 0 - MSI_CAP_MULTIMSG_EXTENSION = 0 - MSI_CAP_NEXTPTR = 96 - MSI_CAP_ON = "TRUE" - MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE" - MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE" - MSIX_BASE_PTR = 156 - MSIX_CAP_ID = 17 - MSIX_CAP_NEXTPTR = 0 - MSIX_CAP_ON = "FALSE" - MSIX_CAP_PBA_BIR = 0 - MSIX_CAP_PBA_OFFSET = 0 - MSIX_CAP_TABLE_BIR = 0 - MSIX_CAP_TABLE_OFFSET = 0 - MSIX_CAP_TABLE_SIZE = 0 - N_FTS_COMCLK_GEN1 = 255 - N_FTS_COMCLK_GEN2 = 254 - N_FTS_GEN1 = 255 - N_FTS_GEN2 = 255 - PCIE_BASE_PTR = 96 - PCIE_CAP_CAPABILITY_ID = 16 - PCIE_CAP_CAPABILITY_VERSION = 2 - PCIE_CAP_DEVICE_PORT_TYPE = 0 - PCIE_CAP_INT_MSG_NUM = 1 - PCIE_CAP_NEXTPTR = 0 - PCIE_CAP_ON = "TRUE" - PCIE_CAP_RSVD_15_14 = 0 - PCIE_CAP_SLOT_IMPLEMENTED = "FALSE" - PCIE_REVISION = 2 - PGL0_LANE = 0 - PGL1_LANE = 1 - PGL2_LANE = 2 - PGL3_LANE = 3 - PGL4_LANE = 4 - PGL5_LANE = 5 - PGL6_LANE = 6 - PGL7_LANE = 7 - PL_AUTO_CONFIG = 0 - PL_FAST_TRAIN = "FALSE" - PM_BASE_PTR = 64 - PM_CAP_AUXCURRENT = 0 - PM_CAP_DSI = "FALSE" - PM_CAP_D1SUPPORT = "FALSE" - PM_CAP_D2SUPPORT = "FALSE" - PM_CAP_ID = 1 - PM_CAP_NEXTPTR = 72 - PM_CAP_ON = "TRUE" - PM_CAP_PME_CLOCK = "FALSE" - PM_CAP_PMESUPPORT = 15 - PM_CAP_RSVD_04 = 0 - PM_CAP_VERSION = 3 - PM_CSR_BPCCEN = "FALSE" - PM_CSR_B2B3 = "FALSE" - PM_CSR_NOSOFTRST = "TRUE" - PM_DATA_SCALE0 = 0 - PM_DATA_SCALE1 = 0 - PM_DATA_SCALE2 = 0 - PM_DATA_SCALE3 = 0 - PM_DATA_SCALE4 = 0 - PM_DATA_SCALE5 = 0 - PM_DATA_SCALE6 = 0 - PM_DATA_SCALE7 = 0 - PM_DATA0 = 0 - PM_DATA1 = 0 - PM_DATA2 = 0 - PM_DATA3 = 0 - PM_DATA4 = 0 - PM_DATA5 = 0 - PM_DATA6 = 0 - PM_DATA7 = 0 - RECRC_CHK = 0 - RECRC_CHK_TRIM = "FALSE" - REVISION_ID = 0 - ROOT_CAP_CRS_SW_VISIBILITY = "FALSE" - SELECT_DLL_IF = "FALSE" - SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE" - SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE" - SLOT_CAP_HOTPLUG_CAPABLE = "FALSE" - SLOT_CAP_HOTPLUG_SURPRISE = "FALSE" - SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE" - SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE" - SLOT_CAP_PHYSICAL_SLOT_NUM = 0 - SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE" - SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE" - SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0 - SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 0 - SPARE_BIT0 = 0 - SPARE_BIT1 = 0 - SPARE_BIT2 = 0 - SPARE_BIT3 = 0 - SPARE_BIT4 = 0 - SPARE_BIT5 = 0 - SPARE_BIT6 = 0 - SPARE_BIT7 = 0 - SPARE_BIT8 = 0 - SPARE_BYTE0 = 0 - SPARE_BYTE1 = 0 - SPARE_BYTE2 = 0 - SPARE_BYTE3 = 0 - SPARE_WORD0 = 0 - SPARE_WORD1 = 0 - SPARE_WORD2 = 0 - SPARE_WORD3 = 0 - SUBSYSTEM_ID = 7 - SUBSYSTEM_VENDOR_ID = 4334 - TL_RBYPASS = "FALSE" - TL_RX_RAM_RADDR_LATENCY = 1 - TL_RX_RAM_RDATA_LATENCY = 3 - TL_RX_RAM_WRITE_LATENCY = 1 - TL_TFC_DISABLE = "FALSE" - TL_TX_CHECKS_DISABLE = "FALSE" - TL_TX_RAM_RADDR_LATENCY = 1 - TL_TX_RAM_RDATA_LATENCY = 3 - TL_TX_RAM_WRITE_LATENCY = 1 - UPCONFIG_CAPABLE = "TRUE" - UPSTREAM_FACING = "TRUE" - EXIT_LOOPBACK_ON_EI = "TRUE" - UR_INV_REQ = "TRUE" - USER_CLK_FREQ = 2 - VC_BASE_PTR = 0 - VC_CAP_ID = 2 - VC_CAP_NEXTPTR = 0 - VC_CAP_ON = "FALSE" - VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE" - VC_CAP_VERSION = 1 - VC0_CPL_INFINITE = "TRUE" - VC0_RX_RAM_LIMIT = 2047 - VC0_TOTAL_CREDITS_CD = 308 - VC0_TOTAL_CREDITS_CH = 36 - VC0_TOTAL_CREDITS_NPH = 12 - VC0_TOTAL_CREDITS_PD = 308 - VC0_TOTAL_CREDITS_PH = 32 - VC0_TX_LASTPACKET = 29 - VENDOR_ID = 4334 - VSEC_BASE_PTR = 0 - VSEC_CAP_HDR_ID = 4660 - VSEC_CAP_HDR_LENGTH = 24 - VSEC_CAP_HDR_REVISION = 1 - VSEC_CAP_ID = 11 - VSEC_CAP_IS_LINK_VISIBLE = "TRUE" - VSEC_CAP_NEXTPTR = 0 - VSEC_CAP_ON = "FALSE" - VSEC_CAP_VERSION = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. - Summary: - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_v6.v". - NO_OF_LANES = 4 - LINK_CAP_MAX_LINK_SPEED = 1 - PIPE_PIPELINE_STAGES = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_misc_v6.v". - PIPE_PIPELINE_STAGES = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_pipe_lane_v6.v". - PIPE_PIPELINE_STAGES = 0 - TCQ = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_gtx_v6.v". - TCQ = 1 - NO_OF_LANES = 4 - LINK_CAP_MAX_LINK_SPEED = 1 - REF_CLK_FREQ = 0 - PL_FAST_TRAIN = "FALSE" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_gtx_v6.v" line 255: Output port of the instance is unconnected or connected to loadless signal. - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit subtractor for signal created at line 485. - Found 5-bit adder for signal created at line 465. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v". - NO_OF_LANES = 4 - REF_CLK_FREQ = 0 - PL_FAST_TRAIN = "FALSE" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_wrapper_v6.v" line 277: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_drp_chanalign_fix_3752_v6.v". - TCQ = 1 - C_SIMULATION = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 13 | - | Inputs | 5 | - | Outputs | 11 | - | Clock | drp_clk (rising_edge) | - | Reset | Reset_n_INV_448_o (positive) | - | Reset type | synchronous | - | Reset State | 0011 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 179. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 10 D-type flip-flop(s). - inferred 7 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_rx_valid_filter_v6.v". - CLK_COR_MIN_LAT = 28 - TCQ = 1 - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 22 | - | Inputs | 7 | - | Outputs | 5 | - | Clock | USER_CLK (rising_edge) | - | Reset | RESET (positive) | - | Reset type | synchronous | - | Reset State | 00001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 10 | - | Inputs | 6 | - | Outputs | 4 | - | Clock | USER_CLK (rising_edge) | - | Reset | RESET (positive) | - | Reset type | synchronous | - | Reset State | 0001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 5-bit adder for signal created at line 309. - Found 4-bit adder for signal created at line 329. - Found 4-bit adder for signal created at line 361. - Found 5-bit comparator greater for signal created at line 284 - Found 4-bit comparator lessequal for signal created at line 357 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 44 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/gtx_tx_sync_rate_v6.v". - TCQ = 1 - C_SIMULATION = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 25-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 21 | - | Transitions | 40 | - | Inputs | 10 | - | Outputs | 21 | - | Clock | USER_CLK (rising_edge) | - | Reset | RESET (positive) | - | Reset type | synchronous | - | Reset State | 0000000000000100000000000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 179. - Found 8-bit adder for signal created at line 180. - Found 1-bit comparator equal for signal created at line 534 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 19 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_top_v6.v". - DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2 - VC0_TX_LASTPACKET = 29 - TLM_TX_OVERHEAD = 24 - TL_TX_RAM_RADDR_LATENCY = 1 - TL_TX_RAM_RDATA_LATENCY = 3 - TL_TX_RAM_WRITE_LATENCY = 1 - VC0_RX_LIMIT = 2047 - TL_RX_RAM_RADDR_LATENCY = 1 - TL_RX_RAM_RDATA_LATENCY = 3 - TL_RX_RAM_WRITE_LATENCY = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_brams_v6.v". - NUM_BRAMS = 4 - RAM_RADDR_LATENCY = 1 - RAM_RDATA_LATENCY = 3 - RAM_WRITE_LATENCY = 1 - TCQ = 1 - Found 13-bit register for signal . - Found 72-bit register for signal . - Found 1-bit register for signal . - Found 13-bit register for signal . - Found 72-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 172 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_bram_v6.v". - DOB_REG = 1 - WIDTH = 7'b0010010 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_upconfig_fix_3451_v6.v". - UPSTREAM_FACING = "TRUE" - PL_FAST_TRAIN = "FALSE" - LINK_CAP_MAX_LINK_WIDTH = 4 - TCQ = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd" line 783: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tlpControl.vhd" line 783: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 280 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_Transact.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_Transact.vhd" line 787: Output port of the instance is unconnected or connected to loadless signal. - Summary: - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/RxIn_Delays.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 35 | - | Inputs | 9 | - | Outputs | 4 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | tk_rst | - | Power Up State | tk_rst | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 10-bit comparator equal for signal created at line 896 - Found 16-bit comparator equal for signal created at line 919 - Found 8-bit comparator equal for signal created at line 936 - Found 8-bit comparator equal for signal created at line 953 - Summary: - inferred 113 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 9 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" line 511: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" line 511: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal >. - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 55-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 27 | - | Inputs | 6 | - | Outputs | 2 | - | Clock | user_clk (rising_edge) | - | Reset | local_Reset (positive) | - | Reset type | asynchronous | - | Reset State | st_mrd_reset | - | Power Up State | st_mrd_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 2 | - | Clock | user_clk (rising_edge) | - | Reset | local_Reset (positive) | - | Reset type | asynchronous | - | Reset State | reqst_idle | - | Power Up State | reqst_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Summary: - inferred 423 D-type flip-flop(s). - inferred 123 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_MWr_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 10-bit register for signal . - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal >. - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 26 | - | Inputs | 4 | - | Outputs | 4 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | st_mwr_reset | - | Power Up State | st_mwr_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 10-bit adder for signal created at line 404. - Found 10-bit adder for signal created at line 463. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 334 D-type flip-flop(s). - inferred 74 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" line 1150: Output port of the instance is unconnected or connected to loadless signal. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 36-bit register for signal . - Found 8-bit register for signal . - Found 13-bit register for signal . - Found 4-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 11-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 36-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 36-bit register for signal . - Found 13-bit register for signal >. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 76 | - | Inputs | 9 | - | Outputs | 6 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | st_cpld_reset | - | Power Up State | st_cpld_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 1077. - Found 4-bit adder for signal created at line 1107. - Found 4-bit adder for signal created at line 1113. - Found 32-bit adder for signal created at line 1302. - Found 6-bit subtractor for signal > created at line 877. - Found 6-bit subtractor for signal > created at line 879. - Found 8-bit comparator equal for signal created at line 1106 - Found 8-bit comparator equal for signal created at line 1112 - Found 8-bit comparator equal for signal created at line 1225 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 6 Adder/Subtractor(s). - inferred 827 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 172 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/FF_tagram64x36.vhd". - Found 1-bit register for signal . - Found 36-bit register for signal . - Found 36-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal >. - Found 36-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2542 D-type flip-flop(s). - inferred 128 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" line 365: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" line 543: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" line 543: Output port of the instance is unconnected or connected to loadless signal. - Found 8-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . -INFO:Xst:1799 - State reqst_quantity is never reached in FSM . -INFO:Xst:1799 - State reqst_fifo_req is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 2 | - | Clock | user_clk (rising_edge) | - | Reset | usDMA_Channel_Rst (positive) | - | Reset type | asynchronous | - | Reset State | reqst_idle | - | Power Up State | reqst_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 530. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 1 Adder/Subtractor(s). - inferred 279 D-type flip-flop(s). - inferred 5 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_Calculate.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 13-bit register for signal . - Found 13-bit register for signal . - Found 13-bit register for signal . - Found 10-bit register for signal >. - Found 12-bit register for signal . - Found 12-bit register for signal . - Found 33-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 18-bit subtractor for signal created at line 684. - Found 48-bit adder for signal created at line 365. - Found 48-bit adder for signal created at line 374. - Found 17-bit adder for signal created at line 398. - Found 17-bit adder for signal created at line 415. - Found 48-bit adder for signal created at line 432. - Found 48-bit adder for signal created at line 450. - Found 13-bit adder for signal created at line 518. - Found 17-bit adder for signal created at line 635. - Found 17-bit adder for signal created at line 652. - Found 12-bit adder for signal created at line 708. - Found 26-bit adder for signal created at line 758. - Found 57-bit adder for signal created at line 792. - Found 16-bit adder for signal created at line 844. - Found 48-bit adder for signal created at line 855. - Found 48-bit adder for signal created at line 865. - Found 13-bit subtractor for signal > created at line 619. - Found 64-bit subtractor for signal > created at line 667. - Found 48-bit subtractor for signal > created at line 922. - Found 8x18-bit Read Only RAM for signal <_n0634> - Summary: - inferred 1 RAM(s). - inferred 19 Adder/Subtractor(s). - inferred 821 D-type flip-flop(s). - inferred 174 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DMA_FSM.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 128-bit register for signal . - Found 32-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 20 | - | Inputs | 7 | - | Outputs | 11 | - | Clock | dma_clk (rising_edge) | - | Reset | dma_reset (positive) | - | Reset type | asynchronous | - | Reset State | dmast_init | - | Power Up State | dmast_init | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 14 | - | Inputs | 6 | - | Outputs | 4 | - | Clock | dma_clk (rising_edge) | - | Reset | dma_reset (positive) | - | Reset type | asynchronous | - | Reset State | fsm_idle | - | Power Up State | fsm_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 8 | - | Inputs | 4 | - | Outputs | 2 | - | Clock | dma_clk (rising_edge) | - | Reset | dma_reset (positive) | - | Reset type | asynchronous | - | Reset State | toutst_idle | - | Power Up State | toutst_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 870. - Found 16-bit adder for signal created at line 877. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 175 D-type flip-flop(s). - inferred 150 Multiplexer(s). - inferred 3 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" line 654: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" line 654: Output port of the instance is unconnected or connected to loadless signal. - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 36-bit register for signal . - Found 64-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit adder for signal created at line 639. - Found 6-bit adder for signal created at line 716. - Found 6-bit subtractor for signal > created at line 718. - Found 1-bit 6-to-1 multiplexer for signal created at line 792. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 2 Adder/Subtractor(s). - inferred 148 D-type flip-flop(s). - inferred 138 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Interrupts.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'Irpt_Qout_i<127:95>', unconnected in block 'Interrupts', is tied to its initial value (000000000000000000000000000000000). -WARNING:Xst:2935 - Signal 'Irpt_Qout_i<93:35>', unconnected in block 'Interrupts', is tied to its initial value (00000000000000000000000000000000000000000000000000000000000). -WARNING:Xst:2935 - Signal 'Irpt_Qout_i<16:10>', unconnected in block 'Interrupts', is tied to its initial value (0000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Register equivalent to has been removed - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 10 | - | Inputs | 4 | - | Outputs | 3 | - | Clock | user_clk (rising_edge) | - | Reset | user_reset (positive) | - | Reset type | asynchronous | - | Reset State | intst_rst | - | Power Up State | intst_rst | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 4-to-1 multiplexer for signal created at line 205. - Summary: - inferred 5 D-type flip-flop(s). - inferred 6 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Transact.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 31-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 8-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 31-bit register for signal . - Found 1-bit register for signal . - Found 12-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 37 | - | Inputs | 9 | - | Outputs | 4 | - | Clock | user_clk (rising_edge) | - | Reset | trn_tx_Reset_n (negative) | - | Reset type | asynchronous | - | Reset State | st_txidle | - | Power Up State | st_txidle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 965 D-type flip-flop(s). - inferred 195 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/tx_Mem_Reader.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 33 | - | Inputs | 16 | - | Outputs | 10 | - | Clock | user_clk (rising_edge) | - | Reset | mReader_Rst_n (negative) | - | Reset type | asynchronous | - | Reset State | st_mr_idle | - | Power Up State | st_mr_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 10-bit adder for signal created at line 467. - Found 10-bit adder for signal created at line 635. - Found 10-bit adder for signal created at line 638. - Found 22-bit adder for signal created at line 854. - Found 10-bit subtractor for signal > created at line 340. - Found 10-bit subtractor for signal > created at line 565. - Found 10-bit subtractor for signal > created at line 599. - Found 10-bit subtractor for signal > created at line 652. - Found 10-bit subtractor for signal > created at line 691. - Summary: - inferred 8 Adder/Subtractor(s). - inferred 477 D-type flip-flop(s). - inferred 352 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd". - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal >. - Found 4-bit register for signal >. - Found 4-bit register for signal >. - Found 4-bit register for signal >. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 8 | - | Inputs | 2 | - | Outputs | 2 | - | Clock | clk (rising_edge) | - | Reset | rst_n (negative) | - | Reset type | asynchronous | - | Reset State | ast_reset | - | Power Up State | ast_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal > created at line 218 - Found 4-bit comparator equal for signal created at line 277 - Found 4-bit comparator equal for signal created at line 277 - Found 4-bit comparator equal for signal created at line 277 - Found 4-bit comparator equal for signal created at line 277 - Summary: - inferred 36 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 11 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/Registers.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 25-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 28-bit register for signal . - Found 28-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal >. - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 64-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit adder for signal created at line 1899. - Found 32-bit adder for signal created at line 1919. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 1395 D-type flip-flop(s). - inferred 1437 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd". - SIMULATION = "FALSE" - DATA_WIDTH = 64 - ADDR_WIDTH = 28 - DDR_UI_DATAWIDTH = 256 - DDR_DQ_WIDTH = 32 - DEVICE_TYPE = "VIRTEX6" - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "KEEP = TRUE" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/ddr_Transact.vhd" line 535: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 4-to-1 multiplexer for signal created at line 251. - Found 1-bit 4-to-1 multiplexer for signal created at line 251. - Summary: - inferred 7 D-type flip-flop(s). - inferred 789 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd". - C_ASYNFIFO_WIDTH = 72 - DATA_WIDTH = 64 - ADDR_WIDTH = 28 - P_SIMULATION = "FALSE" - DDR_DQ_WIDTH = 32 - DDR_PAYLOAD_WIDTH = 256 - DEVICE_TYPE = "VIRTEX6" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 313: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 313: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 345: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/DDRs_Control.vhd" line 369: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'wpipe_f2m_din<127:74>', unconnected in block 'DDRs_Control', is tied to its initial value (000000000000000000000000000000000000000000000000000000). -WARNING:Xst:2935 - Signal 'memc_rd_addr<27>', unconnected in block 'DDRs_Control', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'memc_rd_addr<1:0>', unconnected in block 'DDRs_Control', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'memc_wr_addr<27>', unconnected in block 'DDRs_Control', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'memc_wr_addr<1:0>', unconnected in block 'DDRs_Control', is tied to its initial value (00). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 33-bit register for signal . - Found 33-bit register for signal . - Found 8-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 30-bit register for signal . - Found 3-bit register for signal . - Found 256-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 30-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 9-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 256-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 72-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 20 | - | Inputs | 11 | - | Outputs | 5 | - | Clock | memc_ui_clk (rising_edge) | - | Reset | Rst_i (positive) | - | Reset type | asynchronous | - | Reset State | rdst_reset | - | Power Up State | rdst_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State wrst_1st_data_b2b is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 23 | - | Inputs | 9 | - | Outputs | 5 | - | Clock | memc_ui_clk (rising_edge) | - | Reset | Rst_i (positive) | - | Reset type | asynchronous | - | Reset State | wrst_bram_reset | - | Power Up State | wrst_bram_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 30-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 811. - Found 30-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 859. - Found 9-bit adder for signal created at line 901. - Found 5-bit adder for signal created at line 1241. - Found 30-bit subtractor for signal > created at line 661. - Found 9-bit subtractor for signal > created at line 671. - Found 6-bit subtractor for signal > created at line 703. - Found 30-bit subtractor for signal > created at line 858. - Found 9-bit subtractor for signal created at line 0. - Found 4-bit comparator lessequal for signal created at line 335 - Found 9-bit comparator greater for signal created at line 834 - Found 6-bit comparator greater for signal created at line 839 - Found 9-bit comparator lessequal for signal created at line 931 - Found 5-bit comparator lessequal for signal created at line 932 - Found 6-bit comparator greater for signal created at line 934 - Found 6-bit comparator lessequal for signal created at line 935 - Summary: - inferred 11 Adder/Subtractor(s). - inferred 1420 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 478 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd". - C_ASYNFIFO_WIDTH = 72 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" line 298: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" line 340: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/pcie/common/wb_transact.vhd" line 357: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'rpiped_din<71:64>', unconnected in block 'wb_transact', is tied to its initial value (00000000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 29-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 66-bit register for signal . - Found 66-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 18 | - | Inputs | 9 | - | Outputs | 6 | - | Clock | wb_clk (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | st_reset | - | Power Up State | st_reset | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 29-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit comparator greater for signal created at line 204 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 2 Adder/Subtractor(s). - inferred 309 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 19 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd". - REFCLK_FREQ = 200.0 - IODELAY_GRP = "IODELAY_MIG" - MMCM_ADV_BANDWIDTH = "OPTIMIZED" - CLKFBOUT_MULT_F = 6 - DIVCLK_DIVIDE = 1 - CLKOUT_DIVIDE = 3 - nCK_PER_CLK = 2 - tCK = 2500 - DEBUG_PORT = "OFF" - SIM_BYPASS_INIT_CAL = "OFF" - nCS_PER_RANK = 1 - DQS_CNT_WIDTH = 3 - RANK_WIDTH = 1 - BANK_WIDTH = 3 - CK_WIDTH = 1 - CKE_WIDTH = 1 - COL_WIDTH = 10 - CS_WIDTH = 1 - DM_WIDTH = 8 - DQ_WIDTH = 64 - DQS_WIDTH = 8 - ROW_WIDTH = 14 - BURST_MODE = "4" - BM_CNT_WIDTH = 2 - ADDR_CMD_MODE = "1T" - ORDERING = "NORM" - WRLVL = "ON" - PHASE_DETECT = "ON" - RTT_NOM = "60" - RTT_WR = "OFF" - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000100000000100000000" - DQS_LOC_COL1 = "0000011100000110000001010000010000000011" - DQS_LOC_COL2 = "0" - DQS_LOC_COL3 = "0" - tPRDI = 1000000 - tREFI = 7800000 - tZQI = 128000000 - ADDR_WIDTH = 28 - ECC = "OFF" - ECC_TEST = "OFF" - TCQ = 100 - DATA_WIDTH = 64 - PAYLOAD_WIDTH = 64 - RST_ACT_LOW = 0 - INPUT_CLK_TYPE = "SINGLE_ENDED" - STARVE_LIMIT = 2 - Set property "KEEP = TRUE" for signal . - Set property "KEEP = TRUE" for signal . -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/ddr_v6.vhd" line 642: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/clk_ibuf.vhd". - INPUT_CLK_TYPE = "SINGLE_ENDED" - Set property "KEEP = TRUE" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/iodelay_ctrl.vhd". - TCQ = 100 - IODELAY_GRP = "IODELAY_MIG" - INPUT_CLK_TYPE = "SINGLE_ENDED" - RST_ACT_LOW = 0 - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "syn_maxfan = 10" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 15-bit register for signal . - Summary: - inferred 15 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/infrastructure.vhd". - TCQ = 100 - CLK_PERIOD = 5000 - nCK_PER_CLK = 2 - INPUT_CLK_TYPE = "DIFFERENTIAL" - MMCM_ADV_BANDWIDTH = "OPTIMIZED" - CLKFBOUT_MULT_F = 6 - DIVCLK_DIVIDE = 1 - CLKOUT_DIVIDE = 3 - RST_ACT_LOW = 0 - Set property "syn_maxfan = 10" for signal . - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd". - REFCLK_FREQ = 200.0 - SIM_BYPASS_INIT_CAL = "OFF" - IODELAY_GRP = "IODELAY_MIG" - nCK_PER_CLK = 2 - DRAM_TYPE = "DDR3" - nCS_PER_RANK = 1 - DQ_CNT_WIDTH = 6 - DQS_CNT_WIDTH = 3 - RANK_WIDTH = 1 - BANK_WIDTH = 3 - CK_WIDTH = 1 - CKE_WIDTH = 1 - COL_WIDTH = 10 - CS_WIDTH = 1 - DM_WIDTH = 8 - USE_DM_PORT = 1 - DQ_WIDTH = 64 - DRAM_WIDTH = 8 - DQS_WIDTH = 8 - ROW_WIDTH = 14 - AL = "0" - BURST_MODE = "4" - BURST_TYPE = "SEQ" - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - nAL = 0 - CL = 6 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - BM_CNT_WIDTH = 2 - ADDR_CMD_MODE = "1T" - nBANK_MACHS = 4 - ORDERING = "NORM" - RANKS = 1 - WRLVL = "ON" - PHASE_DETECT = "ON" - CAL_WIDTH = "HALF" - RTT_NOM = "60" - RTT_WR = "OFF" - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000100000000100000000" - DQS_LOC_COL1 = "0000011100000110000001010000010000000011" - DQS_LOC_COL2 = "0" - DQS_LOC_COL3 = "0" - tCK = 2500 - tFAW = 45000 - tPRDI = 1000000 - tRRD = 7500 - tRAS = 36000 - tRCD = 13500 - tREFI = 7800000 - tRFC = 160000 - tRP = 13500 - tRTP = 7500 - tWTR = 7500 - tZQI = 128000000 - tZQCS = 64 - SLOT_0_CONFIG = "00000001" - SLOT_1_CONFIG = "00000000" - DEBUG_PORT = "OFF" - ADDR_WIDTH = 28 - MEM_ADDR_ORDER = "ROW_BANK_COLUMN" - STARVE_LIMIT = 2 - TCQ = 100 - ECC = "OFF" - DATA_WIDTH = 64 - ECC_TEST = "OFF" - PAYLOAD_WIDTH = 64 - APP_DATA_WIDTH = 256 - APP_MASK_WIDTH = 32 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 703: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd" line 895: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/mem_intfc.vhd". - TCQ = 100 - PAYLOAD_WIDTH = 64 - ADDR_CMD_MODE = "1T" - AL = "0" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - BURST_TYPE = "SEQ" - CK_WIDTH = 1 - CL = 6 - COL_WIDTH = 10 - CMD_PIPE_PLUS1 = "ON" - CS_WIDTH = 1 - CKE_WIDTH = 1 - CWL = 5 - DATA_WIDTH = 64 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - DM_WIDTH = 8 - DQ_CNT_WIDTH = 6 - DQ_WIDTH = 64 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - DRAM_TYPE = "DDR3" - DRAM_WIDTH = 8 - ECC = "OFF" - ECC_WIDTH = 0 - MC_ERR_ADDR_WIDTH = 28 - nAL = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - ORDERING = "NORM" - PHASE_DETECT = "ON" - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - RTT_NOM = "60" - RTT_WR = "OFF" - STARVE_LIMIT = 2 - tCK = 2500 - tFAW = 45000 - tPRDI = 1000000 - tRAS = 36000 - tRCD = 13500 - tREFI = 7800000 - tRFC = 160000 - tRP = 13500 - tRRD = 7500 - tRTP = 7500 - tWTR = 7500 - tZQI = 128000000 - tZQCS = 64 - WRLVL = "ON" - DEBUG_PORT = "OFF" - CAL_WIDTH = "HALF" - RANK_WIDTH = 1 - RANKS = 1 - ROW_WIDTH = 14 - SLOT_0_CONFIG = "00000001" - SLOT_1_CONFIG = "00000000" - SIM_BYPASS_INIT_CAL = "OFF" - REFCLK_FREQ = 200.0 - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - USE_DM_PORT = 1 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CL = 6 - COL_WIDTH = 10 - CMD_PIPE_PLUS1 = "ON" - CS_WIDTH = 1 - CWL = 5 - DATA_WIDTH = 64 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - nREFRESH_BANK = 1 - DRAM_TYPE = "DDR3" - DQS_WIDTH = 8 - DQ_WIDTH = 64 - ECC = "OFF" - ECC_WIDTH = 0 - MC_ERR_ADDR_WIDTH = 28 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - ORDERING = "NORM" - PAYLOAD_WIDTH = 64 - RANK_WIDTH = 1 - RANKS = 1 - PHASE_DETECT = "ON" - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - STARVE_LIMIT = 2 - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" - nSLOTS = 1 - tCK = 2500 - tFAW = 45000 - tPRDI = 1000000 - tRAS = 36000 - tRCD = 13500 - tREFI = 7800000 - tRFC = 160000 - tRP = 13500 - tRRD = 7500 - tRTP = 7500 - tWTR = 7500 - tZQI = 128000000 - tZQCS = 64 - Set property "MAX_FANOUT = 10" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" line 1012: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/mc.vhd" line 1012: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 14-bit register for signal . - Found 14-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 10-bit register for signal . - Summary: - inferred 82 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_mach.vhd". - BURST_MODE = "4" - CS_WIDTH = 1 - DRAM_TYPE = "DDR3" - MAINT_PRESCALER_DIV = 40 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - CL = 6 - nFAW = 18 - nREFRESH_BANK = 1 - nRRD = 4 - nWTR = 4 - PERIODIC_RD_TIMER_DIV = 5 - RANK_BM_BV_WIDTH = 4 - RANK_WIDTH = 1 - RANKS = 1 - PHASE_DETECT = "ON" - REFRESH_TIMER_DIV = 39 - ZQ_TIMER_DIV = 640000 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd". - TCQ = 100 - BURST_MODE = "4" - ID = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - CL = 6 - nFAW = 18 - nREFRESH_BANK = 1 - nRRD = 4 - nWTR = 4 - PERIODIC_RD_TIMER_DIV = 5 - RANK_BM_BV_WIDTH = 4 - RANK_WIDTH = 1 - RANKS = 1 - PHASE_DETECT = "ON" - REFRESH_TIMER_DIV = 39 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd" line 305: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 2-bit subtractor for signal created at line 428. - Found 3-bit adder for signal created at line 325. - Found 1-bit adder for signal > created at line 433. - Found 3-bit subtractor for signal > created at line 328. - Found 3-bit subtractor for signal > created at line 372. - Found 3-bit subtractor for signal > created at line 473. - Found 3-bit comparator lessequal for signal created at line 381 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 14 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd". - TCQ = 100 - DRAM_TYPE = "DDR3" - MAINT_PRESCALER_DIV = 40 - nBANK_MACHS = 4 - RANK_WIDTH = 1 - RANKS = 1 - REFRESH_TIMER_DIV = 39 - ZQ_TIMER_DIV = 640000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd" line 392: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_common.vhd" line 477: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 20-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit adder for signal created at line 417. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 1-bit adder for signal > created at line 420. - Found 6-bit subtractor for signal > created at line 276. - Found 6-bit subtractor for signal > created at line 301. - Found 20-bit subtractor for signal > created at line 323. - Summary: - inferred 12 Adder/Subtractor(s). - inferred 43 D-type flip-flop(s). - inferred 21 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd". - TCQ = 100 - WIDTH = 2 - Found 2-bit register for signal . - Found 2-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd". - TCQ = 100 - WIDTH = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_mach.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CS_WIDTH = 1 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - LOW_IDLE_CNT = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nCS_PER_RANK = 1 - nOP_WAIT = 0 - nRAS = 15 - nRCD = 6 - nRFC = 64 - nRTP = 4 - nRP = 6 - nSLOTS = 1 - nWR = 6 - ORDERING = "NORM" - RANK_BM_BV_WIDTH = 4 - RANK_WIDTH = 1 - RANKS = 1 - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - STARVE_LIMIT = 2 - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" - tZQCS = 64 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_mach.vhd" line 909: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_compare.vhd". - BANK_WIDTH = 3 - TCQ = 100 - BURST_MODE = "4" - COL_WIDTH = 10 - DATA_BUF_ADDR_WIDTH = 4 - ECC = "OFF" - RANK_WIDTH = 1 - RANKS = 1 - ROW_WIDTH = 14 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'req_col_r<11:10>', unconnected in block 'bank_compare', is tied to its initial value (00). - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 14-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit shifter logical left for signal > created at line 404 - Found 3-bit comparator equal for signal created at line 338 - Found 14-bit comparator equal for signal created at line 346 - Summary: - inferred 41 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 5 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_1', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Summary: - inferred 5 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 1 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 1 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_2', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 467. - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Summary: - inferred 7 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 15 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 2 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 2 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_3', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 467. - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Found 2-bit adder for signal created at line 377. - Summary: - inferred 8 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 15 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_cntrl.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_WIDTH = 3 - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - COL_WIDTH = 10 - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 3 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRCD = 6 - nRTP = 4 - nRP = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANK_WIDTH = 1 - RANKS = 1 - RAS_TIMER_WIDTH = 3 - ROW_WIDTH = 14 - STARVE_LIMIT = 2 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BM_CNT_WIDTH = 2 - BURST_MODE = "4" - CWL = 5 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - ECC = "OFF" - ID = 3 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2RD_EN = 2 - nCNFG2WR = 2 - nOP_WAIT = 0 - nRAS_CLKS = 8 - nRP = 6 - nRTP = 4 - nRCD = 6 - nWTP_CLKS = 7 - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - RAS_TIMER_WIDTH = 3 - STARVE_LIMIT = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rd_half_rmw_temp', unconnected in block 'bank_state_4', is tied to its initial value (0). - Register equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 548. - Found 2-bit subtractor for signal created at line 822. - Found 2-bit adder for signal created at line 889. - Found 3-bit adder for signal created at line 966. - Found 3-bit subtractor for signal > created at line 686. - Found 2-bit subtractor for signal > created at line 727. - Found 3-bit comparator lessequal for signal created at line 682 - Found 2-bit comparator equal for signal created at line 1029 - Summary: - inferred 6 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_queue.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - nBANK_MACHS = 4 - ORDERING = "NORM" - ID = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 368. - Found 2-bit adder for signal created at line 368. - Found 2-bit adder for signal created at line 467. - Found 2-bit subtractor for signal > created at line 460. - Found 2-bit subtractor for signal > created at line 469. - Found 2-bit subtractor for signal > created at line 500. - Found 2-bit subtractor for signal > created at line 503. - Found 2-bit subtractor for signal > created at line 507. - Found 2-bit subtractor for signal > created at line 674. - Found 2-bit subtractor for signal > created at line 680. - Summary: - inferred 9 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 15 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd". - TCQ = 100 - BM_CNT_WIDTH = 2 - LOW_IDLE_CNT = 0 - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nOP_WAIT = 0 - nRFC = 64 - RANK_WIDTH = 1 - RANKS = 1 - CWL = 5 - tZQCS = 64 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 455. - Found 2-bit adder for signal created at line 455. - Found 2-bit adder for signal created at line 455. - Found 2-bit adder for signal created at line 467. - Found 2-bit adder for signal created at line 467. - Found 2-bit adder for signal created at line 467. - Found 2-bit adder for signal created at line 482. - Found 2-bit adder for signal created at line 482. - Found 2-bit adder for signal created at line 482. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit adder for signal created at line 666. - Found 2-bit subtractor for signal > created at line 686. - Found 6-bit subtractor for signal > created at line 727. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 18 Adder/Subtractor(s). - inferred 21 D-type flip-flop(s). - inferred 13 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_mux.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_VECT_INDX = 11 - BANK_WIDTH = 3 - BURST_MODE = "4" - CS_WIDTH = 1 - DATA_BUF_ADDR_VECT_INDX = 15 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - nCNFG2WR = 2 - nSLOTS = 1 - RANK_VECT_INDX = 3 - RANK_WIDTH = 1 - ROW_VECT_INDX = 55 - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - EARLY_WR_DATA_ADDR = "OFF" - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCNFG2WR = 2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" line 242: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" line 270: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_row_col.vhd" line 323: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/round_robin_arb.vhd". - TCQ = 100 - WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/arb_select.vhd". - TCQ = 100 - ADDR_CMD_MODE = "1T" - BANK_VECT_INDX = 11 - BANK_WIDTH = 3 - BURST_MODE = "4" - CS_WIDTH = 1 - DATA_BUF_ADDR_VECT_INDX = 15 - DATA_BUF_ADDR_WIDTH = 4 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - nBANK_MACHS = 4 - nCK_PER_CLK = 2 - nCS_PER_RANK = 1 - nSLOTS = 1 - RANK_VECT_INDX = 3 - RANK_WIDTH = 1 - ROW_VECT_INDX = 55 - ROW_WIDTH = 14 - RTT_NOM = "60" - RTT_WR = "OFF" - SLOT_0_CONFIG = "00001111" - SLOT_1_CONFIG = "00000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:2935 - Signal 'row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (000000000000000000000). - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit shifter logical left for signal > created at line 526 - Found 1-bit shifter logical left for signal > created at line 527 - Found 1-bit shifter logical left for signal created at line 242 - Summary: - inferred 9 D-type flip-flop(s). - inferred 40 Multiplexer(s). - inferred 3 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd". - TCQ = 100 - BANK_WIDTH = 3 - BURST_MODE = "4" - COL_WIDTH = 10 - CS_WIDTH = 1 - DATA_BUF_ADDR_WIDTH = 4 - DATA_BUF_OFFSET_WIDTH = 1 - DELAY_WR_DATA_CNTRL = 0 - DQS_WIDTH = 8 - DRAM_TYPE = "DDR3" - EARLY_WR_DATA_ADDR = "OFF" - ECC = "OFF" - MC_ERR_ADDR_WIDTH = 28 - nCK_PER_CLK = 2 - nPHY_WRLAT = 0 - nRD_EN2CNFG_WR = 7 - nWR_EN2CNFG_RD = 4 - nWR_EN2CNFG_WR = 4 - RANK_WIDTH = 1 - ROW_WIDTH = 14 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd" line 560: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). - Found 3-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 7-bit register for signal >. - Found 1-bit register for signal >. - Found 7-bit register for signal . - Found 5-bit adder for signal created at line 529. - Found 5-bit adder for signal created at line 547. - Found 3-bit subtractor for signal > created at line 430. - Found 2-bit subtractor for signal > created at line 455. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 4 Adder/Subtractor(s). - inferred 37 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200.0 - DRAM_TYPE = "DDR3" - SLOT_0_CONFIG = "00000001" - SLOT_1_CONFIG = "00000000" - BANK_WIDTH = 3 - CK_WIDTH = 1 - COL_WIDTH = 10 - nCS_PER_RANK = 1 - DQ_CNT_WIDTH = 6 - DQ_WIDTH = 64 - DM_WIDTH = 8 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - ROW_WIDTH = 14 - RANK_WIDTH = 1 - CS_WIDTH = 1 - CKE_WIDTH = 1 - CAL_WIDTH = "HALF" - CALIB_ROW_ADD = "0000000000000000" - CALIB_COL_ADD = "000000000000" - CALIB_BA_ADD = "000" - AL = "0" - BURST_MODE = "4" - BURST_TYPE = "SEQ" - nAL = 0 - nCL = 6 - nCWL = 5 - tRFC = 160000 - OUTPUT_DRV = "HIGH" - REG_CTRL = "OFF" - RTT_NOM = "60" - RTT_WR = "OFF" - WRLVL = "ON" - PHASE_DETECT = "ON" - PD_TAP_REQ = 0 - PD_MSB_SEL = 8 - PD_DQS0_ONLY = "ON" - PD_LHC_WIDTH = 16 - PD_CALIB_MODE = "PARALLEL" - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - USE_DM_PORT = 1 - SIM_BYPASS_INIT_CAL = "OFF" - SIM_INIT_OPTION = "NONE" - SIM_CAL_OPTION = "NONE" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1723: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1723: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1788: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_top.vhd" line 1891: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . - Summary: - inferred 5 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_init.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - BANK_WIDTH = 3 - COL_WIDTH = 10 - nCS_PER_RANK = 1 - DQ_WIDTH = 64 - ROW_WIDTH = 14 - CS_WIDTH = 1 - CKE_WIDTH = 1 - DRAM_TYPE = "DDR3" - REG_CTRL = "OFF" - CALIB_ROW_ADD = "0000000000000000" - CALIB_COL_ADD = "000000000000" - CALIB_BA_ADD = "000" - AL = "0" - BURST_MODE = "4" - BURST_TYPE = "SEQ" - nAL = 0 - nCL = 6 - nCWL = 5 - tRFC = 160000 - OUTPUT_DRV = "HIGH" - RTT_NOM = "60" - RTT_WR = "OFF" - WRLVL = "ON" - PHASE_DETECT = "ON" - DDR2_DQSN_ENABLE = "YES" - nSLOTS = 1 - SIM_INIT_OPTION = "NONE" - SIM_CAL_OPTION = "NONE" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Register > equivalent to > has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Register > equivalent to > has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 1-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal >. - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 14-bit register for signal . - Found 1-bit register for signal . -INFO:Xst:1799 - State 011110 is never reached in FSM . -INFO:Xst:1799 - State 100101 is never reached in FSM . -INFO:Xst:1799 - State 100100 is never reached in FSM . -INFO:Xst:1799 - State 100111 is never reached in FSM . -INFO:Xst:1799 - State 011101 is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 42 | - | Transitions | 90 | - | Inputs | 30 | - | Outputs | 34 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 000000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 7-bit adder for signal created at line 1182. - Found 10-bit adder for signal created at line 1217. - Found 9-bit adder for signal created at line 1236. - Found 8-bit adder for signal created at line 1305. - Found 8-bit adder for signal created at line 1358. - Found 2-bit adder for signal created at line 1395. - Found 2-bit adder for signal created at line 1458. - Found 3-bit adder for signal created at line 1478. - Found 2-bit adder for signal created at line 2034. - Found 2-bit adder for signal created at line 2051. - Found 2-bit adder for signal created at line 2141. - Found 4-bit adder for signal created at line 2243. - Found 5-bit subtractor for signal > created at line 1066. - Found 3-bit subtractor for signal > created at line 2033. - Found 4x3-bit Read Only RAM for signal - Found 2-bit comparator greater for signal created at line 1618 - Found 2-bit comparator greater for signal created at line 1650 - Found 3-bit comparator not equal for signal created at line 2033 - Found 2-bit comparator greater for signal created at line 2079 - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <13:11>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . - WARNING:Xst:2404 - FFs/Latches <2:1>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 1 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <1:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . - Summary: - inferred 1 RAM(s). - inferred 14 Adder/Subtractor(s). - inferred 471 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 24 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd". - Set property "MAX_FANOUT = 1" for signal . - TCQ = 100 - BANK_WIDTH = 3 - RANK_WIDTH = 1 - nCS_PER_RANK = 1 - CS_WIDTH = 1 - CKE_WIDTH = 1 - ROW_WIDTH = 14 - WRLVL = "ON" - nCWL = 5 - DRAM_TYPE = "DDR3" - REG_CTRL = "OFF" - REFCLK_FREQ = 200.0 - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - DDR2_EARLY_CS = 0 - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit tristate buffer for signal created at line 597 - Found 1-bit tristate buffer for signal created at line 598 - Found 1-bit tristate buffer for signal created at line 603 - Found 1-bit tristate buffer for signal created at line 604 - Found 1-bit tristate buffer for signal created at line 607 - Found 1-bit tristate buffer for signal created at line 608 - Found 1-bit tristate buffer for signal created at line 695 - Found 1-bit tristate buffer for signal created at line 696 - Found 1-bit tristate buffer for signal created at line 701 - Found 1-bit tristate buffer for signal created at line 702 - Found 1-bit tristate buffer for signal created at line 705 - Found 1-bit tristate buffer for signal created at line 706 - Found 1-bit tristate buffer for signal created at line 793 - Found 1-bit tristate buffer for signal created at line 794 - Found 1-bit tristate buffer for signal created at line 799 - Found 1-bit tristate buffer for signal created at line 800 - Found 1-bit tristate buffer for signal created at line 803 - Found 1-bit tristate buffer for signal created at line 804 - Found 1-bit tristate buffer for signal created at line 889 - Found 1-bit tristate buffer for signal created at line 890 - Found 1-bit tristate buffer for signal created at line 895 - Found 1-bit tristate buffer for signal created at line 896 - Found 1-bit tristate buffer for signal created at line 992 - Found 1-bit tristate buffer for signal created at line 993 - Found 1-bit tristate buffer for signal created at line 998 - Found 1-bit tristate buffer for signal created at line 999 - Found 1-bit tristate buffer for signal created at line 1002 - Found 1-bit tristate buffer for signal created at line 1003 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1090 - Found 1-bit tristate buffer for signal created at line 1091 - Found 1-bit tristate buffer for signal created at line 1096 - Found 1-bit tristate buffer for signal created at line 1097 - Found 1-bit tristate buffer for signal created at line 1100 - Found 1-bit tristate buffer for signal created at line 1101 - Found 1-bit tristate buffer for signal created at line 1188 - Found 1-bit tristate buffer for signal created at line 1189 - Found 1-bit tristate buffer for signal created at line 1194 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1198 - Found 1-bit tristate buffer for signal created at line 1199 - Found 1-bit tristate buffer for signal created at line 1188 - Found 1-bit tristate buffer for signal created at line 1189 - Found 1-bit tristate buffer for signal created at line 1194 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1198 - Found 1-bit tristate buffer for signal created at line 1199 - Found 1-bit tristate buffer for signal created at line 1188 - Found 1-bit tristate buffer for signal created at line 1189 - Found 1-bit tristate buffer for signal created at line 1194 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1198 - Found 1-bit tristate buffer for signal created at line 1199 - Found 1-bit tristate buffer for signal created at line 1286 - Found 1-bit tristate buffer for signal created at line 1287 - Found 1-bit tristate buffer for signal created at line 1292 - Found 1-bit tristate buffer for signal created at line 1293 - Found 1-bit tristate buffer for signal created at line 1390 - Found 1-bit tristate buffer for signal created at line 1391 - Found 1-bit tristate buffer for signal created at line 1396 - Found 1-bit tristate buffer for signal created at line 1397 - Found 1-bit tristate buffer for signal created at line 1400 - Found 1-bit tristate buffer for signal created at line 1401 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 5 D-type flip-flop(s). - inferred 17 Multiplexer(s). - inferred 140 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_clock_io.vhd". - TCQ = 100 - CK_WIDTH = 1 - WRLVL = "ON" - DRAM_TYPE = "DDR3" - REFCLK_FREQ = 200.0 - IODELAY_GRP = "IODELAY_MIG" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_ck_iob.vhd". - TCQ = 100 - WRLVL = "ON" - DRAM_TYPE = "DDR3" - REFCLK_FREQ = 200.0 - IODELAY_GRP = "IODELAY_MIG" - Found 1-bit tristate buffer for signal created at line 154 - Found 1-bit tristate buffer for signal created at line 155 - Found 1-bit tristate buffer for signal created at line 160 - Found 1-bit tristate buffer for signal created at line 161 - Summary: - inferred 4 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd". - Set property "MAX_FANOUT = 1" for signal . - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - DRAM_WIDTH = 8 - DM_WIDTH = 8 - DQ_WIDTH = 64 - DQS_WIDTH = 8 - DRAM_TYPE = "DDR3" - nCWL = 5 - WRLVL = "ON" - REFCLK_FREQ = 200.0 - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - USE_DM_PORT = 1 - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. - Set property "MAX_FANOUT = 1" for signal >. - Set property "shreg_extract = no" for signal >. - Set property "equivalent_register_removal = no" for signal >. - Set property "syn_maxfan = 1" for signal >. -WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. - Set property "syn_preserve = true" for signal >. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Summary: - inferred 88 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd". - TCQ = 100 - DRAM_TYPE = "DDR3" - REFCLK_FREQ = 200.0 - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit tristate buffer for signal created at line 232 - Found 1-bit tristate buffer for signal created at line 264 - Found 1-bit tristate buffer for signal created at line 265 - Found 1-bit tristate buffer for signal created at line 270 - Found 1-bit tristate buffer for signal created at line 271 - Found 1-bit tristate buffer for signal created at line 274 - Found 1-bit tristate buffer for signal created at line 275 - Found 1-bit tristate buffer for signal created at line 310 - Found 1-bit tristate buffer for signal created at line 311 - Found 1-bit tristate buffer for signal created at line 316 - Found 1-bit tristate buffer for signal created at line 317 - Found 1-bit tristate buffer for signal created at line 320 - Found 1-bit tristate buffer for signal created at line 321 - Found 1-bit tristate buffer for signal created at line 376 - Summary: - inferred 12 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 14 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd". - TCQ = 100 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit 4-to-1 multiplexer for signal created at line 121. - Found 4-bit 4-to-1 multiplexer for signal created at line 153. - Summary: - inferred 17 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd". - TCQ = 100 - nCWL = 5 - DRAM_TYPE = "DDR3" - WRLVL = "ON" - REFCLK_FREQ = 200.0 - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit 8-to-1 multiplexer for signal created at line 219. - Found 1-bit tristate buffer for signal created at line 451 - Found 1-bit tristate buffer for signal created at line 452 - Found 1-bit tristate buffer for signal created at line 457 - Found 1-bit tristate buffer for signal created at line 458 - Found 1-bit tristate buffer for signal created at line 461 - Found 1-bit tristate buffer for signal created at line 462 - Found 1-bit tristate buffer for signal created at line 490 - Found 1-bit tristate buffer for signal created at line 491 - Found 1-bit tristate buffer for signal created at line 495 - Found 1-bit tristate buffer for signal created at line 498 - Summary: - inferred 14 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 10 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dq_iob.vhd". - TCQ = 100 - nCWL = 5 - DRAM_TYPE = "DDR3" - WRLVL = "ON" - REFCLK_FREQ = 200.0 - IBUF_LPWR_MODE = "OFF" - IODELAY_HP_MODE = "ON" - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit 8-to-1 multiplexer for signal created at line 324. - Found 1-bit tristate buffer for signal created at line 260 - Found 1-bit tristate buffer for signal created at line 562 - Found 1-bit tristate buffer for signal created at line 563 - Found 1-bit tristate buffer for signal created at line 568 - Found 1-bit tristate buffer for signal created at line 569 - Found 1-bit tristate buffer for signal created at line 572 - Found 1-bit tristate buffer for signal created at line 573 - Found 1-bit tristate buffer for signal created at line 628 - Summary: - inferred 26 D-type flip-flop(s). - inferred 5 Multiplexer(s). - inferred 8 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd". - TCQ = 100 - DQ_WIDTH = 64 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - RANK_WIDTH = 1 - nCWL = 5 - REG_CTRL = "OFF" - WRLVL = "ON" - PHASE_DETECT = "ON" - DRAM_TYPE = "DDR3" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Summary: - inferred 108 D-type flip-flop(s). - inferred 124 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_write.vhd". - TCQ = 100 - WRLVL = "ON" - DRAM_TYPE = "DDR3" - DQ_WIDTH = 64 - DQS_WIDTH = 8 - nCWL = 5 - REG_CTRL = "OFF" - RANK_WIDTH = 1 - CLKPERF_DLY_USED = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Register > equivalent to > has been removed - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 20-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit adder for signal created at line 1474. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 137 D-type flip-flop(s). - inferred 145 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_wrlvl.vhd". - TCQ = 100 - DQS_CNT_WIDTH = 3 - DQ_WIDTH = 64 - SHIFT_TBY4_TAP = 8 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - CS_WIDTH = 1 - CAL_WIDTH = "HALF" - DQS_TAP_CNT_INDEX = 39 - SIM_CAL_OPTION = "NONE" - Found 40-bit register for signal >. - Found 16-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 5-bit register for signal <0>>. - Found 5-bit register for signal <1>>. - Found 5-bit register for signal <2>>. - Found 5-bit register for signal <3>>. - Found 5-bit register for signal <4>>. - Found 5-bit register for signal <5>>. - Found 5-bit register for signal <6>>. - Found 5-bit register for signal <7>>. - Found 1-bit register for signal . - Found 8-bit register for signal >. - Found 40-bit register for signal >. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <34>>. - Found 1-bit register for signal <33>>. - Found 1-bit register for signal <32>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <39>>. - Found 1-bit register for signal <38>>. - Found 1-bit register for signal <37>>. - Found 1-bit register for signal <36>>. - Found 1-bit register for signal <35>>. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal >. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 23 | - | Inputs | 10 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 369. - Found 2-bit adder for signal created at line 386. - Found 7-bit adder for signal created at line 678. - Found 7-bit adder for signal created at line 678. - Found 7-bit adder for signal created at line 678. - Found 7-bit adder for signal created at line 678. - Found 5-bit adder for signal created at line 761. - Found 4-bit adder for signal created at line 837. - Found 4-bit adder for signal created at line 838. - Found 4-bit adder for signal created at line 839. - Found 2-bit adder for signal created at line 856. - Found 4-bit adder for signal created at line 926. - Found 5-bit subtractor for signal > created at line 808. - Found 3-bit subtractor for signal <_n1484> created at line 851. - Found 3x4-bit multiplier for signal created at line 678. - Found 1-bit 8-to-1 multiplexer for signal created at line 341. - Found 1-bit 8-to-1 multiplexer for signal created at line 370. - Found 1-bit 8-to-1 multiplexer for signal created at line 370. - Found 1-bit 8-to-1 multiplexer for signal created at line 387. - Found 5-bit 8-to-1 multiplexer for signal created at line 444. - Found 1-bit 8-to-1 multiplexer for signal created at line 780. - Found 1-bit 8-to-1 multiplexer for signal created at line 797. - Found 1-bit 16-to-1 multiplexer for signal created at line 925. - Found 1-bit 16-to-1 multiplexer for signal created at line 926. - Found 1-bit 8-to-1 multiplexer for signal created at line 942. - Found 1-bit 8-to-1 multiplexer for signal created at line 945. - Found 2-bit comparator greater for signal created at line 222 - Found 5-bit comparator greater for signal created at line 365 - Found 2-bit comparator greater for signal created at line 368 - Found 2-bit comparator greater for signal created at line 385 - Found 2-bit comparator greater for signal created at line 442 - Found 4-bit comparator greater for signal created at line 442 - Found 5-bit comparator greater for signal created at line 798 - Found 5-bit comparator greater for signal created at line 811 - Found 4-bit comparator lessequal for signal created at line 818 - Found 3-bit comparator equal for signal created at line 851 - Summary: - inferred 1 Multiplier(s). - inferred 14 Adder/Subtractor(s). - inferred 351 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 319 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_read.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200.0 - DQS_WIDTH = 8 - DQ_WIDTH = 64 - DRAM_WIDTH = 8 - IODELAY_GRP = "IODELAY_MIG" - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd". - Set property "MAX_FANOUT = 10" for signal . - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200.0 - DQS_WIDTH = 8 - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - IODELAY_GRP = "IODELAY_MIG" - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . - Set property "IODELAY_GROUP = IODELAY_MIG" for instance . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal >. - Found 8-bit register for signal . - Found 2-bit register for signal >. - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 9-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 11 | - | Inputs | 4 | - | Outputs | 27 | - | Clock | clk (rising_edge) | - | Reset | rst_oserdes (positive) | - | Reset type | synchronous | - | Reset State | reset_idle | - | Power Up State | reset_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 345. - Found 4-bit adder for signal created at line 358. - Found 4-bit adder for signal created at line 365. - Found 4-bit adder for signal created at line 373. - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 500 - Found 1-bit tristate buffer for signal created at line 505 - Found 1-bit tristate buffer for signal created at line 506 - Found 1-bit tristate buffer for signal created at line 509 - Found 1-bit tristate buffer for signal created at line 510 - Found 1-bit tristate buffer for signal created at line 536 - Found 1-bit tristate buffer for signal created at line 537 - Found 1-bit tristate buffer for signal created at line 541 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<4>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<3>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<2>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<1>> created at line 542 - Found 1-bit tristate buffer for signal .u_odelay_cpt_CNTVALUEIN<0>> created at line 542 - Found 1-bit tristate buffer for signal created at line 544 - Found 1-bit tristate buffer for signal created at line 592 - Found 1-bit tristate buffer for signal created at line 597 - Found 1-bit tristate buffer for signal created at line 598 - Found 1-bit tristate buffer for signal created at line 601 - Found 1-bit tristate buffer for signal created at line 602 - Found 1-bit tristate buffer for signal created at line 629 - Found 1-bit tristate buffer for signal created at line 630 - Found 1-bit tristate buffer for signal created at line 634 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal > created at line 635 - Found 1-bit tristate buffer for signal created at line 637 - Found 1-bit tristate buffer for signal created at line 684 - Found 1-bit tristate buffer for signal created at line 689 - Found 1-bit tristate buffer for signal created at line 690 - Found 1-bit tristate buffer for signal created at line 693 - Found 1-bit tristate buffer for signal created at line 694 - Found 1-bit tristate buffer for signal created at line 722 - Found 1-bit tristate buffer for signal created at line 723 - Found 1-bit tristate buffer for signal created at line 727 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal > created at line 728 - Found 1-bit tristate buffer for signal created at line 730 - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -INFO:Xst:2774 - HDL ADVISOR - MAX_FANOUT property attached to signal rst_oserdes may hinder XST clustering optimizations. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 81 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 140 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdctrl_sync.vhd". - TCQ = 100 - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rddata_sync.vhd". - TCQ = 100 - DQ_WIDTH = 64 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - nDQS_COL0 = 3 - nDQS_COL1 = 5 - nDQS_COL2 = 0 - nDQS_COL3 = 0 - DQS_LOC_COL0 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000" - DQS_LOC_COL1 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000110000001010000010000000011" - DQS_LOC_COL2 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - DQS_LOC_COL3 = "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32-bit register for signal . - Found 256-bit register for signal . - Summary: - inferred 288 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/circ_buffer.vhd". - TCQ = 100 - BUF_DEPTH = 6 - DATA_WIDTH = 108 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit adder for signal created at line 153. - Found 3-bit adder for signal created at line 183. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/circ_buffer.vhd". - TCQ = 100 - BUF_DEPTH = 6 - DATA_WIDTH = 180 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit adder for signal created at line 153. - Found 3-bit adder for signal created at line 183. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd". - TCQ = 100 - nCK_PER_CLK = 2 - CLK_PERIOD = 5000 - REFCLK_FREQ = 200 - DQ_WIDTH = 64 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - DRAM_WIDTH = 8 - DRAM_TYPE = "DDR3" - PD_TAP_REQ = 0 - nCL = 6 - SIM_CAL_OPTION = "NONE" - REG_CTRL = "OFF" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Register equivalent to has been removed - Register equivalent to has been removed - Register equivalent to has been removed - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal >. - Found 5-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 3-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 40-bit register for signal . - Found 40-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 12-bit register for signal . - Found 1-bit register for signal . - Found 12-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 40-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 5-bit register for signal >. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 42 | - | Inputs | 18 | - | Outputs | 18 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 00000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 22 | - | Inputs | 10 | - | Outputs | 6 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 15 | - | Inputs | 9 | - | Outputs | 5 | - | Clock | clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 7-bit subtractor for signal created at line 186. - Found 6-bit subtractor for signal created at line 1528. - Found 7-bit subtractor for signal created at line 1773. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 655. - Found 6-bit adder for signal created at line 752. - Found 6-bit adder for signal created at line 752. - Found 6-bit adder for signal created at line 752. - Found 6-bit adder for signal created at line 752. - Found 4-bit adder for signal created at line 807. - Found 4-bit adder for signal created at line 870. - Found 12-bit adder for signal created at line 1120. - Found 12-bit adder for signal created at line 1158. - Found 3-bit adder for signal created at line 1248. - Found 5-bit adder for signal created at line 1272. - Found 7-bit adder for signal created at line 186. - Found 6-bit adder for signal created at line 1522. - Found 6-bit adder for signal created at line 1528. - Found 3-bit adder for signal created at line 1574. - Found 5-bit adder for signal created at line 1642. - Found 6-bit adder for signal created at line 1707. - Found 6-bit adder for signal created at line 1775. - Found 3-bit adder for signal created at line 1897. - Found 5-bit adder for signal created at line 2037. - Found 3-bit adder for signal created at line 2131. - Found 5-bit adder for signal created at line 2278. - Found 2-bit adder for signal created at line 2288. - Found 6-bit adder for signal created at line 2332. - Found 6-bit adder for signal created at line 2332. - Found 6-bit adder for signal created at line 2332. - Found 6-bit adder for signal created at line 2332. - Found 3-bit adder for signal created at line 2349. - Found 4-bit adder for signal created at line 2369. - Found 5-bit subtractor for signal > created at line 1275. - Found 6-bit subtractor for signal > created at line 1524. - Found 6-bit subtractor for signal > created at line 1602. - Found 5-bit subtractor for signal > created at line 1623. - Found 5-bit subtractor for signal > created at line 201. - Found 5-bit subtractor for signal > created at line 201. - Found 5-bit subtractor for signal > created at line 1724. - Found 5-bit subtractor for signal > created at line 1751. - Found 5-bit subtractor for signal > created at line 2061. - Found 5-bit subtractor for signal > created at line 2420. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 5-bit subtractor for signal > created at line 2431. - Found 3x3-bit multiplier for signal created at line 752. - Found 3x3-bit multiplier for signal created at line 2332. - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal - Found 3-bit 3-to-1 multiplexer for signal created at line 632. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 64-to-1 multiplexer for signal created at line 655. - Found 1-bit 64-to-1 multiplexer for signal created at line 656. - Found 1-bit 64-to-1 multiplexer for signal created at line 657. - Found 1-bit 64-to-1 multiplexer for signal created at line 658. - Found 1-bit 16-to-1 multiplexer for signal created at line 2298. - Found 1-bit 16-to-1 multiplexer for signal created at line 2301. - Found 5-bit comparator lessequal for signal created at line 1521 - Found 6-bit comparator greater for signal created at line 1522 - Found 3-bit comparator greater for signal created at line 1568 - Found 6-bit comparator greater for signal created at line 1611 - Found 6-bit comparator lessequal for signal created at line 1705 - Found 6-bit comparator lessequal for signal created at line 1707 - Found 5-bit comparator lessequal for signal created at line 2012 - Found 3-bit comparator greater for signal created at line 2124 - Found 5-bit comparator lessequal for signal created at line 2322 - Found 3-bit comparator greater for signal created at line 2340 - WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . - Summary: - inferred 8 RAM(s). - inferred 2 Multiplier(s). - inferred 51 Adder/Subtractor(s). - inferred 870 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 559 Multiplexer(s). - inferred 3 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd_top.vhd". - TCQ = 100 - DQS_CNT_WIDTH = 3 - DQS_WIDTH = 8 - PD_LHC_WIDTH = 16 - PD_CALIB_MODE = "PARALLEL" - PD_MSB_SEL = 8 - PD_DQS0_ONLY = "ON" - SIM_CAL_OPTION = "NONE" - DEBUG_PORT = "OFF" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd". - TCQ = 100 - SIM_CAL_OPTION = "NONE" - PD_LHC_WIDTH = 16 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 6-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 8 | - | Inputs | 3 | - | Outputs | 9 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 5-bit adder for signal created at line 488. - Found 6-bit adder for signal created at line 597. - Found 16-bit adder for signal created at line 637. - Found 16-bit adder for signal created at line 659. - Found 4-bit adder for signal created at line 716. - Found 5-bit subtractor for signal > created at line 490. - Found 16x1-bit Read Only RAM for signal - Found 1-bit 16-to-1 multiplexer for signal created at line 243. - Found 1-bit 16-to-1 multiplexer for signal created at line 248. - Summary: - inferred 1 RAM(s). - inferred 5 Adder/Subtractor(s). - inferred 67 D-type flip-flop(s). - inferred 10 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_top.vhd". - TCQ = 100 - APP_DATA_WIDTH = 256 - APP_MASK_WIDTH = 32 - BANK_WIDTH = 3 - COL_WIDTH = 10 - CWL = 5 - ECC = "OFF" - ECC_TEST = "OFF" - ORDERING = "NORM" - RANKS = 1 - RANK_WIDTH = 1 - ROW_WIDTH = 14 - MEM_ADDR_ORDER = "ROW_BANK_COLUMN" - Set property "MAX_FANOUT = 10" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 10-bit register for signal . - Summary: - inferred 11 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_cmd.vhd". - Set property "MAX_FANOUT = 20" for signal . - TCQ = 100 - ADDR_WIDTH = 28 - BANK_WIDTH = 3 - COL_WIDTH = 10 - RANK_WIDTH = 1 - ROW_WIDTH = 14 - RANKS = 1 - MEM_ADDR_ORDER = "ROW_BANK_COLUMN" - Found 1-bit register for signal . - Found 28-bit register for signal . - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . -INFO:Xst:2774 - HDL ADVISOR - MAX_FANOUT property attached to signal app_rdy_r may hinder XST clustering optimizations. - Summary: - inferred 70 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_wr_data.vhd". - Set property "MAX_FANOUT = 20" for signal . - TCQ = 100 - APP_DATA_WIDTH = 256 - APP_MASK_WIDTH = 32 - ECC = "OFF" - ECC_TEST = "OFF" - CWL = 5 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 400. - Found 4-bit adder for signal created at line 424. - Found 4-bit adder for signal created at line 443. - Found 5-bit adder for signal created at line 544. - Found 5-bit subtractor for signal > created at line 542. - Found 5-bit 4-to-1 multiplexer for signal created at line 540. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 339 D-type flip-flop(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_rd_data.vhd". - Set property "MAX_FANOUT = 20". - TCQ = 100 - APP_DATA_WIDTH = 256 - ECC = "OFF" - ORDERING = "NORM" - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). - Found 6-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 6-bit adder for signal created at line 273. - Found 6-bit adder for signal created at line 273. - Found 5-bit adder for signal created at line 546. - Found 4-bit adder for signal created at line 586. - Found 5-bit subtractor for signal created at line 237. - Found 5-bit 4-to-1 multiplexer for signal created at line 555. - Found 5-bit comparator equal for signal created at line 491 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 289 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd". - g_ma_interface_mode = pipelined - g_ma_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd". - g_ma_interface_mode = pipelined - g_ma_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = false - g_master_mode = pipelined - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v". -WARNING:Xst:2898 - Port 'master_adr_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. -WARNING:Xst:2898 - Port 'master_stb_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. -WARNING:Xst:2898 - Port 'master_we_i', unconnected in block instance 'i_rs232_syscon', is tied to GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v". - ADR_DIGITS_PP = 8 - DAT_DIGITS_PP = 8 - QTY_DIGITS_PP = 2 - CMD_BUFFER_SIZE_PP = 64 - CMD_PTR_BITS_PP = 5 - WATCHDOG_TIMER_VALUE_PP = 65000 - WATCHDOG_TIMER_BITS_PP = 16 - RD_FIELDS_PP = 8 - RD_FIELD_COUNT_BITS_PP = 4 - RD_DIGIT_COUNT_BITS_PP = 4 - m1_initial_state = 5'b00000 - m1_send_ok = 5'b00001 - m1_send_prompt = 5'b00010 - m1_check_received_char = 5'b00011 - m1_send_crlf = 5'b00100 - m1_parse_error_indicator_crlf = 5'b00101 - m1_parse_error_indicator = 5'b00110 - m1_ack_error_indicator = 5'b00111 - m1_bg_error_indicator = 5'b01000 - m1_cmd_error_indicator = 5'b01001 - m1_adr_error_indicator = 5'b01010 - m1_dat_error_indicator = 5'b01011 - m1_qty_error_indicator = 5'b01100 - m1_scan_command = 5'b10000 - m1_scan_adr_whitespace = 5'b10001 - m1_get_adr_field = 5'b10010 - m1_scan_dat_whitespace = 5'b10011 - m1_get_dat_field = 5'b10100 - m1_scan_qty_whitespace = 5'b10101 - m1_get_qty_field = 5'b10110 - m1_start_execution = 5'b10111 - m1_request_bus = 5'b11000 - m1_bus_granted = 5'b11001 - m1_execute = 5'b11010 - m1_rd_send_adr_sr = 5'b11011 - m1_rd_send_separator = 5'b11100 - m1_rd_send_dat_sr = 5'b11101 - m1_rd_send_space = 5'b11110 - m1_rd_send_crlf = 5'b11111 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" line 371: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:3015 - Contents of array may be accessed with an index that does not cover the full array size or with a negative index. The RAM size is reduced to the index upper access or for only positive index values. - Found 32x8-bit single-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . -INFO:Xst:1799 - State 00101 is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 29 | - | Transitions | 90 | - | Inputs | 24 | - | Outputs | 21 | - | Clock | clk_i (rising_edge) | - | Reset | reset_i (positive) | - | Reset type | synchronous | - | Reset State | 00000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit adder for signal created at line 472. - Found 32-bit adder for signal created at line 475. - Found 5-bit adder for signal created at line 524. - Found 5-bit adder for signal created at line 526. - Found 5-bit adder for signal created at line 1067. - Found 5-bit adder for signal created at line 1096. - Found 4-bit adder for signal created at line 1168. - Found 4-bit adder for signal created at line 1176. - Found 16-bit adder for signal created at line 1186. - Found 5-bit subtractor for signal > created at line 1066. - Found 32x8-bit Read Only RAM for signal - Found 4x2-bit Read Only RAM for signal <_n0677> - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 1-bit tristate buffer for signal > created at line 458 - Found 8-bit comparator equal for signal created at line 939 - Found 8-bit comparator lessequal for signal created at line 1089 - Found 8-bit comparator lessequal for signal created at line 1089 - Found 8-bit comparator lessequal for signal created at line 1090 - Found 8-bit comparator lessequal for signal created at line 1090 - Summary: - inferred 3 RAM(s). - inferred 9 Adder/Subtractor(s). - inferred 148 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 93 Multiplexer(s). - inferred 32 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v". - CLOCK_FACTOR_PP = 8 - LOG2_MAX_COUNT_PP = 16 - m1_idle = 4'b0000 - m1_measure_0 = 4'b0001 - m1_measure_1 = 4'b0010 - m1_measure_2 = 4'b0011 - m1_measure_3 = 4'b0100 - m1_measure_4 = 4'b0101 - m1_verify_0 = 4'b1000 - m1_verify_1 = 4'b1001 - m1_run = 4'b0110 - m1_verify_failed = 4'b0111 - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 24 | - | Inputs | 6 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | reset_i (positive) | - | Reset type | asynchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 322. - Found 16-bit adder for signal created at line 363. - Found 16-bit comparator equal for signal created at line 423 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 46 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 6 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v". - START_BITS_PP = 1 - DATA_BITS_PP = 8 - STOP_BITS_PP = 1 - CLOCK_FACTOR_PP = 8 - TX_BIT_COUNT_BITS_PP = 4 - m1_idle = 0 - m1_waiting = 1 - m1_sending = 3 - m1_sending_last_bit = 2 - Found 4-bit register for signal . - Found 2-bit register for signal . - Found 10-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 12 | - | Inputs | 4 | - | Outputs | 1 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 00 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 656. - Found 4-bit adder for signal created at line 668. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 18 D-type flip-flop(s). - inferred 3 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v". - START_BITS_PP = 1 - DATA_BITS_PP = 8 - STOP_BITS_PP = 1 - CLOCK_FACTOR_PP = 8 - m1_idle = 0 - m1_start = 1 - m1_shift = 3 - m1_over_run = 2 - m1_under_run = 4 - m1_all_low = 5 - m1_extra_1 = 6 - m1_extra_2 = 7 - m2_data_ready_flag = 1 - m2_data_ready_ack = 0 - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 10-bit register for signal . - Found 8-bit register for signal . - Found 3-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 16 | - | Inputs | 7 | - | Outputs | 5 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 539. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 23 D-type flip-flop(s). - inferred 2 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 224. - Found 32-bit adder for signal created at line 228. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 214. - Found 4-bit comparator equal for signal created at line 165 - Found 5-bit comparator not equal for signal created at line 233 - Found 5-bit comparator not equal for signal created at line 234 - Found 5-bit comparator not equal for signal created at line 235 - Summary: - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 174 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 77: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 22528 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = word - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. - Found 22528x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 15-bit comparator greater for signal created at line 119 - Found 15-bit comparator greater for signal created at line 119 - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 16384 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = byte - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16384x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 54 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 409. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v". - Tp = 1 - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 92. - Found 8-bit subtractor for signal created at line 107. - Found 8-bit comparator greater for signal created at line 91 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v". - Tp = 1 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 25 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit comparator greater for signal created at line 100 - Found 7-bit comparator greater for signal created at line 101 - Found 7-bit comparator greater for signal created at line 138 - Summary: - inferred 6 D-type flip-flop(s). - inferred 3 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861. - Found 32-bit comparator lessequal for signal created at line 388 - Found 32-bit comparator greater for signal created at line 907 - Found 32-bit comparator greater for signal created at line 908 - Summary: - inferred 21 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b10100000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 1'b0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0000000 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0010010 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0001100 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000110 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 6 - RESET_VALUE = 6'b111111 - Found 6-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 4 - RESET_VALUE = 4'b1111 - Found 4-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 3 - RESET_VALUE = 3'b000 - Found 3-bit register for signal . - Summary: - inferred 3 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01100100 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 5 - RESET_VALUE = 5'b00000 - Found 5-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 16 - RESET_VALUE = 16'b0000000000000000 - Found 16-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 16-bit subtractor for signal created at line 356. - Found 3-bit adder for signal created at line 304. - Found 5-bit adder for signal created at line 323. - Found 6-bit adder for signal created at line 417. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 72 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 6-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 255. - Found 6-bit adder for signal created at line 274. - Found 6-bit adder for signal created at line 277. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 20 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v". - Tp = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 344. - Found 6-bit comparator equal for signal created at line 249 - Found 4-bit comparator equal for signal created at line 349 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v". - Tp = 1 - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 17-bit subtractor for signal created at line 170. - Found 32-bit subtractor for signal created at line 170. - Found 16-bit adder for signal created at line 162. - Found 16-bit adder for signal created at line 194. - Found 3-bit adder for signal created at line 215. - Found 32-bit comparator lessequal for signal created at line 170 - Found 16-bit comparator equal for signal created at line 199 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 35 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 187 - Found 7-bit comparator not equal for signal created at line 187 - Summary: - inferred 12 D-type flip-flop(s). - inferred 4 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v". - Tp = 1 - Found 32-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 4-bit comparator greater for signal created at line 114 - Found 4-bit comparator greater for signal created at line 115 - Found 4-bit comparator greater for signal created at line 116 - Found 4-bit comparator greater for signal created at line 117 - Found 4-bit comparator greater for signal created at line 118 - Found 4-bit comparator greater for signal created at line 119 - Found 4-bit comparator greater for signal created at line 120 - Found 4-bit comparator greater for signal created at line 121 - Found 4-bit comparator greater for signal created at line 122 - Found 10-bit comparator equal for signal created at line 139 - Summary: - inferred 20 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit comparator greater for signal created at line 213 - Found 4-bit comparator lessequal for signal created at line 314 - Summary: - inferred 40 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v". - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 116. - Found 16-bit adder for signal created at line 120. - Found 5-bit adder for signal created at line 151. - Found 4-bit adder for signal created at line 173. - Found 16-bit comparator greater for signal created at line 131 - Found 16-bit comparator greater for signal created at line 132 - Found 16-bit comparator equal for signal created at line 134 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v". -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 7-bit register for signal . - Found 7-bit register for signal . - Found 2-bit register for signal . - Found 24-bit register for signal . - Found 9-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 773. - Found 16-bit subtractor for signal created at line 777. - Found 16-bit subtractor for signal created at line 781. - Found 16-bit subtractor for signal created at line 785. - Found 30-bit adder for signal created at line 821. - Found 3-bit adder for signal created at line 960. - Found 30-bit adder for signal created at line 964. - Found 3-bit adder for signal created at line 996. - Found 8-bit adder for signal created at line 1395. - Found 8-bit adder for signal created at line 1398. - Found 2-bit adder for signal created at line 1745. - Found 30-bit adder for signal created at line 2001. - Found 2-bit adder for signal created at line 2098. - Found 2-bit adder for signal created at line 2117. - Found 4x2-bit Read Only RAM for signal - Found 4x6-bit Read Only RAM for signal <_n1545> - Found 1-bit 4-to-1 multiplexer for signal created at line 1630. - Found 8-bit 4-to-1 multiplexer for signal created at line 1648. - Found 8-bit 4-to-1 multiplexer for signal created at line 1660. - Found 16-bit 4-to-1 multiplexer for signal created at line 776. - Found 16-bit comparator greater for signal created at line 627 - Found 16-bit comparator greater for signal created at line 803 - Found 16-bit comparator lessequal for signal created at line 898 - Found 8-bit comparator greater for signal created at line 1062 - Found 16-bit comparator greater for signal created at line 1062 - Found 8-bit comparator lessequal for signal created at line 2417 - Found 1-bit comparator equal for signal created at line 2422 - Found 8-bit comparator greater for signal created at line 2423 - Summary: - inferred 2 RAM(s). - inferred 11 Adder/Subtractor(s). - inferred 461 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v". - we_width = 1 - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v". - DATA_WIDTH = 32 - DEPTH = 256 - CNT_WIDTH = 8 - Set property "syn_ramstyle = no_rw_check" for signal . - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 83. - Found 8-bit adder for signal created at line 114. - Found 8-bit adder for signal created at line 122. - Found 8-bit subtractor for signal > created at line 81. - Summary: - inferred 1 RAM(s). - inferred 3 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 16-bit comparator greater for signal created at line 236 - Found 16-bit comparator greater for signal created at line 236 - Found 6-bit comparator equal for signal created at line 310 - Summary: - inferred 18 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 3 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_3389_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_3389_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 299. - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 320. - Found 16-bit adder for signal created at line 1241. - Found 32-bit 7-to-1 multiplexer for signal <_n0442> created at line 206. - Found 32-bit comparator greater for signal created at line 299 - Found 16-bit comparator greater for signal created at line 320 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 254 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 2 - g_adr_width_B = 32 - g_dat_width_A = 16 - g_dat_width_B = 32 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 32 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 32 - g_adr_width_B = 2 - g_dat_width_A = 32 - g_dat_width_B = 16 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 32 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd". - g_sdb_address = "0000000000000000000000000000000000000000001100000000000000000000" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 15-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 13-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 160-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 11-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 12 | - | Transitions | 41 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | _n0497 (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 11-bit adder for signal created at line 222. - Found 6-bit adder for signal created at line 464. - Found 7-bit adder for signal created at line 472. - Found 16-bit adder for signal created at line 1241. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit 3-to-1 multiplexer for signal created at line 242. - Found 1-bit 3-to-1 multiplexer for signal created at line 242. - Found 11-bit comparator equal for signal created at line 456 - Found 11-bit comparator equal for signal created at line 464 - Found 11-bit comparator equal for signal created at line 472 - Found 11-bit comparator greater for signal created at line 482 - Found 16-bit comparator equal for signal created at line 485 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 499 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 84 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 96 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 106 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd". - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 1 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3405_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 28-bit adder for signal created at line 91. - Found 28-bit adder for signal created at line 102. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 61 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 160 - g_width_OUT = 16 - g_protected = 0 - Found 9-bit register for signal . - Found 160-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 170 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 15-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 29 | - | Inputs | 10 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3450_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State ipv4_chksum is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 15 | - | Transitions | 34 | - | Inputs | 13 | - | Outputs | 12 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_parser_reset_OR_16605_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | eth | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 14-bit subtractor for signal created at line 426. - Found 11-bit adder for signal created at line 291. - Found 12-bit adder for signal created at line 405. - Found 12-bit adder for signal created at line 426. - Found 13-bit adder for signal created at line 426. - Found 17-bit adder for signal created at line 504. - Found 15-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 504. - Found 11-bit comparator equal for signal created at line 347 - Found 12-bit comparator equal for signal created at line 405 - Found 12-bit comparator greater for signal created at line 420 - Found 14-bit comparator equal for signal created at line 426 - Found 16-bit comparator equal for signal created at line 447 - Found 11-bit comparator greater for signal created at line 520 - Found 11-bit comparator equal for signal created at line 529 - Summary: - inferred 8 Adder/Subtractor(s). - inferred 244 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 14 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 160 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 160-bit register for signal . - Found 4-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 166 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 15-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . -INFO:Xst:1799 - State zero_pad_wait is never reached in FSM . -INFO:Xst:1799 - State error is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 716 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3494_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 19 | - | Transitions | 145 | - | Inputs | 19 | - | Outputs | 16 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_3494_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit subtractor for signal > created at line 1308. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 4-bit comparator greater for signal created at line 363 - Found 16-bit comparator greater for signal created at line 504 - Found 8-bit comparator greater for signal created at line 584 - Found 8-bit comparator greater for signal created at line 619 - Found 16-bit comparator equal for signal created at line 659 - Found 4-bit comparator greater for signal created at line 716 - Found 8-bit comparator greater for signal created at line 986 - Summary: - inferred 13 Adder/Subtractor(s). - inferred 367 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 65 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 32 - g_size = 16 - g_show_ahead = true - g_with_empty = true - g_with_full = true - g_with_almost_empty = true - g_with_almost_full = true - g_with_count = true - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 - g_register_flag_outputs = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 165: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd". - g_data_width = 32 - g_size = 16 - g_dual_clock = false - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 - Found 4-bit subtractor for signal created at line 64. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd". - g_sdb_address = "0000000000000000000000000000000000000000001100000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 8-to-1 multiplexer for signal <_n0271> created at line 137. - Found 32-bit 8-to-1 multiplexer for signal <_n0289> created at line 168. - Summary: - inferred 328 D-type flip-flop(s). - inferred 22 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (8.88,8.88,8.88,8.88) - g_use_clk_chains = "1111" - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (8.88,8.88,8.88,8.88) - g_use_clk_chains = "1111" - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 547: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 584: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 626: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 938: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1022: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1059: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1059: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1094: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1130: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" line 1168: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 1-bit tristate buffer for signal created at line 1043 - Found 1-bit tristate buffer for signal created at line 1046 - Found 1-bit tristate buffer for signal created at line 1115 - Found 1-bit tristate buffer for signal created at line 1118 - Found 1-bit tristate buffer for signal created at line 1151 - Found 1-bit tristate buffer for signal created at line 1154 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 6 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd". - g_pipeline = 4 - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010111000010000101111011110001010100000000000000000000000000000001001000000001001100100000000010000100110001001110010011000101001101011111010001100100110101000011001100010011001100110000010011010101111101010010010001010100011101010011001000000010000000000001") - g_sdb_addr = "00000000000000000000100000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000001000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100000000000000000000000000000000000000000000000011001110010000100001001000111100010101000100001100000000000000000000000000000001001000000001001000010001001010010101011101000010001011010100100100110010010000110010110101001101011000010111001101110100011001010111001000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000000000000000000000000000000000000000000000000110011100100001000010010001111000101010001000011000000000000000000000000000000010010000000010010000100010010100101010111010000100010110101001001001100100100001100101101010011010110000101110011011101000110010101110010001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010111000010000101111011110001010100000000000000000000000000000001001000000001001100100000000010000100110001001110010011000101001101011111010001100100110101000011001100010011001100110000010011010101111101010010010001010100011101010011001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 6 - g_registered = true - g_address = ("00000000000000000000100000000000","00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000111000000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 7-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 7 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 17-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 297 D-type flip-flop(s). - inferred 35 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd". - g_with_var_loadable = true - g_with_variable = false - g_with_fn_dly_select = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Summary: - inferred 12 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd". - g_with_clk_single_ended = true - g_with_data_single_ended = true - g_with_data_sdr = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clk_period_values = (8.88,8.88,8.88,8.88) - g_use_clk_chains = "1111" - g_clk_default_dly = (5,5,5,5) - g_use_data_chains = "1111" - g_map_clk_data_chains = (-1,-1,-1,-1) - g_data_default_dly = (9,9,9,9) - g_ref_clk = 1 - g_mmcm_param = (1,8.0,8.88,8.0,4) - g_with_bufio_clk_chains = "0000" - g_with_bufr_clk_chains = "1111" - g_with_data_sdr = true - g_with_fn_dly_select = true - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 195: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.88 - g_default_adc_clk_delay = 5 - g_with_ref_clk = false - g_mmcm_param = (1,8.0,8.88,8.0,4) - g_with_fn_dly_select = true - g_with_bufio = false - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 8.88 - g_default_adc_clk_delay = 5 - g_with_ref_clk = true - g_mmcm_param = (1,8.0,8.88,8.0,4) - g_with_fn_dly_select = true - g_with_bufio = false - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd". - g_delay_type = "VAR_LOADABLE" - g_default_adc_data_delay = 9 - g_with_data_sdr = true - g_with_fn_dly_select = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Summary: - inferred 81 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 16 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd". - g_data_width = 16 - g_size = 16 - g_dual_clock = true - g_almost_empty_threshold = 8 - g_almost_full_threshold = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 64 - g_size = 16 - g_show_ahead = false - g_with_empty = true - g_with_full = true - g_with_almost_empty = false - g_with_almost_full = false - g_with_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 - g_register_flag_outputs = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 165: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd". - g_data_width = 64 - g_size = 16 - g_dual_clock = false - g_almost_empty_threshold = 8 - g_almost_full_threshold = 8 - Found 4-bit subtractor for signal created at line 64. - Summary: - inferred 1 Adder/Subtractor(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd". - ARST_LVL = '0' -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit 8-to-1 multiplexer for signal created at line 191. - Summary: - inferred 54 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 26 | - | Inputs | 9 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | st_idle | - | Power Up State | st_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 3-bit subtractor for signal > created at line 1308. - Found 4-bit 6-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 34 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 14-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 64 | - | Inputs | 6 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit subtractor for signal > created at line 1308. - Found 14-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 57 D-type flip-flop(s). - inferred 26 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" line 74: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 12-to-1 multiplexer for signal created at line 126. - Summary: - inferred 80 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v". - Tp = 1 - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 80. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v". - Tp = 1 - Found 12-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 91. - Found 8-bit subtractor for signal created at line 91. - Found 8-bit subtractor for signal created at line 92. - Found 8-bit adder for signal created at line 92. - Found 12-bit adder for signal created at line 116. - Found 1-bit 128-to-1 multiplexer for signal created at line 164. - Found 1-bit 128-to-1 multiplexer for signal created at line 293. - Found 1-bit 128-to-1 multiplexer for signal created at line 294. - Found 12-bit comparator lessequal for signal created at line 137 - Found 12-bit comparator greater for signal created at line 139 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 407 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd". - g_wbs_interface_width = narrow2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd". - g_data_width = 25 - g_size = 32 - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 5-bit adder for signal created at line 150. - Found 5-bit subtractor for signal > created at line 152. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd". - g_size = 32 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd". - g_min_pulse_width = 1 - g_clk_frequency = 130 - g_output_polarity = '0' - g_output_retrig = false - g_output_length = 1 - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 20000000 - Found 25-bit register for signal . - Found 1-bit register for signal . - Found 25-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 26 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 84: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 119: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 158: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 4 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_sdb_addr = "00000000000000000000010000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000011111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_3', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_address = ("00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000011000000000","00000000000000000000011111110000","00000000000000000000011100000000","00000000000000000000011100000000","00000000000000000000011100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 47 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_3829_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_3839_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 5 | - | Inputs | 1 | - | Outputs | 1 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_3839_o (positive) | - | Reset type | synchronous | - | Reset State | 00 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 24-bit register for signal . - Found 24-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 90 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_acq_addr_width = 28 - g_acq_num_channels = 5 - g_acq_channels = (("10000000"),("10000000"),("10000000"),("10000000"),("01000000")) - g_ddr_payload_width = 256 - g_ddr_dq_width = 64 - g_ddr_addr_width = 28 - g_multishot_ram_size = 2048 - g_fifo_fc_size = 256 - g_sim_readback = false -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_acq_addr_width = 28 - g_acq_num_channels = 5 - g_acq_channels = (("10000000"),("10000000"),("10000000"),("10000000"),("01000000")) - g_ddr_payload_width = 256 - g_ddr_dq_width = 64 - g_ddr_addr_width = 28 - g_multishot_ram_size = 2048 - g_fifo_fc_size = 256 - g_sim_readback = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 346: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 444: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 739: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 739: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd" line 873: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit adder for signal created at line 645. - Found 1-bit 5-to-1 multiplexer for signal created at line 496. - Found 1-bit 5-to-1 multiplexer for signal created at line 497. - Found 128-bit 5-to-1 multiplexer for signal created at line 502. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 51 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 14-bit register for signal . - Found 15-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 10-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 564 D-type flip-flop(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 30 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | fs_clk_i (rising_edge) | - | Reset | fs_rst_n_i_INV_3992_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 1241. - Found 16-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 123 D-type flip-flop(s). - inferred 7 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd". - g_data_width = 128 - g_multishot_ram_size = 2048 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. - Found 11-bit register for signal . - Found 11-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 11-bit adder for signal created at line 1241. - Found 11-bit adder for signal created at line 1241. - Found 11-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 200. - Found 11-bit comparator equal for signal created at line 202 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 46 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 7 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 128 - g_size = 2048 - g_with_byte_enable = false - g_addr_conflict_resolution = "read_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 128 - g_size = 2048 - g_with_byte_enable = false - g_addr_conflict_resolution = "read_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 2048x128-bit dual-port RAM for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 256 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd". - g_data_width = 128 - g_addr_width = 28 - g_fifo_size = 256 - g_fc_pipe_size = 4 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 289: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 368: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 368: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 380: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 428: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 452: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd" line 474: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 128-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 32-bit comparator not equal for signal created at line 280 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 227 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 128 - g_size = 256 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = true - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd". - g_data_width = 128 - g_size = 256 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = true - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal >. - Set property "ASYNC_REG = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 256x128-bit dual-port RAM for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 128-bit register for signal . - Found 9-bit adder for signal created at line 1241. - Found 9-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 248. - Found 9-bit subtractor for signal > created at line 262. - Found 9-bit comparator equal for signal created at line 209 - Found 9-bit comparator equal for signal created at line 209 - Found 8-bit comparator equal for signal created at line 219 - Found 8-bit comparator equal for signal created at line 223 - Found 9-bit comparator lessequal for signal created at line 263 - Summary: - inferred 1 RAM(s). - inferred 4 Adder/Subtractor(s). - inferred 222 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd". - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 11 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd". - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 32-bit comparator equal for signal created at line 134 - Found 16-bit comparator equal for signal created at line 191 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 98 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd". - g_data_width = 128 - g_pkt_size_width = 32 - g_addr_width = 28 - g_pipe_size = 4 - Found 32-bit register for signal . - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 128-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 128-bit register for signal . - Found 2-bit register for signal . - Found 28-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 2-bit subtractor for signal > created at line 1308. -INFO:Xst:3019 - HDL ADVISOR - 512 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 128-bit 4-to-1 multiplexer for signal created at line 388. - Found 28-bit 4-to-1 multiplexer for signal created at line 389. - Found 2-bit 4-to-1 multiplexer for signal created at line 390. - Found 1-bit 4-to-1 multiplexer for signal created at line 391. - Found 32-bit comparator equal for signal created at line 247 - Found 2-bit comparator not equal for signal created at line 408 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 869 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 19 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd". - g_acq_addr_width = 28 - g_acq_num_channels = 5 - g_acq_channels = (("10000000"),("10000000"),("10000000"),("10000000"),("01000000")) - g_ddr_payload_width = 256 - g_ddr_dq_width = 64 - g_ddr_addr_width = 28 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 545: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 595: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 637: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 637: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd" line 637: Output port of the instance is unconnected or connected to loadless signal. - Found 16-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 256-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 28-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit subtractor for signal created at line 399. - Found 4-bit adder for signal created at line 438. - Found 4-bit adder for signal created at line 1241. - Found 28-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 418. - Found 9-bit subtractor for signal > created at line 427. - Found 9-bit subtractor for signal > created at line 438. - Found 8x3-bit Read Only RAM for signal - Found 8x2-bit Read Only RAM for signal - Found 8x1-bit Read Only RAM for signal > - Found 32-bit 3-to-1 multiplexer for signal created at line 329. - Found 3-bit 3-to-1 multiplexer for signal created at line 419. - Found 1-bit 4-to-1 multiplexer for signal created at line 509. - Found 5-bit comparator equal for signal created at line 399 - Summary: - inferred 3 RAM(s). - inferred 7 Adder/Subtractor(s). - inferred 377 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 262 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd". - g_data_width = 1 - g_pkt_size_width = 32 - g_addr_width = 28 - g_pipe_size = 4 - Found 32-bit register for signal . - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 28-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 28-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 2-bit subtractor for signal > created at line 1308. - Found 1-bit 4-to-1 multiplexer for signal > created at line 388. - Found 28-bit 4-to-1 multiplexer for signal created at line 389. - Found 2-bit 4-to-1 multiplexer for signal created at line 390. - Found 1-bit 4-to-1 multiplexer for signal created at line 391. - Found 32-bit comparator equal for signal created at line 247 - Found 2-bit comparator equal for signal <_n0276> created at line 408 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 234 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd". - g_data_width = 288 - g_pkt_size_width = 32 - g_addr_width = 1 - g_pipe_size = 4 - Found 32-bit register for signal . - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 288-bit register for signal >. - Found 1-bit register for signal >. - Found 2-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 288-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 32-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 2-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 2-bit subtractor for signal > created at line 1308. -INFO:Xst:3019 - HDL ADVISOR - 1152 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 1-bit 4-to-1 multiplexer for signal > created at line 389. - Found 2-bit 4-to-1 multiplexer for signal created at line 390. - Found 1-bit 4-to-1 multiplexer for signal created at line 391. - Found 32-bit comparator equal for signal created at line 247 - Found 2-bit comparator equal for signal <_n0276> created at line 408 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 1534 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 35 - 128x32-bit single-port Read Only RAM : 2 - 16384x32-bit dual-port RAM : 1 - 16x1-bit single-port Read Only RAM : 1 - 16x32-bit dual-port RAM : 1 - 2048x128-bit dual-port RAM : 2 - 22528x32-bit dual-port RAM : 1 - 256x128-bit dual-port RAM : 1 - 256x32-bit dual-port RAM : 4 - 256x32-bit single-port Read Only RAM : 1 - 32x8-bit single-port RAM : 1 - 32x8-bit single-port Read Only RAM : 1 - 4x2-bit single-port Read Only RAM : 2 - 4x3-bit single-port Read Only RAM : 1 - 4x6-bit single-port Read Only RAM : 1 - 8x1-bit single-port Read Only RAM : 11 - 8x18-bit single-port Read Only RAM : 2 - 8x2-bit single-port Read Only RAM : 1 - 8x3-bit single-port Read Only RAM : 1 -# Multipliers : 3 - 3x3-bit multiplier : 2 - 4x3-bit multiplier : 1 -# Adders/Subtractors : 496 - 1-bit adder : 10 - 10-bit adder : 6 - 10-bit addsub : 1 - 10-bit subtractor : 4 - 11-bit adder : 3 - 11-bit addsub : 1 - 11-bit subtractor : 2 - 12-bit adder : 8 - 12-bit subtractor : 1 - 13-bit adder : 3 - 13-bit subtractor : 2 - 14-bit subtractor : 4 - 15-bit subtractor : 3 - 16-bit adder : 40 - 16-bit subtractor : 10 - 17-bit adder : 10 - 17-bit subtractor : 1 - 18-bit subtractor : 2 - 2-bit adder : 48 - 2-bit addsub : 4 - 2-bit subtractor : 41 - 20-bit subtractor : 1 - 22-bit adder : 1 - 24-bit adder : 1 - 25-bit subtractor : 1 - 26-bit adder : 2 - 28-bit adder : 2 - 29-bit adder : 1 - 3-bit adder : 19 - 3-bit subtractor : 14 - 30-bit adder : 5 - 30-bit subtractor : 2 - 32-bit adder : 19 - 32-bit subtractor : 9 - 4-bit adder : 43 - 4-bit subtractor : 5 - 48-bit adder : 12 - 48-bit subtractor : 2 - 5-bit adder : 19 - 5-bit addsub : 11 - 5-bit subtractor : 15 - 57-bit adder : 2 - 6-bit adder : 25 - 6-bit addsub : 2 - 6-bit subtractor : 7 - 64-bit subtractor : 2 - 7-bit adder : 8 - 7-bit subtractor : 2 - 8-bit adder : 30 - 8-bit addsub : 3 - 8-bit subtractor : 9 - 9-bit adder : 5 - 9-bit subtractor : 13 -# Registers : 5857 - 1-bit register : 4216 - 10-bit register : 20 - 11-bit register : 9 - 12-bit register : 17 - 128-bit register : 22 - 13-bit register : 12 - 14-bit register : 11 - 15-bit register : 5 - 16-bit register : 96 - 160-bit register : 3 - 17-bit register : 13 - 2-bit register : 208 - 20-bit register : 2 - 22-bit register : 1 - 24-bit register : 2 - 25-bit register : 2 - 256-bit register : 9 - 28-bit register : 16 - 288-bit register : 5 - 29-bit register : 1 - 3-bit register : 85 - 30-bit register : 7 - 31-bit register : 2 - 32-bit register : 98 - 33-bit register : 4 - 36-bit register : 71 - 4-bit register : 384 - 40-bit register : 6 - 48-bit register : 8 - 5-bit register : 98 - 55-bit register : 1 - 6-bit register : 170 - 64-bit register : 66 - 66-bit register : 2 - 7-bit register : 16 - 72-bit register : 5 - 8-bit register : 138 - 9-bit register : 25 - 96-bit register : 1 -# Comparators : 187 - 1-bit comparator equal : 5 - 10-bit comparator equal : 2 - 11-bit comparator equal : 6 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 2 - 12-bit comparator lessequal : 3 - 14-bit comparator equal : 5 - 15-bit comparator greater : 2 - 16-bit comparator equal : 9 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 2-bit comparator equal : 6 - 2-bit comparator greater : 7 - 2-bit comparator not equal : 1 - 3-bit comparator equal : 5 - 3-bit comparator greater : 3 - 3-bit comparator lessequal : 5 - 3-bit comparator not equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 32-bit comparator not equal : 1 - 4-bit comparator equal : 10 - 4-bit comparator greater : 13 - 4-bit comparator lessequal : 7 - 5-bit comparator equal : 2 - 5-bit comparator greater : 7 - 5-bit comparator lessequal : 4 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 6-bit comparator greater : 4 - 6-bit comparator lessequal : 5 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 20 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 5 - 9-bit comparator equal : 2 - 9-bit comparator greater : 2 - 9-bit comparator lessequal : 2 -# Multiplexers : 8378 - 1-bit 128-to-1 multiplexer : 3 - 1-bit 16-to-1 multiplexer : 6 - 1-bit 2-to-1 multiplexer : 6481 - 1-bit 3-to-1 multiplexer : 7 - 1-bit 4-to-1 multiplexer : 18 - 1-bit 5-to-1 multiplexer : 2 - 1-bit 6-to-1 multiplexer : 1 - 1-bit 64-to-1 multiplexer : 32 - 1-bit 8-to-1 multiplexer : 298 - 10-bit 2-to-1 multiplexer : 40 - 11-bit 2-to-1 multiplexer : 4 - 12-bit 2-to-1 multiplexer : 12 - 128-bit 2-to-1 multiplexer : 16 - 128-bit 4-to-1 multiplexer : 1 - 128-bit 5-to-1 multiplexer : 1 - 13-bit 2-to-1 multiplexer : 3 - 14-bit 2-to-1 multiplexer : 18 - 15-bit 2-to-1 multiplexer : 4 - 16-bit 2-to-1 multiplexer : 63 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 119 - 2-bit 4-to-1 multiplexer : 3 - 20-bit 2-to-1 multiplexer : 1 - 21-bit 2-to-1 multiplexer : 12 - 22-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 6 - 25-bit 2-to-1 multiplexer : 1 - 28-bit 2-to-1 multiplexer : 11 - 28-bit 4-to-1 multiplexer : 2 - 29-bit 2-to-1 multiplexer : 2 - 3-bit 2-to-1 multiplexer : 106 - 3-bit 3-to-1 multiplexer : 2 - 30-bit 2-to-1 multiplexer : 7 - 31-bit 2-to-1 multiplexer : 1 - 32-bit 12-to-1 multiplexer : 1 - 32-bit 2-to-1 multiplexer : 153 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 1 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 33-bit 2-to-1 multiplexer : 6 - 36-bit 2-to-1 multiplexer : 133 - 4-bit 2-to-1 multiplexer : 102 - 4-bit 4-to-1 multiplexer : 144 - 4-bit 6-to-1 multiplexer : 3 - 40-bit 2-to-1 multiplexer : 7 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 48 - 5-bit 8-to-1 multiplexer : 1 - 6-bit 2-to-1 multiplexer : 90 - 64-bit 2-to-1 multiplexer : 117 - 7-bit 2-to-1 multiplexer : 7 - 72-bit 2-to-1 multiplexer : 1 - 8-bit 2-to-1 multiplexer : 244 - 8-bit 4-to-1 multiplexer : 2 - 8-bit 8-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 14 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 7 - 1-bit shifter logical left : 7 -# Tristates : 1029 - 1-bit tristate buffer : 1027 - 8-bit tristate buffer : 2 -# FSMs : 64 -# Xors : 221 - 1-bit xor2 : 104 - 1-bit xor3 : 14 - 1-bit xor4 : 2 - 32-bit xor2 : 99 - 8-bit xor2 : 2 - -========================================================================= -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -WARNING:Xst:453 - Model 'SRLC32E' has different characteristics in destination library, some ports are missing: - Q31 -Reading core <../../../platform/virtex6/chipscope/ila/chipscope_ila.ngc>. -Reading core <../../../platform/virtex6/chipscope/icon_6_port/chipscope_icon_6_port.ngc>. -Reading core <../../../ip_cores/pcie/ml605/prime_FIFO_plain.ngc>. -Reading core <../../../ip_cores/pcie/ml605/sfifo_15x128.ngc>. -Reading core <../../../ip_cores/pcie/ml605/mbuf_128x72.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 21 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 21 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 12 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 14 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 34 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 18-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 3-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM > will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 2048-word x 128-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . - The following adders/subtractors are grouped into adder tree : - in block , in block , in block . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 6-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 128-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 128-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | enB | connected to signal | high | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 3-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal <4:2>> | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 8-bit | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 8-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:2774 - HDL ADVISOR - MAX_FANOUT property attached to signal rst_final may hinder XST clustering optimizations. -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 35 - 128x32-bit single-port block Read Only RAM : 2 - 16384x32-bit dual-port block RAM : 1 - 16x1-bit single-port distributed Read Only RAM : 1 - 16x32-bit dual-port block RAM : 1 - 2048x128-bit dual-port block RAM : 2 - 22528x32-bit dual-port block RAM : 1 - 256x128-bit dual-port block RAM : 1 - 256x32-bit dual-port block RAM : 3 - 256x32-bit single-port block RAM : 1 - 256x32-bit single-port block Read Only RAM : 1 - 32x8-bit single-port distributed RAM : 1 - 32x8-bit single-port distributed Read Only RAM : 1 - 4x2-bit single-port distributed Read Only RAM : 2 - 4x3-bit single-port distributed Read Only RAM : 1 - 4x6-bit single-port distributed Read Only RAM : 1 - 8x1-bit single-port distributed Read Only RAM : 11 - 8x18-bit single-port distributed Read Only RAM : 2 - 8x2-bit single-port distributed Read Only RAM : 1 - 8x3-bit single-port distributed Read Only RAM : 1 -# Multipliers : 3 - 3x3-bit multiplier : 2 - 4x3-bit multiplier : 1 -# Adders/Subtractors : 298 - 1-bit adder : 9 - 1-bit subtractor : 5 - 10-bit adder : 4 - 10-bit addsub : 1 - 10-bit subtractor : 4 - 11-bit adder : 1 - 11-bit addsub : 1 - 11-bit subtractor : 2 - 12-bit adder : 5 - 12-bit subtractor : 1 - 13-bit adder : 2 - 13-bit subtractor : 2 - 14-bit adder : 1 - 14-bit subtractor : 3 - 16-bit adder : 28 - 16-bit subtractor : 4 - 17-bit adder : 9 - 17-bit subtractor : 3 - 2-bit adder : 16 - 2-bit adder carry in : 1 - 2-bit subtractor : 26 - 22-bit adder : 1 - 26-bit adder : 2 - 28-bit adder : 2 - 3-bit adder : 4 - 3-bit subtractor : 12 - 30-bit adder : 3 - 30-bit subtractor : 2 - 32-bit adder : 10 - 32-bit subtractor : 9 - 4-bit adder : 10 - 4-bit subtractor : 4 - 48-bit adder : 12 - 48-bit subtractor : 2 - 5-bit adder : 7 - 5-bit addsub : 3 - 5-bit subtractor : 13 - 57-bit adder : 2 - 6-bit adder : 25 - 6-bit adder carry in : 1 - 6-bit addsub : 1 - 6-bit subtractor : 5 - 64-bit subtractor : 2 - 7-bit adder : 4 - 7-bit subtractor : 3 - 8-bit adder : 16 - 8-bit subtractor : 3 - 9-bit adder : 4 - 9-bit subtractor : 8 -# Adder Trees : 1 - 2-bit / 4-inputs adder tree : 1 -# Counters : 189 - 1-bit down counter : 4 - 1-bit up counter : 1 - 10-bit up counter : 2 - 11-bit up counter : 1 - 12-bit up counter : 3 - 15-bit down counter : 3 - 16-bit down counter : 6 - 16-bit up counter : 10 - 2-bit down counter : 6 - 2-bit up counter : 24 - 2-bit updown counter : 4 - 20-bit down counter : 1 - 24-bit up counter : 1 - 25-bit down counter : 1 - 29-bit up counter : 1 - 3-bit down counter : 2 - 3-bit up counter : 16 - 30-bit up counter : 2 - 32-bit up counter : 9 - 4-bit down counter : 1 - 4-bit up counter : 32 - 5-bit down counter : 2 - 5-bit up counter : 16 - 5-bit updown counter : 8 - 6-bit down counter : 3 - 6-bit up counter : 1 - 6-bit updown counter : 1 - 7-bit up counter : 1 - 8-bit down counter : 4 - 8-bit up counter : 12 - 8-bit updown counter : 3 - 9-bit down counter : 5 - 9-bit up counter : 3 -# Accumulators : 8 - 11-bit up accumulator : 2 - 16-bit up accumulator : 2 - 5-bit updown loadable accumulator : 2 - 6-bit up accumulator : 1 - 6-bit up loadable accumulator : 1 -# Registers : 28177 - Flip-Flops : 28177 -# Comparators : 187 - 1-bit comparator equal : 5 - 10-bit comparator equal : 2 - 11-bit comparator equal : 6 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 2 - 12-bit comparator lessequal : 3 - 14-bit comparator equal : 5 - 15-bit comparator greater : 2 - 16-bit comparator equal : 9 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 2-bit comparator equal : 6 - 2-bit comparator greater : 7 - 2-bit comparator not equal : 1 - 3-bit comparator equal : 5 - 3-bit comparator greater : 3 - 3-bit comparator lessequal : 5 - 3-bit comparator not equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 32-bit comparator not equal : 1 - 4-bit comparator equal : 10 - 4-bit comparator greater : 13 - 4-bit comparator lessequal : 7 - 5-bit comparator equal : 2 - 5-bit comparator greater : 7 - 5-bit comparator lessequal : 4 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 6-bit comparator greater : 4 - 6-bit comparator lessequal : 5 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 20 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 5 - 9-bit comparator equal : 2 - 9-bit comparator greater : 2 - 9-bit comparator lessequal : 2 -# Multiplexers : 9193 - 1-bit 12-to-1 multiplexer : 32 - 1-bit 128-to-1 multiplexer : 3 - 1-bit 16-to-1 multiplexer : 6 - 1-bit 2-to-1 multiplexer : 7154 - 1-bit 3-to-1 multiplexer : 23 - 1-bit 4-to-1 multiplexer : 306 - 1-bit 5-to-1 multiplexer : 2 - 1-bit 6-to-1 multiplexer : 1 - 1-bit 64-to-1 multiplexer : 32 - 1-bit 8-to-1 multiplexer : 322 - 10-bit 2-to-1 multiplexer : 37 - 11-bit 2-to-1 multiplexer : 3 - 12-bit 2-to-1 multiplexer : 11 - 128-bit 2-to-1 multiplexer : 16 - 128-bit 4-to-1 multiplexer : 1 - 128-bit 5-to-1 multiplexer : 1 - 13-bit 2-to-1 multiplexer : 3 - 14-bit 2-to-1 multiplexer : 18 - 15-bit 2-to-1 multiplexer : 2 - 16-bit 2-to-1 multiplexer : 47 - 2-bit 2-to-1 multiplexer : 109 - 2-bit 4-to-1 multiplexer : 3 - 21-bit 2-to-1 multiplexer : 12 - 22-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 5 - 28-bit 2-to-1 multiplexer : 11 - 28-bit 4-to-1 multiplexer : 2 - 29-bit 2-to-1 multiplexer : 1 - 3-bit 2-to-1 multiplexer : 98 - 3-bit 3-to-1 multiplexer : 2 - 30-bit 2-to-1 multiplexer : 5 - 31-bit 2-to-1 multiplexer : 1 - 32-bit 2-to-1 multiplexer : 139 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 1 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 33-bit 2-to-1 multiplexer : 6 - 36-bit 2-to-1 multiplexer : 132 - 4-bit 2-to-1 multiplexer : 83 - 4-bit 4-to-1 multiplexer : 72 - 4-bit 6-to-1 multiplexer : 3 - 40-bit 2-to-1 multiplexer : 7 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 39 - 5-bit 8-to-1 multiplexer : 1 - 6-bit 2-to-1 multiplexer : 85 - 64-bit 2-to-1 multiplexer : 112 - 7-bit 2-to-1 multiplexer : 6 - 72-bit 2-to-1 multiplexer : 1 - 8-bit 2-to-1 multiplexer : 209 - 8-bit 4-to-1 multiplexer : 2 - 9-bit 2-to-1 multiplexer : 9 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 7 - 1-bit shifter logical left : 7 -# FSMs : 64 -# Xors : 221 - 1-bit xor2 : 104 - 1-bit xor3 : 14 - 1-bit xor4 : 2 - 32-bit xor2 : 99 - 8-bit xor2 : 2 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch _0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 47 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 15 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - st_idle | 000 - st_start | 001 - st_read | 010 - st_write | 011 - st_ack | 100 - st_stop | 101 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 00000 - start_a | 00001 - start_b | 00010 - start_c | 00011 - start_d | 00100 - start_e | 00101 - stop_a | 00110 - stop_b | 00111 - stop_c | 01000 - stop_d | 01001 - rd_a | 01010 - rd_b | 01011 - rd_c | 01100 - rd_d | 01101 - wr_a | 01110 - wr_b | 01111 - wr_c | 10000 - wr_d | 10001 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -Optimizing FSM on signal with sequential encoding. -Optimizing FSM on signal with sequential encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 00001 | 000 - 00010 | 001 - 00100 | 010 - 01000 | 011 - 10000 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0001 | 00 - 0010 | 01 - 0100 | 11 - 1000 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0011 | 000 - 0110 | 001 - 0111 | 011 - 0001 | 010 - 1000 | 110 - 1001 | 111 - 0010 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. ----------------------------------------------------- - State | Encoding ----------------------------------------------------- - 0000000000000100000000000 | 000000000000000000001 - 0010000000000000000000000 | 000000000000000000010 - 0000100000000000000000000 | 000000000000000000100 - 0100000000000000000000000 | 000000000000000001000 - 1000000000000000000000000 | 000000000000000010000 - 0000000010000000000000000 | 000000000000000100000 - 0000000100000000000000000 | 000000000000001000000 - 0000000000000000000000010 | 000000000000010000000 - 0000001000000000000000000 | 000000000000100000000 - 0000000000000000000000001 | 000000000001000000000 - 0000000000010000000000000 | 000000000010000000000 - 0000000000000000010000000 | 000000000100000000000 - 0000010000000000000000000 | 000000001000000000000 - 0000000000000000000000100 | 000000010000000000000 - 0000000000000000000001000 | 000000100000000000000 - 0000000000000000001000000 | 000001000000000000000 - 0000000000100000000000000 | 000010000000000000000 - 0001000000000000000000000 | 000100000000000000000 - 0000000000000000100000000 | 001000000000000000000 - 0000000000000001000000000 | 010000000000000000000 - 0000000000000010000000000 | 100000000000000000000 ----------------------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. --------------------------- - State | Encoding --------------------------- - rdst_reset | 0000 - rdst_idle | 0001 - rdst_acc_req | 0010 - rdst_b4_la | 0011 - rdst_la | 0100 - rdst_cmd | 0101 - rdst_data | 0110 - rdst_wait | 0111 - rdst_last_qw | 1000 --------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------------------- - State | Encoding -------------------------------- - wrst_bram_reset | 000 - wrst_idle | 001 - wrst_acc_req | 011 - wrst_address | 010 - wrst_1st_data | 110 - wrst_1st_data_b2b | unreached - wrst_more_data | 111 - wrst_last_dw | 101 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------- - State | Encoding ------------------------- - st_reset | 000 - st_idle | 001 - st_la | 010 - st_wr_load | 011 - st_wr_send | 100 - st_rd | 101 ------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. --------------------------------- - State | Encoding --------------------------------- - reset_idle | 0000001 - reset_pulse_wc | 0000010 - reset_enable_clk | 0000100 - reset_disable_clk | 0001000 - reset_deassert_rst | 0010000 - reset_pulse_clk | 0100000 - reset_done | 1000000 --------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------------------- - State | Encoding -------------------------------------------------- - 000000 | 0000000000000000000000000000000000001 - 000001 | 0000000000000000000000000000000000010 - 000010 | 0000000000000000000000000000000000100 - 000011 | 0000000000000000000000000000000001000 - 000100 | 0000000000000000000000000000000010000 - 010110 | 0000000000000000000000000000000100000 - 000101 | 0000000000000000000000000000001000000 - 000110 | 0000000000000000000000000000010000000 - 000111 | 0000000000000000000000000000100000000 - 001000 | 0000000000000000000000000001000000000 - 001001 | 0000000000000000000000000010000000000 - 001010 | 0000000000000000000000000100000000000 - 001011 | 0000000000000000000000001000000000000 - 001100 | 0000000000000000000000010000000000000 - 001101 | 0000000000000000000000100000000000000 - 010101 | 0000000000000000000001000000000000000 - 011010 | 0000000000000000000010000000000000000 - 011001 | 0000000000000000000100000000000000000 - 001111 | 0000000000000000001000000000000000000 - 010010 | 0000000000000000010000000000000000000 - 010100 | 0000000000000000100000000000000000000 - 010011 | 0000000000000001000000000000000000000 - 010111 | 0000000000000010000000000000000000000 - 011111 | 0000000000000100000000000000000000000 - 011000 | 0000000000001000000000000000000000000 - 011011 | 0000000000010000000000000000000000000 - 011100 | 0000000000100000000000000000000000000 - 010001 | 0000000001000000000000000000000000000 - 101000 | 0000000010000000000000000000000000000 - 001110 | 0000000100000000000000000000000000000 - 100011 | 0000001000000000000000000000000000000 - 101010 | 0000010000000000000000000000000000000 - 010000 | 0000100000000000000000000000000000000 - 011110 | unreached - 100000 | 0001000000000000000000000000000000000 - 100001 | 0010000000000000000000000000000000000 - 100010 | 0100000000000000000000000000000000000 - 100101 | unreached - 100100 | unreached - 100111 | unreached - 011101 | unreached - 101001 | 1000000000000000000000000000000000000 -------------------------------------------------- -INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 0111 | 0111 - 0110 | 0110 - 0101 | 0101 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 110 | 011 - 100 | 100 - 101 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 00000 | 00000 - 00001 | 00001 - 00010 | 00010 - 00011 | 00011 - 01100 | 01100 - 01011 | 01011 - 00100 | 00100 - 00111 | 00111 - 00101 | 00101 - 01101 | 01101 - 00110 | 00110 - 01000 | 01000 - 10010 | 10010 - 01010 | 01010 - 01111 | 01111 - 01110 | 01110 - 10000 | 10000 - 01001 | 01001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0010 | 0010 - 0011 | 0011 - 0100 | 0100 - 0110 | 0110 - 0101 | 0101 - 0111 | 0111 - 1000 | 1000 - 1001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 011 | 011 - 100 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------------------- - State | Encoding -------------------------------- - st_txidle | 0000 - st_d_cmdreq | 0001 - st_d_cmdack | 0010 - st_d_header0 | 0011 - st_d_header2 | 0100 - st_d_1st_data | 0101 - st_d_payload | 0110 - st_d_payload_used | 0111 - st_d_tail | 1000 - st_d_tail_chk | 1001 - st_nd_prepare | 1010 - st_nd_header2 | 1011 - st_nd_headerlast | 1100 - st_nd_arbitration | 1101 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - st_mr_idle | 000 - st_mr_cmdlatch | 001 - st_mr_transfer | 010 - st_mr_wb_a | 011 - st_mr_ddr_a | 100 - st_mr_ddr_c | 101 - st_mr_last | 110 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------------- - State | Encoding -------------------------- - ast_reset | 00 - ast_idle | 01 - ast_readone | 10 - ast_ready | 11 -------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - tk_rst | 000 - tk_idle | 001 - tk_mwr_3hdr_c | 010 - tk_mwr_4hdr_c | 011 - tk_cpld_hdr_c | 100 - tk_body | 101 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. --------------------------- - State | Encoding --------------------------- - st_mrd_reset | 00 - st_mrd_idle | 01 - st_mrd_head2 | 11 - st_mrd_tail | 10 --------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------ - State | Encoding ------------------------------ - reqst_idle | 00 - reqst_1read | 01 - reqst_decision | 10 - reqst_nfifo_req | 11 ------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. --------------------------------------- - State | Encoding --------------------------------------- - st_mwr_reset | 0000 - st_mwr_idle | 0001 - st_mwr3_head2 | 0010 - st_mwr4_head2 | 0011 - st_mwr4_1st_data | 0100 - st_mwr_1st_data | 0101 - st_mwr_1st_data_throttle | 0110 - st_mwr_data | 0111 - st_mwr_data_throttle | 1000 --------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------- - State | Encoding -------------------------------- - intst_rst | 00001 - intst_idle | 00010 - intst_asserting | 00100 - intst_asserted | 01000 - intst_deasserting | 10000 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - toutst_idle | 00 - toutst_countup | 01 - toutst_pause | 10 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ------------------------------- - State | Encoding ------------------------------- - dmast_init | 000 - dmast_load_param | 001 - dmast_snout | 010 - dmast_stomp | 011 - dmast_body | 100 - dmast_tail | 101 - dmast_nextdex | 110 - dmast_await_dex | 111 ------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ------------------------ - State | Encoding ------------------------ - fsm_idle | 000 - fsm_busy1 | 001 - fsm_busy2 | 010 - fsm_busy3 | 011 - fsm_busy4 | 100 - fsm_busy5 | 101 - fsm_done | 110 ------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. ------------------------------ - State | Encoding ------------------------------ - reqst_idle | 00 - reqst_1read | 01 - reqst_decision | 10 - reqst_nfifo_req | 11 - reqst_quantity | unreached - reqst_fifo_req | unreached ------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------------ - State | Encoding ------------------------------------------ - st_cpld_reset | 0000 - st_cpld_idle | 0001 - st_cpl_head2 | 0010 - st_cpld_head2 | 0011 - st_cpld_afetch_special | 0100 - st_cpld_afetch_special_tail | 0101 - st_cpld_afetch | 0110 - st_cpld_afetch_throttle | 0111 - st_cpld_only_1dw | 1000 - st_cpld_1st_data | 1001 - st_cpld_1st_data_throttle | 1010 - st_cpld_data | 1011 - st_cpld_data_throttle | 1100 - st_cpld_last_data | 1101 ------------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 00000 | 00000 - 00010 | 00001 - 00001 | 00011 - 00011 | 00010 - 00100 | 00110 - 10000 | 00111 - 00101 | unreached - 00110 | 00101 - 00111 | 00100 - 01000 | 01100 - 01001 | 01101 - 01010 | 01111 - 01011 | 01110 - 01100 | 01010 - 10111 | 01011 - 10001 | 01001 - 10010 | 01000 - 10011 | 11000 - 10100 | 11001 - 10101 | 11011 - 10110 | 11010 - 11000 | 11110 - 11001 | 11111 - 11010 | 11101 - 11101 | 11100 - 11011 | 10100 - 11100 | 10101 - 11110 | 10111 - 11111 | 10110 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0010 | 0010 - 0011 | 0011 - 0100 | 0100 - 0101 | 0101 - 1000 | 1000 - 0110 | 0110 - 1001 | 1001 - 0111 | 0111 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------- - State | Encoding -------------------- - 00 | 001 - 11 | 010 - 10 | 100 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 100 | 010 - 011 | 011 - 010 | 100 - 101 | 101 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - idle | 000 - pre_trig | 001 - wait_trig | 010 - wait_trig_skip | 011 - post_trig | 100 - post_trig_skip | 101 - decr_shot | 110 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - eth | 0001 - eth_capture | 0010 - eth_chk | 0011 - ipv4 | 0100 - ipv4_capture | 0101 - ipv4_chksum | unreached - ipv4_opt | 0111 - udp | 1000 - udp_fetch_buf | 1001 - udp_capture | 1010 - chk | 1011 - done | 1100 - errors | 1101 - waits | 1110 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 000 - header | 001 - payload | 010 - padding | 011 - done | 100 - errors | 101 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------ - State | Encoding ------------------------------------ - idle | 00000 - eb_hdr_rec | 00001 - eb_hdr_proc | 00010 - eb_hdr_probe_id | 00011 - eb_hdr_probe_rdy | 00100 - cyc_hdr_rec | 00101 - cyc_hdr_read_proc | 00110 - cyc_hdr_read_get_adr | 00111 - wb_read_rdy | 01000 - wb_read | 01001 - cyc_hdr_write_proc | 01010 - cyc_hdr_write_get_adr | 01011 - wb_write_rdy | 01100 - wb_write | 01101 - wb_write_done | 01110 - cyc_done | 01111 - eb_done | 10000 - error | 10001 - error_wait | 10010 ------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------- - State | Encoding -------------------------------------- - idle | 000000000001 - eb_hdr_init | 000000000100 - eb_hdr_probe_id | 001000000000 - eb_hdr_probe_wait | 000010000000 - packet_hdr_send | 000001000000 - eb_hdr_send | 000100000000 - rdy | 000000000010 - cyc_hdr_init | 000000001000 - cyc_hdr_send | 010000000000 - base_write_adr_send | 000000010000 - data_send | 100000000000 - zero_pad_write | 000000100000 - zero_pad_wait | unreached - error | unreached -------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - calc_chksum | 0001 - wait_send_req | 0010 - prep_eth | 0011 - eth | 0100 - ipv4 | 0101 - udp | 0110 - hdr_send | 0111 - payload_send | 1000 - padding | 1001 - wait_ifgap | 1010 - error | 1011 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - addup | 001 - carries | 010 - finalise | 011 - output | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ----------------------- - State | Encoding ----------------------- - idle | 00 - init | 01 - transfer | 11 - waiting | unreached - done | 10 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - init | 001 - transfer | 010 - waiting | unreached - done | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 00 | 00 - 01 | 01 - 11 | 11 -------------------- -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL. - You should achieve better results by setting this init to 1. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:1901 - Instance num_brams.brams[3].ram/use_ramb36.ramb36 in unit num_brams.brams[3].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance num_brams.brams[2].ram/use_ramb36.ramb36 in unit num_brams.brams[2].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance num_brams.brams[1].ram/use_ramb36.ramb36 in unit num_brams.brams[1].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance num_brams.brams[0].ram/use_ramb36.ramb36 in unit num_brams.brams[0].ram/use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 9 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 32 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. -WARNING:Xst:2042 - Unit rs232_syscon: 32 internal tristates are replaced by logic (pull-up yes): data_out<0>, data_out<10>, data_out<11>, data_out<12>, data_out<13>, data_out<14>, data_out<15>, data_out<16>, data_out<17>, data_out<18>, data_out<19>, data_out<1>, data_out<20>, data_out<21>, data_out<22>, data_out<23>, data_out<24>, data_out<25>, data_out<26>, data_out<27>, data_out<28>, data_out<29>, data_out<2>, data_out<30>, data_out<31>, data_out<3>, data_out<4>, data_out<5>, data_out<6>, data_out<7>, data_out<8>, data_out<9>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:638 - in unit dbe_bpm_fmc130m_4ch_pcie Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_fmc130m_4ch_pcie Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_fmc130m_4ch_pcie Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<71> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<70> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<70> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<70> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<69> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<69> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<69> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<71> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<71> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<70> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<70> signal will be lost. -WARNING:Xst:638 - in unit cmp_bpm_pcie_ml605 Conflict on KEEP property on signal pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/wr_lat_2.wdata_dly<68> and pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<69> pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/wr_lat_2.wdata_dly<69> signal will be lost. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 4 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : - - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : - - -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : - -Mapping all equations... -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -Annotating constraints using XCF file '/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xcf' -XCF parsing done. -Building and optimizing final netlist ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_fmc130m_4ch_pcie, actual ratio is 21. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/rstdiv0_sync_r_6 has been replicated 7 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_infrastructure/rstdiv0_sync_r_7 has been replicated 70 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 15 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_oserdes_sync_r_8 has been replicated 3 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/rst_final has been replicated 5 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 4 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/ram_init_done_r_lcl has been replicated 1 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_0 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_1 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_2 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_3 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_copy_r_4 has been replicated 6 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_r_0 has been replicated 1 time(s) -FlipFlop cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_ui_top/ui_rd_data0/rd_buf_indx_r_3 has been replicated 1 time(s) -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_3 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_2 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_1 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxD_0 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_7 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_6 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_5 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_4 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_3 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_2 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_1 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_dbe_periph/cmp_wb_dbe_periph/cmp_leds/Wrapped_GPIO/out_reg_0 has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxEn has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/MTxErr has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/miim1/clkgen/Mdc has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_pga_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_shdn_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_dith_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_adc_rand_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_trigger_dir_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_trigger_term_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_vcxo_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_vcxo_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_clk_distrib_si571_oe_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_ad9510_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_ad9510_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_clk_distrib_pll_function_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_clk_distrib_clk_sel_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_eeprom_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_eeprom_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_lm75_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/iscl_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_lm75_i2c/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/bit_ctrl/isda_oen has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_monitor_led2_int has been replicated 1 time(s) to handle iob=true attribute. -FlipFlop cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_wb_fmc_130m_4ch_csr/wb_fmc_130m_4ch_csr_monitor_led3_int has been replicated 1 time(s) to handle iob=true attribute. - -Final Macro Processing ... - -Processing Unit : - Found 6-bit shift register for signal . - Found 3-bit shift register for signal . - Found 19-bit shift register for signal . - Found 16-bit shift register for signal . - Found 3-bit shift register for signal . - Found 16-bit shift register for signal . - Found 16-bit shift register for signal . - Found 16-bit shift register for signal . - Found 16-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 4-bit shift register for signal . -INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal and currently occupies 7 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -Unit processed. - -Processing Unit : - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . -INFO:Xst:741 - HDL ADVISOR - A 7-bit shift register was found for signal and currently occupies 7 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. -Unit processed. - -Processing Unit : - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 3-bit shift register for signal . - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 24969 - Flip-Flops : 24969 -# Shift Registers : 261 - 16-bit shift register : 5 - 19-bit shift register : 1 - 2-bit shift register : 104 - 3-bit shift register : 141 - 4-bit shift register : 1 - 5-bit shift register : 8 - 6-bit shift register : 1 - -========================================================================= -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- ----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+-------+ -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 6092 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| MMCM_ADV:CLKOUT0 | 2411 | -mrx_clk_pad_i | IBUF | 287 | -mtx_clk_pad_i | IBUF | 1012 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[3].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 34 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[2].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 34 | -cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 34 | -cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk | MMCM_ADV:CLKOUT1 | 9029 | -cmp_bpm_pcie_ml605/cfg_err_ecrc | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_block_i) | 1 | -cmp_bpm_pcie_ml605/pcie_core_i/TxOutClk | BUFG | 21 | -sys_clk_p_i | MMCM_ADV:CLKOUT1+MMCM_ADV:CLKOUT1 | 9727 | -cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> | BUFR | 1542 | -cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> | BUFR | 928 | -cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 1083 | -cmp_chipscope_icon_0/CONTROL3<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)| 1 | -cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL5<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[5].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL4<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[4].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL2<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD) | 1 | ----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+-------+ -(*) These 6 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -FindSrcOfAsyncThruGates : 100 (1) -FindSrcOfAsyncThruGates : 200 (1) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 62 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/N11(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 62 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0_fmc130m_4ch_clk0/XST_VCC:P) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_fmc130m_4ch_clk1/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_2_ethmac_tx/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_3_fmc130m_4ch_periph/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_4_bpm_acq/XST_VCC:P) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_5_bpm_acq/XST_VCC:P) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 56 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[0].ram/use_ramb36.ramb36/num_brams.brams[0].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[2].ram/use_ramb36.ramb36/num_brams.brams[2].ram/use_ramb36.ramb36) | 36 | -cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/N01(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/num_brams.brams[3].ram/use_ramb36.ramb36/num_brams.brams[3].ram/use_ramb36.ramb36) | 36 | -cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G) | NONE(cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch_cmp_interconnect/rom/Mram_rom1) | 30 | -cmp_bpm_pcie_ml605/cfg_err_ecrc(cmp_bpm_pcie_ml605/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/num_brams.brams[1].ram/use_ramb36.ramb36/num_brams.brams[1].ram/use_ramb36.ramb36) | 16 | -cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_0_fmc130m_4ch_clk0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1_fmc130m_4ch_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_3_fmc130m_4ch_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_4_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_5_bpm_acq/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1) | 6 | -cmp_bpm_pcie_ml605/LoopBack_BRAM_Off.DDRs_ctrl_module/u_ddr_control/DDR_pipe_write_f2m_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/LoopBack_BRAM_Off.DDRs_ctrl_module/u_ddr_control/DDR_pipe_write_f2m_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G)| NONE(cmp_bpm_pcie_ml605/LoopBack_BRAM_Off.DDRs_ctrl_module/u_ddr_control/DDR_pipe_write_f2m_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Downstream_DMA_Engine/DMA_DSP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Downstream_DMA_Engine/DMA_DSP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Downstream_DMA_Engine/DMA_DSP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/MRd_Channel/pioCplD_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/MRd_Channel/pioCplD_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/MRd_Channel/pioCplD_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Upstream_DMA_Engine/US_TLP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/DBITERR(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Upstream_DMA_Engine/US_TLP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/XST_GND:G) | NONE(cmp_bpm_pcie_ml605/theTlpControl/rx_Itf/Upstream_DMA_Engine/US_TLP_Buffer/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram) | 4 | -cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_ddr3_iface/cmp_acq_cnt/Msub_GND_5370_o_GND_5370_o_sub_13_OUT<31:0>_lut<31>(XST_VCC:P) | NONE(cmp_xwb_fmc130m_4ch/cmp_wb_fmc130m_4ch/cmp_fmc_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_14569_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_14569_o1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo) | 4 | -cmp_bpm_pcie_ml605/m_axis_rx_tkeep<0>(cmp_bpm_pcie_ml605/XST_VCC:P) | NONE(cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync) | 2 | -cmp_bpm_pcie_ml605/pcie_core_i/phy_rdy_n_INV_524_o(cmp_bpm_pcie_ml605/pcie_core_i/phy_rdy_n_INV_524_o1_INV_0:O) | NONE(cmp_bpm_pcie_ml605/pcie_core_i/pcie_2_0_i/pcie_block_i) | 2 | -cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_xhdl2_0(cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_xhdl2_0:Q) | NONE(cmp_bpm_pcie_ml605/u_ddr_core/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync) | 2 | -cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/dpram0_wea(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/Mmux_dpram0_wea11:O) | NONE(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/cmp_multishot_dpram0/gen_single_clk.U_RAM_SC/Mram_ram8) | 2 | -cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/dpram1_wea(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/Mmux_dpram1_wea11:O) | NONE(cmp_xwb_acq_core/cmp_wb_acq_core/cmp_acq_multishot_dpram/cmp_multishot_dpram1/gen_single_clk.U_RAM_SC/Mram_ram8) | 2 | -------------------------------------------------------------------------------------------------------------------INFO:TclTasksC:1850 - process run : Generate Programming File is done. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 9.390ns (Maximum Frequency: 106.497MHz) - Minimum input arrival time before clock: 4.791ns - Maximum output required time after clock: 2.719ns - Maximum combinational path delay: 0.485ns -WARNING:Xst:1415 - No path found for this constraint. -WARNING:Xst:2245 - Timing constraint is not met. - -========================================================================= - -Process "Synthesize - XST" failed - -real 5m25.669s -user 5m4.904s -sys 0m1.296s -Mon Feb 10 09:10:37 BRST 2014 diff --git a/hdl/syn/ml605/dbe_bpm_fmc516/Manifest.py b/hdl/syn/ml605/dbe_bpm_fmc516/Manifest.py deleted file mode 100755 index b4fdacc7..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc516/Manifest.py +++ /dev/null @@ -1,14 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_fmc516" -#syn_top = "xwb_fmc516" -syn_project = "dbe_bpm_fmc516.xise" -#syn_project = "wb_fmc516.xise" - -modules = { "local" : [ "../../../top/ml_605/dbe_bpm_fmc516" ] }; -#modules = { "local" : [ "../../../modules/dbe_wishbone/wb_fmc516", -# "../../"] }; diff --git a/hdl/syn/ml605/dbe_bpm_fmc516/dbe_bpm_fmc516.xise b/hdl/syn/ml605/dbe_bpm_fmc516/dbe_bpm_fmc516.xise deleted file mode 100644 index 139c7dc7..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc516/dbe_bpm_fmc516.xise +++ /dev/null @@ -1,1610 +0,0 @@ - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_fmc516/make_output b/hdl/syn/ml605/dbe_bpm_fmc516/make_output deleted file mode 100644 index c1e555c9..00000000 --- a/hdl/syn/ml605/dbe_bpm_fmc516/make_output +++ /dev/null @@ -1,13895 +0,0 @@ -echo "project open dbe_bpm_fmc516.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.syr" -Reading design: dbe_bpm_fmc516.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/ip_cores/dds_adc_input.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 94. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_cop.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" included at line 64. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 65. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 165. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 166. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 87. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 77. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 74. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" into library work -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 317: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 318: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 322: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_defines.v" Line 323: Macro is redefined. -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 67. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 42. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 198: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 199: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 220: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" Line 221: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 80. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/timescale.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 112. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xilinx_dist_ram_16x32.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 74. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 75. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 83. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" included at line 240. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 241. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 69. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 82. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" into library work -Parsing module . -WARNING:HDLCompiler:327 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" Line 377: Concatenation with unsized literal; will interpret as 32 bits -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 45. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 133: Macro is redefined. -WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" Line 159: Macro is redefined. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" into library work -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/spi_bidir_defines.v" included at line 43. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 44. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 85. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" into library work -Parsing package . -Parsing package body . -WARNING:HDLCompiler:797 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 704: Subprogram does not conform with its declaration. -INFO:HDLCompiler:1408 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd" Line 251. f_num_adc_pins is declared here -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_private_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_4096.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_32768.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_65536.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/ila/chipscope_ila_131072.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/platform/virtex6/chipscope/vio/chipscope_vio_256.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work -Parsing package . -Parsing package body . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/wb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_bidir/xwb_spi_bidir.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x3ffe0000]" -Note: "Mapping slave #1[0x10000000/0x3ffe0000]" -Note: "Mapping slave #2[0x20000000/0x3fff0000]" -Note: "Mapping slave #3[0x30004000/0x3fffffe0]" -Note: "Mapping slave #4[0x30005000/0x3ffffe00]" -Note: "Mapping slave #5[0x30006000/0x3fffff00]" -Note: "Mapping slave #6[0x30007000/0x3fffff00]" -Note: "Mapping slave #7[0x30010000/0x3ffff000]" -Note: "Mapping slave #8[0x30020000/0x3ffff000]" -Note: "Mapping slave #9[0x30000000/0x3ffffc00]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE. -Going to verilog side to elaborate module lm32_top_medium_icache_debug - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -Going to vhdl side to elaborate module lm32_ram - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 146: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 147: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 187: Comparison between arrays of unequal length always returns FALSE. -Back to verilog to continue elaboration -Going to vhdl side to elaborate module lm32_ram - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Back to verilog to continue elaboration -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 66223: Assignment to pc_w ignored, since the identifier is never used - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 66289: Assignment to x_result_sel_logic_d ignored, since the identifier is never used - -Elaborating module . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 69491. $display Data bus error. Address: 0 -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 69639. $display Warning: Non-aligned halfword access. Address: 0x0 Time: $time . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 69641. $display Warning: Non-aligned word access. Address: 0x0 Time: $time . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -Going to vhdl side to elaborate module lm32_dp_ram - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 146: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 147: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 187: Comparison between arrays of unequal length always returns FALSE. -Back to verilog to continue elaboration -Going to vhdl side to elaborate module lm32_dp_ram -Back to verilog to continue elaboration - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 64280: Assignment to jrstn ignored, since the identifier is never used -Back to vhdl to continue elaboration -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 146: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 164: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" Line 123: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 71: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 73: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module ethmac - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 883: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target. - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used -"/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted - -Elaborating module . -Back to vhdl to continue elaboration - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net does not have a driver. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" Line 248: Using initial value "00000000000000000000000000000000" for zero_din_width since it is never assigned - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -WARNING:UtilitiesC:159 - Message file "usenglish/ip.msg" wasn't found. -INFO:ip - 0: (0,0) : 36x1024 u:32 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 36x1024 u:32 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Assignment ignored -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 509: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 428: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 432: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 168: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 169: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" Line 305: Using initial value (('0','0',"0000000000000000"),('0','0',"0000000000000000"),('0','0',"0000000000000000"),('0','0',"0000000000000000")) for adc_in_sdr_dummy since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" Line 466: Using initial value '0' for dummy_bit_low since it is never assigned -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" Line 467: Using initial value "00000000" for dummy_adc_vector_low since it is never assigned - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xf00]" -Note: "Mapping slave #1[0x100/0xf00]" -Note: "Mapping slave #2[0x200/0xf00]" -Note: "Mapping slave #3[0x300/0xf00]" -Note: "Mapping slave #4[0x400/0xf00]" -Note: "Mapping slave #5[0x500/0xf00]" -Note: "Mapping slave #6[0x600/0xf00]" -Note: "Mapping slave #7[0x800/0xe00]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 208: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 209: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 210: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 211: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" Line 212: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "[ map vector(0) = 1 ]" -Note: "[ map vector(1) = 0 ]" -Note: "[ map vector(2) = 0 ]" -Note: "[ map vector(3) = 1 ]" -Note: "[ intercon(0) = 1 ]" -Note: "[ intercon(1) = 0 ]" -Note: "[ intercon(2) = 0 ]" -Note: "[ intercon(3) = 1 ]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd" Line 161: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" Line 207: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -INFO:ip - 0: (0,0) : 18x1024 u:16 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 18x1024 u:16 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 2776: Range is empty (null range) -WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 2776: Assignment ignored - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" Line 141: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims -INFO:ip - 0: (0,0) : 36x1024 u:36 -INFO:ip - 1: (36,0) : 36x1024 u:28 -library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so -Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo -INFO:ip - 0: (0,0) : 36x1024 u:36 -INFO:ip - 1: (36,0) : 36x1024 u:28 - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" Line 135: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" Line 204. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" Line 561. Case statement is complete. others clause is never selected -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" Line 354. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" Line 90: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_top - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" Line 250: Assignment to three_mode ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" Line 67: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module spi_top - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" Line 250: Assignment to three_mode ignored, since the identifier is never used - -Elaborating module . -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" Line 67: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Going to verilog side to elaborate module sockit_owm - -Elaborating module . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" Line 156: Net does not have a driver. -Back to vhdl to continue elaboration -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" Line 97: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" Line 325: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0x700]" -Note: "Mapping slave #1[0x100/0x700]" -Note: "Mapping slave #2[0x200/0x700]" -Note: "Mapping slave #3[0x300/0x7f0]" -Note: "Mapping slave #4[0x400/0x600]" - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" Line 65: Net does not have a driver. - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" Line 356: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" Line 357: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" Line 358: Net does not have a driver. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 543: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 543: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 652: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 652: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 652: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 652: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 652: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 652: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 791: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 995: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 995: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd" line 995: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 7-bit register for signal . - Found 1-bit register for signal . - Found 7-bit adder for signal created at line 1241. - Found 1-bit tristate buffer for signal created at line 727 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 1 - g_logdelay = 10 - g_syncdepth = 3 - Found 1-bit register for signal . - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 14 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 9 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000000000000001100000000001000000100000000000000000000000000000000000000000000110000000000100000000000000000000000000000000000000000000000000011000000000010000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000011000000000001000010000000000000000000000000000000000000000000001100000000000100000000000000000000000000000000000000000000000000110000000000010000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000110000000000000111000000000000000000000000000000000000000000000011000000000000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000001100000000000001100000000000000000000000000000000000000000000000110000000000000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000110000000000000101000000000000000000000000000000000000000000000011000000000000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000110000000000000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010101111 -10011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_sdb_addr = "00110000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000000000000001100000000001000000100000000000000000000000000000000000000000000110000000000100000000000000000000000000000000000000000000000000011000000000010000011111111111100000000000000000000000000000000000000000000000000000110010100011110111011110000101100011001100000000000000000000000000000000001001000000001001000000101000100010101011101000010001101000010110101000010011100100110100101100100011001110110010100101101010001110101001101001001001000000010000000100000001000000010000000000010","000000000000000000000000000000000011000000000001000010000000000000000000000000000000000000000000001100000000000100000000000000000000000000000000000000000000000000110000000000010000111111111111000000000000000000000000000000000000000000000000000001100101000111101110111100001011000110011000000000000000000000000000000000010010000000010010000001010001000101010111010000100011010000101101010000100111001001101001011001000110011101100101001011010100011101010011010010010010000000100000001000000010000000100000000 -00010","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000000110000000000000111000000000000000000000000000000000000000000000011000000000000011100001111111100000000000000000000000000000000000000000000000000000110010100010110100000100000001010110010001000000000000000000000000000000001001000000001001000001001000100100100011101010011010010010101111101000101010101000100100001000101010100100100001001001111010011100100010101011111010000110100011001000111001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000001100000000000001100000000000000000000000000000000000000000000000110000000000000110000011111111000100000000000000000000000000000000000000000000000100100001010100101111111110011010001010001110000000000000000000000000000000010010000000010011000001110000000101000101010101000100100001001101010000010100001101011111010000010100010001000001010100000101010001000101010100100010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000110000000000000101000000000000000000000000000000000000000000000011000000000000010100011111111100010000000000000000000000000000010011100010110000000101111001011111100011001111111010110001011000000000000000000000000000000001001000000001001000010010000100100100111101000011010011110101001001000101010100110101111101000101010101000100100001001101010000010100001100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000110000000000000100000000011111000000000000000000000000000000000000000000000000000001100101000111001010101110101011101001010110000000000000000000000000000000010010000000010010000001010001100001010111010000100011010000101101010100110111010001110010011001010110000101101101011010010110111001100111001011010100010001001101010000010101111 -10011000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000 -01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000111111111111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_1', is tied to its initial value. - Found 256x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 8 - g_num_slaves = 10 - g_registered = true - g_address = ("00110000000000000000000000000000","00110000000000100000000000000000","00110000000000010000000000000000","00110000000000000111000000000000","00110000000000000110000000000000","00110000000000000101000000000000","00110000000000000100000000000000","00100000000000000000000000000000","00010000000000000000000000000000","00000000000000000000000000000000") - g_mask = ("00111111111111111111110000000000","00111111111111111111000000000000","00111111111111111111000000000000","00111111111111111111111100000000","00111111111111111111111100000000","00111111111111111111111000000000","00111111111111111111111111100000","00111111111111110000000000000000","00111111111111100000000000000000","00111111111111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 11-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 89 D-type flip-flop(s). - inferred 88 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd". - g_profile = "medium_icache_debug" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. - Found 3-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 688. - Found 32-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 3-bit subtractor for signal > created at line 650. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 70 D-type flip-flop(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 64271: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - eba_reset = 32'b00000000000000000000000000000000 - deba_reset = 32'b00010000000000000000000000000000 - icache_associativity = 1 - icache_sets = 256 - icache_bytes_per_line = 16 - icache_base_address = 32'b00000000000000000000000000000000 - icache_limit = 32'b01111111111111111111111111111111 - dcache_associativity = 1 - dcache_sets = 512 - dcache_bytes_per_line = 16 - dcache_base_address = 0 - dcache_limit = 0 - watchpoints = 32'b00000000000000000000000000000100 - breakpoints = 0 - interrupts = 32 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 66159: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 66269: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 23-bit register for signal . - Found 23-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 29-bit adder for signal created at line 66956. - Found 32-bit 3-to-1 multiplexer for signal created at line 66967. - Found 1-bit 8-to-1 multiplexer for signal created at line 67004. - Found 5-bit comparator equal for signal created at line 66707 - Found 5-bit comparator equal for signal created at line 66713 - Found 5-bit comparator equal for signal created at line 66894 - Found 5-bit comparator equal for signal created at line 66895 - Found 5-bit comparator equal for signal created at line 66896 - Found 5-bit comparator equal for signal created at line 66897 - Found 5-bit comparator equal for signal created at line 66898 - Found 5-bit comparator equal for signal created at line 66899 - Found 32-bit comparator equal for signal created at line 66998 - Found 1-bit comparator equal for signal created at line 67011 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 441 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - eba_reset = 32'b00000000000000000000000000000000 - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 29-bit adder for signal created at line 74164. - Found 2-bit adder for signal created at line 74394. - Found 8-bit 4-to-1 multiplexer for signal created at line 74326. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 314 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 18 | - | Inputs | 11 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit subtractor for signal created at line 71585. - Found 2-bit adder for signal created at line 71662. - Found 20-bit comparator equal for signal created at line 71467 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 41 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 8 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd". - data_width = 32 - address_width = 10 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 1024 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 1024 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 1024 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1024x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 10-bit comparator equal for signal <_n0022> created at line 58 - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd". - data_width = 20 - address_width = 8 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 20-bit register for signal . - Summary: - inferred 21 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 20 - g_size = 256 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 20 - g_size = 256 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 20 - g_size = 256 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 256x20-bit dual-port RAM for signal . - Found 20-bit register for signal . - Found 20-bit register for signal . - Found 8-bit comparator equal for signal <_n0022> created at line 58 - Summary: - inferred 1 RAM(s). - inferred 40 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 512 - bytes_per_line = 16 - base_address = 0 - limit = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 69246. - Summary: - inferred 180 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v". - Found 33-bit subtractor for signal created at line 69. - Found 33-bit subtractor for signal created at line 69. - Found 33-bit adder for signal created at line 68. - Found 33-bit adder for signal created at line 68. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v". - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Summary: - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 64-bit shifter logical right for signal created at line 104 - Summary: - inferred 33 D-type flip-flop(s). - inferred 3 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v". - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 115. - Found 16-bit adder for signal created at line 115. - Found 16x16-bit multiplier for signal created at line 109. - Found 16x16-bit multiplier for signal created at line 110. - Found 16x16-bit multiplier for signal created at line 111. - Summary: - inferred 3 Multiplier(s). - inferred 2 Adder/Subtractor(s). - inferred 160 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - interrupts = 32 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 75866. - Summary: - inferred 78 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 36 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 75285. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 80 D-type flip-flop(s). - inferred 13 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - breakpoints = 0 - watchpoints = 32'b00000000000000000000000000000100 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal <31>>. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 36 | - | Inputs | 8 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit comparator equal for signal created at line 73093 - Found 32-bit comparator equal for signal created at line 73093 - Found 32-bit comparator equal for signal created at line 73093 - Found 32-bit comparator equal for signal created at line 73093 - Summary: - inferred 138 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 35 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd". - addr_width = 5 - addr_depth = 32 - data_width = 32 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 32 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 32 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 32 - g_with_byte_enable = false - g_addr_conflict_resolution = "write_first" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 5-bit comparator equal for signal <_n0022> created at line 58 - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v". - Found 11-bit register for signal . - Found 11-bit register for signal . - Summary: - inferred 22 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v". - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 224. - Found 32-bit adder for signal created at line 228. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 214. - Found 4-bit comparator equal for signal created at line 165 - Found 5-bit comparator not equal for signal created at line 233 - Found 5-bit comparator not equal for signal created at line 234 - Found 5-bit comparator not equal for signal created at line 235 - Summary: - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 174 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16 - g_with_byte_enable = false - g_addr_conflict_resolution = "dont_care" - g_init_file = "none" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 32768 - g_init_file = "../../../embedded-sw/dbe.ram" - g_must_have_init_file = true - g_slave1_interface_mode = pipelined - g_slave2_interface_mode = pipelined - g_slave1_granularity = byte - g_slave2_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 32768 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../embedded-sw/dbe.ram" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 32768 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "../../../embedded-sw/dbe.ram" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32768x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 16384 - g_init_file = "" - g_must_have_init_file = false - g_slave1_interface_mode = classic - g_slave2_interface_mode = classic - g_slave1_granularity = byte - g_slave2_granularity = word -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 79: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 95: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = classic - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 16384 - g_with_byte_enable = true - g_addr_conflict_resolution = "dont_care" - g_init_file = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16384x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd". - g_ma_interface_mode = classic - g_ma_address_granularity = byte - g_sl_interface_mode = pipelined - g_sl_address_granularity = byte -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 167: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = byte - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/ethmac.v" line 370: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 54 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_miim.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit register for signal . - Found 7-bit adder for signal created at line 409. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_clockgen.v". - Tp = 1 - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 92. - Found 8-bit subtractor for signal created at line 107. - Found 8-bit comparator greater for signal created at line 91 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v". - Tp = 1 - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Summary: - inferred 25 D-type flip-flop(s). - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 7-bit comparator greater for signal created at line 100 - Found 7-bit comparator greater for signal created at line 101 - Found 7-bit comparator greater for signal created at line 138 - Summary: - inferred 6 D-type flip-flop(s). - inferred 3 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_registers.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861. - Found 32-bit comparator lessequal for signal created at line 388 - Found 32-bit comparator greater for signal created at line 907 - Found 32-bit comparator greater for signal created at line 908 - Summary: - inferred 21 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b10100000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 1'b0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0000000 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0010010 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 7 - RESET_VALUE = 7'b0001100 - Found 7-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b00000110 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01000000 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 6 - RESET_VALUE = 6'b111111 - Found 6-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 4 - RESET_VALUE = 4'b1111 - Found 4-bit register for signal . - Summary: - inferred 4 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 3 - RESET_VALUE = 3'b000 - Found 3-bit register for signal . - Summary: - inferred 3 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 8 - RESET_VALUE = 8'b01100100 - Found 8-bit register for signal . - Summary: - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 1 - RESET_VALUE = 0 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 5 - RESET_VALUE = 5'b00000 - Found 5-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_register.v". - WIDTH = 16 - RESET_VALUE = 16'b0000000000000000 - Found 16-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_maccontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 5-bit register for signal . - Found 6-bit register for signal . - Found 16-bit subtractor for signal created at line 356. - Found 3-bit adder for signal created at line 304. - Found 5-bit adder for signal created at line 323. - Found 6-bit adder for signal created at line 417. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 72 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 6-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit adder for signal created at line 255. - Found 6-bit adder for signal created at line 274. - Found 6-bit adder for signal created at line 277. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 27 D-type flip-flop(s). - inferred 20 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v". - Tp = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" line 480: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 344. - Found 6-bit comparator equal for signal created at line 249 - Found 4-bit comparator equal for signal created at line 349 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v". - Tp = 1 - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 17-bit subtractor for signal created at line 170. - Found 32-bit subtractor for signal created at line 170. - Found 16-bit adder for signal created at line 162. - Found 16-bit adder for signal created at line 194. - Found 3-bit adder for signal created at line 215. - Found 32-bit comparator lessequal for signal created at line 170 - Found 16-bit comparator equal for signal created at line 199 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 35 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_txstatem.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 170 - Found 7-bit comparator lessequal for signal created at line 187 - Found 7-bit comparator not equal for signal created at line 187 - Summary: - inferred 12 D-type flip-flop(s). - inferred 4 Comparator(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v". - Tp = 1 - Found 32-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v". - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 4-bit comparator greater for signal created at line 114 - Found 4-bit comparator greater for signal created at line 115 - Found 4-bit comparator greater for signal created at line 116 - Found 4-bit comparator greater for signal created at line 117 - Found 4-bit comparator greater for signal created at line 118 - Found 4-bit comparator greater for signal created at line 119 - Found 4-bit comparator greater for signal created at line 120 - Found 4-bit comparator greater for signal created at line 121 - Found 4-bit comparator greater for signal created at line 122 - Found 10-bit comparator equal for signal created at line 139 - Summary: - inferred 20 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 6-bit register for signal . - Found 1-bit register for signal . - Found 4-bit comparator greater for signal created at line 213 - Found 4-bit comparator lessequal for signal created at line 314 - Summary: - inferred 40 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 6 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v". - Found 5-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 116. - Found 16-bit adder for signal created at line 120. - Found 5-bit adder for signal created at line 151. - Found 4-bit adder for signal created at line 173. - Found 16-bit comparator greater for signal created at line 131 - Found 16-bit comparator greater for signal created at line 132 - Found 16-bit comparator equal for signal created at line 134 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v". - Tp = 1 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit 8-to-1 multiplexer for signal created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 1-bit 4-to-1 multiplexer for signal > created at line 204. - Found 8-bit comparator equal for signal created at line 171 - Found 8-bit comparator equal for signal created at line 174 - Found 8-bit comparator equal for signal created at line 177 - Found 8-bit comparator equal for signal created at line 180 - Found 8-bit comparator equal for signal created at line 183 - Found 8-bit comparator equal for signal created at line 186 - Summary: - inferred 4 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 48 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v". -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2355: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" line 2377: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 30-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 7-bit register for signal . - Found 7-bit register for signal . - Found 2-bit register for signal . - Found 24-bit register for signal . - Found 9-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 773. - Found 16-bit subtractor for signal created at line 777. - Found 16-bit subtractor for signal created at line 781. - Found 16-bit subtractor for signal created at line 785. - Found 30-bit adder for signal created at line 821. - Found 3-bit adder for signal created at line 960. - Found 30-bit adder for signal created at line 964. - Found 3-bit adder for signal created at line 996. - Found 8-bit adder for signal created at line 1395. - Found 8-bit adder for signal created at line 1398. - Found 2-bit adder for signal created at line 1745. - Found 30-bit adder for signal created at line 2001. - Found 2-bit adder for signal created at line 2098. - Found 2-bit adder for signal created at line 2117. - Found 4x2-bit Read Only RAM for signal - Found 4x6-bit Read Only RAM for signal <_n1573> - Found 1-bit 4-to-1 multiplexer for signal created at line 1630. - Found 8-bit 4-to-1 multiplexer for signal created at line 1648. - Found 8-bit 4-to-1 multiplexer for signal created at line 1660. - Found 16-bit 4-to-1 multiplexer for signal created at line 776. - Found 16-bit comparator greater for signal created at line 627 - Found 16-bit comparator greater for signal created at line 803 - Found 16-bit comparator lessequal for signal created at line 898 - Found 8-bit comparator greater for signal created at line 1062 - Found 16-bit comparator greater for signal created at line 1062 - Found 8-bit comparator lessequal for signal created at line 2417 - Found 1-bit comparator equal for signal created at line 2422 - Found 8-bit comparator greater for signal created at line 2423 - Summary: - inferred 2 RAM(s). - inferred 11 Adder/Subtractor(s). - inferred 461 D-type flip-flop(s). - inferred 8 Comparator(s). - inferred 104 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v". - we_width = 1 - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_fifo.v". - DATA_WIDTH = 32 - DEPTH = 256 - CNT_WIDTH = 8 - Set property "syn_ramstyle = no_rw_check" for signal . - Found 256x32-bit dual-port RAM for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 83. - Found 8-bit adder for signal created at line 114. - Found 8-bit adder for signal created at line 122. - Found 8-bit subtractor for signal > created at line 81. - Summary: - inferred 1 RAM(s). - inferred 3 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac/eth_macstatus.v". - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 16-bit comparator greater for signal created at line 236 - Found 16-bit comparator greater for signal created at line 236 - Found 6-bit comparator equal for signal created at line 310 - Summary: - inferred 18 D-type flip-flop(s). - inferred 3 Comparator(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 3 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_853_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State waiting is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 6 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_i (rising_edge) | - | Reset | rstn_i_INV_853_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit adder for signal created at line 299. - Found 32-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 320. - Found 16-bit adder for signal created at line 1241. - Found 32-bit 7-to-1 multiplexer for signal <_n0442> created at line 206. - Found 32-bit comparator greater for signal created at line 299 - Found 16-bit comparator greater for signal created at line 320 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 254 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 7 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 2 - g_adr_width_B = 32 - g_dat_width_A = 16 - g_dat_width_B = 32 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 32 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 36 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd". - g_adr_width_A = 32 - g_adr_width_B = 2 - g_dat_width_A = 32 - g_dat_width_B = 16 - g_pipeline = 3 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 32 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 42 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 15-bit register for signal . - Found 48-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 13-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 160-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 11-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 12 | - | Transitions | 41 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | _n0497 (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 11-bit adder for signal created at line 222. - Found 6-bit adder for signal created at line 464. - Found 7-bit adder for signal created at line 472. - Found 16-bit adder for signal created at line 1241. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit 3-to-1 multiplexer for signal created at line 242. - Found 1-bit 3-to-1 multiplexer for signal created at line 242. - Found 11-bit comparator equal for signal created at line 456 - Found 11-bit comparator equal for signal created at line 464 - Found 11-bit comparator equal for signal created at line 472 - Found 11-bit comparator greater for signal created at line 482 - Found 16-bit comparator equal for signal created at line 485 - Summary: - inferred 5 Adder/Subtractor(s). - inferred 499 D-type flip-flop(s). - inferred 5 Comparator(s). - inferred 86 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 96 - g_width_OUT = 16 - g_protected = 1 - Found 9-bit register for signal . - Found 96-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 106 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd". - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 7 | - | Inputs | 1 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_869_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 28-bit adder for signal created at line 91. - Found 28-bit adder for signal created at line 102. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 61 D-type flip-flop(s). - inferred 4 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd". - g_width_IN = 160 - g_width_OUT = 16 - g_protected = 0 - Found 9-bit register for signal . - Found 160-bit register for signal . - Found 1-bit register for signal . - Found 9-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 170 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 15-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 29 | - | Inputs | 10 | - | Outputs | 5 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_929_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- -INFO:Xst:1799 - State ipv4_chksum is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 15 | - | Transitions | 34 | - | Inputs | 13 | - | Outputs | 12 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_parser_reset_OR_12293_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | eth | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 14-bit subtractor for signal created at line 426. - Found 11-bit adder for signal created at line 291. - Found 12-bit adder for signal created at line 405. - Found 12-bit adder for signal created at line 426. - Found 13-bit adder for signal created at line 426. - Found 17-bit adder for signal created at line 504. - Found 15-bit subtractor for signal > created at line 1308. - Found 11-bit subtractor for signal > created at line 504. - Found 11-bit comparator equal for signal created at line 347 - Found 12-bit comparator equal for signal created at line 405 - Found 12-bit comparator greater for signal created at line 420 - Found 14-bit comparator equal for signal created at line 426 - Found 16-bit comparator equal for signal created at line 447 - Found 11-bit comparator greater for signal created at line 520 - Found 11-bit comparator equal for signal created at line 529 - Summary: - inferred 8 Adder/Subtractor(s). - inferred 244 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 14 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd". - g_width_IN = 16 - g_width_OUT = 160 - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 160-bit register for signal . - Found 4-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 166 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 9-bit register for signal . - Found 9-bit register for signal . - Found 15-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . -INFO:Xst:1799 - State zero_pad_wait is never reached in FSM . -INFO:Xst:1799 - State error is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 716 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_1016_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 19 | - | Transitions | 145 | - | Inputs | 19 | - | Outputs | 16 | - | Clock | clk_i (rising_edge) | - | Reset | nRst_i_INV_1016_o (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 8-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 9-bit subtractor for signal > created at line 1308. - Found 9-bit subtractor for signal > created at line 1308. - Found 15-bit subtractor for signal > created at line 1308. - Found 16-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 8-bit subtractor for signal > created at line 1308. - Found 4-bit comparator greater for signal created at line 363 - Found 16-bit comparator greater for signal created at line 504 - Found 8-bit comparator greater for signal created at line 584 - Found 8-bit comparator greater for signal created at line 619 - Found 16-bit comparator equal for signal created at line 659 - Found 4-bit comparator greater for signal created at line 716 - Found 8-bit comparator greater for signal created at line 986 - Summary: - inferred 13 Adder/Subtractor(s). - inferred 359 D-type flip-flop(s). - inferred 7 Comparator(s). - inferred 65 Multiplexer(s). - inferred 2 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 32 - g_size = 16 - g_show_ahead = true - g_with_empty = true - g_with_full = true - g_with_almost_empty = true - g_with_almost_full = true - g_with_count = true - g_almost_empty_threshold = 1 - g_almost_full_threshold = 11 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 1 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 32 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 0 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_PROG_FULL_TYPE = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 1 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd". - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_WR_RST_MAXFAN = 2 - C_RD_RST_MAXFAN = 3 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Summary: - inferred 15 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 1 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 32 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_READ_WIDTH_B = 32 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 4 - C_WRITE_WIDTH_A = 32 - C_WRITE_WIDTH_A_CORE = 32 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 4 - C_WRITE_WIDTH_B = 32 - C_WRITE_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 4 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 32 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 32 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 4 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 32 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 32 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "00000000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 32 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 32 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_1', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 32 - C_READ_WIDTH_A = 32 - C_READ_WIDTH_B = 32 - C_READ_WIDTH_A_CORE = 32 - C_READ_WIDTH_B_CORE = 32 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_USE_EMBEDDED_REG = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic_1', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_1', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd". - C_HAS_ALMOST_EMPTY = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY_FB', unconnected in block 'rd_status_flags_ss', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd". - C_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd". - C_PROG_EMPTY_TYPE = 1 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 1 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 2 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 210. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd". - C_RD_PNTR_WIDTH = 4 - Summary: -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd". - C_COUNTER_RESET_VAL = 0 - C_PNTR_WIDTH = 4 - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 126. - Found 4-bit subtractor for signal > created at line 128. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 4 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_FULL_FLAGS_RST_VAL = 1 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 1 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 151. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 1 - C_PROG_EMPTY_TYPE = 1 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss_1', is tied to its initial value (1). -WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss_1', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd". - C_HAS_RST = 1 - C_PROG_FULL_TYPE = 1 - C_PROG_FULL_THRESH_ASSERT_VAL = 11 - C_PROG_FULL_THRESH_NEGATE_VAL = 10 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_FULL_FLAGS_RST_VAL = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal >. - Found 5-bit adder for signal created at line 243. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 7 D-type flip-flop(s). - inferred 5 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd". - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 1 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 32 - C_DOUT_WIDTH = 32 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 1 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 1 - C_PROG_FULL_TYPE = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd". - g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 48-bit register for signal . - Found 16-bit register for signal . - Found 64-bit register for signal . - Found 32-bit register for signal . - Found 64-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 8-to-1 multiplexer for signal <_n0259> created at line 137. - Found 32-bit 8-to-1 multiplexer for signal <_n0277> created at line 168. - Summary: - inferred 328 D-type flip-flop(s). - inferred 22 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (4.0,4.0,4.0,4.0) - g_use_clk_chains = "0011" - g_use_data_chains = "1111" - g_map_clk_data_chains = (1,0,0,1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" line 193: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd". - g_fpga_device = "VIRTEX6" - g_interface_mode = pipelined - g_address_granularity = byte - g_adc_clk_period_values = (4.0,4.0,4.0,4.0) - g_use_clk_chains = "0011" - g_use_data_chains = "1111" - g_map_clk_data_chains = (1,0,0,1) - g_ref_clk = 1 - g_packet_size = 32 - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 553: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 590: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 633: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1002: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1132: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1170: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1216: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1216: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1255: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1296: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1296: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1329: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1329: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" line 1364: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit register for signal >. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 16-bit adder for signal created at line 1241. - Found 1-bit tristate buffer for signal created at line 1154 - Found 1-bit tristate buffer for signal created at line 1157 - Found 1-bit tristate buffer for signal created at line 1195 - Found 1-bit tristate buffer for signal created at line 1276 - Found 1-bit tristate buffer for signal created at line 1280 - Found 1-bit tristate buffer for signal created at line 1317 - Found 1-bit tristate buffer for signal created at line 1350 - Summary: - inferred 4 Adder/Subtractor(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 7 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 7 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001101111111100010000000000000000000000000000010011100010110000000101111001010101001001011111101110110000100100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111100110001010111110101011101001001010100100100010100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000101000000000000000000000000000000000000000000000000000000000000010111111111000100000000000000000000000000000100111000101100000001011110010101010010010111111011101100001001000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111001100010101111101010111010010010101001001000101001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100010000000000000000000000000000010011100010110000000101111001011001011110110110001100100011110100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101001001001100100100001101011111010011010100000101010011010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000100000000000000000000000000000100111000101100000001011110010101000000001010000110010000010111000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010100110101000001001001001000000010000000100000001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010011110111001010100110100000100000000000000000000000000000001001000000001001000010001001001000100110001001110010011000101001101011111010001100100110101000011001101010011000100110110010111110101001001000101010001110101001100100000001000000010000000000001") - g_sdb_addr = "00000000000000000000100000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001101111111100010000000000000000000000000000010011100010110000000101111001010101001001011111101110110000100100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111100110001010111110101011101001001010100100100010100100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000101000000000000000000000000000000000000000000000000000000000000010111111111000100000000000000000000000000000100111000101100000001011110010101010010010111111011101100001001000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111001100010101111101010111010010010101001001000101001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001001111111100010000000000000000000000000000010011100010110000000101111001011001011110110110001100100011110100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101001001001100100100001101011111010011010100000101010011010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111111111000100000000000000000000000000000100111000101100000001011110010101000000001010000110010000010111000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010100110101000001001001001000000010000000100000001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101111111100010000000000000000000000000000010011100010110000000101111001010100000000101000011001000001011100000000000000000000000000000001001000000001001000010001001001000100111101000011010011110101001001000101010100110101111101010011010100000100100100100000001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111111000100000000000000000000000000000100111000101100000001011110010110010111101101100011001000111101000000000000000000000000000000010010000000010010000100010010010001001111010000110100111101010010010001010101001101011111010010010011001001000011010111110100110101000001010100110101010001000101010100100010000 -00010000000000001","00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010011110111001010100110100000100000000000000000000000000000001001000000001001000010001001001000100110001001110010011000101001101011111010001100100110101000011001101010011000100110110010111110101001001000101010001110101001100100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_2', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 8 - g_registered = true - g_address = ("00000000000000000000100000000000","00000000000000000000011000000000","00000000000000000000010100000000","00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000111000000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000","00000000000000000000111100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 10 D-type flip-flop(s). - inferred 9 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32-bit register for signal . - Found 27-bit register for signal . - Found 30-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 6-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 22-bit register for signal . - Found 22-bit register for signal . - Found 22-bit register for signal . - Found 22-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 506 D-type flip-flop(s). - inferred 145 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_dly_iface.vhd". - g_with_var_loadable = true - g_with_variable = true - g_with_fn_dly_select = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Summary: - inferred 16 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_buf.vhd". - g_with_clk_single_ended = false - g_with_data_single_ended = false - g_with_data_sdr = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clk_period_values = (4.0,4.0,4.0,4.0) - g_use_clk_chains = "0011" - g_clk_default_dly = (5,5,5,5) - g_use_data_chains = "1111" - g_map_clk_data_chains = (1,0,0,1) - g_data_default_dly = (9,9,9,9) - g_ref_clk = 1 - g_with_bufio_clk_chains = "1111" - g_with_bufr_clk_chains = "1111" - g_with_data_sdr = false - g_with_fn_dly_select = false - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd" line 194: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 4.0 - g_default_adc_clk_delay = 5 - g_with_ref_clk = false - g_with_fn_dly_select = false - g_with_bufio = true - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_clk.vhd". - g_fpga_device = "VIRTEX6" - g_delay_type = "VAR_LOADABLE" - g_adc_clock_period = 4.0 - g_default_adc_clk_delay = 5 - g_with_ref_clk = true - g_with_fn_dly_select = false - g_with_bufio = true - g_with_bufr = true - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd". - g_delay_type = "VAR_LOADABLE" - g_default_adc_data_delay = 9 - g_with_data_sdr = false - g_with_fn_dly_select = false - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_data.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Summary: - inferred 97 D-type flip-flop(s). - inferred 26 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd". - g_data_width = 16 - g_size = 16 - g_show_ahead = false - g_with_rd_empty = true - g_with_rd_full = false - g_with_rd_almost_empty = false - g_with_rd_almost_full = false - g_with_rd_count = false - g_with_wr_empty = false - g_with_wr_full = true - g_with_wr_almost_empty = false - g_with_wr_almost_full = false - g_with_wr_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" line 238: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 0 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 16 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 16 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 0 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 2 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_PROG_FULL_TYPE = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 0 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 0 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 0 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 0 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 0 - C_HAS_SRST = 0 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 16 - C_READ_WIDTH_B = 16 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 16 - C_READ_WIDTH_B = 16 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 2 - C_WRITE_WIDTH_A = 16 - C_WRITE_WIDTH_A_CORE = 16 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 2 - C_WRITE_WIDTH_B = 16 - C_WRITE_WIDTH_B_CORE = 16 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 1 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(18,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 2 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 16 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 16 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 2 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 16 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 16 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 18 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 16 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). -WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 16 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 18 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 16 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 18 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 18 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 18 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 18 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_2', is tied to its initial value (000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 16 - C_READ_WIDTH_A = 16 - C_READ_WIDTH_B = 16 - C_READ_WIDTH_A_CORE = 16 - C_READ_WIDTH_B_CORE = 16 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_MSGON_VAL = 1 - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Set property "ASYNC_REG = TRUE" for signal . - Set property "MSGON = TRUE" for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 0 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_USE_EMBEDDED_REG = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 241: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'DATA_COUNT', unconnected in block 'rd_logic_2', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_2', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_ALMOST_EMPTY = 0 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY', unconnected in block 'rd_status_flags_as', is tied to its initial value (0). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_FULL_FLAGS_RST_VAL = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 243: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 0 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 270. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 12 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_almost_full_i', unconnected in block 'wr_status_flags_as', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 0 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 16 - C_DOUT_WIDTH = 16 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_OVERFLOW = 0 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd" line 88: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd". - g_data_width = 64 - g_size = 16 - g_show_ahead = false - g_with_empty = true - g_with_full = true - g_with_almost_empty = false - g_with_almost_full = false - g_with_count = false - g_almost_empty_threshold = 0 - g_almost_full_threshold = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd". - C_COMMON_CLOCK = 1 - C_COUNT_TYPE = 0 - C_DATA_COUNT_WIDTH = 4 - C_DEFAULT_VALUE = "BlankString" - C_DIN_WIDTH = 64 - C_DOUT_RST_VAL = "0" - C_DOUT_WIDTH = 64 - C_ENABLE_RLOCS = 0 - C_FAMILY = "virtex6" - C_FULL_FLAGS_RST_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_BACKUP = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_INT_CLK = 0 - C_HAS_MEMINIT_FILE = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_RD_RST = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_WR_RST = 0 - C_IMPLEMENTATION_TYPE = 0 - C_INIT_WR_PNTR_VAL = 0 - C_MEMORY_TYPE = 1 - C_MIF_FILE_NAME = "BlankString" - C_OPTIMIZATION_MODE = 0 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_PRIM_FIFO_TYPE = "1kx18" - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_PROG_FULL_TYPE = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_DEPTH = 16 - C_RD_FREQ = 1 - C_RD_PNTR_WIDTH = 4 - C_UNDERFLOW_LOW = 0 - C_USE_DOUT_RST = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_USE_FIFO16_FLAGS = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_VALID_LOW = 0 - C_WR_ACK_LOW = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_FREQ = 1 - C_WR_PNTR_WIDTH = 4 - C_WR_RESPONSE_LATENCY = 1 - C_MSGON_VAL = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_MEMORY_TYPE = 1 - C_PRELOAD_REGS = 0 - C_PRELOAD_LATENCY = 1 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_DOUT_RST_VAL = "0" - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_WR = 1 - C_DEPTH_RATIO_RD = 1 - C_FULL_FLAGS_RST_VAL = 1 - C_USE_EMBEDDED_REG = 0 - C_MSGON_VAL = 1 - C_HAS_ALMOST_EMPTY = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_HAS_DATA_COUNT = 0 - C_DATA_COUNT_WIDTH = 4 - C_HAS_RD_DATA_COUNT = 0 - C_RD_DATA_COUNT_WIDTH = 4 - C_HAS_WR_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_ECC = 0 - C_USE_DOUT_RST = 1 - C_ENABLE_RST_SYNC = 1 - C_ERROR_INJECTION_TYPE = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd". - C_COMMON_CLOCK = 1 - C_IMPLEMENTATION_TYPE = 0 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_HAS_INT_CLK = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_RD = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_EMBEDDED_REG = 1 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd". - C_FAMILY = "virtex6" - C_COMMON_CLOCK = 1 - C_HAS_SRST = 0 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_USE_DOUT_RST = 1 - C_DOUT_RST_VAL = "0" - C_MEMORY_TYPE = 1 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_LARGER_DEPTH = 16 - C_RD_DEPTH = 16 - C_WR_DEPTH = 16 - C_SMALLER_DATA_WIDTH = 64 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_USE_ECC = 0 - C_USE_EMBEDDED_REG = 0 - C_ERROR_INJECTION_TYPE = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "READ_FIRST" - C_WRITE_WIDTH_A = 64 - C_READ_WIDTH_A = 64 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "READ_FIRST" - C_WRITE_WIDTH_B = 64 - C_READ_WIDTH_B = 64 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_ECC = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_ALGORITHM = 1 - C_PRIM_TYPE = 3 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 64 - C_READ_WIDTH_A = 64 - C_WRITE_DEPTH_A = 16 - C_READ_DEPTH_A = 16 - C_ADDRA_WIDTH = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 64 - C_READ_WIDTH_B = 64 - C_WRITE_DEPTH_B = 16 - C_READ_DEPTH_B = 16 - C_ADDRB_WIDTH = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 - C_HAS_INJECTERR = 0 - C_SIM_COLLISION_CHECK = "ALL" - C_COMMON_CLK = 0 - C_DISABLE_WARN_BHV_COLL = 0 - C_DISABLE_WARN_BHV_RANGE = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd". - C_FAMILY = "virtex6" - C_MEM_TYPE = 1 - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_HAS_ENA = 1 - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WEA_I_WIDTH = 8 - C_WRITE_WIDTH_A = 64 - C_WRITE_WIDTH_A_CORE = 64 - C_ADDRA_WIDTH = 4 - C_ADDRA_WIDTH_CORE = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_HAS_ENB = 1 - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WEB_I_WIDTH = 8 - C_WRITE_WIDTH_B = 64 - C_WRITE_WIDTH_B_CORE = 64 - C_ADDRB_WIDTH = 4 - C_ADDRB_WIDTH_CORE = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_HAS_SOFTECC_INPUT_REGS_A = 0 - C_HAS_SOFTECC_INPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_HAS_INJECTERR = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_TOTAL_PRIMS = 2 - C_DEPTH_RESOLUTION = 1024 - C_START_WIDTH = -(0,36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_START_DEPTH = -(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_WIDTH = -(36,36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_PRIM_DEPTH = -(1024,1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_USED_WIDTH = -(36,28,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 -,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RSTA_WIDTH = 1 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0" - C_HAS_REGCEA = 0 - C_REGCEA_WIDTH = 1 - C_USE_BYTE_WEA = 0 - C_WE_WIDTH_A = 8 - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 64 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 64 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RSTB_WIDTH = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000" - C_HAS_REGCEB = 0 - C_REGCEB_WIDTH = 1 - C_USE_BYTE_WEB = 0 - C_WE_WIDTH_B = 8 - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 64 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 64 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_MUX_PIPELINE_STAGES_A = 0 - C_MUX_PIPELINE_STAGES_B = 0 - C_USE_SOFTECC = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 36 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "000000000000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "000000000000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 0 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 36 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_3', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd". - C_FAMILY = "virtex6" - C_XDEVICEFAMILY = "virtex6" - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 36 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 28 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_RST_TYPE = "SYNC" - C_HAS_RSTA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_INITA_VAL = "0000000000000000000000000000" - C_USE_BYTE_WEA = 0 - C_WEA_WIDTH = 1 - C_WRITE_MODE_A = "WRITE_FIRST" - C_RATIO_WA = 1 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 4 - C_HAS_RSTB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_INITB_VAL = "0000000000000000000000000000" - C_USE_BYTE_WEB = 0 - C_WEB_WIDTH = 1 - C_WRITE_MODE_B = "WRITE_FIRST" - C_RATIO_WB = 1 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 4 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:2935 - Signal 'dina_pad<35:34>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dina_pad<26:25>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dina_pad<17:16>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dina_pad<8:7>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<35:34>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<26:25>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<17:16>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). -WARNING:Xst:2935 - Signal 'dinb_pad<8:7>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (00). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd". - C_ELABORATION_DIR = "" - C_MEM_TYPE = 1 - C_BYTE_SIZE = 9 - C_USER_WIDTH = 64 - C_USER_DEPTH = 16 - C_START_WIDTH = 36 - C_START_DEPTH = 0 - C_PRIM_WIDTH = 36 - C_PRIM_DEPTH = 1024 - C_USED_WIDTH = 28 - C_LOAD_INIT_FILE = 0 - C_INIT_FILE_NAME = "no_coe_file_loaded" - C_USE_DEFAULT_DATA = 0 - C_DEFAULT_DATA = "0" - C_USE_BYTE_WE = 0 - C_WEA_WIDTH = 1 - C_WEB_WIDTH = 1 - C_HAS_SSRA = 0 - C_RST_PRIORITY_A = "CE" - C_RSTRAM_A = 0 - C_SINITA_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_A = "WRITE_FIRST" - C_WRITE_WIDTH_A = 36 - C_RATIO_WA = 1 - C_READ_WIDTH_A = 36 - C_RATIO_RA = 1 - C_ADDR_WIDTH_A = 10 - C_HAS_SSRB = 1 - C_RST_PRIORITY_B = "CE" - C_RSTRAM_B = 0 - C_SINITB_VAL = "000000000000000000000000000000000000" - C_WRITE_MODE_B = "WRITE_FIRST" - C_WRITE_WIDTH_B = 36 - C_RATIO_WB = 1 - C_READ_WIDTH_B = 36 - C_RATIO_RB = 1 - C_ADDR_WIDTH_B = 10 - C_HAS_MEM_OUTPUT_REGS_A = 0 - C_HAS_MEM_OUTPUT_REGS_B = 0 - C_HAS_MUX_OUTPUT_REGS_A = 0 - C_HAS_MUX_OUTPUT_REGS_B = 0 - C_EN_ECC_READ = false - C_EN_ECC_WRITE = false - C_COMMON_CLK = 0 - C_SIM_COLLISION_CHECK = "ALL" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_4', is tied to its initial value (000000000000000000000000000000000000). -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd". - C_MEM_TYPE = 1 - C_WRITE_WIDTH_A = 64 - C_READ_WIDTH_A = 64 - C_READ_WIDTH_B = 64 - C_READ_WIDTH_A_CORE = 64 - C_READ_WIDTH_B_CORE = 64 - C_ADDRB_WIDTH = 4 - C_HAS_SOFTECC_OUTPUT_REGS_A = 0 - C_HAS_SOFTECC_OUTPUT_REGS_B = 0 - C_USE_SOFTECC = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_RD_DATA_COUNT = 0 - C_USE_FWFT_DATA_COUNT = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_SRST = 0 - C_HAS_VALID = 0 - C_VALID_LOW = 0 - C_HAS_UNDERFLOW = 0 - C_UNDERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_RD_DEPTH = 16 - C_RD_PNTR_WIDTH = 4 - C_WR_DEPTH = 16 - C_WR_PNTR_WIDTH = 4 - C_PROG_EMPTY_TYPE = 0 - C_PROG_EMPTY_THRESH_ASSERT_VAL = 0 - C_PROG_EMPTY_THRESH_NEGATE_VAL = 1 - C_USE_EMBEDDED_REG = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic_3', is tied to its initial value (00000). -WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic_3', is tied to its initial value (0). - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd". - C_COMMON_CLOCK = 1 - C_HAS_ALMOST_FULL = 0 - C_HAS_WR_DATA_COUNT = 0 - C_HAS_RST = 1 - C_HAS_WR_ACK = 0 - C_WR_ACK_LOW = 0 - C_HAS_OVERFLOW = 1 - C_OVERFLOW_LOW = 0 - C_PRELOAD_LATENCY = 1 - C_PRELOAD_REGS = 0 - C_DEPTH_RATIO_RD = 1 - C_DEPTH_RATIO_WR = 1 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_FULL_THRESH_ASSERT_VAL = 0 - C_PROG_FULL_THRESH_NEGATE_VAL = -1 - C_FULL_FLAGS_RST_VAL = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd". - C_HAS_ALMOST_FULL = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_PNTR_WIDTH = 4 - C_COMMON_CLOCK = 1 - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 151. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 8 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd". - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_HAS_RST = 1 - C_HAS_ALMOST_FULL = 0 - C_PROG_FULL_TYPE = 0 - C_PROG_EMPTY_TYPE = 0 - C_FULL_FLAGS_RST_VAL = 1 - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . - Set property "equivalent_register_removal = no" for signal . -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss_2', is tied to its initial value (1). -WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss_2', is tied to its initial value (1). - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd". - C_COMMON_CLOCK = 1 - C_DATA_COUNT_WIDTH = 4 - C_DIN_WIDTH = 64 - C_DOUT_WIDTH = 64 - C_HAS_ALMOST_EMPTY = 0 - C_HAS_ALMOST_FULL = 0 - C_HAS_DATA_COUNT = 0 - C_HAS_OVERFLOW = 1 - C_HAS_RD_DATA_COUNT = 0 - C_HAS_UNDERFLOW = 0 - C_HAS_VALID = 0 - C_HAS_WR_ACK = 0 - C_HAS_WR_DATA_COUNT = 0 - C_PROG_EMPTY_TYPE = 0 - C_PROG_FULL_TYPE = 0 - C_DEPTH_RATIO_WR = 1 - C_RD_DATA_COUNT_WIDTH = 4 - C_RD_PNTR_WIDTH = 4 - C_WR_PNTR_WIDTH = 4 - C_WR_DATA_COUNT_WIDTH = 4 - C_USE_FWFT_DATA_COUNT = 0 - C_USE_ECC = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 64 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" line 98: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd". - ARST_LVL = '0' -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit 8-to-1 multiplexer for signal created at line 191. - Summary: - inferred 54 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 26 | - | Inputs | 9 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | st_idle | - | Power Up State | st_idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 3-bit subtractor for signal > created at line 1308. - Found 4-bit 6-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Found 1-bit 3-to-1 multiplexer for signal created at line 264. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 20 D-type flip-flop(s). - inferred 34 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd". - Found 3-bit register for signal . - Found 3-bit register for signal . - Found 16-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 14-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 64 | - | Inputs | 6 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | nReset (negative) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit subtractor for signal > created at line 1308. - Found 14-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 57 D-type flip-flop(s). - inferred 26 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd". - g_three_wire_mode = 1 - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd". - g_three_wire_mode = 1 - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v". - g_three_wire_mode = 1 - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 7-to-1 multiplexer for signal created at line 123. - Summary: - inferred 75 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v". - Tp = 1 - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 16-bit subtractor for signal created at line 80. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v". - g_three_wire_mode = 1 - Tp = 1 - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 99. - Found 8-bit adder for signal created at line 99. - Found 1-bit 128-to-1 multiplexer for signal created at line 147. - Found 1-bit 128-to-1 multiplexer for signal created at line 260. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 138 D-type flip-flop(s). - inferred 141 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd". - g_three_wire_mode = 0 - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd". - g_three_wire_mode = 0 - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" line 76: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v". - g_three_wire_mode = 0 - Tp = 1 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 16-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 32-bit 7-to-1 multiplexer for signal created at line 123. - Summary: - inferred 74 D-type flip-flop(s). - inferred 18 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v". - g_three_wire_mode = 0 - Tp = 1 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 98. - Found 8-bit subtractor for signal created at line 99. - Found 8-bit adder for signal created at line 99. - Found 1-bit 128-to-1 multiplexer for signal created at line 147. - Found 1-bit 128-to-1 multiplexer for signal created at line 260. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 138 D-type flip-flop(s). - inferred 141 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_ports = 1 - g_ow_btp_normal = "5.0" - g_ow_btp_overdrive = "1.0" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_ports = 1 - g_ow_btp_normal = "5.0" - g_ow_btp_overdrive = "1.0" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" line 117: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v". - OVD_E = 1 - CDR_E = 1 - BDW = 32 - OWN = 1 - BAW = 1 - BTP_N = "5.0" - BTP_O = "1.0" - T_RSTH_N = 96 - T_RSTL_N = 96 - T_RSTP_N = 15 - T_DAT0_N = 12 - T_DAT1_N = 1 - T_BITS_N = 3 - T_RCVR_N = 1 - T_IDLE_N = 200 - T_RSTH_O = 48 - T_RSTL_O = 48 - T_RSTP_O = 10 - T_DAT0_O = 6 - T_DAT1_O = 1 - T_BITS_O = 2 - T_RCVR_O = 2 - T_IDLE_O = 96 - CDR_N = 4 - CDR_O = 0 -WARNING:Xst:2935 - Signal 'owr_sel', unconnected in block 'sockit_owm', is tied to its initial value (0). - Found 16-bit register for signal . - Found 16-bit register for signal
. - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit subtractor for signal created at line 392. - Found 8-bit subtractor for signal created at line 393. - Found 16-bit adder for signal created at line 305. - Found 1-bit shifter logical left for signal created at line 100 - Found 16-bit comparator equal for signal created at line 309 - Found 8-bit comparator equal for signal created at line 399 - Found 8-bit comparator equal for signal created at line 400 - Found 8-bit comparator equal for signal created at line 409 - Found 8-bit comparator equal for signal created at line 410 - Found 8-bit comparator not equal for signal created at line 411 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 65 D-type flip-flop(s). - inferred 6 Comparator(s). - inferred 11 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd". - g_wbs_interface_width = narrow2 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd". - g_data_width = 25 - g_size = 32 - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 25-bit register for signal >. - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 25-bit register for signal >. - Found 5-bit adder for signal created at line 142. - Found 5-bit subtractor for signal > created at line 144. -INFO:Xst:3019 - HDL ADVISOR - 800 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 25-bit 32-to-1 multiplexer for signal created at line 109. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 806 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd". - g_min_pulse_width = 1 - g_clk_frequency = 100 - g_output_polarity = '0' - g_output_retrig = false - g_output_length = 1 - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal >. - Found 1-bit register for signal . - Found 2-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 9 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 20000000 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd". - g_interface_mode = classic - g_address_granularity = word - g_cntr_period = 100000 - g_num_leds = 8 - g_num_buttons = 8 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 84: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 119: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 134: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 158: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" line 182: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 4 - g_registered = true - g_wraparound = true - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_sdb_addr = "00000000000000000000010000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000111100000000000000000000000000000000000000000000000011001110010000101111110110101111101110011101110100000000000000000000000000000001001000000001001100000010001001010100001101000101010100100100111001011111010101000100100101000011010100110101111101000011010011110101010101001110010101000100010101010010001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000011111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000110011100100001010001010010101110001100110101110000000000000000000000000000000010010000000010010000100000001000101000011010001010101001001001110010111110101001101001001010011010101000001001100010001010101111101010101010000010101001001010100001000000010000000100 -00000000001") - g_bus_end = "0000000000000000000000000000000000000000000000000000011111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom_3', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 1 - g_num_slaves = 5 - g_registered = true - g_address = ("00000000000000000000010000000000","00000000000000000000001100000000","00000000000000000000001000000000","00000000000000000000000100000000","00000000000000000000000000000000") - g_mask = ("00000000000000000000011000000000","00000000000000000000011111110000","00000000000000000000011100000000","00000000000000000000011100000000","00000000000000000000011100000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 7 D-type flip-flop(s). - inferred 6 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 8-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 46 D-type flip-flop(s). - inferred 4 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1500_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_1510_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = pipelined - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd". - g_interface_mode = pipelined - g_address_granularity = word - g_period = 100000 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" line 73: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 24-bit register for signal . - Found 24-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 90 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = word -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 18 - 1024x32-bit dual-port RAM : 1 - 128x32-bit single-port Read Only RAM : 2 - 16384x32-bit dual-port RAM : 1 - 16x32-bit dual-port RAM : 1 - 256x20-bit dual-port RAM : 1 - 256x32-bit dual-port RAM : 4 - 256x32-bit single-port Read Only RAM : 1 - 32768x32-bit dual-port RAM : 1 - 32x32-bit dual-port RAM : 2 - 4x2-bit single-port Read Only RAM : 1 - 4x6-bit single-port Read Only RAM : 1 - 8x1-bit single-port Read Only RAM : 2 -# Multipliers : 3 - 16x16-bit multiplier : 3 -# Adders/Subtractors : 160 - 10-bit adder : 1 - 11-bit adder : 2 - 11-bit subtractor : 1 - 12-bit adder : 2 - 13-bit adder : 1 - 14-bit subtractor : 3 - 15-bit subtractor : 3 - 16-bit adder : 17 - 16-bit subtractor : 7 - 17-bit adder : 2 - 17-bit subtractor : 1 - 2-bit adder : 8 - 2-bit addsub : 1 - 2-bit subtractor : 2 - 24-bit adder : 1 - 28-bit adder : 1 - 29-bit adder : 2 - 3-bit adder : 4 - 3-bit subtractor : 3 - 30-bit adder : 3 - 32-bit adder : 8 - 32-bit subtractor : 6 - 33-bit adder : 2 - 33-bit subtractor : 2 - 4-bit adder : 20 - 4-bit addsub : 2 - 5-bit adder : 10 - 5-bit addsub : 4 - 6-bit adder : 3 - 7-bit adder : 3 - 8-bit adder : 12 - 8-bit addsub : 3 - 8-bit subtractor : 14 - 9-bit subtractor : 6 -# Registers : 2057 - 1-bit register : 1369 - 10-bit register : 3 - 11-bit register : 15 - 14-bit register : 2 - 15-bit register : 3 - 16-bit register : 79 - 160-bit register : 3 - 17-bit register : 1 - 2-bit register : 50 - 20-bit register : 3 - 22-bit register : 4 - 23-bit register : 2 - 24-bit register : 2 - 25-bit register : 128 - 27-bit register : 1 - 28-bit register : 1 - 29-bit register : 9 - 3-bit register : 24 - 30-bit register : 4 - 32-bit register : 95 - 4-bit register : 103 - 48-bit register : 4 - 5-bit register : 25 - 6-bit register : 18 - 64-bit register : 2 - 7-bit register : 10 - 8-bit register : 88 - 9-bit register : 8 - 96-bit register : 1 -# Comparators : 109 - 1-bit comparator equal : 2 - 10-bit comparator equal : 2 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 7 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 20-bit comparator equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator equal : 10 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 21 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 1 - 8-bit comparator not equal : 2 -# Multiplexers : 1968 - 1-bit 128-to-1 multiplexer : 4 - 1-bit 2-to-1 multiplexer : 1366 - 1-bit 3-to-1 multiplexer : 5 - 1-bit 4-to-1 multiplexer : 41 - 1-bit 8-to-1 multiplexer : 3 - 11-bit 2-to-1 multiplexer : 10 - 14-bit 2-to-1 multiplexer : 4 - 15-bit 2-to-1 multiplexer : 3 - 16-bit 2-to-1 multiplexer : 52 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 29 - 20-bit 2-to-1 multiplexer : 3 - 23-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 6 - 25-bit 32-to-1 multiplexer : 4 - 28-bit 2-to-1 multiplexer : 4 - 29-bit 2-to-1 multiplexer : 8 - 3-bit 2-to-1 multiplexer : 21 - 30-bit 2-to-1 multiplexer : 4 - 32-bit 2-to-1 multiplexer : 135 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 4 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 80 - 4-bit 6-to-1 multiplexer : 2 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 16 - 6-bit 2-to-1 multiplexer : 4 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 120 - 8-bit 4-to-1 multiplexer : 3 - 8-bit 8-to-1 multiplexer : 2 - 9-bit 2-to-1 multiplexer : 9 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 3 - 1-bit shifter logical left : 2 - 64-bit shifter logical right : 1 -# Tristates : 10 - 1-bit tristate buffer : 8 - 8-bit tristate buffer : 2 -# FSMs : 17 -# Xors : 410 - 1-bit xor2 : 289 - 1-bit xor3 : 18 - 1-bit xor4 : 10 - 32-bit xor2 : 93 - -========================================================================= -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Reading core <../../platform/virtex6/chipscope/ila/chipscope_ila.ngc>. -Reading core <../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc>. -Reading core <../../platform/virtex6/chipscope/ila/chipscope_ila_131072.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 6 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 12 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 14 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 34 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch grstd1.grst_full.rst_d1 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block rstblk. - You should achieve better results by setting this init to 0. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into accumulator : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into accumulator : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 2-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 4-word x 6-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 1024-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 1024-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32768-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32768-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16384-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal > | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | weB | connected to signal | high | - | addrB | connected to signal > | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block , in block . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block . - Found pipelined multiplier on signal : - - 1 pipeline level(s) found in a register connected to the multiplier macro output. - Pushing register(s) into the multiplier macro. -INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s). -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 18 - 1024x32-bit dual-port block RAM : 1 - 128x32-bit single-port block Read Only RAM : 2 - 16384x32-bit dual-port block RAM : 1 - 16x32-bit dual-port block RAM : 1 - 256x20-bit dual-port block RAM : 1 - 256x32-bit dual-port block RAM : 3 - 256x32-bit single-port block RAM : 1 - 256x32-bit single-port block Read Only RAM : 1 - 32768x32-bit dual-port block RAM : 1 - 32x32-bit dual-port block RAM : 2 - 4x2-bit single-port distributed Read Only RAM : 1 - 4x6-bit single-port distributed Read Only RAM : 1 - 8x1-bit single-port distributed Read Only RAM : 2 -# MACs : 2 - 16x16-to-16-bit MAC : 2 -# Multipliers : 1 - 16x16-bit registered multiplier : 1 -# Adders/Subtractors : 91 - 1-bit subtractor : 1 - 11-bit adder : 1 - 11-bit subtractor : 1 - 12-bit adder : 2 - 14-bit adder : 1 - 14-bit subtractor : 2 - 16-bit adder : 8 - 16-bit subtractor : 2 - 17-bit adder : 1 - 17-bit subtractor : 1 - 2-bit adder : 6 - 28-bit adder : 1 - 29-bit adder : 2 - 3-bit adder : 2 - 3-bit subtractor : 3 - 30-bit adder : 1 - 32-bit adder : 7 - 32-bit subtractor : 2 - 33-bit adder carry in : 1 - 33-bit subtractor borrow in : 1 - 4-bit adder : 16 - 5-bit adder : 8 - 6-bit adder : 1 - 7-bit adder : 4 - 7-bit subtractor : 4 - 8-bit adder : 4 - 8-bit subtractor : 6 - 9-bit subtractor : 2 -# Counters : 65 - 10-bit up counter : 1 - 15-bit down counter : 3 - 16-bit down counter : 5 - 16-bit up counter : 7 - 2-bit down counter : 1 - 2-bit up counter : 2 - 2-bit updown counter : 1 - 24-bit up counter : 1 - 3-bit up counter : 2 - 30-bit up counter : 2 - 32-bit down counter : 4 - 32-bit up counter : 1 - 4-bit up counter : 4 - 4-bit updown counter : 2 - 5-bit up counter : 6 - 5-bit updown counter : 4 - 6-bit up counter : 1 - 7-bit up counter : 1 - 8-bit down counter : 4 - 8-bit up counter : 6 - 8-bit updown counter : 3 - 9-bit down counter : 4 -# Accumulators : 3 - 11-bit up accumulator : 2 - 6-bit up loadable accumulator : 1 -# Registers : 7856 - Flip-Flops : 7856 -# Shift Registers : 100 - 32-bit dynamic shift register : 100 -# Comparators : 105 - 1-bit comparator equal : 2 - 10-bit comparator equal : 1 - 11-bit comparator equal : 5 - 11-bit comparator greater : 2 - 12-bit comparator equal : 1 - 12-bit comparator greater : 1 - 14-bit comparator equal : 1 - 16-bit comparator equal : 7 - 16-bit comparator greater : 9 - 16-bit comparator lessequal : 1 - 20-bit comparator equal : 1 - 32-bit comparator equal : 5 - 32-bit comparator greater : 3 - 32-bit comparator lessequal : 2 - 4-bit comparator equal : 2 - 4-bit comparator greater : 12 - 4-bit comparator lessequal : 1 - 5-bit comparator equal : 8 - 5-bit comparator not equal : 3 - 6-bit comparator equal : 2 - 7-bit comparator greater : 3 - 7-bit comparator lessequal : 3 - 7-bit comparator not equal : 1 - 8-bit comparator equal : 20 - 8-bit comparator greater : 6 - 8-bit comparator lessequal : 1 - 8-bit comparator not equal : 2 -# Multiplexers : 2407 - 1-bit 128-to-1 multiplexer : 4 - 1-bit 2-to-1 multiplexer : 1831 - 1-bit 3-to-1 multiplexer : 5 - 1-bit 4-to-1 multiplexer : 41 - 1-bit 7-to-1 multiplexer : 64 - 1-bit 8-to-1 multiplexer : 19 - 11-bit 2-to-1 multiplexer : 9 - 14-bit 2-to-1 multiplexer : 4 - 16-bit 2-to-1 multiplexer : 37 - 16-bit 3-to-1 multiplexer : 1 - 2-bit 2-to-1 multiplexer : 24 - 20-bit 2-to-1 multiplexer : 1 - 23-bit 2-to-1 multiplexer : 2 - 24-bit 2-to-1 multiplexer : 5 - 28-bit 2-to-1 multiplexer : 4 - 29-bit 2-to-1 multiplexer : 8 - 3-bit 2-to-1 multiplexer : 18 - 30-bit 2-to-1 multiplexer : 2 - 32-bit 2-to-1 multiplexer : 113 - 32-bit 25-to-1 multiplexer : 1 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 2 - 32-bit 8-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 74 - 4-bit 6-to-1 multiplexer : 2 - 48-bit 2-to-1 multiplexer : 9 - 5-bit 2-to-1 multiplexer : 14 - 6-bit 2-to-1 multiplexer : 1 - 64-bit 2-to-1 multiplexer : 1 - 7-bit 2-to-1 multiplexer : 6 - 8-bit 2-to-1 multiplexer : 92 - 8-bit 4-to-1 multiplexer : 3 - 9-bit 2-to-1 multiplexer : 4 - 96-bit 2-to-1 multiplexer : 1 -# Logic shifters : 3 - 1-bit shifter logical left : 2 - 64-bit shifter logical right : 1 -# FSMs : 17 -# Xors : 410 - 1-bit xor2 : 289 - 1-bit xor3 : 18 - 1-bit xor4 : 10 - 32-bit xor2 : 93 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d1 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1426 - The value init of the FF/Latch cmp_adc_data_async_fifo/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0 hinder the constant cleaning in the block fmc_adc_data. - You should achieve better results by setting this init to 0. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - st_idle | 000 - st_start | 001 - st_read | 010 - st_write | 011 - st_ack | 100 - st_stop | 101 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 00000 - start_a | 00001 - start_b | 00010 - start_c | 00011 - start_d | 00100 - start_e | 00101 - stop_a | 00110 - stop_b | 00111 - stop_c | 01000 - stop_d | 01001 - rd_a | 01010 - rd_b | 01011 - rd_c | 01100 - rd_d | 01101 - wr_a | 01110 - wr_b | 01111 - wr_c | 10000 - wr_d | 10001 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - eth | 0001 - eth_capture | 0010 - eth_chk | 0011 - ipv4 | 0100 - ipv4_capture | 0101 - ipv4_chksum | unreached - ipv4_opt | 0111 - udp | 1000 - udp_fetch_buf | 1001 - udp_capture | 1010 - chk | 1011 - done | 1100 - errors | 1101 - waits | 1110 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - idle | 000 - header | 001 - payload | 010 - padding | 011 - done | 100 - errors | 101 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------------------ - State | Encoding ------------------------------------ - idle | 00000 - eb_hdr_rec | 00001 - eb_hdr_proc | 00010 - eb_hdr_probe_id | 00011 - eb_hdr_probe_rdy | 00100 - cyc_hdr_rec | 00101 - cyc_hdr_read_proc | 00110 - cyc_hdr_read_get_adr | 00111 - wb_read_rdy | 01000 - wb_read | 01001 - cyc_hdr_write_proc | 01010 - cyc_hdr_write_get_adr | 01011 - wb_write_rdy | 01100 - wb_write | 01101 - wb_write_done | 01110 - cyc_done | 01111 - eb_done | 10000 - error | 10001 - error_wait | 10010 ------------------------------------ -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------- - State | Encoding -------------------------------------- - idle | 000000000001 - eb_hdr_init | 000000000100 - eb_hdr_probe_id | 001000000000 - eb_hdr_probe_wait | 000010000000 - packet_hdr_send | 000001000000 - eb_hdr_send | 000100000000 - rdy | 000000000010 - cyc_hdr_init | 000000001000 - cyc_hdr_send | 010000000000 - base_write_adr_send | 000000010000 - data_send | 100000000000 - zero_pad_write | 000000100000 - zero_pad_wait | unreached - error | unreached -------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------------- - State | Encoding ---------------------------- - idle | 0000 - calc_chksum | 0001 - wait_send_req | 0010 - prep_eth | 0011 - eth | 0100 - ipv4 | 0101 - udp | 0110 - hdr_send | 0111 - payload_send | 1000 - padding | 1001 - wait_ifgap | 1010 - error | 1011 ---------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - addup | 001 - carries | 010 - finalise | 011 - output | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ----------------------- - State | Encoding ----------------------- - idle | 00 - init | 01 - transfer | 11 - waiting | unreached - done | 10 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------- - State | Encoding ----------------------- - idle | 000 - init | 001 - transfer | 010 - waiting | unreached - done | 100 ----------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0110 | 0010 - 0101 | 0011 - 0010 | 0100 - 0011 | 0101 - 0100 | 0110 - 0111 | 0111 - 1000 | 1000 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0001 | 00 - 0010 | 01 - 0100 | 11 - 1000 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 011 | 011 - 100 | 100 -------------------- -WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL. - You should achieve better results by setting this init to 1. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:1901 - Instance gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufio.cmp_adc_clk_bufio in unit fmc_adc_iface of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufio.cmp_adc_clk_bufio in unit fmc_adc_iface of type BUFIO has been replaced by BUFIODQS -INFO:Xst:1901 - Instance gen_adc_data[0].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[1].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[2].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[3].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[4].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[5].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[6].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_data[7].gen_with_ddr.cmp_iddr in unit fmc_adc_data of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2973 - All outputs of instance of block are unconnected in block . Underlying logic will be removed. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:638 - in unit dbe_bpm_fmc516 Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_fmc516 Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost. -WARNING:Xst:638 - in unit dbe_bpm_fmc516 Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 5 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : - -Mapping all equations... -Building and optimizing final netlist ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_fmc516, actual ratio is 12. - -Final Macro Processing ... - -Processing Unit : - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 5-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 7647 - Flip-Flops : 7647 -# Shift Registers : 76 - 2-bit shift register : 67 - 3-bit shift register : 1 - 5-bit shift register : 8 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- ---------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ---------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -sys_clk_p_i | IBUFGDS+BUFG | 11 | -cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| MMCM_ADV:CLKOUT0 | 1906 | -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 7253 | -mrx_clk_pad_i | BUFGP | 287 | -mtx_clk_pad_i | BUFGP | 1006 | -cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 259 | -cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/adc_clk_ibufgds_dly| BUFR | 260 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtag_cores/jtag_tap/update_delay)| 23 | -cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 961 | -cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL3<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/CONTROL2<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | -cmp_chipscope_icon_0/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD) | 1 | -cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC) | 1 | ---------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+ -(*) These 4 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -FindSrcOfAsyncThruGates : 100 (1) -FindSrcOfAsyncThruGates : 200 (1) -FindSrcOfAsyncThruGates : 300 (1) -FindSrcOfAsyncThruGates : 400 (1) -FindSrcOfAsyncThruGates : 500 (1) -FindSrcOfAsyncThruGates : 600 (1) -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_131072_0_adc/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 1040 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.U_SBRAM_2/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_SBRAM_3/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[14].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[15].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[16].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[17].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[18].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[19].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[20].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[21].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[22].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[23].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[25].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[26].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[27].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[28].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[29].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[30].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[31].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[32].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[33].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[34].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[35].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[36].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[37].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[38].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[39].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[40].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[41].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[42].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[43].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[44].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[45].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[46].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[47].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[48].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[49].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[50].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[51].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[52].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[53].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[54].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[55].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[56].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[57].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[58].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[59].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[60].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[61].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[62].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[63].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[64].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_131072_0_adc/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_EQ_112K_OR_128K.u_sBRAM_1/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G) | NONE(cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_adc_data_chains[1].gen_adc_data_chains_check.cmp_fmc_adc_data/cmp_adc_data_async_fifo/wrapped_gen/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM18.ram) | 60 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_fmc516_clk1/XST_VCC:P) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_2_ethmac_tx/XST_VCC:P) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_3_fmc516_periph/XST_VCC:P) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1_fmc516_clk1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_2_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_3_fmc516_periph/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1) | 6 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo) | 4 | -cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_10923_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_10923_o1:O) | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo) | 4 | -cmp_xwb_fmc516/cmp_wb_fmc516/gen_wbs_interfaces[0].gen_wbs_interfaces_ch.cmp_wb_stream_source_gen/cmp_fifo/do_write(XST_VCC:P) | NONE(cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_bufr.cmp_adc_clk_bufr) | 2 | -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 7.345ns (Maximum Frequency: 136.147MHz) - Minimum input arrival time before clock: 4.831ns - Maximum output required time after clock: 1.801ns - Maximum combinational path delay: 0.896ns - -========================================================================= - -Process "Synthesize - XST" completed successfully - -Started : "Translate". -Running ngdbuild... -Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope/icon_4_port -sd ../../platform/virtex6/chipscope/icon_7_port -sd ../../platform/virtex6/chipscope/icon_8_port -sd ../../platform/virtex6/chipscope/icon_13_port -sd ../../platform/virtex6/chipscope/ila -sd ../../platform/virtex6/chipscope/vio -sd ../../platform/virtex6/ip_cores -sd ../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_fmc516.ngc dbe_bpm_fmc516.ngd - -Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle -ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd -../../platform/virtex6/chipscope/icon_2_port -sd -../../platform/virtex6/chipscope/icon_4_port -sd -../../platform/virtex6/chipscope/icon_7_port -sd -../../platform/virtex6/chipscope/icon_8_port -sd -../../platform/virtex6/chipscope/icon_13_port -sd -../../platform/virtex6/chipscope/ila -sd ../../platform/virtex6/chipscope/vio --sd ../../platform/virtex6/ip_cores -sd -../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf -p -xc6vlx240t-ff1156-1 dbe_bpm_fmc516.ngc dbe_bpm_fmc516.ngd - -Reading NGO file -"/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.ngc" ... -Loading design module -"../../platform/virtex6/chipscope/ila/chipscope_ila.ngc"... -Loading design module -"../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc"... -Loading design module -"../../platform/virtex6/chipscope/ila/chipscope_ila_131072.ngc"... - /dbe_bpm_fmc516/dbe_bpm_fmc516 - /dbe_bpm_fmc516/cmp_chipscope_ila_1_fmc516_clk1 - /dbe_bpm_fmc516/cmp_chipscope_ila_3_fmc516_periph - /dbe_bpm_fmc516/cmp_chipscope_ila_2_ethmac_tx - /dbe_bpm_fmc516/cmp_chipscope_ila_131072_0_adc - ------------------------------------------------ -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - ------------------------------------------------ - ------------------------------------------------ -Gathering constraint information from source properties... -Done. - -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf" ... -Resolving constraint associations... -Checking Constraint Associations... -WARNING:ConstraintSystem:137 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 25)]: No appropriate instances for the TNM constraint are driven by - "adc_clk0_p_i". - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 26)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named - 'adc_clk0_p_i'. - -WARNING:ConstraintSystem:137 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 28)]: No appropriate instances for the TNM constraint are driven by - "adc_clk1_p_i". - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 29)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named - 'adc_clk1_p_i'. - -WARNING:ConstraintSystem:137 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 31)]: No appropriate instances for the TNM constraint are driven by - "adc_clk2_p_i". - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 32)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named - 'adc_clk2_p_i'. - -WARNING:ConstraintSystem:137 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 34)]: No appropriate instances for the TNM constraint are driven by - "adc_clk3_p_i". - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 35)]: Unable to find an active 'TNM' or 'TimeGrp' constraint named - 'adc_clk3_p_i'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 90)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint - named 'TNM_ADC_DATA_2'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 91)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint - named 'TNM_ADC_DATA_2'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 93)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint - named 'TNM_ADC_DATA_3'. - -WARNING:ConstraintSystem:56 - Constraint - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 94)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint - named 'TNM_ADC_DATA_3'. - -WARNING:ConstraintSystem:191 - The TNM 'adc_clk0_p_i', does not directly or - indirectly drive any flip-flops, latches and/or RAMS and cannot be actively - used by the referencing Period constraint 'TS_adc_clk0_p_i'. If clock manager - blocks are directly or indirectly driven, a new TNM constraint will not be - derived even though the referencing constraint is a PERIOD constraint unless - an output of the clock manager drives flip-flops, latches or RAMs. This TNM - is used in the following user PERIOD specification: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 26)] - -WARNING:ConstraintSystem:197 - The following specification is invalid because - the referenced TNM constraint was removed: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 26)] - -WARNING:ConstraintSystem:191 - The TNM 'adc_clk1_p_i', does not directly or - indirectly drive any flip-flops, latches and/or RAMS and cannot be actively - used by the referencing Period constraint 'TS_adc_clk1_p_i'. If clock manager - blocks are directly or indirectly driven, a new TNM constraint will not be - derived even though the referencing constraint is a PERIOD constraint unless - an output of the clock manager drives flip-flops, latches or RAMs. This TNM - is used in the following user PERIOD specification: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 29)] - -WARNING:ConstraintSystem:197 - The following specification is invalid because - the referenced TNM constraint was removed: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 29)] - -WARNING:ConstraintSystem:191 - The TNM 'adc_clk2_p_i', does not directly or - indirectly drive any flip-flops, latches and/or RAMS and cannot be actively - used by the referencing Period constraint 'TS_adc_clk2_p_i'. If clock manager - blocks are directly or indirectly driven, a new TNM constraint will not be - derived even though the referencing constraint is a PERIOD constraint unless - an output of the clock manager drives flip-flops, latches or RAMs. This TNM - is used in the following user PERIOD specification: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 32)] - -WARNING:ConstraintSystem:197 - The following specification is invalid because - the referenced TNM constraint was removed: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 32)] - -WARNING:ConstraintSystem:191 - The TNM 'adc_clk3_p_i', does not directly or - indirectly drive any flip-flops, latches and/or RAMS and cannot be actively - used by the referencing Period constraint 'TS_adc_clk3_p_i'. If clock manager - blocks are directly or indirectly driven, a new TNM constraint will not be - derived even though the referencing constraint is a PERIOD constraint unless - an output of the clock manager drives flip-flops, latches or RAMs. This TNM - is used in the following user PERIOD specification: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 35)] - -WARNING:ConstraintSystem:197 - The following specification is invalid because - the referenced TNM constraint was removed: - - [/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf(1 - 35)] - -Done... - -Checking expanded design ... - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 20 - -Writing NGD file "dbe_bpm_fmc516.ngd" ... -Total REAL time to NGDBUILD completion: 41 sec -Total CPU time to NGDBUILD completion: 40 sec - -Writing NGDBUILD log file "dbe_bpm_fmc516.bld"... - -NGDBUILD done. - -Process "Translate" completed successfully - -Started : "Map". -Running map... -Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_fmc516_map.ncd dbe_bpm_fmc516.ngd dbe_bpm_fmc516.pcf -Using target part "6vlx240tff1156-1". -INFO:Map:284 - Map is running with the multi-threading option on. Map currently - supports the use of up to 2 processors. Based on the the user options and - machine load, Map will use 2 processors during this run. -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part -'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<7> connected to top level port - adc_data_ch3_p_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<7> connected to top level port - adc_data_ch3_n_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<6> connected to top level port - adc_data_ch3_p_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<6> connected to top level port - adc_data_ch3_n_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<5> connected to top level port - adc_data_ch3_p_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<5> connected to top level port - adc_data_ch3_n_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<4> connected to top level port - adc_data_ch3_p_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<4> connected to top level port - adc_data_ch3_n_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<3> connected to top level port - adc_data_ch3_p_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<3> connected to top level port - adc_data_ch3_n_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<2> connected to top level port - adc_data_ch3_p_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<2> connected to top level port - adc_data_ch3_n_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<1> connected to top level port - adc_data_ch3_p_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<1> connected to top level port - adc_data_ch3_n_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_p_i<0> connected to top level port - adc_data_ch3_p_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch3_n_i<0> connected to top level port - adc_data_ch3_n_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<7> connected to top level port - adc_data_ch2_p_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<7> connected to top level port - adc_data_ch2_n_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<6> connected to top level port - adc_data_ch2_p_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<6> connected to top level port - adc_data_ch2_n_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<5> connected to top level port - adc_data_ch2_p_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<5> connected to top level port - adc_data_ch2_n_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<4> connected to top level port - adc_data_ch2_p_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<4> connected to top level port - adc_data_ch2_n_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<3> connected to top level port - adc_data_ch2_p_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<3> connected to top level port - adc_data_ch2_n_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<2> connected to top level port - adc_data_ch2_p_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<2> connected to top level port - adc_data_ch2_n_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<1> connected to top level port - adc_data_ch2_p_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<1> connected to top level port - adc_data_ch2_n_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_p_i<0> connected to top level port - adc_data_ch2_p_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch2_n_i<0> connected to top level port - adc_data_ch2_n_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<7> connected to top level port - adc_data_ch1_p_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<7> connected to top level port - adc_data_ch1_n_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<6> connected to top level port - adc_data_ch1_p_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<6> connected to top level port - adc_data_ch1_n_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<5> connected to top level port - adc_data_ch1_p_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<5> connected to top level port - adc_data_ch1_n_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<4> connected to top level port - adc_data_ch1_p_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<4> connected to top level port - adc_data_ch1_n_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<3> connected to top level port - adc_data_ch1_p_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<3> connected to top level port - adc_data_ch1_n_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<2> connected to top level port - adc_data_ch1_p_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<2> connected to top level port - adc_data_ch1_n_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<1> connected to top level port - adc_data_ch1_p_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<1> connected to top level port - adc_data_ch1_n_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_p_i<0> connected to top level port - adc_data_ch1_p_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch1_n_i<0> connected to top level port - adc_data_ch1_n_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<7> connected to top level port - adc_data_ch0_p_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<7> connected to top level port - adc_data_ch0_n_i<7> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<6> connected to top level port - adc_data_ch0_p_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<6> connected to top level port - adc_data_ch0_n_i<6> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<5> connected to top level port - adc_data_ch0_p_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<5> connected to top level port - adc_data_ch0_n_i<5> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<4> connected to top level port - adc_data_ch0_p_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<4> connected to top level port - adc_data_ch0_n_i<4> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<3> connected to top level port - adc_data_ch0_p_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<3> connected to top level port - adc_data_ch0_n_i<3> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<2> connected to top level port - adc_data_ch0_p_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<2> connected to top level port - adc_data_ch0_n_i<2> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<1> connected to top level port - adc_data_ch0_p_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<1> connected to top level port - adc_data_ch0_n_i<1> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_p_i<0> connected to top level port - adc_data_ch0_p_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_data_ch0_n_i<0> connected to top level port - adc_data_ch0_n_i<0> has been removed. -WARNING:MapLib:701 - Signal adc_clk3_p_i connected to top level port - adc_clk3_p_i has been removed. -WARNING:MapLib:701 - Signal adc_clk3_n_i connected to top level port - adc_clk3_n_i has been removed. -WARNING:MapLib:701 - Signal adc_clk2_p_i connected to top level port - adc_clk2_p_i has been removed. -WARNING:MapLib:701 - Signal adc_clk2_n_i connected to top level port - adc_clk2_n_i has been removed. -WARNING:MapLib:701 - Signal adc_clk1_p_i connected to top level port - adc_clk1_p_i has been removed. -WARNING:MapLib:701 - Signal adc_clk1_n_i connected to top level port - adc_clk1_n_i has been removed. -WARNING:MapLib:701 - Signal adc_clk0_p_i connected to top level port - adc_clk0_p_i has been removed. -WARNING:MapLib:701 - Signal adc_clk0_n_i connected to top level port - adc_clk0_n_i has been removed. -WARNING:MapLib:41 - All members of TNM group "TNM_ADC_DATA_1" have been - optimized out of the design. -WARNING:MapLib:41 - All members of TNM group "TNM_ADC_DATA_0" have been - optimized out of the design. -WARNING:MapLib:53 - The offset specification "TIMEGRP TNM_ADC_DATA_0 OFFSET=IN - -200 pS VALID 1200 pS BEFORE adc_clk0_p_i RISING" has been discarded because - the referenced clock pad net (adc_clk0_p_i) was optimized away. -WARNING:MapLib:53 - The offset specification "TIMEGRP TNM_ADC_DATA_0 OFFSET=IN - -200 pS VALID 1200 pS BEFORE adc_clk0_p_i FALLING" has been discarded because - the referenced clock pad net (adc_clk0_p_i) was optimized away. -WARNING:MapLib:53 - The offset specification "TIMEGRP TNM_ADC_DATA_1 OFFSET=IN - -200 pS VALID 1200 pS BEFORE adc_clk1_p_i RISING" has been discarded because - the referenced clock pad net (adc_clk1_p_i) was optimized away. -WARNING:MapLib:53 - The offset specification "TIMEGRP TNM_ADC_DATA_1 OFFSET=IN - -200 pS VALID 1200 pS BEFORE adc_clk1_p_i FALLING" has been discarded because - the referenced clock pad net (adc_clk1_p_i) was optimized away. -Running directed packing... -Running delay-based LUT packing... -Updating timing models... -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 1 mins 5 secs -Total CPU time at the beginning of Placer: 1 mins 4 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:cf421cdb) REAL time: 1 mins 17 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:cf421cdb) REAL time: 1 mins 19 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:163dc79c) REAL time: 1 mins 19 secs - -Phase 4.37 Local Placement Optimization -Phase 4.37 Local Placement Optimization (Checksum:163dc79c) REAL time: 1 mins 19 secs - -Phase 5.2 Initial Placement for Architecture Specific Features - -...... - - -There are 12 clock regions on the target FPGA device: -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 1 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: | -| 4 BUFRs available, 1 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 2 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 1 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 1 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: | -| 4 BUFRs available, 1 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 2 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 1 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 1 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 1/4; bufrs - 1/4; regional-clock-spines - 2/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | Upper/ | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/ | 2 | 0 | 0 | 0 | 0 | 147 | 4 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 1/4; center-bufios - 0/4; bufrs - 1/4; regional-clock-spines - 2/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFIO | Upper/Lower | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 2 | 0 | 0 | 0 | 0 | 146 | 4 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - - - -###################################################################################### -# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT: -# -# Number of Regional Clocking Regions in the device: 12 (6 clock spines in each) -# Number of Regional Clock Networks used in this design: 4 (each network can be -# composed of up to 3 clock spines and cover up to 3 regional clock regions) -# -###################################################################################### - -# IO-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" driven by -"BUFIODQS_X1Y2" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_b -ufio.cmp_adc_clk_bufio" LOC = "BUFIODQS_X1Y2" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# IO-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" driven by -"BUFIODQS_X0Y6" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_b -ufio.cmp_adc_clk_bufio" LOC = "BUFIODQS_X0Y6" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufio" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -# Regional-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" driven by -"BUFR_X1Y1" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[1].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_b -ufr.cmp_adc_clk_bufr" LOC = "BUFR_X1Y1" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[1]_adc_clk_bufr" RANGE = -CLOCKREGION_X0Y0, CLOCKREGION_X0Y1; - - -# Regional-Clock "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" driven by -"BUFR_X0Y2" -INST -"cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/gen_clock_chains[0].gen_clock_chains_check.cmp_fmc_adc_clk/gen_with_b -ufr.cmp_adc_clk_bufr" LOC = "BUFR_X0Y2" ; -NET "cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" TNM_NET = -"TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" ; -TIMEGRP "TN_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" AREA_GROUP = -"CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc516/cmp_wb_fmc516/cmp_fmc516_adc_iface/adc_clk_chain_priv[0]_adc_clk_bufr" RANGE = -CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0; - - -Phase 5.2 Initial Placement for Architecture Specific Features (Checksum:bcaebca2) REAL time: 1 mins 33 secs - -Phase 6.36 Local Placement Optimization -Phase 6.36 Local Placement Optimization (Checksum:bcaebca2) REAL time: 1 mins 33 secs - -Phase 7.30 Global Clock Region Assignment -Phase 7.30 Global Clock Region Assignment (Checksum:bcaebca2) REAL time: 1 mins 33 secs - -Phase 8.3 Local Placement Optimization -Phase 8.3 Local Placement Optimization (Checksum:bcaebca2) REAL time: 1 mins 33 secs - -Phase 9.5 Local Placement Optimization -Phase 9.5 Local Placement Optimization (Checksum:bcaebca2) REAL time: 1 mins 33 secs - -Phase 10.8 Global Placement -............................................................................................................. -.................................................................................................................................................................................................... -........................................................................................... -..... -Phase 10.8 Global Placement (Checksum:c1e1183e) REAL time: 2 mins 8 secs - -Phase 11.5 Local Placement Optimization -Phase 11.5 Local Placement Optimization (Checksum:c1e1183e) REAL time: 2 mins 8 secs - -Phase 12.18 Placement Optimization -Phase 12.18 Placement Optimization (Checksum:5fe78458) REAL time: 2 mins 33 secs - -Phase 13.5 Local Placement Optimization -Phase 13.5 Local Placement Optimization (Checksum:5fe78458) REAL time: 2 mins 33 secs - -Phase 14.34 Placement Validation -Phase 14.34 Placement Validation (Checksum:8a0205f9) REAL time: 2 mins 34 secs - -Total REAL time to Placer completion: 2 mins 36 secs -Total CPU time to Placer completion: 2 mins 47 secs -Running post-placement packing... -Writing output files... - -Design Summary: -Number of errors: 0 -Number of warnings: 116 -Slice Logic Utilization: - Number of Slice Registers: 10,363 out of 301,440 3% - Number used as Flip Flops: 10,356 - Number used as Latches: 6 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 13,415 out of 150,720 8% - Number used as logic: 12,427 out of 150,720 8% - Number using O6 output only: 9,736 - Number using O5 output only: 525 - Number using O5 and O6: 2,166 - Number used as ROM: 0 - Number used as Memory: 707 out of 58,400 1% - Number used as Dual Port RAM: 0 - Number used as Single Port RAM: 0 - Number used as Shift Register: 707 - Number using O6 output only: 503 - Number using O5 output only: 1 - Number using O5 and O6: 203 - Number used exclusively as route-thrus: 281 - Number with same-slice register load: 241 - Number with same-slice carry load: 40 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 6,067 out of 37,680 16% - Number of LUT Flip Flop pairs used: 17,013 - Number with an unused Flip Flop: 7,684 out of 17,013 45% - Number with an unused LUT: 3,598 out of 17,013 21% - Number of fully used LUT-FF pairs: 5,731 out of 17,013 33% - Number of unique control sets: 545 - Number of slice register sites lost - to control set restrictions: 1,648 out of 301,440 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 72 out of 600 12% - Number of LOCed IOBs: 72 out of 72 100% - IOB Flip Flops: 32 - IOB Master Pads: 2 - IOB Slave Pads: 2 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 359 out of 416 86% - Number using RAMB36E1 only: 359 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 14 out of 832 1% - Number using RAMB18E1 only: 14 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 10 out of 32 31% - Number used as BUFGs: 10 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 32 out of 720 4% - Number used as ILOGICE1s: 32 - Number used as ISERDESE1s: 0 - Number of OLOGICE1/OSERDESE1s: 4 out of 720 1% - Number used as OLOGICE1s: 4 - Number used as OSERDESE1s: 0 - Number of BSCANs: 2 out of 4 50% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 2 out of 72 2% - Number of BUFRs: 2 out of 36 5% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 3 out of 768 1% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 5 out of 18 27% - Number of IODELAYE1s: 34 out of 720 4% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - Number of RPM macros: 49 -Average Fanout of Non-Clock Nets: 4.63 - -Peak Memory Usage: 1529 MB -Total REAL time to MAP completion: 2 mins 50 secs -Total CPU time to MAP completion (all processors): 3 mins 1 secs - -Mapping completed. -See MAP report file "dbe_bpm_fmc516_map.mrp" for details. - -Process "Map" completed successfully - -Started : "Place & Route". -Running par... -Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_fmc516_map.ncd dbe_bpm_fmc516.ncd dbe_bpm_fmc516.pcf - - - -Constraints file: dbe_bpm_fmc516.pcf. -Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_fmc516" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRODUCTION 1.17 2012-01-07". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 10,363 out of 301,440 3% - Number used as Flip Flops: 10,356 - Number used as Latches: 6 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 13,415 out of 150,720 8% - Number used as logic: 12,427 out of 150,720 8% - Number using O6 output only: 9,736 - Number using O5 output only: 525 - Number using O5 and O6: 2,166 - Number used as ROM: 0 - Number used as Memory: 707 out of 58,400 1% - Number used as Dual Port RAM: 0 - Number used as Single Port RAM: 0 - Number used as Shift Register: 707 - Number using O6 output only: 503 - Number using O5 output only: 1 - Number using O5 and O6: 203 - Number used exclusively as route-thrus: 281 - Number with same-slice register load: 241 - Number with same-slice carry load: 40 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 6,067 out of 37,680 16% - Number of LUT Flip Flop pairs used: 17,013 - Number with an unused Flip Flop: 7,684 out of 17,013 45% - Number with an unused LUT: 3,598 out of 17,013 21% - Number of fully used LUT-FF pairs: 5,731 out of 17,013 33% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 72 out of 600 12% - Number of LOCed IOBs: 72 out of 72 100% - IOB Flip Flops: 32 - IOB Master Pads: 2 - IOB Slave Pads: 2 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 359 out of 416 86% - Number using RAMB36E1 only: 359 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 14 out of 832 1% - Number using RAMB18E1 only: 14 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 10 out of 32 31% - Number used as BUFGs: 10 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 32 out of 720 4% - Number used as ILOGICE1s: 32 - Number used as ISERDESE1s: 0 - Number of OLOGICE1/OSERDESE1s: 4 out of 720 1% - Number used as OLOGICE1s: 4 - Number used as OSERDESE1s: 0 - Number of BSCANs: 2 out of 4 50% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 2 out of 72 2% - Number of BUFRs: 2 out of 36 5% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 3 out of 768 1% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 5 out of 18 27% - Number of IODELAYE1s: 34 out of 720 4% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -Starting initial Timing Analysis. REAL time: 15 secs -Finished initial Timing Analysis. REAL time: 15 secs - -Starting Router - - -Phase 1 : 156312 unrouted; REAL time: 20 secs - -Phase 2 : 105569 unrouted; REAL time: 29 secs - -Phase 3 : 36639 unrouted; REAL time: 1 mins 28 secs - -Phase 4 : 36639 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 35 secs - -Updating file: dbe_bpm_fmc516.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 56 secs - -Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 56 secs - -Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 56 secs - -Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 56 secs - -Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 56 secs - -Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 56 secs -Total REAL time to Router completion: 1 mins 56 secs -Total CPU time to Router completion: 1 mins 56 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -| clk_sys |BUFGCTRL_X0Y29| No | 2652 | 0.462 | 2.048 | -+---------------------+--------------+------+------+------------+-------------+ -| mtx_clk_pad_i_BUFGP | BUFGCTRL_X0Y2| No | 289 | 0.216 | 1.827 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<0> |BUFGCTRL_X0Y27| No | 819 | 0.461 | 2.048 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/adc_out[0]_ | | | | | | -| adc_clk | BUFGCTRL_X0Y1| No | 994 | 0.464 | 2.048 | -+---------------------+--------------+------+------+------------+-------------+ -| mrx_clk_pad_i_BUFGP | BUFGCTRL_X0Y3| No | 103 | 0.178 | 1.835 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain_priv[1]_adc_clk_ | | | | | | -| bufr | Regional Clk| No | 57 | 0.282 | 1.182 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain_priv[0]_adc_clk_ | | | | | | -| bufr | Regional Clk| No | 55 | 0.219 | 1.080 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_gen |BUFGCTRL_X0Y31| No | 5 | 0.004 | 1.810 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_200mhz |BUFGCTRL_X0Y28| No | 5 | 0.260 | 1.826 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_I1 | Local| | 3 | 0.000 | 1.665 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/gen_clock_ | | | | | | -|chains[1].gen_clock_ | | | | | | -|chains_check.cmp_fmc | | | | | | -|_adc_clk/gen_with_re | | | | | | -|f_clk.cmp_mmcm_adc_c | | | | | | -| lk_ML_NEW_I1 | Local| | 3 | 0.000 | 2.387 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL3<13> | Local| | 4 | 0.000 | 0.591 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_lm32/gen_profile | | | | | | -|_medium_icache_debug | | | | | | -|.U_Wrapped_LM32/jtck | | | | | | -| | Local| | 7 | 1.211 | 3.412 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL2<13> | Local| | 4 | 0.000 | 0.722 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_324_ML_NE | | | | | | -| W_CLK | Local| | 3 | 0.135 | 0.358 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/gen_clock_ | | | | | | -|chains[1].gen_clock_ | | | | | | -|chains_check.cmp_fmc | | | | | | -|_adc_clk/gen_with_re | | | | | | -|f_clk.cmp_mmcm_adc_c | | | | | | -| lk_ML_NEW_OUT | Local| | 2 | 0.000 | 0.359 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_OUT | Local| | 2 | 0.000 | 0.230 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_332_ML_NE | | | | | | -| W_CLK | Local| | 3 | 0.000 | 0.906 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<13> | Local| | 4 | 0.000 | 1.001 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL1<13> | Local| | 4 | 0.000 | 0.655 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_chipscope_icon_0 | | | | | | -| /U0/iUPDATE_OUT | Local| | 1 | 0.000 | 0.848 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain_priv[1]_adc_clk_ | | | | | | -| bufio | Local| | 32 | 0.211 | 1.499 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc516/cmp_w | | | | | | -|b_fmc516/cmp_fmc516_ | | | | | | -|adc_iface/adc_clk_ch | | | | | | -|ain_priv[0]_adc_clk_ | | | | | | -| bufio | Local| | 32 | 0.222 | 1.510 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -* The fanout is the number of component pins not the individual BEL loads, -for example SLICE loads not FF loads. - -Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) - - - -Generating Pad Report. - -All signals are completely routed. - -Total REAL time to PAR completion: 2 mins 4 secs -Total CPU time to PAR completion: 2 mins 4 secs - -Peak Memory Usage: 1329 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - No errors found. - -Number of error messages: 0 -Number of warning messages: 0 -Number of info messages: 0 - -Writing design to file dbe_bpm_fmc516.ncd - - - -PAR done! - -Process "Place & Route" completed successfully - -Started : "Generate Post-Place & Route Static Timing". -Running trce... -Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_fmc516.twx dbe_bpm_fmc516.ncd -o dbe_bpm_fmc516.twr dbe_bpm_fmc516.pcf -Loading device for application Rf_Device from file '6vlx240t.nph' in environment -/opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_fmc516" is an NCD, version 3.2, device xc6vlx240t, package ff1156, -speed -1 - -Analysis completed Fri Sep 13 17:04:14 2013 --------------------------------------------------------------------------------- - -Generating Report ... - -Number of warnings: 0 -Total time: 35 secs - -Process "Generate Post-Place & Route Static Timing" completed successfully - -Started : "Generate Programming File". -Running bitgen... -Command Line: bitgen -intstyle ise -f dbe_bpm_fmc516.ut dbe_bpm_fmc516.ncd -INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most - commonly, bitgen has determined and will use a specific value instead of the - generic command-line value of "Auto". Alternately, this message appears if - the same option is specified multiple times on the command-line. In this - case, the option listed last will be used. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL3<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL2<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For - DELAY_SRC I programming the IDATAIN or DATAIN input pins of IODELAYE1 must be - connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For DELAY_SRC I programming the - IDATAIN or DATAIN input pins of IODELAYE1 must be connected. -ERROR:PhysDesignRules:1762 - Issue with pin connections and/or configuration on - block::. For DELAY_SRC I programming the - IDATAIN or DATAIN input pins of IODELAYE1 must be connected. -ERROR:Bitgen:25 - DRC detected 34 errors and 4 warnings. Please see the - previously displayed individual error or warning messages for more details. - -Process "Generate Programming File" failed diff --git a/hdl/syn/ml605/dbe_bpm_simple/Makefile b/hdl/syn/ml605/dbe_bpm_simple/Makefile deleted file mode 100644 index 8540583a..00000000 --- a/hdl/syn/ml605/dbe_bpm_simple/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -######################################## -# This file was generated by hdlmake # -# http://ohwr.org/projects/hdl-make/ # -######################################## - -PROJECT := dbe_bpm_simple.xise -ISE_CRAP := *.b dbe_bpm_simple_top_summary.html *.tcl dbe_bpm_simple_top.bld dbe_bpm_simple_top.cmd_log *.drc dbe_bpm_simple_top.lso *.ncd dbe_bpm_simple_top.ngc dbe_bpm_simple_top.ngd dbe_bpm_simple_top.ngr dbe_bpm_simple_top.pad dbe_bpm_simple_top.par dbe_bpm_simple_top.pcf dbe_bpm_simple_top.prj dbe_bpm_simple_top.ptwx dbe_bpm_simple_top.stx dbe_bpm_simple_top.syr dbe_bpm_simple_top.twr dbe_bpm_simple_top.twx dbe_bpm_simple_top.gise dbe_bpm_simple_top.unroutes dbe_bpm_simple_top.ut dbe_bpm_simple_top.xpi dbe_bpm_simple_top.xst dbe_bpm_simple_top_bitgen.xwbt dbe_bpm_simple_top_envsettings.html dbe_bpm_simple_top_guide.ncd dbe_bpm_simple_top_map.map dbe_bpm_simple_top_map.mrp dbe_bpm_simple_top_map.ncd dbe_bpm_simple_top_map.ngm dbe_bpm_simple_top_map.xrpt dbe_bpm_simple_top_ngdbuild.xrpt dbe_bpm_simple_top_pad.csv dbe_bpm_simple_top_pad.txt dbe_bpm_simple_top_par.xrpt dbe_bpm_simple_top_summary.xml dbe_bpm_simple_top_usage.xml dbe_bpm_simple_top_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl - -#target for performing local synthesis -local: - echo "project open $(PROJECT)" > run.tcl - echo "process run {Generate Programming File} -force rerun_all" >> run.tcl - xtclsh run.tcl - - -#target for cleaing all intermediate stuff -clean: - rm -f $(ISE_CRAP) - rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo - -#target for cleaning final files -mrproper: - rm -f *.bit *.bin *.mcs - diff --git a/hdl/syn/ml605/dbe_bpm_simple/Manifest.py b/hdl/syn/ml605/dbe_bpm_simple/Manifest.py deleted file mode 100755 index e185129d..00000000 --- a/hdl/syn/ml605/dbe_bpm_simple/Manifest.py +++ /dev/null @@ -1,10 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc6vlx240t" -syn_grade = "-1" -syn_package = "ff1156" -syn_top = "dbe_bpm_simple_top" -syn_project = "dbe_bpm_simple.xise" - -modules = { "local" : [ "../../../top/ml_605/dbe_bpm_simple" ] }; diff --git a/hdl/syn/ml605/dbe_bpm_simple/dbe_bpm_simple.xise b/hdl/syn/ml605/dbe_bpm_simple/dbe_bpm_simple.xise deleted file mode 100644 index f1bc8bb0..00000000 --- a/hdl/syn/ml605/dbe_bpm_simple/dbe_bpm_simple.xise +++ /dev/null @@ -1,1611 +0,0 @@ - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hdl/syn/ml605/dbe_bpm_simple/make_output b/hdl/syn/ml605/dbe_bpm_simple/make_output deleted file mode 100644 index 96e9375e..00000000 --- a/hdl/syn/ml605/dbe_bpm_simple/make_output +++ /dev/null @@ -1,5960 +0,0 @@ -echo "project open dbe_bpm_simple.xise" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl -WARNING:ProjectMgmt - File /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_ngo - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/bitgen.xmsgs is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/map.xmsgs is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/ngdbuild.xmsgs is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/par.xmsgs is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/trce.xmsgs is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/xst.xmsgs is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.bld is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.cmd_log - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.drc is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.lso is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ncd is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngc is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngd is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngr is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.pad is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.par is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.pcf is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.prj is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ptwx is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.stx is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.syr is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twr is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twx is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.unroutes - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ut is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.xpi is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.xst is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_guide.ncd - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.map - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.mrp - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.ncd - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.ngm - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.xrpt - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_ngdbuild. - xrpt is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_pad.csv - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_pad.txt - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_par.xrpt - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_summary.x - ml is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_usage.xml - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_xst.xrpt - is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/webtalk.log is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/webtalk_pn.xml is missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/xlnx_auto_0_xdb is missing. -WARNING:ProjectMgmt - File /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/xst - is missing. - -Started : "Synthesize - XST". -Running xst... -Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.syr" -Reading design: dbe_bpm_simple_top.prj -INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL - -========================================================================= -* HDL Parsing * -========================================================================= -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 42. -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" into library work -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 34. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work -Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29. -Parsing module . -Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" into library work -Parsing module . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_wfifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value. -WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value. -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1 -Parsing package . -Parsing package body . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . -Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1 -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= -WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" Line 50: Range is empty (null range) - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 157: Using initial value ("UUUU") for wbs_src_i since it is never assigned - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 376: Assignment to clk_adc_rstn ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . -Warning: "Wishbone slave device #1 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." -Warning: "Wishbone slave device #0 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar." - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -Note: "Mapping slave #0[0x0/0xfffe0000]" -Note: "Mapping slave #1[0x10000000/0xfffe0000]" -Note: "Mapping slave #2[0x20000400/0xffffffe0]" -Note: "Mapping slave #3[0x20000500/0xffffff00]" -Note: "Mapping slave #4[0x20000600/0xffffff00]" -Note: "Mapping slave #5[0x20000700/0xffffff00]" -Note: "Mapping slave #6[0x20000800/0xffffff00]" -Note: "Mapping slave #7[0x20000000/0xfffffe00]" - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE. -Going to verilog side to elaborate module lm32_top_medium_icache_debug - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 49056: Result of 30-bit expression is truncated to fit in 29-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 41108: Assignment to pc_w ignored, since the identifier is never used - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45380: Assignment to op_user ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45414: Assignment to multiply ignored, since the identifier is never used -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45624: Result of 32-bit expression is truncated to fit in 29-bit target. - -Elaborating module . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44387. $display Data bus error. Address: 0 -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44535. $display Warning: Non-aligned halfword access. Address: 0x0 Time: $time . -"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44537. $display Warning: Non-aligned word access. Address: 0x0 Time: $time . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" Line 128: Result of 64-bit expression is truncated to fit in 32-bit target. - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Result of 3-bit expression is truncated to fit in 1-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Assignment to ie_csr_read_data ignored, since the identifier is never used -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Result of 32-bit expression is truncated to fit in 1-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Assignment to ip_csr_read_data ignored, since the identifier is never used -WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Result of 32-bit expression is truncated to fit in 1-bit target. -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Assignment to im_csr_read_data ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 47797: Net does not have a driver. - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 42753: Assignment to x_result_sel_logic_x ignored, since the identifier is never used - -Elaborating module . - -Elaborating module . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 39170: Assignment to jrstn ignored, since the identifier is never used -Back to vhdl to continue elaboration -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 72: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 74: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" Line 451. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" Line 114: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" Line 122: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" Line 393. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" Line 108: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" Line 383. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" Line 106: remains a black-box since it has no binding entity. - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" Line 398. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" Line 109: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" Line 121: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" Line 122: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 177: fsm_state should be on the sensitivity list of the process - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 67: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 68: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 69: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 70: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 71: Assignment to allzeros ignored, since the identifier is never used -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 324. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" Line 77: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" Line 190: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 186: fsm_state should be on the sensitivity list of the process -WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 188: stored_we should be on the sensitivity list of the process -WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 194: fsm_state should be on the sensitivity list of the process - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to rd_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to wr_int ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allones ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 61: Assignment to allzeros ignored, since the identifier is never used - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected - -Elaborating entity (architecture ) from library . -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 130: Net does not have a driver. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net does not have a driver. - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . - -Elaborating entity (architecture ) with generics from library . -INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net does not have a driver. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 266: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 274: remains a black-box since it has no binding entity. -WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 232: Net does not have a driver. -WARNING:Xst:2972 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 336. All outputs of instance of block are unconnected in block . Underlying logic will be removed. -WARNING:Xst:2972 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 359. All outputs of instance of block are unconnected in block . Underlying logic will be removed. - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 327: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 327: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 336: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 359: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 459: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 557: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 572: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 572: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 660: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 660: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 660: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd". - g_clkin_period = 5.0 - g_clkbout_mult_f = 5.0 - g_clk0_divide_f = 10.0 - g_clk1_divide = 5 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd". - g_clocks = 2 - g_logdelay = 10 - g_syncdepth = 3 - Found 10-bit register for signal . - Found 3-bit register for signal >. - Found 3-bit register for signal >. - Found 1-bit register for signal . - Found 10-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 17 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd". - g_sync_edge = "positive" - Register equivalent to has been removed - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd". - g_width = 255 - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit subtractor for signal > created at line 1308. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 33 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd". - g_num_masters = 4 - g_num_slaves = 7 - g_registered = true - g_wraparound = false - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000100000000000000000000000000000000000000000000010000000000000000010001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000111000000000000000000000000000000000000000000100000000000000000011111111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000000100000000000000000011000000000000000000000000000000000000000000010000000000000000001101111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000101000000000000000000000000000000000000000000100000000000000000010111111111000100000000000000000000000000000000000000000000000100100001010111111000110000010101000011000001000000000000000000000000000000010010000000010010000100000001000001001100010011100100110001010011010111110100011001001101010000110011000100110101001100000010000000100000001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000010000000000000000000000000000000000000000000010000000000000000001000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000010000 -00010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_sdb_addr = "00100000000000000000000000000000" - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd". - g_layout = -("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000100000000000000000000000000000000000000000000010000000000000000010001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000111000000000000000000000000000000000000000000100000000000000000011111111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000 -00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000000100000000000000000011000000000000000000000000000000000000000000010000000000000000001101111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000101000000000000000000000000000000000000000000100000000000000000010111111111000100000000000000000000000000000000000000000000000100100001010111111000110000010101000011000001000000000000000000000000000000010010000000010010000100000001000001001100010011100100110001010011010111110100011001001101010000110011000100110101001100000010000000100000001000000010000000100000001000000010000000100 -00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000010000000000000000000000000000000000000000000010000000000000000001000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000010000 -00010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001") - g_bus_end = "0000000000000000000000000000000011111111111111111111111111111111" -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom', is tied to its initial value. - Found 128x32-bit single-port Read Only RAM for signal . - Found 1-bit register for signal . - Found 7-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd". - g_num_masters = 4 - g_num_slaves = 8 - g_registered = true - g_address = ("00100000000000000000000000000000","00100000000000000000100000000000","00100000000000000000011100000000","00100000000000000000011000000000","00100000000000000000010100000000","00100000000000000000010000000000","00010000000000000000000000000000","00000000000000000000000000000000") - g_mask = ("11111111111111111111111000000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111111100000","11111111111111100000000000000000","11111111111111100000000000000000") -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 9-bit register for signal >. - Found 9-bit register for signal >. - Found 9-bit register for signal >. - Found 9-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 37 D-type flip-flop(s). - inferred 36 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd". - g_profile = "medium_icache_debug" -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port of the instance is unconnected or connected to loadless signal. - Found 3-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit subtractor for signal created at line 688. - Found 32-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 1241. - Found 3-bit subtractor for signal > created at line 650. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 70 D-type flip-flop(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 39161: Output port of the instance is unconnected or connected to loadless signal. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - eba_reset = 32'b00000000000000000000000000000000 - deba_reset = 32'b00010000000000000000000000000000 - icache_associativity = 1 - icache_sets = 256 - icache_bytes_per_line = 16 - icache_base_address = 32'b00000000000000000000000000000000 - icache_limit = 32'b01111111111111111111111111111111 - dcache_associativity = 1 - dcache_sets = 512 - dcache_bytes_per_line = 16 - dcache_base_address = 0 - dcache_limit = 0 - watchpoints = 32'b00000000000000000000000000000100 - breakpoints = 0 - interrupts = 32 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41044: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41154: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 23-bit register for signal . - Found 23-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 29-bit adder for signal created at line 41841. - Found 32-bit 3-to-1 multiplexer for signal created at line 41852. - Found 1-bit 8-to-1 multiplexer for signal created at line 41889. - Found 5-bit comparator equal for signal created at line 41592 - Found 5-bit comparator equal for signal created at line 41598 - Found 5-bit comparator equal for signal created at line 41779 - Found 5-bit comparator equal for signal created at line 41780 - Found 5-bit comparator equal for signal created at line 41781 - Found 5-bit comparator equal for signal created at line 41782 - Found 5-bit comparator equal for signal created at line 41783 - Found 5-bit comparator equal for signal created at line 41784 - Found 32-bit comparator equal for signal created at line 41883 - Found 1-bit comparator equal for signal created at line 41896 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 441 D-type flip-flop(s). - inferred 10 Comparator(s). - inferred 74 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 29-bit register for signal . - Found 29-bit adder for signal created at line 48969. - Found 2-bit adder for signal created at line 49199. - Found 8-bit 4-to-1 multiplexer for signal created at line 49131. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 314 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 256 - bytes_per_line = 16 - base_address = 32'b00000000000000000000000000000000 - limit = 32'b01111111111111111111111111111111 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 29-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 18 | - | Inputs | 11 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0001 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit subtractor for signal created at line 46392. - Found 2-bit adder for signal created at line 46469. - Found 20-bit comparator equal for signal created at line 46274 - Summary: - inferred 2 Adder/Subtractor(s). - inferred 41 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 8 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v". - data_width = 32 - address_width = 10 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1024x32-bit dual-port RAM for signal . - Found 10-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 10 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v". - data_width = 20 - address_width = 8 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 256x20-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - inferred 10 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - associativity = 1 - sets = 512 - bytes_per_line = 16 - base_address = 0 - limit = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 44142. - Summary: - inferred 180 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v". - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v". - Found 33-bit subtractor for signal created at line 69. - Found 33-bit subtractor for signal created at line 69. - Found 33-bit adder for signal created at line 68. - Found 33-bit adder for signal created at line 68. - Summary: - inferred 4 Adder/Subtractor(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v". - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Found 1-bit 4-to-1 multiplexer for signal > created at line 72. - Summary: - inferred 32 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 64-bit shifter logical right for signal created at line 128 - Summary: - inferred 33 D-type flip-flop(s). - inferred 3 Multiplexer(s). - inferred 1 Combinational logic shifter(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v". - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 115. - Found 16-bit adder for signal created at line 115. - Found 16x16-bit multiplier for signal created at line 109. - Found 16x16-bit multiplier for signal created at line 110. - Found 16x16-bit multiplier for signal created at line 111. - Summary: - inferred 3 Multiplier(s). - inferred 2 Adder/Subtractor(s). - inferred 160 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - interrupts = 32 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 11-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 3-to-1 multiplexer for signal created at line 50671. - Summary: - inferred 78 D-type flip-flop(s). - inferred 17 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 36 | - | Inputs | 13 | - | Outputs | 8 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 16-bit adder for signal created at line 50090. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 80 D-type flip-flop(s). - inferred 13 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v". - breakpoints = 0 - watchpoints = 32'b00000000000000000000000000000100 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <31>>. - Found 1-bit register for signal <30>>. - Found 1-bit register for signal <29>>. - Found 1-bit register for signal <28>>. - Found 1-bit register for signal <27>>. - Found 1-bit register for signal <26>>. - Found 1-bit register for signal <25>>. - Found 1-bit register for signal <24>>. - Found 1-bit register for signal <23>>. - Found 1-bit register for signal <22>>. - Found 1-bit register for signal <21>>. - Found 1-bit register for signal <20>>. - Found 1-bit register for signal <19>>. - Found 1-bit register for signal <18>>. - Found 1-bit register for signal <17>>. - Found 1-bit register for signal <16>>. - Found 1-bit register for signal <15>>. - Found 1-bit register for signal <14>>. - Found 1-bit register for signal <13>>. - Found 1-bit register for signal <12>>. - Found 1-bit register for signal <11>>. - Found 1-bit register for signal <10>>. - Found 1-bit register for signal <9>>. - Found 1-bit register for signal <8>>. - Found 1-bit register for signal <7>>. - Found 1-bit register for signal <6>>. - Found 1-bit register for signal <5>>. - Found 1-bit register for signal <4>>. - Found 1-bit register for signal <3>>. - Found 1-bit register for signal <2>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal <1>>. - Found 1-bit register for signal <0>>. - Found 1-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal <31>>. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 36 | - | Inputs | 8 | - | Outputs | 4 | - | Clock | clk_i (rising_edge) | - | Reset | rst_i (positive) | - | Reset type | synchronous | - | Reset State | 000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 32-bit comparator equal for signal created at line 47900 - Found 32-bit comparator equal for signal created at line 47900 - Found 32-bit comparator equal for signal created at line 47900 - Found 32-bit comparator equal for signal created at line 47900 - Summary: - inferred 138 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 35 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v". - addr_width = 5 - addr_depth = 32 - data_width = 32 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 32x32-bit dual-port RAM for signal . - Found 5-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v". - Found 11-bit register for signal . - Found 11-bit register for signal . - Summary: - inferred 22 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd". - logRingLen = 4 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16x32-bit dual-port RAM for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 32-bit adder for signal created at line 197. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit adder for signal created at line 213. - Found 5-bit adder for signal created at line 1241. - Found 5-bit adder for signal created at line 1241. - Found 32-bit subtractor for signal > created at line 1308. - Found 32-bit 7-to-1 multiplexer for signal created at line 180. - Found 4-bit comparator equal for signal created at line 224 - Found 5-bit comparator not equal for signal created at line 236 - Found 5-bit comparator not equal for signal created at line 237 - Found 5-bit comparator not equal for signal created at line 238 - Summary: - inferred 1 RAM(s). - inferred 7 Adder/Subtractor(s). - inferred 218 D-type flip-flop(s). - inferred 4 Comparator(s). - inferred 175 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd". - g_size = 22528 - g_init_file = "../../../embedded-sw/dbe.ram" - g_init_value = "" - g_must_have_init_file = true - g_slave1_interface_mode = pipelined - g_slave2_interface_mode = pipelined - g_slave1_granularity = byte - g_slave2_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 2 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = true - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "read_first" - g_init_file = "../../../embedded-sw/dbe.ram" - g_init_value = "" - g_dual_clock = false - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd". - g_data_width = 32 - g_size = 22528 - g_with_byte_enable = true - g_addr_conflict_resolution = "read_first" - g_init_file = "../../../embedded-sw/dbe.ram" - g_init_value = "" - g_fail_if_file_not_found = true -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. - Found 22528x32-bit dual-port RAM for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 64 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd". - g_interface_mode = classic - g_address_granularity = byte - g_packet_size = 32 - g_sim = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd". - g_interface_mode = classic - g_address_granularity = byte - g_packet_size = 32 - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 296: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 448: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 448: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 5-bit register for signal . - Found 5-bit adder for signal created at line 1241. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 5 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd". - g_sim = 0 -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 16-bit register for signal . - Found 16-bit register for signal . - Summary: - inferred 32 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd". - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd". - C_DEFAULT_DELAY = 0 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd". - C_NBITS = 14 - C_DEFAULT_DELAY = 15 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd". - Found 10-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 10-bit adder for signal created at line 53. - Found 10-bit comparator greater for signal created at line 52 - Summary: - inferred 1 Adder/Subtractor(s). - inferred 13 D-type flip-flop(s). - inferred 1 Comparator(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd". - g_sim = 0 -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" line 416: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 62-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 103 D-type flip-flop(s). - inferred 11 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd". - START_ADDR = "0000000000000000000000000000" - STOP_ADDR = "1111111111111111111111111111" - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" line 360: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" line 513: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 28-bit register for signal . - Found 28-bit register for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 9 | - | Inputs | 3 | - | Outputs | 8 | - | Clock | serial_clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 222. - Found 4-bit adder for signal created at line 485. - Found 32-bit subtractor for signal > created at line 445. - Found 1-bit tristate buffer for signal created at line 595 - Found 28-bit comparator greater for signal created at line 328 - Found 28-bit comparator lessequal for signal created at line 337 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 185 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 23 Multiplexer(s). - inferred 1 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd". - START_ADDR = "0000000000000000000000000000" - STOP_ADDR = "1111111111111111111111111111" -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 109: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 119: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 129: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 139: Output port of the instance is unconnected or connected to loadless signal. - Found 64-bit register for signal . - Found 28-bit register for signal . - Found 28-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 156 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 9 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd". - START_ADDR = "0000000000000000000000000000" - STOP_ADDR = "1111111111111111111111111111" - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" line 311: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" line 455: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 8 | - | Inputs | 3 | - | Outputs | 5 | - | Clock | serial_clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 180. - Found 5-bit adder for signal created at line 427. - Found 32-bit subtractor for signal > created at line 387. - Found 1-bit tristate buffer for signal created at line 496 - Found 28-bit comparator greater for signal created at line 279 - Found 28-bit comparator lessequal for signal created at line 288 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 132 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 18 Multiplexer(s). - inferred 1 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd". - START_ADDR = "0000000000000000000000000000" - STOP_ADDR = "1111111111111111111111111111" - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" line 300: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" line 446: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 2-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 8 | - | Inputs | 3 | - | Outputs | 5 | - | Clock | serial_clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 177. - Found 5-bit adder for signal created at line 417. - Found 32-bit subtractor for signal > created at line 377. - Found 1-bit tristate buffer for signal created at line 488 - Found 28-bit comparator greater for signal created at line 268 - Found 28-bit comparator lessequal for signal created at line 277 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 128 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 17 Multiplexer(s). - inferred 1 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd". - START_ADDR = "0000000000000000000000000000" - STOP_ADDR = "1111111111111111111111111111" - g_sim = 0 -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" line 316: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" line 462: Output port of the instance is unconnected or connected to loadless signal. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 2-bit register for signal . - Found 2-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 16-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 4 | - | Transitions | 8 | - | Inputs | 3 | - | Outputs | 5 | - | Clock | serial_clk (rising_edge) | - | Reset | rst (positive) | - | Reset type | asynchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit adder for signal created at line 182. - Found 5-bit adder for signal created at line 433. - Found 32-bit subtractor for signal > created at line 392. - Found 1-bit tristate buffer for signal created at line 503 - Found 28-bit comparator greater for signal created at line 282 - Found 28-bit comparator lessequal for signal created at line 291 - Summary: - inferred 3 Adder/Subtractor(s). - inferred 162 D-type flip-flop(s). - inferred 2 Comparator(s). - inferred 19 Multiplexer(s). - inferred 1 Tristate(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = pipelined - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 6-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 16-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 5-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit 7-to-1 multiplexer for signal created at line 104. - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 111 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" line 96: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd". - g_data_width = 43 - g_size = 32 - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 43-bit register for signal >. - Found 1-bit register for signal . - Found 5-bit register for signal . - Found 43-bit register for signal >. - Found 5-bit adder for signal created at line 142. - Found 5-bit subtractor for signal > created at line 144. -INFO:Xst:3019 - HDL ADVISOR - 1376 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. - Found 43-bit 32-to-1 multiplexer for signal created at line 109. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 1382 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd". - g_with_virtual_uart = false - g_with_physical_uart = true - g_interface_mode = pipelined - g_address_granularity = byte -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 175: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 175: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 226: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 41 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = pipelined - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 3 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. - Found 7-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - Summary: - inferred 45 D-type flip-flop(s). - inferred 8 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd". - g_baud_acc_width = 16 - Found 8-bit register for signal . - Found 17-bit register for signal . - Found 17-bit adder for signal created at line 39. - Summary: - inferred 1 Adder/Subtractor(s). - inferred 25 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd". - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 13 | - | Transitions | 26 | - | Inputs | 2 | - | Outputs | 6 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_518_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 1-bit 8-to-1 multiplexer for signal created at line 130. - Summary: - inferred 9 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd". - Found 1-bit register for signal . - Found 2-bit register for signal . - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 2-bit register for signal . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 10 | - | Transitions | 30 | - | Inputs | 3 | - | Outputs | 3 | - | Clock | clk_sys_i (rising_edge) | - | Reset | rst_n_i_INV_528_o (positive) | - | Reset type | synchronous | - | Reset State | 0000 | - | Encoding | auto | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 2-bit adder for signal created at line 1241. - Found 4-bit adder for signal created at line 1241. - Found 2-bit subtractor for signal > created at line 1308. - Summary: - inferred 2 Adder/Subtractor(s). - inferred 19 D-type flip-flop(s). - inferred 1 Multiplexer(s). - inferred 1 Finite State Machine(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd". - g_interface_mode = classic - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd". - g_interface_mode = classic - g_address_granularity = byte - g_num_pins = 8 - g_with_builtin_tristates = false -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port of the instance is unconnected or connected to loadless signal. -WARNING:Xst:2563 - Inout is never assigned. Tied to value Z. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 8x1-bit Read Only RAM for signal > - Found 8-bit tristate buffer for signal created at line 56 - Summary: - inferred 1 RAM(s). - inferred 97 D-type flip-flop(s). - inferred 8 Multiplexer(s). - inferred 1 Tristate(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd". - g_master_use_struct = true - g_master_mode = classic - g_master_granularity = word - g_slave_use_struct = false - g_slave_mode = classic - g_slave_granularity = byte -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. - Summary: - no macro. -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 9 - 1024x32-bit dual-port RAM : 1 - 128x32-bit single-port Read Only RAM : 1 - 16x32-bit dual-port RAM : 1 - 22528x32-bit dual-port RAM : 1 - 256x20-bit dual-port RAM : 1 - 32x32-bit dual-port RAM : 2 - 8x1-bit single-port Read Only RAM : 2 -# Multipliers : 3 - 16x16-bit multiplier : 3 -# Adders/Subtractors : 43 - 10-bit adder : 2 - 16-bit adder : 3 - 17-bit adder : 1 - 2-bit adder : 2 - 2-bit addsub : 1 - 2-bit subtractor : 1 - 29-bit adder : 2 - 3-bit subtractor : 1 - 32-bit adder : 4 - 32-bit subtractor : 6 - 33-bit adder : 2 - 33-bit subtractor : 2 - 4-bit adder : 6 - 5-bit adder : 8 - 5-bit addsub : 1 - 8-bit subtractor : 1 -# Registers : 752 - 1-bit register : 543 - 10-bit register : 3 - 11-bit register : 3 - 16-bit register : 11 - 17-bit register : 1 - 2-bit register : 7 - 23-bit register : 2 - 28-bit register : 10 - 29-bit register : 9 - 3-bit register : 5 - 32-bit register : 63 - 4-bit register : 12 - 43-bit register : 32 - 5-bit register : 20 - 6-bit register : 1 - 62-bit register : 1 - 64-bit register : 4 - 7-bit register : 2 - 8-bit register : 19 - 9-bit register : 4 -# Comparators : 28 - 1-bit comparator equal : 1 - 10-bit comparator greater : 1 - 20-bit comparator equal : 1 - 28-bit comparator greater : 4 - 28-bit comparator lessequal : 4 - 32-bit comparator equal : 5 - 4-bit comparator equal : 1 - 5-bit comparator equal : 8 - 5-bit comparator not equal : 3 -# Multiplexers : 651 - 1-bit 2-to-1 multiplexer : 435 - 1-bit 4-to-1 multiplexer : 32 - 1-bit 8-to-1 multiplexer : 2 - 10-bit 2-to-1 multiplexer : 1 - 11-bit 2-to-1 multiplexer : 2 - 16-bit 2-to-1 multiplexer : 4 - 2-bit 2-to-1 multiplexer : 5 - 23-bit 2-to-1 multiplexer : 2 - 28-bit 2-to-1 multiplexer : 1 - 29-bit 2-to-1 multiplexer : 7 - 3-bit 2-to-1 multiplexer : 6 - 32-bit 2-to-1 multiplexer : 102 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 6 - 43-bit 32-to-1 multiplexer : 1 - 5-bit 2-to-1 multiplexer : 13 - 64-bit 2-to-1 multiplexer : 8 - 8-bit 2-to-1 multiplexer : 14 - 8-bit 4-to-1 multiplexer : 1 - 9-bit 2-to-1 multiplexer : 4 -# Logic shifters : 1 - 64-bit shifter logical right : 1 -# Tristates : 6 - 1-bit tristate buffer : 4 - 8-bit tristate buffer : 2 -# FSMs : 9 -# Xors : 101 - 1-bit xor2 : 69 - 32-bit xor2 : 32 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Reading core <../../platform/virtex6/chipscope/chipscope_ila.ngc>. -Reading core <../../platform/virtex6/chipscope/icon_2_port/chipscope_icon_2_port.ngc>. -Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc>. -Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc>. -Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc>. -Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc>. -Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc>. -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -Loading core for timing and area information for instance . -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1 -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block . -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . -WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA<3> | connected to signal > | high | - | weA<2> | connected to signal > | high | - | weA<1> | connected to signal > | high | - | weA<0> | connected to signal > | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 22528-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | weB<3> | connected to signal > | high | - | weB<2> | connected to signal > | high | - | weB<1> | connected to signal > | high | - | weB<0> | connected to signal > | high | - | addrB | connected to signal | | - | diB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 32-word x 32-bit | | - | mode | read-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal > | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 1024-word x 32-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal <(refill_address<11:4>,refill_offset)> | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 1024-word x 32-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal > | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block , in block . - Multiplier in block and adder/subtractor in block are combined into a MAC. - The following registers are also absorbed by the MAC: in block . - Found pipelined multiplier on signal : - - 1 pipeline level(s) found in a register connected to the multiplier macro output. - Pushing register(s) into the multiplier macro. -INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s). -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 20-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 128-word x 32-bit | | - | mode | write-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3218 - HDL ADVISOR - The RAM > will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 8-word x 1-bit | | - | weA | connected to signal | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - | doA | connected to signal | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -The following registers are absorbed into counter : 1 register on signal . -INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 16-word x 32-bit | | - | clkA | connected to signal | rise | - | weA | connected to internal node | high | - | addrA | connected to signal > | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 16-word x 32-bit | | - | addrB | connected to signal > | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. - Found 32-bit dynamic shift register for signal >. -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 9 - 1024x32-bit dual-port block RAM : 1 - 128x32-bit single-port block Read Only RAM : 1 - 16x32-bit dual-port distributed RAM : 1 - 22528x32-bit dual-port block RAM : 1 - 256x20-bit dual-port block RAM : 1 - 32x32-bit dual-port block RAM : 2 - 8x1-bit single-port distributed Read Only RAM : 2 -# MACs : 2 - 16x16-to-16-bit MAC : 2 -# Multipliers : 1 - 16x16-bit registered multiplier : 1 -# Adders/Subtractors : 29 - 1-bit subtractor : 1 - 10-bit adder : 1 - 16-bit adder : 1 - 17-bit adder : 1 - 2-bit adder : 2 - 29-bit adder : 2 - 3-bit subtractor : 1 - 32-bit adder : 4 - 32-bit subtractor : 5 - 33-bit adder carry in : 1 - 33-bit subtractor borrow in : 1 - 4-bit adder : 5 - 5-bit adder : 4 -# Counters : 19 - 10-bit up counter : 2 - 2-bit updown counter : 1 - 32-bit down counter : 1 - 4-bit up counter : 5 - 5-bit up counter : 8 - 5-bit updown counter : 1 - 8-bit down counter : 1 -# Registers : 3793 - Flip-Flops : 3793 -# Shift Registers : 43 - 32-bit dynamic shift register : 43 -# Comparators : 28 - 1-bit comparator equal : 1 - 10-bit comparator greater : 1 - 20-bit comparator equal : 1 - 28-bit comparator greater : 4 - 28-bit comparator lessequal : 4 - 32-bit comparator equal : 5 - 4-bit comparator equal : 1 - 5-bit comparator equal : 8 - 5-bit comparator not equal : 3 -# Multiplexers : 941 - 1-bit 2-to-1 multiplexer : 751 - 1-bit 4-to-1 multiplexer : 32 - 1-bit 8-to-1 multiplexer : 2 - 10-bit 2-to-1 multiplexer : 1 - 11-bit 2-to-1 multiplexer : 1 - 16-bit 2-to-1 multiplexer : 3 - 2-bit 2-to-1 multiplexer : 5 - 23-bit 2-to-1 multiplexer : 2 - 28-bit 2-to-1 multiplexer : 1 - 29-bit 2-to-1 multiplexer : 7 - 3-bit 2-to-1 multiplexer : 5 - 32-bit 2-to-1 multiplexer : 92 - 32-bit 3-to-1 multiplexer : 3 - 32-bit 7-to-1 multiplexer : 2 - 4-bit 2-to-1 multiplexer : 5 - 5-bit 2-to-1 multiplexer : 10 - 64-bit 2-to-1 multiplexer : 8 - 8-bit 2-to-1 multiplexer : 6 - 8-bit 4-to-1 multiplexer : 1 - 9-bit 2-to-1 multiplexer : 4 -# Logic shifters : 1 - 64-bit shifter logical right : 1 -# FSMs : 9 -# Xors : 101 - 1-bit xor2 : 69 - 32-bit xor2 : 32 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 11 FFs/Latches, which will be removed : -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ----------------------------- - State | Encoding ----------------------------- - idle | 000 - reg_write | 001 - start_reg_read | 010 - reg_read | 011 - data_valid | 100 ----------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------- - State | Encoding ------------------------- - idle | 00 - instruct | 01 - data_io | 10 - data_valid | 11 ------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------- - State | Encoding ------------------------- - idle | 00 - instruct | 01 - data_io | 10 - data_valid | 11 ------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ------------------------- - State | Encoding ------------------------- - idle | 00 - instruct | 01 - data_io | 10 - data_valid | 11 ------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0100 | 0100 - 0011 | 0011 - 1000 | 1000 - 1001 | 1001 - 1010 | 1010 - 1011 | 1011 - 1100 | 1100 - 1101 | 1101 - 1110 | 1110 - 1111 | 1111 - 0010 | 0010 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 1000 | 0001 - 1001 | 0010 - 1010 | 0011 - 1011 | 0100 - 1100 | 0101 - 1101 | 0110 - 1110 | 0111 - 1111 | 1000 - 0001 | 1001 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with sequential encoding. -------------------- - State | Encoding -------------------- - 0000 | 0000 - 0001 | 0001 - 0110 | 0010 - 0101 | 0011 - 0010 | 0100 - 0011 | 0101 - 0100 | 0110 - 0111 | 0111 - 1000 | 1000 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------- - State | Encoding -------------------- - 0001 | 00 - 0010 | 01 - 0100 | 11 - 1000 | 10 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 000 | 000 - 001 | 001 - 010 | 010 - 011 | 011 - 100 | 100 -------------------- -INFO:Xst:2146 - In block , Shifter <32>> <35>> <33>> <34>> are equivalent, XST will keep only <32>>. -INFO:Xst:2146 - In block , Shifter <38>> <37>> <39>> <40>> are equivalent, XST will keep only <38>>. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[0].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[1].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[2].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[3].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[4].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[5].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance gen_adc_lvds_ddr[6].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK -INFO:Xst:1901 - Instance oserdes_clock in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[0].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[1].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[2].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[3].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[4].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[5].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[6].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance dac_data[7].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:1901 - Instance oserdes_frame in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1 -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>. -WARNING:Xst:2041 - Unit cdce72010_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo. -WARNING:Xst:2041 - Unit ads62p49_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo. -WARNING:Xst:2041 - Unit dac3283_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo. -WARNING:Xst:2041 - Unit amc7823_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 2 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : -INFO:Xst:3203 - The FF/Latch in Unit is the opposite to the following FF/Latch, which will be removed : - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block dbe_bpm_simple_top, actual ratio is 4. - -Final Macro Processing ... - -Processing Unit : - Found 3-bit shift register for signal . - Found 2-bit shift register for signal . -Unit processed. - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 3014 - Flip-Flops : 3014 -# Shift Registers : 2 - 2-bit shift register : 1 - 3-bit shift register : 1 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Clock Information: ------------------- ---------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ---------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+ -sys_clk_p_i | MMCM_ADV:CLKOUT0 | 3395 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_adc_if/gen_adc_clk.cmp_adc_str/s_strobe_dly | MMCM_ADV:CLKOUT0 | 868 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/serial_clk | BUFG | 303 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/gen_serial_clk.clk_div_3| BUFG | 82 | -sys_clk_p_i | IBUFGDS+BUFG | 11 | -cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL | BUFG | 379 | -cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)| 1 | -cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O) | NONE(*)(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)| 1 | -cmp_chipscope_icon_0/U0/iUPDATE_OUT | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD) | 1 | ---------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+ -(*) These 2 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 124 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36) | 72 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0/XST_VCC:P) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36) | 56 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1/XST_VCC:P) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 56 | -cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1) | 8 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w1:O) | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram) | 8 | -cmp_button_sys_ffs/rst_n_i_inv(XST_GND:G) | NONE(cmp_interconnect/rom/Mram_rom1) | 6 | -cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_4271_o(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_4271_o1:O) | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem) | 4 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/ads62p49_init_mem_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/ads62p49_init_mem_inst/XST_GND:G) | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/ads62p49_init_mem_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram) | 4 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/amc7823_init_mem_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/amc7823_init_mem_inst/XST_GND:G) | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/amc7823_init_mem_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram) | 4 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_ext_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_ext_inst/XST_GND:G) | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_ext_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram) | 4 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_int_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_int_inst/XST_GND:G) | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_int_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram) | 4 | -cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/dac3283_init_mem_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/dac3283_init_mem_inst/XST_GND:G) | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/dac3283_init_mem_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram) | 4 | -cbar_slave_i[1]_sel<0>(XST_VCC:P) | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_adc_if/gen_adc_clk.cmp_adc_str/cmp_bufr) | 2 | -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -1 - - Minimum period: 6.594ns (Maximum Frequency: 151.653MHz) - Minimum input arrival time before clock: 4.763ns - Maximum output required time after clock: 3.092ns - Maximum combinational path delay: 2.230ns - -========================================================================= - -Process "Synthesize - XST" completed successfully - -Started : "Translate". -Running ngdbuild... -Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope -sd ../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_simple_top.ngc dbe_bpm_simple_top.ngd - -Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle -ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd -../../platform/virtex6/chipscope/icon_2_port -sd -../../platform/virtex6/chipscope -sd -../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc -/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf --p xc6vlx240t-ff1156-1 dbe_bpm_simple_top.ngc dbe_bpm_simple_top.ngd - -Reading NGO file -"/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngc" ... -Loading design module "../../platform/virtex6/chipscope/chipscope_ila.ngc"... -Loading design module -"../../platform/virtex6/chipscope/icon_2_port/chipscope_icon_2_port.ngc"... -Loading design module -"../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc"... -Loading design module -"../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc"... -Loading design module -"../../modules/dbe_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc"... -Loading design module -"../../modules/dbe_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc"... -Loading design module -"../../modules/dbe_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc"... - /dbe_bpm_simple_top/dbe_bpm_simple_top - /dbe_bpm_simple_top/cmp_chipscope_ila_1 - /dbe_bpm_simple_top/cmp_chipscope_ila_0 - ------------------------------------------------ -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - ------------------------------------------------ - ------------------------------------------------ -Gathering constraint information from source properties... -Done. - -Annotating constraints to design from ucf file -"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf" -... -Resolving constraint associations... -Checking Constraint Associations... - - - - -Done... - -Checking expanded design ... - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 0 - -Writing NGD file "dbe_bpm_simple_top.ngd" ... -Total REAL time to NGDBUILD completion: 21 sec -Total CPU time to NGDBUILD completion: 21 sec - -Writing NGDBUILD log file "dbe_bpm_simple_top.bld"... - -NGDBUILD done. - -Process "Translate" completed successfully - -Started : "Map". -Running map... -Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_simple_top_map.ncd dbe_bpm_simple_top.ngd dbe_bpm_simple_top.pcf -Using target part "6vlx240tff1156-1". -INFO:Map:284 - Map is running with the multi-threading option on. Map currently - supports the use of up to 2 processors. Based on the the user options and - machine load, Map will use 2 processors during this run. -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part -'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -Running directed packing... -Running delay-based LUT packing... -Updating timing models... -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 1 mins 4 secs -Total CPU time at the beginning of Placer: 1 mins 4 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:15e7a8a3) REAL time: 1 mins 16 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:15e7a8a3) REAL time: 1 mins 18 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:f61fec8f) REAL time: 1 mins 18 secs - -Phase 4.37 Local Placement Optimization -Phase 4.37 Local Placement Optimization (Checksum:f61fec8f) REAL time: 1 mins 18 secs - -Phase 5.2 Initial Placement for Architecture Specific Features - -...... - - -There are 12 clock regions on the target FPGA device: -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: | -| 4 BUFRs available, 1 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 1 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| -| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: | -| 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | -| 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | -| 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | -| 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | -| | | -|------------------------------------------|------------------------------------------| - - -Clock-Region: - key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 0/4; bufrs - 1/4; regional-clock-spines - 1/6 -|----------------------------------------------------------------------------------------------------------------------------------------------------------- -| | clock | BRAM | | | | | | | | | | | | -| | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Upper Region| 96 | 0 | 0 | 80 | 80 | 26880 | 9600 | 17280 | 64 | 0 | 0 | 0 | <- Available resources in the upper region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| |CurrentRegion| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the current region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| | Lower Region| 96 | 0 | 0 | 80 | 80 | 23040 | 9600 | 13440 | 64 | 0 | 0 | 0 | <- Available resources in the lower region -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| clock | region | ----------------------------------------------- -| type | expansion | | -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- -| BUFR | Upper/Lower | 0 | 0 | 0 | 14 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" -|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- - - - - -###################################################################################### -# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT: -# -# Number of Regional Clocking Regions in the device: 12 (6 clock spines in each) -# Number of Regional Clock Networks used in this design: 1 (each network can be -# composed of up to 3 clock spines and cover up to 3 regional clock regions) -# -###################################################################################### - -# Regional-Clock "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" driven by "BUFR_X0Y6" -INST "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_adc_if/gen_adc_clk.cmp_adc_str/cmp_bufr" LOC = "BUFR_X0Y6" ; -NET "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" TNM_NET = -"TN_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" ; -TIMEGRP "TN_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" AREA_GROUP = -"CLKAG_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" ; -AREA_GROUP "CLKAG_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" RANGE = CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, -CLOCKREGION_X0Y2; - - -Phase 5.2 Initial Placement for Architecture Specific Features (Checksum:4b412ef8) REAL time: 1 mins 37 secs - -Phase 6.36 Local Placement Optimization -Phase 6.36 Local Placement Optimization (Checksum:4b412ef8) REAL time: 1 mins 37 secs - -Phase 7.30 Global Clock Region Assignment -Phase 7.30 Global Clock Region Assignment (Checksum:4b412ef8) REAL time: 1 mins 37 secs - -Phase 8.3 Local Placement Optimization -Phase 8.3 Local Placement Optimization (Checksum:4b412ef8) REAL time: 1 mins 37 secs - -Phase 9.5 Local Placement Optimization -Phase 9.5 Local Placement Optimization (Checksum:4b412ef8) REAL time: 1 mins 37 secs - -Phase 10.8 Global Placement -............................................................................................................................................ -......................................................................................................................................................................................... -....................... -.................................... -Phase 10.8 Global Placement (Checksum:7339deaa) REAL time: 2 mins 2 secs - -Phase 11.5 Local Placement Optimization -Phase 11.5 Local Placement Optimization (Checksum:7339deaa) REAL time: 2 mins 2 secs - -Phase 12.18 Placement Optimization -Phase 12.18 Placement Optimization (Checksum:ed97b792) REAL time: 2 mins 20 secs - -Phase 13.5 Local Placement Optimization -Phase 13.5 Local Placement Optimization (Checksum:ed97b792) REAL time: 2 mins 20 secs - -Phase 14.34 Placement Validation -Phase 14.34 Placement Validation (Checksum:f785ef2f) REAL time: 2 mins 21 secs - -Total REAL time to Placer completion: 2 mins 21 secs -Total CPU time to Placer completion: 2 mins 27 secs -Running post-placement packing... -Writing output files... - -Design Summary: -Number of errors: 0 -Number of warnings: 17 -Slice Logic Utilization: - Number of Slice Registers: 4,454 out of 301,440 1% - Number used as Flip Flops: 4,449 - Number used as Latches: 4 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 5,190 out of 150,720 3% - Number used as logic: 4,494 out of 150,720 2% - Number using O6 output only: 3,522 - Number using O5 output only: 154 - Number using O5 and O6: 818 - Number used as ROM: 0 - Number used as Memory: 400 out of 58,400 1% - Number used as Dual Port RAM: 24 - Number using O6 output only: 4 - Number using O5 output only: 0 - Number using O5 and O6: 20 - Number used as Single Port RAM: 0 - Number used as Shift Register: 376 - Number using O6 output only: 262 - Number using O5 output only: 0 - Number using O5 and O6: 114 - Number used exclusively as route-thrus: 296 - Number with same-slice register load: 281 - Number with same-slice carry load: 15 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 2,245 out of 37,680 5% - Number of LUT Flip Flop pairs used: 6,580 - Number with an unused Flip Flop: 2,836 out of 6,580 43% - Number with an unused LUT: 1,390 out of 6,580 21% - Number of fully used LUT-FF pairs: 2,354 out of 6,580 35% - Number of unique control sets: 209 - Number of slice register sites lost - to control set restrictions: 701 out of 301,440 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 90 out of 600 15% - Number of LOCed IOBs: 90 out of 90 100% - IOB Flip Flops: 14 - IOB Master Pads: 10 - IOB Slave Pads: 10 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 51 out of 416 12% - Number using RAMB36E1 only: 51 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 11 out of 832 1% - Number using RAMB18E1 only: 11 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 10 out of 32 31% - Number used as BUFGs: 10 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 14 out of 720 1% - Number used as ILOGICE1s: 14 - Number used as ISERDESE1s: 0 - Number of OLOGICE1/OSERDESE1s: 14 out of 720 1% - Number used as OLOGICE1s: 4 - Number used as OSERDESE1s: 10 - Number of BSCANs: 1 out of 4 25% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 1 out of 36 2% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 3 out of 768 1% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 1 out of 18 5% - Number of IODELAYE1s: 15 out of 720 2% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - Number of RPM macros: 24 -Average Fanout of Non-Clock Nets: 3.63 - -Peak Memory Usage: 1291 MB -Total REAL time to MAP completion: 2 mins 31 secs -Total CPU time to MAP completion (all processors): 2 mins 37 secs - -Mapping completed. -See MAP report file "dbe_bpm_simple_top_map.mrp" for details. - -Process "Map" completed successfully - -Started : "Place & Route". -Running par... -Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_simple_top_map.ncd dbe_bpm_simple_top.ncd dbe_bpm_simple_top.pcf - - - -Constraints file: dbe_bpm_simple_top.pcf. -Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_simple_top" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part. -WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRODUCTION 1.17 2012-01-07". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 4,454 out of 301,440 1% - Number used as Flip Flops: 4,449 - Number used as Latches: 4 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 1 - Number of Slice LUTs: 5,190 out of 150,720 3% - Number used as logic: 4,494 out of 150,720 2% - Number using O6 output only: 3,522 - Number using O5 output only: 154 - Number using O5 and O6: 818 - Number used as ROM: 0 - Number used as Memory: 400 out of 58,400 1% - Number used as Dual Port RAM: 24 - Number using O6 output only: 4 - Number using O5 output only: 0 - Number using O5 and O6: 20 - Number used as Single Port RAM: 0 - Number used as Shift Register: 376 - Number using O6 output only: 262 - Number using O5 output only: 0 - Number using O5 and O6: 114 - Number used exclusively as route-thrus: 296 - Number with same-slice register load: 281 - Number with same-slice carry load: 15 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 2,245 out of 37,680 5% - Number of LUT Flip Flop pairs used: 6,580 - Number with an unused Flip Flop: 2,836 out of 6,580 43% - Number with an unused LUT: 1,390 out of 6,580 21% - Number of fully used LUT-FF pairs: 2,354 out of 6,580 35% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 90 out of 600 15% - Number of LOCed IOBs: 90 out of 90 100% - IOB Flip Flops: 14 - IOB Master Pads: 10 - IOB Slave Pads: 10 - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 51 out of 416 12% - Number using RAMB36E1 only: 51 - Number using FIFO36E1 only: 0 - Number of RAMB18E1/FIFO18E1s: 11 out of 832 1% - Number using RAMB18E1 only: 11 - Number using FIFO18E1 only: 0 - Number of BUFG/BUFGCTRLs: 10 out of 32 31% - Number used as BUFGs: 10 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 14 out of 720 1% - Number used as ILOGICE1s: 14 - Number used as ISERDESE1s: 0 - Number of OLOGICE1/OSERDESE1s: 14 out of 720 1% - Number used as OLOGICE1s: 4 - Number used as OSERDESE1s: 10 - Number of BSCANs: 1 out of 4 25% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 1 out of 36 2% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 3 out of 768 1% - Number of EFUSE_USRs: 0 out of 1 0% - Number of FRAME_ECCs: 0 out of 1 0% - Number of GTXE1s: 0 out of 20 0% - Number of IBUFDS_GTXE1s: 0 out of 12 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 1 out of 18 5% - Number of IODELAYE1s: 15 out of 720 2% - Number of MMCM_ADVs: 2 out of 12 16% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 4 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx - Command Line Tools User Guide for information on generating a TSI report. -Starting initial Timing Analysis. REAL time: 25 secs -Finished initial Timing Analysis. REAL time: 25 secs - -WARNING:Par:288 - The signal cmp_dma/Mram_ring4_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring3_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring5_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring2_RAMD_D1_O has no load. PAR will not attempt to route this signal. -WARNING:Par:288 - The signal cmp_dma/Mram_ring1_RAMD_D1_O has no load. PAR will not attempt to route this signal. -Starting Router - - -Phase 1 : 48177 unrouted; REAL time: 31 secs - -Phase 2 : 37657 unrouted; REAL time: 36 secs - -Phase 3 : 12446 unrouted; REAL time: 1 mins 25 secs - -Phase 4 : 12446 unrouted; (Setup:0, Hold:15229, Component Switching Limit:0) REAL time: 1 mins 36 secs - -Updating file: dbe_bpm_simple_top.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0) REAL time: 1 mins 47 secs - -Phase 6 : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0) REAL time: 1 mins 47 secs - -Phase 7 : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0) REAL time: 1 mins 47 secs - -Phase 8 : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0) REAL time: 1 mins 47 secs - -Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 48 secs - -Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 48 secs -Total REAL time to Router completion: 1 mins 48 secs -Total CPU time to Router completion: 1 mins 49 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -| clk_sys | BUFGCTRL_X0Y4| No | 1215 | 0.313 | 1.893 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc150/cmp_w | | | | | | -|b_fmc150/cmp_fmc150_ | | | | | | -|testbench/cmp_fmc150 | | | | | | -|_ctrl/cdce72010_ctrl | | | | | | -|_inst/serial_clk_BUF | | | | | | -| G |BUFGCTRL_X0Y29| No | 105 | 0.186 | 1.780 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_adc | BUFGCTRL_X0Y2| No | 206 | 0.356 | 2.020 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<0> |BUFGCTRL_X0Y28| No | 166 | 0.435 | 2.019 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc150/cmp_w | | | | | | -|b_fmc150/cmp_fmc150_ | | | | | | -|testbench/cmp_fmc150 | | | | | | -|_ctrl/cdce72010_ctrl | | | | | | -|_inst/gen_serial_clk | | | | | | -| .clk_div_3_BUFG |BUFGCTRL_X0Y30| No | 27 | 0.261 | 1.860 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc150/cmp_w | | | | | | -|b_fmc150/cmp_fmc150_ | | | | | | -| testbench/adc_str | Regional Clk| No | 36 | 0.043 | 0.951 | -+---------------------+--------------+------+------+------------+-------------+ -| sys_clk_gen |BUFGCTRL_X0Y31| No | 5 | 0.004 | 1.822 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc150/cmp_w | | | | | | -|b_fmc150/cmp_fmc150_ | | | | | | -|testbench/clk_adc_2x | | | | | | -| | BUFGCTRL_X0Y0| No | 10 | 0.021 | 1.736 | -+---------------------+--------------+------+------+------------+-------------+ -| clk_200mhz | BUFGCTRL_X0Y5| No | 1 | 0.000 | 1.681 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL1<13> | Local| | 4 | 0.000 | 0.591 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_76_ML_NEW | | | | | | -| _CLK | Local| | 2 | 0.000 | 0.504 | -+---------------------+--------------+------+------+------------+-------------+ -|MMCM_PHASE_CALIBRATI | | | | | | -|ON_ML_LUT2_68_ML_NEW | | | | | | -| _CLK | Local| | 3 | 0.121 | 0.462 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc150/cmp_w | | | | | | -|b_fmc150/cmp_fmc150_ | | | | | | -|testbench/gen_clk.cm | | | | | | -|p_mmcm_adc_ML_NEW_OU | | | | | | -| T | Local| | 2 | 0.000 | 0.355 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_OUT | Local| | 2 | 0.000 | 0.562 | -+---------------------+--------------+------+------+------------+-------------+ -| CONTROL0<13> | Local| | 5 | 0.000 | 0.519 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_xwb_fmc150/cmp_w | | | | | | -|b_fmc150/cmp_fmc150_ | | | | | | -|testbench/gen_clk.cm | | | | | | -|p_mmcm_adc_ML_NEW_I1 | | | | | | -| | Local| | 3 | 0.000 | 1.074 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_sys_pll_inst/cmp | | | | | | -| _mmcm_ML_NEW_I1 | Local| | 3 | 0.000 | 1.424 | -+---------------------+--------------+------+------+------------+-------------+ -|cmp_chipscope_icon_0 | | | | | | -| /U0/iUPDATE_OUT | Local| | 1 | 0.000 | 0.992 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -* The fanout is the number of component pins not the individual BEL loads, -for example SLICE loads not FF loads. - -Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) - -Number of Timing Constraints that were not applied: 4 - -Asterisk (*) preceding a constraint indicates it was not met. - This may be due to a setup or hold violation. - ----------------------------------------------------------------------------------------------------------- - Constraint | Check | Worst Case | Best Case | Timing | Timing - | | Slack | Achievable | Errors | Score ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | MINPERIOD | 6.709ns| 1.429ns| 0| 0 - 0_testbench_adc_str_2x_out_0 = PERIOD | | | | | - TIMEGRP "cmp_xwb_fmc150_cmp_ | | | | | - wb_fmc150_cmp_fmc150_testbench_adc_str_2x | | | | | - _out_0" TS_adc_clk_ab_n_i / 2 HIG | | | | | - H 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | MINPERIOD | 6.709ns| 1.429ns| 0| 0 - 0_testbench_adc_str_2x_out_1 = PERIOD | | | | | - TIMEGRP "cmp_xwb_fmc150_cmp_ | | | | | - wb_fmc150_cmp_fmc150_testbench_adc_str_2x | | | | | - _out_1" TS_adc_clk_ab_p_i / 2 HIG | | | | | - H 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_adc_clk_ab_n_i = PERIOD TIMEGRP "adc_c | MINLOWPULSE | 10.276ns| 6.000ns| 0| 0 - lk_ab_n_i" 16.276 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_adc_clk_ab_p_i = PERIOD TIMEGRP "adc_c | SETUP | 14.354ns| 1.922ns| 0| 0 - lk_ab_p_i" 16.276 ns HIGH 50% | HOLD | 0.300ns| | 0| 0 - | MINLOWPULSE | 10.276ns| 6.000ns| 0| 0 ----------------------------------------------------------------------------------------------------------- - TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = I | SETUP | 7.855ns| 0.283ns| 0| 0 - N 8.138 ns VALID 16.276 ns BEFORE | HOLD | 6.300ns| | 0| 0 - COMP "adc_clk_ab_n_i" "RISING" | | | | | ----------------------------------------------------------------------------------------------------------- - TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = I | SETUP | 7.855ns| 0.283ns| 0| 0 - N 8.138 ns VALID 16.276 ns BEFORE | HOLD | 6.300ns| | 0| 0 - COMP "adc_clk_ab_p_i" "RISING" | | | | | ----------------------------------------------------------------------------------------------------------- - TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = I | SETUP | 7.873ns| 0.265ns| 0| 0 - N 8.138 ns VALID 16.276 ns BEFORE | HOLD | 6.318ns| | 0| 0 - COMP "adc_clk_ab_n_i" "RISING" | | | | | ----------------------------------------------------------------------------------------------------------- - TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = I | SETUP | 7.873ns| 0.265ns| 0| 0 - N 8.138 ns VALID 16.276 ns BEFORE | HOLD | 6.318ns| | 0| 0 - COMP "adc_clk_ab_p_i" "RISING" | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | SETUP | 10.362ns| 5.914ns| 0| 0 - 0_testbench_adc_str_out_1 = PERIOD | HOLD | 0.019ns| | 0| 0 - TIMEGRP "cmp_xwb_fmc150_cmp_wb_ | | | | | - fmc150_cmp_fmc150_testbench_adc_str_out_1 | | | | | - " TS_adc_clk_ab_p_i HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | MINPERIOD | 14.054ns| 2.222ns| 0| 0 - 0_testbench_adc_str_out_0 = PERIOD | | | | | - TIMEGRP "cmp_xwb_fmc150_cmp_wb_ | | | | | - fmc150_cmp_fmc150_testbench_adc_str_out_0 | | | | | - " TS_adc_clk_ab_n_i HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - - -Derived Constraint Report -Review Timing Report for more details on the following derived constraints. -To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" -or "Run Timing Analysis" from Timing Analyzer (timingan). -Derived Constraints for TS_adc_clk_ab_n_i -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|TS_adc_clk_ab_n_i | 16.276ns| 6.000ns| 2.858ns| 0| 0| 0| 0| -| TS_cmp_xwb_fmc150_cmp_wb_fmc15| 8.138ns| 1.429ns| N/A| 0| 0| 0| 0| -| 0_cmp_fmc150_testbench_adc_str| | | | | | | | -| _2x_out_0 | | | | | | | | -| TS_cmp_xwb_fmc150_cmp_wb_fmc15| 16.276ns| 2.222ns| N/A| 0| 0| 0| 0| -| 0_cmp_fmc150_testbench_adc_str| | | | | | | | -| _out_0 | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -Derived Constraints for TS_adc_clk_ab_p_i -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -| | Period | Actual Period | Timing Errors | Paths Analyzed | -| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| -| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | -+-------------------------------+-------------+-------------+----------WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/bitgen.xmsgs is - missing. ----+-------------+-------------+-------------+-------------+ -|TS_adc_clk_ab_p_i | 16.276ns| 6.000ns| 5.914ns| 0| 0| 28| 5775| -| TS_cmp_xwb_fmc150_cmp_wb_fmc15| 8.138ns| 1.429ns| N/A| 0| 0| 0| 0| -| 0_cmp_fmc150_testbench_adc_str| | | | | | | | -| _2x_out_1 | | | | | | | | -| TS_cmp_xwb_fmc150_cmp_wb_fmc15| 16.276ns| 5.914ns| N/A| 0| 0| 5775| 0| -| 0_cmp_fmc150_testbench_adc_str| | | | | | | | -| _out_1 | | | | | | | | -+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ - -All constraints were met. - - -Generating Pad Report. - -All signals are completely routed. - -WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - -Total REAL time to PAR completion: 1 mins 57 secs -Total CPU time to PAR completion: 1 mins 57 secs - -Peak Memory Usage: 1166 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - No errors found. - -Number of error messages: 0 -Number of warning messages: 7 -Number of info messages: 1 - -Writing design to file dbe_bpm_simple_top.ncd - - - -PAR done! -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/trce.xmsgs is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.drc is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twr is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twx is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ut is - missing. -WARNING:ProjectMgmt - File - /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/webtalk.log is missing. - -Process "Place & Route" completed successfully - -Started : "Generate Post-Place & Route Static Timing". -Running trce... -Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_simple_top.twx dbe_bpm_simple_top.ncd -o dbe_bpm_simple_top.twr dbe_bpm_simple_top.pcf -Loading device for application Rf_Device from file '6vlx240t.nph' in environment -/opt/Xilinx/13.4/ISE_DS/ISE/. - "dbe_bpm_simple_top" is an NCD, version 3.2, device xc6vlx240t, package -ff1156, speed -1 - -Analysis completed Wed Oct 24 16:30:41 2012 --------------------------------------------------------------------------------- - -Generating Report ... - -Number of warnings: 0 -Total time: 26 secs - -Process "Generate Post-Place & Route Static Timing" completed successfully - -Started : "Generate Programming File". -Running bitgen... -Command Line: bitgen -intstyle ise -f dbe_bpm_simple_top.ut dbe_bpm_simple_top.ncd -INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most - commonly, bitgen has determined and will use a specific value instead of the - generic command-line value of "Auto". Alternately, this message appears if - the same option is specified multiple times on the command-line. In this - case, the option listed last will be used. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal is - incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/oserdes_clock - with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. - -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/oserdes_frame - with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. - -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[4].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[1].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[6].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[3].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[0].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for cINFO:TclTasksC:1850 - process run : Generate Programming File is done. -omp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[5].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[2].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. -WARNING:PhysDesignRules:1362 - Unexpected programming for comp - cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[7].oser - des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to - be set 4. - -Process "Generate Programming File" completed successfully diff --git a/hdl/syn/pcie/.gitignore b/hdl/syn/pcie/.gitignore deleted file mode 100644 index 9cc5e2f7..00000000 --- a/hdl/syn/pcie/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -#Vivado working dirs -*.cache/ -*.hw/ -*.sim/ -*.runs/ -#Vivado project -*.xpr -#Other crap -*.jou -*.log diff --git a/hdl/syn/pcie/HDLMAKE_NOT_SUPPORTED b/hdl/syn/pcie/HDLMAKE_NOT_SUPPORTED deleted file mode 100644 index 905497f1..00000000 --- a/hdl/syn/pcie/HDLMAKE_NOT_SUPPORTED +++ /dev/null @@ -1,3 +0,0 @@ -As of version 2.1 HDLMake still doesn't support nor *.XCI definitions nor *.XDC constraints. -Therefore it won't be able to create complete project. -Use TCL script for creating proper Vivado project. diff --git a/hdl/syn/pcie/Manifest.py b/hdl/syn/pcie/Manifest.py deleted file mode 100644 index bca6bcad..00000000 --- a/hdl/syn/pcie/Manifest.py +++ /dev/null @@ -1,29 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc7k325t" #KC705 evalboard -#syn_device = "xc7a200t" #Creotech PCB - -syn_package = "ffg900" #KC705 evalboard -#syn_package = "ffg1156" #Creotech PCB - -syn_grade = "-2" #-1 for AFC, -2 for AFCK, KC705 -syn_top = "top" -syn_project = "bpm_pcie_k7" -#syn_project = "bpm_pcie_a7" -syn_tool = "vivado" - -if (syn_device == "xc7k325t"): - modules = {"local" : ["../../top/pcie", - "../../modules/pcie", - "../../ip_cores/pcie/7k325ffg900"]} - - files = "kc705.xdc" - -if (syn_device == "xc7a200t"): - modules = {"local" : ["../../top/pcie", - "../../modules/pcie", - "../../ip_cores/pcie/7a200ffg1156"]} - - files = "xc7a200tffg1156.xdc" - diff --git a/hdl/syn/pcie/afck.xdc b/hdl/syn/pcie/afck.xdc deleted file mode 100644 index 0ca6c486..00000000 --- a/hdl/syn/pcie/afck.xdc +++ /dev/null @@ -1,46 +0,0 @@ -################################################################# -# KC705 -################################################################# - -### IO constrainst ### -set_property IOSTANDARD LVCMOS25 [get_ports sys_rst_n] -set_property PULLUP true [get_ports sys_rst_n] -set_property PACKAGE_PIN AC26 [get_ports sys_rst_n] - -set_property LOC IBUFDS_GTE2_X0Y1 [get_cells -hier -filter {name=~ */pcieclk_ibuf}] - -set_property PACKAGE_PIN AG10 [get_ports ddr_sys_clk_p] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_p] -#set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddr_sys_clk_p] - -set_property PACKAGE_PIN AH10 [get_ports ddr_sys_clk_n] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_n] -#set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddr_sys_clk_n] - -#place DDR input PLL close input pins and DDR logic -set_property LOC PLLE2_ADV_X1Y2 [get_cells plle2_adv_inst] - -# PCIe Lane 0 -set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] -# PCIe Lane 1 -set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] -# PCIe Lane 2 -set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] -# PCIe Lane 3 -set_property LOC GTXE2_CHANNEL_X0Y3 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}] - -### Timing constraints -create_clock -name pci_sys_clk -period 10 [get_ports pci_sys_clk_p] - -create_clock -name ddr_sys_clk -period 8 [get_ports ddr_sys_clk_p] - -set_clock_groups -asynchronous \ - -group [get_clocks -include_generated_clocks bpm_pcie_i/pcie_core_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK] \ - -group [get_clocks -include_generated_clocks ddr_sys_clk] - -set_false_path -from [get_ports sys_rst_n] - -###### Bitstream settings ################## -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] diff --git a/hdl/syn/pcie/afcv3.xdc b/hdl/syn/pcie/afcv3.xdc deleted file mode 100644 index dbfb4fd6..00000000 --- a/hdl/syn/pcie/afcv3.xdc +++ /dev/null @@ -1,55 +0,0 @@ -################################################################# -# KC705 -################################################################# - -### IO constrainst ### -set_property IOSTANDARD LVCMOS25 [get_ports sys_rst_n] -set_property PULLUP true [get_ports sys_rst_n] -set_property PACKAGE_PIN AG26 [get_ports sys_rst_n] - -set_property LOC IBUFDS_GTE2_X0Y3 [get_cells -hier -filter {name=~ */pcieclk_ibuf}] - -set_property PACKAGE_PIN AK7 [get_ports ddr_sys_clk_p] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_p] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddr_sys_clk_p] - -set_property PACKAGE_PIN AL7 [get_ports ddr_sys_clk_n] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_n] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddr_sys_clk_n] - -#place DDR input PLL close input pins and DDR logic -set_property LOC PLLE2_ADV_X1Y1 [get_cells plle2_adv_inst] - -#XDC supplied by PCIe IP core generates GTP connection in reverse order, we have to swap it. -#Simply providing correct connections will generate errors "Cannot set LOC ... because the bel is occupied by ..." -#So, firstly set PCIe lanes to temporary locations -set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -# ..., and then the correct ones: -# PCIe Lane 0 -set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -# PCIe Lane 1 -set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -# PCIe Lane 2 -set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] -# PCIe Lane 3 -set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] - - -### Timing constraints -create_clock -name pci_sys_clk -period 10 [get_ports pci_sys_clk_p] - -create_clock -name ddr_sys_clk -period 8 [get_ports ddr_sys_clk_p] - -set_clock_groups -asynchronous \ - -group [get_clocks -include_generated_clocks bpm_pcie_i/pcie_core_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/TXOUTCLK] \ - -group [get_clocks -include_generated_clocks ddr_sys_clk] - -set_false_path -from [get_ports sys_rst_n] - -###### Bitstream settings ################## -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] diff --git a/hdl/syn/pcie/bpm_pcie_afck.tcl b/hdl/syn/pcie/bpm_pcie_afck.tcl deleted file mode 100644 index 6cb79410..00000000 --- a/hdl/syn/pcie/bpm_pcie_afck.tcl +++ /dev/null @@ -1,544 +0,0 @@ -# -# Vivado (TM) v2015.2 (64-bit) -# -# bpm_pcie_afck.tcl: Tcl script for re-creating project 'bpm_pcie_afck' -# -# Generated by Vivado on Fri Oct 02 20:17:24 CEST 2015 -# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 -# -# This file contains the Vivado Tcl commands for re-creating the project to the state* -# when this script was generated. In order to re-create the project, please source this -# file in the Vivado Tcl Shell. -# -# * Note that the runs in the created project will be configured the same way as the -# original project, however they will not be launched automatically. To regenerate the -# run results please launch the synthesis/implementation runs as needed. -# -#***************************************************************************************** -# NOTE: In order to use this script for source control purposes, please make sure that the -# following files are added to the source control system:- -# -# 1. This project restoration tcl script (bpm_pcie_afck.tcl) that was generated. -# -# 2. The following source(s) files that were local or imported into the original project. -# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) -# -# -# -# 3. The following remote source files that were added to the original project:- -# -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_Calculate.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_FSM.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/RxIn_Delays.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Interrupts.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Registers.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ipcores_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tlpControl.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/ddr_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_mem.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/bpm_pcie.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/top/pcie/top_afck.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ddr_core/mig_b.prj" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ddr_core/mig_a.prj" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/axi_interconnect/axi_interconnect.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/axi_datamover_0/axi_datamover_0.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/pcie_core/pcie_core.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ddr_core/ddr_core.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/syn/pcie/afck.xdc" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/tests.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/tf64_pcie_axi.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sample_tests1.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/board_common.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/helper_tasks.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_tx.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_rx.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_pl.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_expect_tasks.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_com.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_cfg.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_axi_trn_bridge.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_2_1_rport_7x.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/xilinx_pcie_2_1_rport_7x.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/wiredly.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen_ds.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model_parameters.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model.sv" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/board.v" -# -#***************************************************************************************** - -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project bpm_pcie_afck ./bpm_pcie_afck - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [get_projects bpm_pcie_afck] -set_property "default_lib" "xil_defaultlib" $obj -set_property "part" "xc7k325tffg900-2" $obj -set_property "simulator_language" "Mixed" $obj -set_property "source_mgmt_mode" "DisplayOnly" $obj -set_property "target_simulator" "Questa" $obj - -# Create 'sources_1' fileset (if not found) -if {[string equal [get_filesets -quiet sources_1] ""]} { - create_fileset -srcset sources_1 -} - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Interrupts.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Registers.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tx_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../platform/kintex7/afck/ipcores_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/wb_transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tlpControl.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/wb_mem.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/bpm_pcie.vhd"]"\ - "[file normalize "$origin_dir/../../top/pcie/top_afck.vhd"]"\ - "[file normalize "$origin_dir/../../platform/kintex7/afck/ddr_core/mig_b.prj"]"\ - "[file normalize "$origin_dir/../../platform/kintex7/afck/ddr_core/mig_a.prj"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Interrupts.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Registers.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tx_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../platform/kintex7/afck/ipcores_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/wb_transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tlpControl.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/wb_mem.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/bpm_pcie.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../top/pcie/top_afck.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset properties -set obj [get_filesets sources_1] -set_property "top" "top" $obj - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/afck/axi_interconnect/axi_interconnect.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/afck/axi_interconnect/axi_interconnect.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/afck/axi_datamover_0/axi_datamover_0.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/afck/axi_datamover_0/axi_datamover_0.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/afck/pcie_core/pcie_core.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/afck/pcie_core/pcie_core.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/afck/ddr_core/ddr_core.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/afck/ddr_core/ddr_core.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Create 'constrs_1' fileset (if not found) -if {[string equal [get_filesets -quiet constrs_1] ""]} { - create_fileset -constrset constrs_1 -} - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set file "[file normalize "$origin_dir/afck.xdc"]" -set file_added [add_files -norecurse -fileset $obj $file] -set file "$origin_dir/afck.xdc" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] -set_property "file_type" "XDC" $file_obj -set_property "used_in_synthesis" "0" $file_obj - -# Set 'constrs_1' fileset properties -set obj [get_filesets constrs_1] - -# Create 'sim_1' fileset (if not found) -if {[string equal [get_filesets -quiet sim_1] ""]} { - create_fileset -simset sim_1 -} - -# Set 'sim_1' fileset object -set obj [get_filesets sim_1] -set files [list \ - "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/tests.vh"]"\ - "[file normalize "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/sample_tests1.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/board_common.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/helper_tasks.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_tx.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_rx.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_pl.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_com.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_cfg.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pcie_axi_trn_bridge.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pcie_2_1_rport_7x.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/xilinx_pcie_2_1_rport_7x.v"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/wiredly.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen_ds.v"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv"]"\ - "[file normalize "$origin_dir/../../testbench/pcie/board.v"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sim_1' fileset file properties for remote files -set file "$origin_dir/../../sim/pcie/tests.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/sample_tests1.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/board_common.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "SystemVerilog" $file_obj - - -# Set 'sim_1' fileset file properties for local files -# None - -# Set 'sim_1' fileset properties -set obj [get_filesets sim_1] -set_property "questa.compile.vlog.more_options" "+define+SIMULATION +define+x1Gb +define+sg125 +define+x8" $obj -set_property "questa.simulate.log_all_signals" "1" $obj -set_property "questa.simulate.runtime" "300000ns" $obj -set_property "questa.simulate.vsim.more_options" "+notimingchecks+" $obj -set_property "runtime" "" $obj -set_property "top" "board" $obj - -# Create 'synth_1' run (if not found) -if {[string equal [get_runs -quiet synth_1] ""]} { - create_run -name synth_1 -part xc7k325tffg900-2 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 -} else { - set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] - set_property flow "Vivado Synthesis 2015" [get_runs synth_1] -} -set obj [get_runs synth_1] -set_property "part" "xc7k325tffg900-2" $obj - -# set the current synth run -current_run -synthesis [get_runs synth_1] - -# Create 'impl_1' run (if not found) -if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part xc7k325tffg900-2 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 -} else { - set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] - set_property flow "Vivado Implementation 2015" [get_runs impl_1] -} -set obj [get_runs impl_1] -set_property "part" "xc7k325tffg900-2" $obj -set_property "steps.opt_design.args.directive" "Explore" $obj -set_property "steps.place_design.args.directive" "Explore" $obj -set_property "steps.phys_opt_design.is_enabled" "1" $obj -set_property "steps.phys_opt_design.args.directive" "Explore" $obj -set_property "steps.route_design.args.directive" "Explore" $obj -set_property "steps.post_route_phys_opt_design.is_enabled" "1" $obj -set_property "steps.post_route_phys_opt_design.args.directive" "Explore" $obj -set_property "steps.write_bitstream.args.readback_file" "0" $obj -set_property "steps.write_bitstream.args.verbose" "0" $obj - -# set the current impl run -current_run -implementation [get_runs impl_1] - -puts "INFO: Project created:bpm_pcie_afck" diff --git a/hdl/syn/pcie/bpm_pcie_afcv3.tcl b/hdl/syn/pcie/bpm_pcie_afcv3.tcl deleted file mode 100644 index d1d5dcd6..00000000 --- a/hdl/syn/pcie/bpm_pcie_afcv3.tcl +++ /dev/null @@ -1,536 +0,0 @@ -# -# Vivado (TM) v2015.2 (64-bit) -# -# bpm_pcie_afcv3.tcl: Tcl script for re-creating project 'bpm_pcie_afcv3' -# -# Generated by Vivado on Fri Oct 02 18:20:15 CEST 2015 -# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 -# -# This file contains the Vivado Tcl commands for re-creating the project to the state* -# when this script was generated. In order to re-create the project, please source this -# file in the Vivado Tcl Shell. -# -# * Note that the runs in the created project will be configured the same way as the -# original project, however they will not be launched automatically. To regenerate the -# run results please launch the synthesis/implementation runs as needed. -# -#***************************************************************************************** -# NOTE: In order to use this script for source control purposes, please make sure that the -# following files are added to the source control system:- -# -# 1. This project restoration tcl script (bpm_pcie_afcv3.tcl) that was generated. -# -# 2. The following source(s) files that were local or imported into the original project. -# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) -# -# -# -# 3. The following remote source files that were added to the original project:- -# -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_FSM.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_Calculate.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/RxIn_Delays.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Interrupts.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Registers.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/ipcores_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tlpControl.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/ddr_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/bpm_pcie.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_mem.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/top/pcie/top_afcv3.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/ddr_core/mig_a.prj" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/ddr_core/mig_b.prj" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/pcie_core/pcie_core.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/ddr_core/ddr_core.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/axi_datamover_0/axi_datamover_0.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/artix7/afcv3/axi_interconnect/axi_interconnect.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/syn/pcie/afcv3.xdc" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/tests.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/tf64_pcie_axi.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sample_tests1.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/board_common.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/helper_tasks.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_tx.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_rx.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_pl.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_expect_tasks.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_com.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_cfg.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_axi_trn_bridge.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_2_1_rport_7x.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/xilinx_pcie_2_1_rport_7x.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/wiredly.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen_ds.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model_parameters.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model.sv" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/board.v" -# -#***************************************************************************************** - -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project bpm_pcie_afc_v3 ./bpm_pcie_afc_v3 - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [get_projects bpm_pcie_afc_v3] -set_property "default_lib" "xil_defaultlib" $obj -set_property "part" "xc7a200tffg1156-1" $obj -set_property "simulator_language" "Mixed" $obj -set_property "target_simulator" "Questa" $obj - -# Create 'sources_1' fileset (if not found) -if {[string equal [get_filesets -quiet sources_1] ""]} { - create_fileset -srcset sources_1 -} - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Interrupts.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tx_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Registers.vhd"]"\ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/ipcores_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/wb_transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tlpControl.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/bpm_pcie.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/wb_mem.vhd"]"\ - "[file normalize "$origin_dir/../../top/pcie/top_afcv3.vhd"]"\ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/ddr_core/mig_a.prj"]"\ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/ddr_core/mig_b.prj"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Interrupts.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tx_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Registers.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../platform/artix7/afc_v3/ipcores_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/wb_transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tlpControl.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/bpm_pcie.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/wb_mem.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../top/pcie/top_afcv3.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset properties -set obj [get_filesets sources_1] -set_property "top" "top" $obj - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/pcie_core/pcie_core.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/artix7/afc_v3/pcie_core/pcie_core.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/ddr_core/ddr_core.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/artix7/afc_v3/ddr_core/ddr_core.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/axi_datamover_0/axi_datamover_0.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/artix7/afc_v3/axi_datamover_0/axi_datamover_0.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/artix7/afc_v3/axi_interconnect/axi_interconnect.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/artix7/afc_v3/axi_interconnect/axi_interconnect.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Create 'constrs_1' fileset (if not found) -if {[string equal [get_filesets -quiet constrs_1] ""]} { - create_fileset -constrset constrs_1 -} - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set file "[file normalize "$origin_dir/afcv3.xdc"]" -set file_added [add_files -norecurse -fileset $obj $file] -set file "$origin_dir/afcv3.xdc" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] -set_property "file_type" "XDC" $file_obj -set_property "used_in_synthesis" "0" $file_obj - -# Set 'constrs_1' fileset properties -set obj [get_filesets constrs_1] - -# Create 'sim_1' fileset (if not found) -if {[string equal [get_filesets -quiet sim_1] ""]} { - create_fileset -simset sim_1 -} - -# Set 'sim_1' fileset object -set obj [get_filesets sim_1] -set files [list \ - "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/tests.vh"]"\ - "[file normalize "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/sample_tests1.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/board_common.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/helper_tasks.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_tx.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_rx.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_pl.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_com.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_cfg.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pcie_axi_trn_bridge.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pcie_2_1_rport_7x.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/xilinx_pcie_2_1_rport_7x.v"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/wiredly.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen_ds.v"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv"]"\ - "[file normalize "$origin_dir/../../testbench/pcie/board.v"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sim_1' fileset file properties for remote files -set file "$origin_dir/../../sim/pcie/tests.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/sample_tests1.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/board_common.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "SystemVerilog" $file_obj - - -# Set 'sim_1' fileset file properties for local files -# None - -# Set 'sim_1' fileset properties -set obj [get_filesets sim_1] -set_property "questa.compile.vlog.more_options" "+define+SIMULATION +define+x1Gb +define+sg125 +define+x8" $obj -set_property "questa.simulate.log_all_signals" "1" $obj -set_property "questa.simulate.runtime" "300000ns" $obj -set_property "questa.simulate.vsim.more_options" "+notimingchecks+" $obj -set_property "runtime" "" $obj -set_property "top" "board" $obj - -# Create 'synth_1' run (if not found) -if {[string equal [get_runs -quiet synth_1] ""]} { - create_run -name synth_1 -part xc7a200tffg1156-1 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 -} else { - set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] - set_property flow "Vivado Synthesis 2015" [get_runs synth_1] -} -set obj [get_runs synth_1] -set_property "part" "xc7a200tffg1156-1" $obj - -# set the current synth run -current_run -synthesis [get_runs synth_1] - -# Create 'impl_1' run (if not found) -if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part xc7a200tffg1156-1 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 -} else { - set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] - set_property flow "Vivado Implementation 2015" [get_runs impl_1] -} -set obj [get_runs impl_1] -set_property "part" "xc7a200tffg1156-1" $obj -set_property "steps.write_bitstream.args.readback_file" "0" $obj -set_property "steps.write_bitstream.args.verbose" "0" $obj - -# set the current impl run -current_run -implementation [get_runs impl_1] - -puts "INFO: Project created:bpm_pcie_afcv3" diff --git a/hdl/syn/pcie/bpm_pcie_kc705.tcl b/hdl/syn/pcie/bpm_pcie_kc705.tcl deleted file mode 100644 index 77b75955..00000000 --- a/hdl/syn/pcie/bpm_pcie_kc705.tcl +++ /dev/null @@ -1,544 +0,0 @@ -# -# Vivado (TM) v2015.2 (64-bit) -# -# bpm_pcie_kc705.tcl: Tcl script for re-creating project 'bpm_pcie_kc705' -# -# Generated by Vivado on Fri Oct 02 15:38:18 CEST 2015 -# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 -# -# This file contains the Vivado Tcl commands for re-creating the project to the state* -# when this script was generated. In order to re-create the project, please source this -# file in the Vivado Tcl Shell. -# -# * Note that the runs in the created project will be configured the same way as the -# original project, however they will not be launched automatically. To regenerate the -# run results please launch the synthesis/implementation runs as needed. -# -#***************************************************************************************** -# NOTE: In order to use this script for source control purposes, please make sure that the -# following files are added to the source control system:- -# -# 1. This project restoration tcl script (bpm_pcie_kc705.tcl) that was generated. -# -# 2. The following source(s) files that were local or imported into the original project. -# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) -# -# -# -# 3. The following remote source files that were added to the original project:- -# -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_Calculate.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_FSM.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Mem_Reader.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MWr_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MRd_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_CplD_Channel.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/RxIn_Delays.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Interrupts.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Registers.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/ipcores_pkg.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tlpControl.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/ddr_Transact.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_mem.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/bpm_pcie.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/top/pcie/top_kc705.vhd" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/ddr_core/mig_b.prj" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/ddr_core/mig_a.prj" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/axi_interconnect/axi_interconnect.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/axi_datamover_0/axi_datamover_0.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/pcie_core/pcie_core.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/kc705/ddr_core/ddr_core.xci" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/syn/pcie/kc705.xdc" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/tests.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/tf64_pcie_axi.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sample_tests1.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/board_common.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/helper_tasks.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_tx.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_rx.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_pl.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_expect_tasks.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_com.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_cfg.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_axi_trn_bridge.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_2_1_rport_7x.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/xilinx_pcie_2_1_rport_7x.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/wiredly.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen_ds.v" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model_parameters.vh" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model.sv" -# "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/board.v" -# -#***************************************************************************************** - -# Set the reference directory for source file relative paths (by default the value is script directory path) -set origin_dir "." - -# Set the directory path for the original project from where this script was exported -set orig_proj_dir "[file normalize "$origin_dir/"]" - -# Create project -create_project bpm_pcie_kc705 ./bpm_pcie_kc705 - -# Set the directory path for the new project -set proj_dir [get_property directory [current_project]] - -# Set project properties -set obj [get_projects bpm_pcie_kc705] -set_property "default_lib" "xil_defaultlib" $obj -set_property "part" "xc7k325tffg900-2" $obj -set_property "simulator_language" "Mixed" $obj -set_property "source_mgmt_mode" "DisplayOnly" $obj -set_property "target_simulator" "Questa" $obj - -# Create 'sources_1' fileset (if not found) -if {[string equal [get_filesets -quiet sources_1] ""]} { - create_fileset -srcset sources_1 -} - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Interrupts.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/Registers.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tx_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/rx_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd"]"\ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/ipcores_pkg.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/wb_transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/tlpControl.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/common/wb_mem.vhd"]"\ - "[file normalize "$origin_dir/../../modules/pcie/bpm_pcie.vhd"]"\ - "[file normalize "$origin_dir/../../top/pcie/top_kc705.vhd"]"\ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/ddr_core/mig_b.prj"]"\ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/ddr_core/mig_a.prj"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Interrupts.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/Registers.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tx_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/rx_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../platform/kintex7/kc705/ipcores_pkg.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/wb_transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/tlpControl.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/common/wb_mem.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../modules/pcie/bpm_pcie.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - -set file "$origin_dir/../../top/pcie/top_kc705.vhd" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property "file_type" "VHDL" $file_obj - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset properties -set obj [get_filesets sources_1] -set_property "top" "top" $obj - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/axi_interconnect/axi_interconnect.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/kc705/axi_interconnect/axi_interconnect.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_0.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_0.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/pcie_core/pcie_core.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/kc705/pcie_core/pcie_core.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - "[file normalize "$origin_dir/../../platform/kintex7/kc705/ddr_core/ddr_core.xci"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/../../platform/kintex7/kc705/ddr_core/ddr_core.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -if { ![get_property "is_locked" $file_obj] } { - set_property "synth_checkpoint_mode" "Singular" $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Create 'constrs_1' fileset (if not found) -if {[string equal [get_filesets -quiet constrs_1] ""]} { - create_fileset -constrset constrs_1 -} - -# Set 'constrs_1' fileset object -set obj [get_filesets constrs_1] - -# Add/Import constrs file and set constrs file properties -set file "[file normalize "$origin_dir/kc705.xdc"]" -set file_added [add_files -norecurse -fileset $obj $file] -set file "$origin_dir/kc705.xdc" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] -set_property "file_type" "XDC" $file_obj -set_property "used_in_synthesis" "0" $file_obj - -# Set 'constrs_1' fileset properties -set obj [get_filesets constrs_1] - -# Create 'sim_1' fileset (if not found) -if {[string equal [get_filesets -quiet sim_1] ""]} { - create_fileset -simset sim_1 -} - -# Set 'sim_1' fileset object -set obj [get_filesets sim_1] -set files [list \ - "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/tests.vh"]"\ - "[file normalize "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/sample_tests1.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/board_common.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/helper_tasks.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_tx.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_rx.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_pl.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_com.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_cfg.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pcie_axi_trn_bridge.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/pcie_2_1_rport_7x.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/xilinx_pcie_2_1_rport_7x.v"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/wiredly.v"]"\ - "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen_ds.v"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh"]"\ - "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv"]"\ - "[file normalize "$origin_dir/../../testbench/pcie/board.v"]"\ -] -add_files -norecurse -fileset $obj $files - -# Set 'sim_1' fileset file properties for remote files -set file "$origin_dir/../../sim/pcie/tests.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/sample_tests1.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/board_common.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "Verilog Header" $file_obj - -set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] -set_property "file_type" "SystemVerilog" $file_obj - - -# Set 'sim_1' fileset file properties for local files -# None - -# Set 'sim_1' fileset properties -set obj [get_filesets sim_1] -set_property "questa.compile.vlog.more_options" "+define+SIMULATION +define+x1Gb +define+sg125 +define+x8" $obj -set_property "questa.simulate.log_all_signals" "1" $obj -set_property "questa.simulate.runtime" "300000ns" $obj -set_property "questa.simulate.vsim.more_options" "+notimingchecks+" $obj -set_property "runtime" "" $obj -set_property "top" "board" $obj - -# Create 'synth_1' run (if not found) -if {[string equal [get_runs -quiet synth_1] ""]} { - create_run -name synth_1 -part xc7k325tffg900-2 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 -} else { - set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] - set_property flow "Vivado Synthesis 2015" [get_runs synth_1] -} -set obj [get_runs synth_1] -set_property "part" "xc7k325tffg900-2" $obj - -# set the current synth run -current_run -synthesis [get_runs synth_1] - -# Create 'impl_1' run (if not found) -if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part xc7k325tffg900-2 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 -} else { - set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] - set_property flow "Vivado Implementation 2015" [get_runs impl_1] -} -set obj [get_runs impl_1] -set_property "part" "xc7k325tffg900-2" $obj -set_property "steps.opt_design.args.directive" "Explore" $obj -set_property "steps.place_design.args.directive" "Explore" $obj -set_property "steps.phys_opt_design.is_enabled" "1" $obj -set_property "steps.phys_opt_design.args.directive" "Explore" $obj -set_property "steps.route_design.args.directive" "Explore" $obj -set_property "steps.post_route_phys_opt_design.is_enabled" "1" $obj -set_property "steps.post_route_phys_opt_design.args.directive" "Explore" $obj -set_property "steps.write_bitstream.args.readback_file" "0" $obj -set_property "steps.write_bitstream.args.verbose" "0" $obj - -# set the current impl run -current_run -implementation [get_runs impl_1] - -puts "INFO: Project created:bpm_pcie_kc705" diff --git a/hdl/syn/pcie/kc705.xdc b/hdl/syn/pcie/kc705.xdc deleted file mode 100644 index d94d3338..00000000 --- a/hdl/syn/pcie/kc705.xdc +++ /dev/null @@ -1,38 +0,0 @@ -################################################################# -# KC705 -################################################################# - -### IO constrainst ### -set_property IOSTANDARD LVCMOS25 [get_ports sys_rst_n] -set_property PULLUP true [get_ports sys_rst_n] -set_property PACKAGE_PIN G25 [get_ports sys_rst_n] - -set_property LOC IBUFDS_GTE2_X0Y1 [get_cells -hier -filter {name=~ */pcieclk_ibuf}] - -set_property PACKAGE_PIN AD12 [get_ports ddr_sys_clk_p] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_p] -set_property VCCAUX_IO DONTCARE [get_ports ddr_sys_clk_p] - -set_property PACKAGE_PIN AD11 [get_ports ddr_sys_clk_n] -set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_n] -set_property VCCAUX_IO DONTCARE [get_ports ddr_sys_clk_n] - -### Timing constraints -create_clock -name pci_sys_clk -period 10 [get_ports pci_sys_clk_p] - -create_clock -name ddr_sys_clk -period 5 [get_ports ddr_sys_clk_p] - -set_clock_groups -asynchronous \ - -group [get_clocks -include_generated_clocks bpm_pcie_i/pcie_core_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK] \ - -group [get_clocks -include_generated_clocks ddr_sys_clk] - -set_false_path -from [get_ports sys_rst_n] - -###### Bitstream settings ################## -set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-2 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] -set_property CONFIG_MODE BPI16 [current_design] -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] diff --git a/hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/Manifest.py b/hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/Manifest.py deleted file mode 100644 index 83ba5d26..00000000 --- a/hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/Manifest.py +++ /dev/null @@ -1,10 +0,0 @@ -files = [ - "dbe_bpm2_with_dcc_rtm.vhd" -] - -modules = { - "local" : [ - "../../..", - "../dbe_bpm_gen" - ] -} diff --git a/hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/dbe_bpm2_with_dcc_rtm.vhd b/hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/dbe_bpm2_with_dcc_rtm.vhd deleted file mode 100644 index 809d700a..00000000 --- a/hdl/top/afc_v3/dbe_bpm2_with_dcc_rtm/dbe_bpm2_with_dcc_rtm.vhd +++ /dev/null @@ -1,759 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top FMC250M design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2016-02-19 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control of the DSP with --- FMC250M_4ch board -------------------------------------------------------------------------------- --- Copyright (c) 2016 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2016-02-19 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- FMC516 definitions -use work.fmc_adc_pkg.all; --- IP cores constants -use work.ipcores_pkg.all; --- AFC definitions -use work.afc_base_pkg.all; - -entity dbe_bpm2_with_dcc_rtm is -generic ( - -- Number of RTM SFP GTs - g_NUM_SFPS : integer := 4; - -- Start index of the RTM SFP GTs - g_SFP_START_ID : integer := 4; - -- Number of P2P GTs - g_NUM_P2P_GTS : integer := 8; - -- Start index of the P2P GTs - g_P2P_GT_START_ID : integer := 0 -); -port( - --------------------------------------------------------------------------- - -- Clocking pins - --------------------------------------------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - aux_clk_p_i : in std_logic; - aux_clk_n_i : in std_logic; - - afc_fp2_clk1_p_i : in std_logic; - afc_fp2_clk1_n_i : in std_logic; - - --------------------------------------------------------------------------- - -- Reset Button - --------------------------------------------------------------------------- - sys_rst_button_n_i : in std_logic := '1'; - - --------------------------------------------------------------------------- - -- UART pins - --------------------------------------------------------------------------- - - uart_rxd_i : in std_logic := '1'; - uart_txd_o : out std_logic; - - --------------------------------------------------------------------------- - -- Trigger pins - --------------------------------------------------------------------------- - trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0); - trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0); - - --------------------------------------------------------------------------- - -- AFC Diagnostics - --------------------------------------------------------------------------- - - diag_spi_cs_i : in std_logic := '0'; - diag_spi_si_i : in std_logic := '0'; - diag_spi_so_o : out std_logic; - diag_spi_clk_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- ADN4604ASVZ - --------------------------------------------------------------------------- - adn4604_vadj2_clk_updt_n_o : out std_logic; - - --------------------------------------------------------------------------- - -- AFC I2C. - --------------------------------------------------------------------------- - -- Si57x oscillator - afc_si57x_scl_b : inout std_logic; - afc_si57x_sda_b : inout std_logic; - - -- Si57x oscillator output enable - afc_si57x_oe_o : out std_logic; - - --------------------------------------------------------------------------- - -- PCIe pins - --------------------------------------------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0); - ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0); - ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0); - ddr3_cs_n_o : out std_logic_vector(0 downto 0); - ddr3_ras_n_o : out std_logic; - ddr3_cas_n_o : out std_logic; - ddr3_we_n_o : out std_logic; - ddr3_reset_n_o : out std_logic; - ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0); - ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0); - ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0); - ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0); - - -- PCIe transceivers - pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0); - - -- PCI clock and reset signals - pcie_clk_p_i : in std_logic; - pcie_clk_n_i : in std_logic; - - --------------------------------------------------------------------------- - -- User LEDs - --------------------------------------------------------------------------- - leds_o : out std_logic_vector(2 downto 0); - - --------------------------------------------------------------------------- - -- FMC interface - --------------------------------------------------------------------------- - - board_i2c_scl_b : inout std_logic; - board_i2c_sda_b : inout std_logic; - - --------------------------------------------------------------------------- - -- Flash memory SPI interface - --------------------------------------------------------------------------- - -- - -- spi_sclk_o : out std_logic; - -- spi_cs_n_o : out std_logic; - -- spi_mosi_o : out std_logic; - -- spi_miso_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- P2P GT pins - --------------------------------------------------------------------------- - -- P2P - p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0'); - p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1'); - p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - - ----------------------------- - -- FMC1_250m_4ch ports - ----------------------------- - - -- ADC clock (half of the sampling frequency) divider reset - fmc1_adc_clk_div_rst_p_o : out std_logic; - fmc1_adc_clk_div_rst_n_o : out std_logic; - fmc1_adc_ext_rst_n_o : out std_logic; - fmc1_adc_sleep_o : out std_logic; - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - fmc1_adc_clk0_p_i : in std_logic := '0'; - fmc1_adc_clk0_n_i : in std_logic := '0'; - fmc1_adc_clk1_p_i : in std_logic := '0'; - fmc1_adc_clk1_n_i : in std_logic := '0'; - fmc1_adc_clk2_p_i : in std_logic := '0'; - fmc1_adc_clk2_n_i : in std_logic := '0'; - fmc1_adc_clk3_p_i : in std_logic := '0'; - fmc1_adc_clk3_n_i : in std_logic := '0'; - - -- DDR ADC data channels. - fmc1_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc1_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - - ---- FMC General Status - --fmc1_prsnt_i : in std_logic; - --fmc1_pg_m2c_i : in std_logic; - --fmc1_clk_dir_i : in std_logic; - - -- Trigger - fmc1_trig_dir_o : out std_logic; - fmc1_trig_term_o : out std_logic; - fmc1_trig_val_p_b : inout std_logic; - fmc1_trig_val_n_b : inout std_logic; - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - fmc1_adc_spi_clk_o : out std_logic; - fmc1_adc_spi_mosi_o : out std_logic; - fmc1_adc_spi_miso_i : in std_logic; - fmc1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0 - fmc1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1 - fmc1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2 - fmc1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3 - - -- Si571 clock gen - fmc1_si571_scl_pad_b : inout std_logic; - fmc1_si571_sda_pad_b : inout std_logic; - fmc1_si571_oe_o : out std_logic; - - -- AD9510 clock distribution PLL - fmc1_spi_ad9510_cs_o : out std_logic; - fmc1_spi_ad9510_sclk_o : out std_logic; - fmc1_spi_ad9510_mosi_o : out std_logic; - fmc1_spi_ad9510_miso_i : in std_logic; - - fmc1_pll_function_o : out std_logic; - fmc1_pll_status_i : in std_logic; - - -- AD9510 clock copy - fmc1_fpga_clk_p_i : in std_logic; - fmc1_fpga_clk_n_i : in std_logic; - - -- Clock reference selection (TS3USB221) - fmc1_clk_sel_o : out std_logic; - - -- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are - -- behind a I2C switch that can access FMC I2C bus - --eeprom_scl_pad_b : inout std_logic; - --eeprom_sda_pad_b : inout std_logic; - - -- AMC7823 temperature monitor - fmc1_amc7823_spi_cs_o : out std_logic; - fmc1_amc7823_spi_sclk_o : out std_logic; - fmc1_amc7823_spi_mosi_o : out std_logic; - fmc1_amc7823_spi_miso_i : in std_logic; - fmc1_amc7823_davn_i : in std_logic; - - -- FMC LEDs - fmc1_led1_o : out std_logic; - fmc1_led2_o : out std_logic; - fmc1_led3_o : out std_logic; - - ----------------------------- - -- FMC2_250m_4ch ports - ----------------------------- - -- ADC clock (half of the sampling frequency) divider reset - fmc2_adc_clk_div_rst_p_o : out std_logic; - fmc2_adc_clk_div_rst_n_o : out std_logic; - fmc2_adc_ext_rst_n_o : out std_logic; - fmc2_adc_sleep_o : out std_logic; - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - fmc2_adc_clk0_p_i : in std_logic := '0'; - fmc2_adc_clk0_n_i : in std_logic := '0'; - fmc2_adc_clk1_p_i : in std_logic := '0'; - fmc2_adc_clk1_n_i : in std_logic := '0'; - fmc2_adc_clk2_p_i : in std_logic := '0'; - fmc2_adc_clk2_n_i : in std_logic := '0'; - fmc2_adc_clk3_p_i : in std_logic := '0'; - fmc2_adc_clk3_n_i : in std_logic := '0'; - - -- DDR ADC data channels. - fmc2_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - fmc2_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0'); - - ---- FMC General Status - --fmc2_prsnt_i : in std_logic; - --fmc2_pg_m2c_i : in std_logic; - --fmc2_clk_dir_i : in std_logic; - - -- Trigger - fmc2_trig_dir_o : out std_logic; - fmc2_trig_term_o : out std_logic; - fmc2_trig_val_p_b : inout std_logic; - fmc2_trig_val_n_b : inout std_logic; - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - fmc2_adc_spi_clk_o : out std_logic; - fmc2_adc_spi_mosi_o : out std_logic; - fmc2_adc_spi_miso_i : in std_logic; - fmc2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0 - fmc2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1 - fmc2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2 - fmc2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3 - - -- Si571 clock gen - fmc2_si571_scl_pad_b : inout std_logic; - fmc2_si571_sda_pad_b : inout std_logic; - fmc2_si571_oe_o : out std_logic; - - -- AD9510 clock distribution PLL - fmc2_spi_ad9510_cs_o : out std_logic; - fmc2_spi_ad9510_sclk_o : out std_logic; - fmc2_spi_ad9510_mosi_o : out std_logic; - fmc2_spi_ad9510_miso_i : in std_logic; - - fmc2_pll_function_o : out std_logic; - fmc2_pll_status_i : in std_logic; - - -- AD9510 clock copy - fmc2_fpga_clk_p_i : in std_logic; - fmc2_fpga_clk_n_i : in std_logic; - - -- Clock reference selection (TS3USB221) - fmc2_clk_sel_o : out std_logic; - - -- EEPROM (Connected to the CPU) - --eeprom_scl_pad_b : inout std_logic; - --eeprom_sda_pad_b : inout std_logic; - - -- AMC7823 temperature monitor - fmc2_amc7823_spi_cs_o : out std_logic; - fmc2_amc7823_spi_sclk_o : out std_logic; - fmc2_amc7823_spi_mosi_o : out std_logic; - fmc2_amc7823_spi_miso_i : in std_logic; - fmc2_amc7823_davn_i : in std_logic; - - -- FMC LEDs - fmc2_led1_o : out std_logic; - fmc2_led2_o : out std_logic; - fmc2_led3_o : out std_logic; - - --------------------------------------------------------------------------- - -- RTM board pins - --------------------------------------------------------------------------- - -- SFP - rtm_sfp_rx_p_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '0'); - rtm_sfp_rx_n_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID) := (others => '1'); - rtm_sfp_tx_p_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID); - rtm_sfp_tx_n_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID); - - -- RTM I2C. - -- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8 - -- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55 - rtm_scl_b : inout std_logic; - rtm_sda_b : inout std_logic; - - -- Si570 oscillator output enable - rtm_si570_oe_o : out std_logic; - - ---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected directly to - -- AFC - --rtm_rtm_sync_clk_p_o : out std_logic; - --rtm_rtm_sync_clk_n_o : out std_logic; - - -- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock - rtm_clk_in_sel_o : out std_logic; - - -- FPGA clocks from CDCLVD1212 - rtm_fpga_clk1_p_i : in std_logic := '0'; - rtm_fpga_clk1_n_i : in std_logic := '0'; - rtm_fpga_clk2_p_i : in std_logic := '0'; - rtm_fpga_clk2_n_i : in std_logic := '0'; - - -- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits. - -- The PISO chips are organized like this: - -- - -- Parallel load - rtm_sfp_status_reg_pl_o : out std_logic; - -- Clock N - rtm_sfp_status_reg_clk_n_o : out std_logic; - -- Serial output - rtm_sfp_status_reg_out_i : in std_logic := '0'; - - -- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits. - -- The SIPO chips are organized like this: - -- - -- Strobe - rtm_sfp_ctl_str_n_o : out std_logic; - -- Data input - rtm_sfp_ctl_din_n_o : out std_logic; - -- Parallel output enable - rtm_sfp_ctl_oe_n_o : out std_logic; - - -- External clock from RTM to FPGA - rtm_ext_clk_p_i : in std_logic := '0'; - rtm_ext_clk_n_i : in std_logic := '0' -); -end dbe_bpm2_with_dcc_rtm; - -architecture rtl of dbe_bpm2_with_dcc_rtm is - -begin - - cmp_dbe_bpm_gen : entity work.dbe_bpm_gen - generic map ( - g_fmc_adc_type => "FMC250M", - g_WITH_RTM_SFP => true, - g_NUM_SFPS => g_NUM_SFPS, - g_SFP_START_ID => g_SFP_START_ID, - g_WITH_RTM_SFP_FOFB_DCC => true, - g_NUM_P2P_GTS => g_NUM_P2P_GTS, - g_P2P_GT_START_ID => g_P2P_GT_START_ID, - g_WITH_P2P_FOFB_DCC => true - ) - port map ( - --------------------------------------------------------------------------- - -- Clocking pins - --------------------------------------------------------------------------- - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - - aux_clk_p_i => aux_clk_p_i, - aux_clk_n_i => aux_clk_n_i, - - afc_fp2_clk1_p_i => afc_fp2_clk1_p_i, - afc_fp2_clk1_n_i => afc_fp2_clk1_n_i, - - --------------------------------------------------------------------------- - -- Reset Button - --------------------------------------------------------------------------- - sys_rst_button_n_i => sys_rst_button_n_i, - - --------------------------------------------------------------------------- - -- UART pins - --------------------------------------------------------------------------- - - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o, - - --------------------------------------------------------------------------- - -- Trigger pins - --------------------------------------------------------------------------- - trig_dir_o => trig_dir_o, - trig_b => trig_b, - - --------------------------------------------------------------------------- - -- AFC Diagnostics - --------------------------------------------------------------------------- - - diag_spi_cs_i => diag_spi_cs_i, - diag_spi_si_i => diag_spi_si_i, - diag_spi_so_o => diag_spi_so_o, - diag_spi_clk_i => diag_spi_clk_i, - - --------------------------------------------------------------------------- - -- ADN4604ASVZ - --------------------------------------------------------------------------- - adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o, - - --------------------------------------------------------------------------- - -- AFC I2C. - --------------------------------------------------------------------------- - -- Si57x oscillator - afc_si57x_scl_b => afc_si57x_scl_b, - afc_si57x_sda_b => afc_si57x_sda_b, - - -- Si57x oscillator output enable - afc_si57x_oe_o => afc_si57x_oe_o, - - --------------------------------------------------------------------------- - -- PCIe pins - --------------------------------------------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b => ddr3_dq_b, - ddr3_dqs_p_b => ddr3_dqs_p_b, - ddr3_dqs_n_b => ddr3_dqs_n_b, - ddr3_addr_o => ddr3_addr_o, - ddr3_ba_o => ddr3_ba_o, - ddr3_cs_n_o => ddr3_cs_n_o, - ddr3_ras_n_o => ddr3_ras_n_o, - ddr3_cas_n_o => ddr3_cas_n_o, - ddr3_we_n_o => ddr3_we_n_o, - ddr3_reset_n_o => ddr3_reset_n_o, - ddr3_ck_p_o => ddr3_ck_p_o, - ddr3_ck_n_o => ddr3_ck_n_o, - ddr3_cke_o => ddr3_cke_o, - ddr3_dm_o => ddr3_dm_o, - ddr3_odt_o => ddr3_odt_o, - - -- PCIe transceivers - pci_exp_rxp_i => pci_exp_rxp_i, - pci_exp_rxn_i => pci_exp_rxn_i, - pci_exp_txp_o => pci_exp_txp_o, - pci_exp_txn_o => pci_exp_txn_o, - - -- PCI clock and reset signals - pcie_clk_p_i => pcie_clk_p_i, - pcie_clk_n_i => pcie_clk_n_i, - - --------------------------------------------------------------------------- - -- User LEDs - --------------------------------------------------------------------------- - leds_o => leds_o, - - --------------------------------------------------------------------------- - -- FMC interface - --------------------------------------------------------------------------- - - board_i2c_scl_b => board_i2c_scl_b, - board_i2c_sda_b => board_i2c_sda_b, - - --------------------------------------------------------------------------- - -- Flash memory SPI interface - --------------------------------------------------------------------------- - -- - -- spi_sclk_o => spi_sclk_o, - -- spi_cs_n_o => spi_cs_n_o, - -- spi_mosi_o => spi_mosi_o, - -- spi_miso_i => spi_miso_i, - - --------------------------------------------------------------------------- - -- P2P GT pins - --------------------------------------------------------------------------- - -- P2P - p2p_gt_rx_p_i => p2p_gt_rx_p_i, - p2p_gt_rx_n_i => p2p_gt_rx_n_i, - p2p_gt_tx_p_o => p2p_gt_tx_p_o, - p2p_gt_tx_n_o => p2p_gt_tx_n_o, - - ----------------------------- - -- FMC1_250m_4ch ports - ----------------------------- - - -- ADC clock (half of the sampling frequency) divider reset - fmc250_1_adc_clk_div_rst_p_o => fmc1_adc_clk_div_rst_p_o, - fmc250_1_adc_clk_div_rst_n_o => fmc1_adc_clk_div_rst_n_o, - fmc250_1_adc_ext_rst_n_o => fmc1_adc_ext_rst_n_o, - fmc250_1_adc_sleep_o => fmc1_adc_sleep_o, - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - fmc250_1_adc_clk0_p_i => fmc1_adc_clk0_p_i, - fmc250_1_adc_clk0_n_i => fmc1_adc_clk0_n_i, - fmc250_1_adc_clk1_p_i => fmc1_adc_clk1_p_i, - fmc250_1_adc_clk1_n_i => fmc1_adc_clk1_n_i, - fmc250_1_adc_clk2_p_i => fmc1_adc_clk2_p_i, - fmc250_1_adc_clk2_n_i => fmc1_adc_clk2_n_i, - fmc250_1_adc_clk3_p_i => fmc1_adc_clk3_p_i, - fmc250_1_adc_clk3_n_i => fmc1_adc_clk3_n_i, - - -- DDR ADC data channels. - fmc250_1_adc_data_ch0_p_i => fmc1_adc_data_ch0_p_i, - fmc250_1_adc_data_ch0_n_i => fmc1_adc_data_ch0_n_i, - fmc250_1_adc_data_ch1_p_i => fmc1_adc_data_ch1_p_i, - fmc250_1_adc_data_ch1_n_i => fmc1_adc_data_ch1_n_i, - fmc250_1_adc_data_ch2_p_i => fmc1_adc_data_ch2_p_i, - fmc250_1_adc_data_ch2_n_i => fmc1_adc_data_ch2_n_i, - fmc250_1_adc_data_ch3_p_i => fmc1_adc_data_ch3_p_i, - fmc250_1_adc_data_ch3_n_i => fmc1_adc_data_ch3_n_i, - - ---- FMC General Status - --fmc250_1_prsnt_i : in std_logic := '0'; - --fmc250_1_pg_m2c_i : in std_logic := '0'; - --fmc250_1_clk_dir_i : in std_logic := '0'; - - -- Trigger - fmc250_1_trig_dir_o => fmc1_trig_dir_o, - fmc250_1_trig_term_o => fmc1_trig_term_o, - fmc250_1_trig_val_p_b => fmc1_trig_val_p_b, - fmc250_1_trig_val_n_b => fmc1_trig_val_n_b, - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - fmc250_1_adc_spi_clk_o => fmc1_adc_spi_clk_o, - fmc250_1_adc_spi_mosi_o => fmc1_adc_spi_mosi_o, - fmc250_1_adc_spi_miso_i => fmc1_adc_spi_miso_i, - fmc250_1_adc_spi_cs_adc0_n_o => fmc1_adc_spi_cs_adc0_n_o, - fmc250_1_adc_spi_cs_adc1_n_o => fmc1_adc_spi_cs_adc1_n_o, - fmc250_1_adc_spi_cs_adc2_n_o => fmc1_adc_spi_cs_adc2_n_o, - fmc250_1_adc_spi_cs_adc3_n_o => fmc1_adc_spi_cs_adc3_n_o, - - -- Si571 clock gen - fmc250_1_si571_scl_pad_b => fmc1_si571_scl_pad_b, - fmc250_1_si571_sda_pad_b => fmc1_si571_sda_pad_b, - fmc250_1_si571_oe_o => fmc1_si571_oe_o, - - -- AD9510 clock distribution PLL - fmc250_1_spi_ad9510_cs_o => fmc1_spi_ad9510_cs_o, - fmc250_1_spi_ad9510_sclk_o => fmc1_spi_ad9510_sclk_o, - fmc250_1_spi_ad9510_mosi_o => fmc1_spi_ad9510_mosi_o, - fmc250_1_spi_ad9510_miso_i => fmc1_spi_ad9510_miso_i, - - fmc250_1_pll_function_o => fmc1_pll_function_o, - fmc250_1_pll_status_i => fmc1_pll_status_i, - - -- AD9510 clock copy - fmc250_1_fpga_clk_p_i => fmc1_fpga_clk_p_i, - fmc250_1_fpga_clk_n_i => fmc1_fpga_clk_n_i, - - -- Clock reference selection (TS3USB221) - fmc250_1_clk_sel_o => fmc1_clk_sel_o, - - -- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are - -- behind a I2C switch that can access FMC I2C bus - --eeprom_scl_pad_b : inout std_logic; - --eeprom_sda_pad_b : inout std_logic; - - -- AMC7823 temperature monitor - fmc250_1_amc7823_spi_cs_o => fmc1_amc7823_spi_cs_o, - fmc250_1_amc7823_spi_sclk_o => fmc1_amc7823_spi_sclk_o, - fmc250_1_amc7823_spi_mosi_o => fmc1_amc7823_spi_mosi_o, - fmc250_1_amc7823_spi_miso_i => fmc1_amc7823_spi_miso_i, - fmc250_1_amc7823_davn_i => fmc1_amc7823_davn_i, - - -- FMC LEDs - fmc250_1_led1_o => fmc1_led1_o, - fmc250_1_led2_o => fmc1_led2_o, - fmc250_1_led3_o => fmc1_led3_o, - - ----------------------------- - -- FMC2_250m_4ch ports - ----------------------------- - -- ADC clock (half of the sampling frequency) divider reset - fmc250_2_adc_clk_div_rst_p_o => fmc2_adc_clk_div_rst_p_o, - fmc250_2_adc_clk_div_rst_n_o => fmc2_adc_clk_div_rst_n_o, - fmc250_2_adc_ext_rst_n_o => fmc2_adc_ext_rst_n_o, - fmc250_2_adc_sleep_o => fmc2_adc_sleep_o, - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - fmc250_2_adc_clk0_p_i => fmc2_adc_clk0_p_i, - fmc250_2_adc_clk0_n_i => fmc2_adc_clk0_n_i, - fmc250_2_adc_clk1_p_i => fmc2_adc_clk1_p_i, - fmc250_2_adc_clk1_n_i => fmc2_adc_clk1_n_i, - fmc250_2_adc_clk2_p_i => fmc2_adc_clk2_p_i, - fmc250_2_adc_clk2_n_i => fmc2_adc_clk2_n_i, - fmc250_2_adc_clk3_p_i => fmc2_adc_clk3_p_i, - fmc250_2_adc_clk3_n_i => fmc2_adc_clk3_n_i, - - -- DDR ADC data channels. - fmc250_2_adc_data_ch0_p_i => fmc2_adc_data_ch0_p_i, - fmc250_2_adc_data_ch0_n_i => fmc2_adc_data_ch0_n_i, - fmc250_2_adc_data_ch1_p_i => fmc2_adc_data_ch1_p_i, - fmc250_2_adc_data_ch1_n_i => fmc2_adc_data_ch1_n_i, - fmc250_2_adc_data_ch2_p_i => fmc2_adc_data_ch2_p_i, - fmc250_2_adc_data_ch2_n_i => fmc2_adc_data_ch2_n_i, - fmc250_2_adc_data_ch3_p_i => fmc2_adc_data_ch3_p_i, - fmc250_2_adc_data_ch3_n_i => fmc2_adc_data_ch3_n_i, - - ---- FMC General Status - --fmc250_2_prsnt_i : in std_logic := '0'; - --fmc250_2_pg_m2c_i : in std_logic := '0'; - --fmc250_2_clk_dir_i : in std_logic := '0'; - - -- Trigger - fmc250_2_trig_dir_o => fmc2_trig_dir_o, - fmc250_2_trig_term_o => fmc2_trig_term_o, - fmc250_2_trig_val_p_b => fmc2_trig_val_p_b, - fmc250_2_trig_val_n_b => fmc2_trig_val_n_b, - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - fmc250_2_adc_spi_clk_o => fmc2_adc_spi_clk_o, - fmc250_2_adc_spi_mosi_o => fmc2_adc_spi_mosi_o, - fmc250_2_adc_spi_miso_i => fmc2_adc_spi_miso_i, - fmc250_2_adc_spi_cs_adc0_n_o => fmc2_adc_spi_cs_adc0_n_o, - fmc250_2_adc_spi_cs_adc1_n_o => fmc2_adc_spi_cs_adc1_n_o, - fmc250_2_adc_spi_cs_adc2_n_o => fmc2_adc_spi_cs_adc2_n_o, - fmc250_2_adc_spi_cs_adc3_n_o => fmc2_adc_spi_cs_adc3_n_o, - - -- Si571 clock gen - fmc250_2_si571_scl_pad_b => fmc2_si571_scl_pad_b, - fmc250_2_si571_sda_pad_b => fmc2_si571_sda_pad_b, - fmc250_2_si571_oe_o => fmc2_si571_oe_o, - - -- AD9510 clock distribution PLL - fmc250_2_spi_ad9510_cs_o => fmc2_spi_ad9510_cs_o, - fmc250_2_spi_ad9510_sclk_o => fmc2_spi_ad9510_sclk_o, - fmc250_2_spi_ad9510_mosi_o => fmc2_spi_ad9510_mosi_o, - fmc250_2_spi_ad9510_miso_i => fmc2_spi_ad9510_miso_i, - - fmc250_2_pll_function_o => fmc2_pll_function_o, - fmc250_2_pll_status_i => fmc2_pll_status_i, - - -- AD9510 clock copy - fmc250_2_fpga_clk_p_i => fmc2_fpga_clk_p_i, - fmc250_2_fpga_clk_n_i => fmc2_fpga_clk_n_i, - - -- Clock reference selection (TS3USB221) - fmc250_2_clk_sel_o => fmc2_clk_sel_o, - - -- EEPROM (Connected to the CPU) - --eeprom_scl_pad_b : inout std_logic; - --eeprom_sda_pad_b : inout std_logic; - - -- AMC7823 temperature monitor - fmc250_2_amc7823_spi_cs_o => fmc2_amc7823_spi_cs_o, - fmc250_2_amc7823_spi_sclk_o => fmc2_amc7823_spi_sclk_o, - fmc250_2_amc7823_spi_mosi_o => fmc2_amc7823_spi_mosi_o, - fmc250_2_amc7823_spi_miso_i => fmc2_amc7823_spi_miso_i, - fmc250_2_amc7823_davn_i => fmc2_amc7823_davn_i, - - -- FMC LEDs - fmc250_2_led1_o => fmc2_led1_o, - fmc250_2_led2_o => fmc2_led2_o, - fmc250_2_led3_o => fmc2_led3_o, - - --------------------------------------------------------------------------- - -- RTM board pins - --------------------------------------------------------------------------- - - -- SFP - rtm_sfp_rx_p_i => rtm_sfp_rx_p_i, - rtm_sfp_rx_n_i => rtm_sfp_rx_n_i, - rtm_sfp_tx_p_o => rtm_sfp_tx_p_o, - rtm_sfp_tx_n_o => rtm_sfp_tx_n_o, - - -- RTM I2C. - -- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8 - -- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55 - rtm_scl_b => rtm_scl_b, - rtm_sda_b => rtm_sda_b, - - -- Si570 oscillator output enable - rtm_si570_oe_o => rtm_si570_oe_o, - - ---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected to FPGA - -- rtm_sync_clk_p_o => rtm_sync_clk_p_o, - -- rtm_sync_clk_n_o => rtm_sync_clk_n_o, - - -- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock - rtm_clk_in_sel_o => rtm_clk_in_sel_o, - - -- FPGA clocks from CDCLVD1212 - rtm_fpga_clk1_p_i => rtm_fpga_clk1_p_i, - rtm_fpga_clk1_n_i => rtm_fpga_clk1_n_i, - rtm_fpga_clk2_p_i => rtm_fpga_clk2_p_i, - rtm_fpga_clk2_n_i => rtm_fpga_clk2_n_i, - - -- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits. - -- - -- Parallel load - rtm_sfp_status_reg_pl_o => rtm_sfp_status_reg_pl_o, - -- Clock N - rtm_sfp_status_reg_clk_n_o => rtm_sfp_status_reg_clk_n_o, - -- Serial output - rtm_sfp_status_reg_out_i => rtm_sfp_status_reg_out_i, - - -- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits. - -- - -- Strobe - rtm_sfp_ctl_str_n_o => rtm_sfp_ctl_str_n_o, - -- Data input - rtm_sfp_ctl_din_n_o => rtm_sfp_ctl_din_n_o, - -- Parallel output enable - rtm_sfp_ctl_oe_n_o => rtm_sfp_ctl_oe_n_o, - - -- External clock from RTM to FPGA - rtm_ext_clk_p_i => rtm_ext_clk_p_i, - rtm_ext_clk_n_i => rtm_ext_clk_n_i - ); - -end rtl; diff --git a/hdl/top/afc_v3/test_adc_clk/Manifest.py b/hdl/top/afc_v3/test_adc_clk/Manifest.py deleted file mode 100644 index 7d44a7cc..00000000 --- a/hdl/top/afc_v3/test_adc_clk/Manifest.py +++ /dev/null @@ -1,10 +0,0 @@ -files = [ - "dbe_bpm_dsp.vhd", - "dbe_bpm_dsp.xdc" -] - -modules = { - "local" : [ - "../../.." - ] -} diff --git a/hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.vhd b/hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.vhd deleted file mode 100755 index c7cd961e..00000000 --- a/hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.vhd +++ /dev/null @@ -1,136 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top DSP design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2013-09-01 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control of the DSP with --- FMC130M_4ch board -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2013-09-01 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_dsp is -port( - ----------------------------- - -- FMC1_130m_4ch ports - ----------------------------- - - -- ADC0 LTC2208 - fmc1_adc0_clk_i : in std_logic; - - -- FMC LEDs - fmc1_led1_o : out std_logic; - fmc1_led2_o : out std_logic; - fmc1_led3_o : out std_logic; - - ----------------------------- - -- FMC2_130m_4ch ports - ----------------------------- - - -- ADC0 LTC2208 - fmc2_adc0_clk_i : in std_logic; - - -- FMC LEDs - fmc2_led1_o : out std_logic; - fmc2_led2_o : out std_logic; - fmc2_led3_o : out std_logic -); -end dbe_bpm_dsp; - -architecture rtl of dbe_bpm_dsp is - - constant c_max_count : natural := 113000000; - - signal fmc1_adc0_clk_buf : std_logic; - signal fmc2_adc0_clk_buf : std_logic; - signal fmc1_adc0_clk_bufg : std_logic; - signal fmc2_adc0_clk_bufg : std_logic; - -begin - -cmp_ibuf_adc1_clk0 : ibuf -generic map( - IOSTANDARD => "LVCMOS25" -) -port map( - i => fmc1_adc0_clk_i, - o => fmc1_adc0_clk_buf -); - -cmp_bufg_adc1_clk0 : BUFG -port map( - O => fmc1_adc0_clk_bufg, - I => fmc1_adc0_clk_buf -); - -cmp_ibuf_adc2_clk0 : ibuf -generic map( - IOSTANDARD => "LVCMOS25" -) -port map( - i => fmc2_adc0_clk_i, - o => fmc2_adc0_clk_buf -); - -cmp_bufg_adc2_clk0 : BUFG -port map( - O => fmc2_adc0_clk_bufg, - I => fmc2_adc0_clk_buf -); - -p_counter1 : process(fmc1_adc0_clk_bufg) - variable count : natural range 0 to c_max_count; -begin - if rising_edge(fmc1_adc0_clk_bufg) then - if count < c_max_count/2 then - count := count + 1; - fmc1_led1_o <= '1'; - elsif count < c_max_count then - fmc1_led1_o <= '0'; - count := count + 1; - else - fmc1_led1_o <= '1'; - count := 0; - end if; - end if; -end process; - -fmc1_led2_o <= '0'; -fmc1_led3_o <= '0'; - -p_counter2 : process(fmc2_adc0_clk_bufg) - variable count : natural range 0 to c_max_count; -begin - if rising_edge(fmc2_adc0_clk_bufg) then - if count < c_max_count/2 then - count := count + 1; - fmc2_led1_o <= '1'; - elsif count < c_max_count then - fmc2_led1_o <= '0'; - count := count + 1; - else - fmc2_led1_o <= '1'; - count := 0; - end if; - end if; -end process; - -fmc2_led2_o <= '0'; -fmc2_led3_o <= '0'; - -end rtl; diff --git a/hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.xdc b/hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.xdc deleted file mode 100644 index 154f46ec..00000000 --- a/hdl/top/afc_v3/test_adc_clk/dbe_bpm_dsp.xdc +++ /dev/null @@ -1,64 +0,0 @@ -####################################################################### -## Artix 7 AMC V3 ## -####################################################################### - -####################################################################### -## FMC Connector HPC1 ## -####################################################################### - -#// LEDs -#// LA16_N -set_property PACKAGE_PIN L9 [get_ports fmc1_led1_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc1_led1_o] -#// LA16_P -set_property PACKAGE_PIN L10 [get_ports fmc1_led2_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc1_led2_o] -#// LA26_P -set_property PACKAGE_PIN T2 [get_ports fmc1_led3_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc1_led3_o] - -####################################################################### -## FMC Connector HPC2 ## -####################################################################### - -#// LEDs -#// LA16_N -set_property PACKAGE_PIN AD34 [get_ports fmc2_led1_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc2_led1_o] -#// LA16_P -set_property PACKAGE_PIN AD33 [get_ports fmc2_led2_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc2_led2_o] -#// LA26_P -set_property PACKAGE_PIN AC32 [get_ports fmc2_led3_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc2_led3_o] - -####################################################################### -## FMC Connector HPC1 # -## LTC ADC lines # -####################################################################### - -#// ADC0 -#// LA17_CC_P -set_property PACKAGE_PIN T5 [get_ports fmc1_adc0_clk_i] -set_property IOSTANDARD LVCMOS25 [get_ports fmc1_adc0_clk_i] - -####################################################################### -## FMC Connector HPC2 # -## LTC ADC lines # -####################################################################### - -#// ADC0 -#// LA17_CC_P -set_property PACKAGE_PIN AB31 [get_ports fmc2_adc0_clk_i] -set_property IOSTANDARD LVCMOS25 [get_ports fmc2_adc0_clk_i] - -####################################################################### -## Clocks ## -####################################################################### - -# real jitter is about 22ps peak-to-peak -create_clock -period 8.000 -name fmc1_adc0_clk_i [get_ports fmc1_adc0_clk_i] -set_input_jitter fmc1_adc0_clk_i 0.050 -create_clock -period 8.000 -name fmc2_adc0_clk_i [get_ports fmc2_adc0_clk_i] -set_input_jitter fmc2_adc0_clk_i 0.050 - diff --git a/hdl/top/afc_v3/wb_trigger/Manifest.py b/hdl/top/afc_v3/wb_trigger/Manifest.py deleted file mode 100644 index 2dba0978..00000000 --- a/hdl/top/afc_v3/wb_trigger/Manifest.py +++ /dev/null @@ -1,12 +0,0 @@ -files = [ - "wb_trigger_top.vhd", - "sys_pll.vhd", - "clk_gen.vhd", - "wb_trigger_top.xdc" -] - -modules = { - "local" : [ - "../../.." - ] -} diff --git a/hdl/top/afc_v3/wb_trigger/clk_gen.vhd b/hdl/top/afc_v3/wb_trigger/clk_gen.vhd deleted file mode 100644 index 7c332d91..00000000 --- a/hdl/top/afc_v3/wb_trigger/clk_gen.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic; - sys_clk_bufg_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DIFF_SSTL15" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - sys_clk_o <= s_sys_clk; - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/afc_v3/wb_trigger/sys_pll.vhd b/hdl/top/afc_v3/wb_trigger/sys_pll.vhd deleted file mode 100644 index 41913ea4..00000000 --- a/hdl/top/afc_v3/wb_trigger/sys_pll.vhd +++ /dev/null @@ -1,155 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_divclk_divide : integer := 1; - g_clkbout_mult_f : integer := 5; - - -- Reference jitter - g_ref_jitter : real := 0.010; - - -- 100 MHz output clock - g_clk0_divide_f : integer := 10; - -- 200 MHz output clock - g_clk1_divide : integer := 5; - g_clk2_divide : integer := 6 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - clk2_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; - signal s_clk2 : std_logic; -begin - - -- Clock PLL - cmp_sys_pll : PLLE2_ADV - generic map ( - BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW - CLKFBOUT_MULT => g_clkbout_mult_f, -- Multiply value for all CLKOUT, (2-64) - CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000). - -- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz). - CLKIN1_PERIOD => g_clkin_period, - CLKIN2_PERIOD => g_clkin_period, - -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128) - CLKOUT0_DIVIDE => g_clk0_divide_f, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT2_DIVIDE => g_clk2_divide, - CLKOUT3_DIVIDE => 1, - CLKOUT4_DIVIDE => 1, - CLKOUT5_DIVIDE => 1, - -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999). - CLKOUT0_DUTY_CYCLE => 0.5, - CLKOUT1_DUTY_CYCLE => 0.5, - CLKOUT2_DUTY_CYCLE => 0.5, - CLKOUT3_DUTY_CYCLE => 0.5, - CLKOUT4_DUTY_CYCLE => 0.5, - CLKOUT5_DUTY_CYCLE => 0.5, - -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000). - CLKOUT0_PHASE => 0.0, - CLKOUT1_PHASE => 0.0, - CLKOUT2_PHASE => 0.0, - CLKOUT3_PHASE => 0.0, - CLKOUT4_PHASE => 0.0, - CLKOUT5_PHASE => 0.0, - COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL - DIVCLK_DIVIDE => g_divclk_divide, -- Master division value (1-56) - -- REF_JITTER: Reference input jitter in UI (0.000-0.999). - REF_JITTER1 => g_ref_jitter, - REF_JITTER2 => g_ref_jitter, - STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE") - ) - port map ( - -- Clock Outputs: 1-bit (each) output: User configurable clock outputs - CLKOUT0 => s_clk0, -- 1-bit output: CLKOUT0 - CLKOUT1 => s_clk1, -- 1-bit output: CLKOUT1 - CLKOUT2 => s_clk2, -- 1-bit output: CLKOUT2 - CLKOUT3 => open, -- 1-bit output: CLKOUT3 - CLKOUT4 => open, -- 1-bit output: CLKOUT4 - CLKOUT5 => open, -- 1-bit output: CLKOUT5 - -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports - DO => open, -- 16-bit output: DRP data - DRDY => open, -- 1-bit output: DRP ready - -- Feedback Clocks: 1-bit (each) output: Clock feedback ports - CLKFBOUT => s_mmcm_fbout, -- 1-bit output: Feedback clock - LOCKED => locked_o, -- 1-bit output: LOCK - -- Clock Inputs: 1-bit (each) input: Clock inputs - CLKIN1 => clk_i, -- 1-bit input: Primary clock - CLKIN2 => '0', -- 1-bit input: Secondary clock - -- Control Ports: 1-bit (each) input: PLL control ports - CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2 - PWRDWN => '0', -- 1-bit input: Power-down - RST => rst_i, -- 1-bit input: Reset - -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports - DADDR => (others => '0'), -- 7-bit input: DRP address - DCLK => '0', -- 1-bit input: DRP clock - DEN => '0', -- 1-bit input: DRP enable - DI => (others => '0'), -- 16-bit input: DRP data - DWE => '0', -- 1-bit input: DRP write enable - -- Feedback Clocks: 1-bit (each) input: Clock feedback ports - CLKFBIN => s_mmcm_fbin -- 1-bit input: Feedback clock - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - - cmp_clkout2_buf : BUFG - port map( - O => clk2_o, - I => s_clk2 - ); - -end syn; diff --git a/hdl/top/afc_v3/wb_trigger/wb_trigger_top.vhd b/hdl/top/afc_v3/wb_trigger/wb_trigger_top.vhd deleted file mode 100644 index 9de9454a..00000000 --- a/hdl/top/afc_v3/wb_trigger/wb_trigger_top.vhd +++ /dev/null @@ -1,569 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Wishbone trigger component toplevel --- Project : -------------------------------------------------------------------------------- --- File : wb_trigger_top.vhd --- Author : Vitor Finotti Ferreira --- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM --- Created : 2016-02-02 --- Last update: 2016-05-10 --- Platform : --- Standard : VHDL'93/02 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM - --- This program is free software: you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public License --- as published by the Free Software Foundation, either version 3 of --- the License, or (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, but --- WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this program. If not, see --- . -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2016-02-02 1.0 vfinotti Created -------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Custom common cores -use work.ifc_common_pkg.all; --- Trigger definitons -use work.trigger_pkg.all; --- Positicon Calc constants -use work.machine_pkg.all; --- Genrams -use work.genram_pkg.all; - --- Meta Package ---use work.synthesis_descriptor_pkg.all; --- AXI cores ---use work.pcie_cntr_axi_pkg.all; -use work.bpm_pcie_a7_const_pkg.all; --- PCIe Core -use work.bpm_pcie_a7_pkg.all; - - - -library UNISIM; -use UNISIM.vcomponents.all; - -entity wb_trigger_top is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - - ----------------------------------------- - -- PCIe pins - ----------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b : inout std_logic_vector(c_ddr_dq_width-1 downto 0); - ddr3_dqs_p_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0); - ddr3_dqs_n_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0); - ddr3_addr_o : out std_logic_vector(c_ddr_row_width-1 downto 0); - ddr3_ba_o : out std_logic_vector(c_ddr_bank_width-1 downto 0); - ddr3_cs_n_o : out std_logic_vector(0 downto 0); - ddr3_ras_n_o : out std_logic; - ddr3_cas_n_o : out std_logic; - ddr3_we_n_o : out std_logic; - ddr3_reset_n_o : out std_logic; - ddr3_ck_p_o : out std_logic_vector(c_ddr_ck_width-1 downto 0); - ddr3_ck_n_o : out std_logic_vector(c_ddr_ck_width-1 downto 0); - ddr3_cke_o : out std_logic_vector(c_ddr_cke_width-1 downto 0); - ddr3_dm_o : out std_logic_vector(c_ddr_dm_width-1 downto 0); - ddr3_odt_o : out std_logic_vector(c_ddr_odt_width-1 downto 0); - - -- PCIe transceivers - pci_exp_rxp_i : in std_logic_vector(c_pcie_lanes - 1 downto 0); - pci_exp_rxn_i : in std_logic_vector(c_pcie_lanes - 1 downto 0); - pci_exp_txp_o : out std_logic_vector(c_pcie_lanes - 1 downto 0); - pci_exp_txn_o : out std_logic_vector(c_pcie_lanes - 1 downto 0); - - -- PCI clock and reset signals - pcie_clk_p_i : in std_logic; - pcie_clk_n_i : in std_logic; - - -- Trigger signals - trig_dir_o : out std_logic_vector(7 downto 0); - trig_b : inout std_logic_vector(7 downto 0) - - ); -end wb_trigger_top; - -architecture structural of wb_trigger_top is - - -------------------------------------------------------------------------------- --- Chipscope -------------------------------------------------------------------------------- - - component chipscope_icon_1_port is - port ( - CONTROL0 : inout std_logic_vector(35 downto 0)); - end component chipscope_icon_1_port; - - component chipscope_ila is - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0)); - end component chipscope_ila; - - component chipscope_vio_16 is - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - SYNC_OUT : out std_logic_vector(15 downto 0)); - end component chipscope_vio_16; - - ----------------------------------------------------------------------------- - -- Clock and system - ----------------------------------------------------------------------------- - - component clk_gen is - port ( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic; - sys_clk_bufg_o : out std_logic); - end component clk_gen; - - component sys_pll is - generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_divclk_divide : integer := 1; - g_clkbout_mult_f : integer := 5; - - -- Reference jitter - g_ref_jitter : real := 0.010; - - -- 100 MHz output clock - g_clk0_divide_f : integer := 10; - -- 200 MHz output clock - g_clk1_divide : integer := 5; - g_clk2_divide : integer := 6 - ); - port ( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - clk2_o : out std_logic; - locked_o : out std_logic); - end component sys_pll; - - -- Constants - - constant c_width_bus_size : positive := 8; - constant c_rcv_len_bus_width : positive := 8; - constant c_transm_len_bus_width : positive := 8; - constant c_sync_edge : string := "positive"; - constant c_trig_num : positive := 8; - constant c_intern_num : positive := 8; - constant c_rcv_intern_num : positive := 2; - constant c_counter_wid : positive := 16; - constant c_num_tlvl_clks : natural := 3; - - constant c_masters : natural := 1; - constant c_slaves : natural := 3; - - constant c_slv_trigger_iface_id : natural := 0; - constant c_slv_trigger_mux0_id : natural := 1; - constant c_slv_trigger_mux1_id : natural := 2; - - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( - c_slv_trigger_iface_id => f_sdb_embed_device(c_xwb_trigger_iface_sdb, x"10000000"), - c_slv_trigger_mux0_id => f_sdb_embed_device(c_xwb_trigger_mux_sdb, x"20000000"), - c_slv_trigger_mux1_id => f_sdb_embed_device(c_xwb_trigger_mux_sdb, x"30000000") - ); - - constant c_button_rst_width : natural := 255; - constant c_sdb_address : t_wishbone_address := x"00000000"; - constant c_ma_pcie_id : natural := 0; - - constant c_num_mux_interfaces : natural := 2; - - - signal c_clk_sys_id : natural := 0; - signal c_clk_200mhz_id : natural := 1; - signal c_clk_133mhz_id : natural := 2; - - signal CONTROL0 : std_logic_vector(35 downto 0); - - -- Global Clock Single ended - signal clk_sys, clk_200mhz, clk_133mhz : std_logic; - signal sys_clk_gen_bufg : std_logic; - signal sys_clk_gen : std_logic; - signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0); - signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0); - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_pcie_rstn : std_logic; - signal clk_sys_pcie_rst : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - signal clk_200mhz_rst : std_logic; - signal clk_200mhz_rstn : std_logic; - signal clk_133mhz_rst : std_logic; - signal clk_133mhz_rstn : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - signal wb_ma_pcie_rst : std_logic; - signal wb_ma_pcie_rstn : std_logic; - signal wb_ma_pcie_rstn_sync : std_logic; - - signal wb_slv_in : t_wishbone_slave_in; - signal wb_slv_out : t_wishbone_slave_out; - - signal trig_rcv_intern : t_trig_channel_array2d(1 downto 0, 1 downto 0); - signal trig_pulse_transm : t_trig_channel_array2d(1 downto 0, 7 downto 0); - signal trig_pulse_rcv : t_trig_channel_array2d(1 downto 0, 7 downto 0); - - signal trig_dir_int : std_logic_vector(7 downto 0); - -begin - - - cmp_chipscope_icon_1 : chipscope_icon_1_port - port map ( - CONTROL0 => CONTROL0); - - cmp_chipscope_ila_0 : chipscope_ila - port map ( - CONTROL => CONTROL0, - CLK => clk_133mhz, - TRIG0(31 downto 24) => trig_dir_int, - TRIG0(23) => trig_pulse_rcv(0, 7).pulse, - TRIG0(22) => trig_pulse_rcv(0, 6).pulse, - TRIG0(21) => trig_pulse_rcv(0, 5).pulse, - TRIG0(20) => trig_pulse_rcv(0, 4).pulse, - TRIG0(19) => trig_pulse_rcv(0, 3).pulse, - TRIG0(18) => trig_pulse_rcv(0, 2).pulse, - TRIG0(17) => trig_pulse_rcv(0, 1).pulse, - TRIG0(16) => trig_pulse_rcv(0, 0).pulse, - TRIG0(15) => trig_pulse_transm(0, 7).pulse, - TRIG0(14) => trig_pulse_transm(0, 6).pulse, - TRIG0(13) => trig_pulse_transm(0, 5).pulse, - TRIG0(12) => trig_pulse_transm(0, 4).pulse, - TRIG0(11) => trig_pulse_transm(0, 3).pulse, - TRIG0(10) => trig_pulse_transm(0, 2).pulse, - TRIG0(9) => trig_pulse_transm(0, 1).pulse, - TRIG0(8) => trig_pulse_transm(0, 0).pulse, - TRIG0(7 downto 2) => (others => '0'), - TRIG0(1) => trig_rcv_intern(0, 1).pulse, - TRIG0(0) => trig_rcv_intern(0, 0).pulse, - TRIG1 => (others => '0'), - TRIG2 => (others => '0'), - TRIG3 => (others => '0')); - - trig_dir_o <= trig_dir_int; - - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen, - sys_clk_bufg_o => sys_clk_gen_bufg - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - generic map ( - -- 125 MHz input clock - g_clkin_period => 8.000, - g_divclk_divide => 5, - g_clkbout_mult_f => 32, - - -- 100 MHz output clock - g_clk0_divide_f => 8, - -- 200 MHz output clock - g_clk1_divide => 4, - -- 133 MHz output clock - g_clk2_divide => 6 - ) - port map ( - rst_i => '0', - clk_i => sys_clk_gen_bufg, - --clk_i => sys_clk_gen, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - clk2_o => clk_133mhz, -- 133MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200 - ) - port map( - --free_clk_i => sys_clk_gen, - free_clk_i => sys_clk_gen_bufg, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(c_clk_sys_id) <= clk_sys; - reset_clks(c_clk_200mhz_id) <= clk_200mhz; - reset_clks(c_clk_133mhz_id) <= clk_133mhz; - - -- Reset for PCIe core. Caution when resetting the PCIe core after the - -- initialization. The PCIe core needs to retrain the link and the PCIe - -- host (linux OS, likely) will not be able to do that automatically, - -- probably. - clk_sys_pcie_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n; - clk_sys_pcie_rst <= not clk_sys_pcie_rstn; - -- Reset for all other modules - clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and - wb_ma_pcie_rstn_sync; - clk_sys_rst <= not clk_sys_rstn; - -- Reset synchronous to clk200mhz - clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id); - clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id)); - -- Reset synchronous to clk133mhz - clk_133mhz_rstn <= reset_rstn(c_clk_133mhz_id); - clk_133mhz_rst <= not(reset_rstn(c_clk_133mhz_id)); - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => '0', --sys_rst_button_n_i, - npulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched gc - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => true, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - --lm32_rstn <= clk_sys_rstn; - - --cmp_lm32 : xwb_lm32 - --generic map( - -- g_profile => "medium_icache_debug" - --) -- Including JTAG and I-cache (no divide) - --port map( - -- clk_sys_i => clk_sys, - -- rst_n_i => lm32_rstn, - -- irq_i => lm32_interrupt, - -- dwb_o => cbar_slave_i(0), -- Data bus - -- dwb_i => cbar_slave_o(0), - -- iwb_o => cbar_slave_i(1), -- Instruction bus - -- iwb_i => cbar_slave_o(1) - --); - - -- Interrupt '0' is Button(0). - -- Interrupts 31 downto 1 are disabled - - --lm32_interrupt <= (0 => not buttons_i(0), others => '0'); - - ---------------------------------- - -- PCIe Core -- - ---------------------------------- - - cmp_xwb_bpm_pcie_a7 : xwb_bpm_pcie_a7 - generic map ( - g_ma_interface_mode => PIPELINED, - g_ma_address_granularity => BYTE, - g_ext_rst_pin => false, - g_sim_bypass_init_cal => "OFF" - ) - port map ( - -- DDR3 memory pins - ddr3_dq_b => ddr3_dq_b, - ddr3_dqs_p_b => ddr3_dqs_p_b, - ddr3_dqs_n_b => ddr3_dqs_n_b, - ddr3_addr_o => ddr3_addr_o, - ddr3_ba_o => ddr3_ba_o, - ddr3_cs_n_o => ddr3_cs_n_o, - ddr3_ras_n_o => ddr3_ras_n_o, - ddr3_cas_n_o => ddr3_cas_n_o, - ddr3_we_n_o => ddr3_we_n_o, - ddr3_reset_n_o => ddr3_reset_n_o, - ddr3_ck_p_o => ddr3_ck_p_o, - ddr3_ck_n_o => ddr3_ck_n_o, - ddr3_cke_o => ddr3_cke_o, - ddr3_dm_o => ddr3_dm_o, - ddr3_odt_o => ddr3_odt_o, - - -- PCIe transceivers - pci_exp_rxp_i => pci_exp_rxp_i, - pci_exp_rxn_i => pci_exp_rxn_i, - pci_exp_txp_o => pci_exp_txp_o, - pci_exp_txn_o => pci_exp_txn_o, - - -- Necessity signals - ddr_clk_p_i => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL) - ddr_clk_n_i => '0', --200 MHz DDR core clock (connect through BUFG or PLL) - pcie_clk_p_i => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin) - pcie_clk_n_i => pcie_clk_n_i, --100 MHz PCIe Clock - pcie_rst_n_i => clk_sys_pcie_rstn, -- PCIe core reset - - -- DDR memory controller interface -- - ddr_core_rst_i => clk_sys_pcie_rst, - memc_ui_clk_o => open, - memc_ui_rst_o => open, - memc_cmd_rdy_o => open, - memc_cmd_en_i => '0', - memc_cmd_instr_i => (others => '0'), - memc_cmd_addr_i => (others => '0'), - memc_wr_en_i => '0', - memc_wr_end_i => '0', - memc_wr_mask_i => (others => '0'), - memc_wr_data_i => (others => '0'), - memc_wr_rdy_o => open, - memc_rd_data_o => open, - memc_rd_valid_o => open, - ---- memory arbiter interface - memarb_acc_req_i => '0', - memarb_acc_gnt_o => open, - - -- Wishbone interface -- - wb_clk_i => clk_sys, - -- Reset wishbone interface with the same reset as the other - -- modules, including a reset coming from the PCIe itself. - wb_rst_i => clk_sys_rst, - wb_ma_i => cbar_slave_o(c_ma_pcie_id), - wb_ma_o => cbar_slave_i(c_ma_pcie_id), - -- Additional exported signals for instantiation - wb_ma_pcie_rst_o => wb_ma_pcie_rst, - - -- Debug signals - dbg_app_addr_o => open, - dbg_app_cmd_o => open, - dbg_app_en_o => open, - dbg_app_wdf_data_o => open, - dbg_app_wdf_end_o => open, - dbg_app_wdf_wren_o => open, - dbg_app_wdf_mask_o => open, - dbg_app_rd_data_o => open, - dbg_app_rd_data_end_o => open, - dbg_app_rd_data_valid_o => open, - dbg_app_rdy_o => open, - dbg_app_wdf_rdy_o => open, - dbg_ddr_ui_clk_o => open, - dbg_ddr_ui_reset_o => open, - - dbg_arb_req_o => open, - dbg_arb_gnt_o => open - ); - - wb_ma_pcie_rstn <= not wb_ma_pcie_rst; - - cmp_pcie_reset_synch : reset_synch - port map - ( - clk_i => clk_sys, - arst_n_i => wb_ma_pcie_rstn, - rst_n_o => wb_ma_pcie_rstn_sync - ); - - cmp_xwb_trigger : xwb_trigger - generic map ( - g_interface_mode => PIPELINED, - g_address_granularity => BYTE, - g_sync_edge => c_sync_edge, - g_trig_num => c_trig_num, - g_intern_num => c_intern_num, - g_rcv_intern_num => c_rcv_intern_num, - g_num_mux_interfaces => c_num_mux_interfaces, - g_out_resolver => "fanout", - g_in_resolver => "or" - ) - port map ( - rst_n_i => clk_sys_rstn, - clk_i => clk_sys, - - ref_clk_i => clk_133mhz, - ref_rst_n_i => clk_133mhz_rstn, - - fs_clk_array_i => (clk_133mhz, clk_133mhz), - fs_rst_n_array_i => (clk_133mhz_rstn, clk_133mhz_rstn), - - wb_slv_trigger_iface_i => cc_dummy_slave_in, - wb_slv_trigger_iface_o => open, - - wb_slv_trigger_mux_i => (cc_dummy_slave_in, cc_dummy_slave_in), - wb_slv_trigger_mux_o => open, - - trig_dir_o => trig_dir_int, - trig_rcv_intern_i => trig_rcv_intern, - trig_pulse_transm_i => trig_pulse_transm, - trig_pulse_rcv_o => trig_pulse_rcv, - trig_b => trig_b); - -end architecture structural; diff --git a/hdl/top/afc_v3/wb_trigger/wb_trigger_top.xdc b/hdl/top/afc_v3/wb_trigger/wb_trigger_top.xdc deleted file mode 100644 index 2bc6a34d..00000000 --- a/hdl/top/afc_v3/wb_trigger/wb_trigger_top.xdc +++ /dev/null @@ -1,668 +0,0 @@ -####################################################################### -## Artix 7 AMC V3 ## -####################################################################### - -# All timing constraint translations are rough conversions, intended to act as a template for further manual refinement. The translations should not be expected to produce semantically identical results to the original ucf. Each xdc timing constraint must be manually inspected and verified to ensure it captures the desired intent - -# In xdc, all clocks are related by default. This differs from ucf, where clocks are unrelated unless specified otherwise. As a result, you may now see cross-clock paths that were previously unconstrained in ucf. Commented out xdc false path constraints have been generated and can be uncommented, should you wish to remove these new paths. These commands are located after the last clock definition - -#// FPGA_CLK1_P -set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p_i] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_p_i] -#// FPGA_CLK1_N -set_property PACKAGE_PIN AL7 [get_ports sys_clk_n_i] -set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n_i] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_n_i] - - -# System Reset -# Bank 16 VCCO - VADJ_FPGA - IO_25_16. NET = FPGA_RESET_DN, PIN = IO_L19P_T3_13 -#set_false_path -through [get_nets sys_rst_button_n_i] -#set_property PACKAGE_PIN AG26 [get_ports sys_rst_button_n_i] -#set_property IOSTANDARD LVCMOS25 [get_ports sys_rst_button_n_i] -#set_property PULLUP true [get_ports sys_rst_button_n_i] - - -####################################################################### -## Clocks ## -####################################################################### - -# 125 MHz AMC TCLKB input clock -create_clock -period 8.000 -name sys_clk_p_i [get_ports sys_clk_p_i] - -## 100 MHz wihsbone clock -# A PERIOD placed on an internal net will result in a clock defined with an internal source. Any upstream source clock latency will not be analyzed -create_clock -name clk_sys -period 10.000 [get_pins cmp_sys_pll_inst/cmp_clkout0_buf/O] - -# 200 MHz DDR3 and IDELAY CONTROL clock -# A PERIOD placed on an internal net will result in a clock defined with an internal source. Any upstream source clock latency will not be analyzed -create_clock -name clk_200mhz -period 5.000 [get_pins cmp_sys_pll_inst/cmp_clkout1_buf/O] - - - -####################################################################### -## Cross Clock Constraints ## -####################################################################### - -# Reset synchronization path -#set_false_path -through [get_nets cmp_reset/master_rstn] -set_false_path -through [get_pins -hier -filter {name=~ cmp_reset/master_rstn_reg/C}] -# This reset is synched with PCIe user_clk but we decouple it with a -# chain of FFs synched with clk_sys. We use asynchronous assertion and -# synchronous deassertion -set_false_path -through [get_nets cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/theTlpControl/Memory_Space/wb_FIFO_Rst_i0] -# DDR 3 temperature monitor reset path -set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000 - - -####################################################################### -## Trigger ## -####################################################################### - -set_property PACKAGE_PIN AM9 [get_ports {trig_b[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[0]}] - -set_property PACKAGE_PIN AP11 [get_ports {trig_b[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[1]}] - -set_property PACKAGE_PIN AP10 [get_ports {trig_b[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[2]}] - -set_property PACKAGE_PIN AM11 [get_ports {trig_b[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[3]}] - -set_property PACKAGE_PIN AN8 [get_ports {trig_b[4]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[4]}] - -set_property PACKAGE_PIN AP8 [get_ports {trig_b[5]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[5]}] - -set_property PACKAGE_PIN AL8 [get_ports {trig_b[6]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[6]}] - -set_property PACKAGE_PIN AL9 [get_ports {trig_b[7]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_b[7]}] - - -####################################################################### -## Direction ## -####################################################################### - -set_property PACKAGE_PIN AJ10 [get_ports {trig_dir_o[0]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[0]}] - -set_property PACKAGE_PIN AK11 [get_ports {trig_dir_o[1]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[1]}] - -set_property PACKAGE_PIN AJ11 [get_ports {trig_dir_o[2]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[2]}] - -set_property PACKAGE_PIN AL10 [get_ports {trig_dir_o[3]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[3]}] - -set_property PACKAGE_PIN AM10 [get_ports {trig_dir_o[4]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[4]}] - -set_property PACKAGE_PIN AN11 [get_ports {trig_dir_o[5]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[5]}] - -set_property PACKAGE_PIN AN9 [get_ports {trig_dir_o[6]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[6]}] - -set_property PACKAGE_PIN AP9 [get_ports {trig_dir_o[7]}] -set_property IOSTANDARD LVCMOS15 [get_ports {trig_dir_o[7]}] - -####################################################################### -## PCIe constraints ## -####################################################################### - -#PCIe clock -#// MGT216_CLK1_N -> MGTREFCLK0N_216 -set_property PACKAGE_PIN G18 [get_ports pcie_clk_n_i] -#// MGT216_CLK1_P -> MGTREFCLK0P_216 -set_property PACKAGE_PIN H18 [get_ports pcie_clk_p_i] -#PCIe lane 0 -#// TX216_0_P -> MGTPTXP0_216 -set_property PACKAGE_PIN B23 [get_ports {pci_exp_txp_o[0]}] -#// TX216_0_N -> MGTPTXN0_216 -set_property PACKAGE_PIN A23 [get_ports {pci_exp_txn_o[0]}] -#// RX216_0_P -> MGTPRXP0_216 -set_property PACKAGE_PIN F21 [get_ports {pci_exp_rxp_i[0]}] -#// RX216_0_N -> MGTPRXN0_216 -set_property PACKAGE_PIN E21 [get_ports {pci_exp_rxn_i[0]}] -#PCIe lane 1 -#// TX216_1_P -> MGTPTXP1_216 -set_property PACKAGE_PIN D22 [get_ports {pci_exp_txp_o[1]}] -#// TX216_1_N -> MGTPTXN1_216 -set_property PACKAGE_PIN C22 [get_ports {pci_exp_txn_o[1]}] -#// RX216_1_P -> MGTPRXP1_216 -set_property PACKAGE_PIN D20 [get_ports {pci_exp_rxp_i[1]}] -#// RX216_1_N -> MGTPRXN1_216 -set_property PACKAGE_PIN C20 [get_ports {pci_exp_rxn_i[1]}] -#PCIe lane 2 -#// TX216_2_P -> MGTPTXP2_216 -set_property PACKAGE_PIN B21 [get_ports {pci_exp_txp_o[2]}] -#// TX216_2_N -> MGTPTXN2_216 -set_property PACKAGE_PIN A21 [get_ports {pci_exp_txn_o[2]}] -#// RX216_2_P -> MGTPRXP2_216 -set_property PACKAGE_PIN F19 [get_ports {pci_exp_rxp_i[2]}] -#// RX216_2_N -> MGTPRXN2_216 -set_property PACKAGE_PIN E19 [get_ports {pci_exp_rxn_i[2]}] -#PCIe lane 3 -#// TX216_3_P -> MGTPTXP3_216 -set_property PACKAGE_PIN B19 [get_ports {pci_exp_txp_o[3]}] -#// TX216_3_N -> MGTPTXN3_216 -set_property PACKAGE_PIN A19 [get_ports {pci_exp_txn_o[3]}] -#// RX216_3_P -> MGTPRXP3_216 -set_property PACKAGE_PIN D18 [get_ports {pci_exp_rxp_i[3]}] -#// RX216_3_N -> MGTPRXN3_216 -set_property PACKAGE_PIN C18 [get_ports {pci_exp_rxn_i[3]}] - - - - - - - - - - - - -################################################################################################## -## -## Xilinx, Inc. 2010 www.xilinx.com -## sáb fev 21 11:40:05 2015 -## Generated by MIG Version 2.3 -## -################################################################################################## -## File name : ddr_core.xdc -## Details : Constraints file -## FPGA Family: ARTIX7 -## FPGA Part: XC7A200T-FFG1156 -## Speedgrade: -1 -## Design Entry: VHDL -## Frequency: 0 MHz -## Time Period: 2500 ps -################################################################################################## - -################################################################################################## -## Controller 0 -## Memory Device: DDR3_SDRAM->Components->MT41J512M8XX-125 -## Data Width: 32 -## Time Period: 2500 -## Data Mask: 1 -################################################################################################## - -#create_clock -period -2.14748e+06 [get_ports sys_clk_i] -#set_propagated_clock sys_clk_i - -############## NET - IOSTANDARD ################## - - -# PadFunction: IO_L22P_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[0]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[0]}] -set_property PACKAGE_PIN AD11 [get_ports {ddr3_dq_b[0]}] - -# PadFunction: IO_L24N_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[1]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[1]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[1]}] -set_property PACKAGE_PIN AE10 [get_ports {ddr3_dq_b[1]}] - -# PadFunction: IO_L20P_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[2]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[2]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[2]}] -set_property PACKAGE_PIN AF12 [get_ports {ddr3_dq_b[2]}] - -# PadFunction: IO_L23P_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[3]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[3]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[3]}] -set_property PACKAGE_PIN AG11 [get_ports {ddr3_dq_b[3]}] - -# PadFunction: IO_L22N_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[4]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[4]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[4]}] -set_property PACKAGE_PIN AE11 [get_ports {ddr3_dq_b[4]}] - -# PadFunction: IO_L23N_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[5]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[5]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[5]}] -set_property PACKAGE_PIN AH11 [get_ports {ddr3_dq_b[5]}] - -# PadFunction: IO_L20N_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[6]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[6]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[6]}] -set_property PACKAGE_PIN AG12 [get_ports {ddr3_dq_b[6]}] - -# PadFunction: IO_L19P_T3_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[7]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[7]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[7]}] -set_property PACKAGE_PIN AH9 [get_ports {ddr3_dq_b[7]}] - -# PadFunction: IO_L13P_T2_MRCC_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[8]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[8]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[8]}] -set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq_b[8]}] - -# PadFunction: IO_L14N_T2_SRCC_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[9]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[9]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[9]}] -set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq_b[9]}] - -# PadFunction: IO_L18P_T2_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[10]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[10]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[10]}] -set_property PACKAGE_PIN AF9 [get_ports {ddr3_dq_b[10]}] - -# PadFunction: IO_L17P_T2_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[11]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[11]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[11]}] -set_property PACKAGE_PIN AH7 [get_ports {ddr3_dq_b[11]}] - -# PadFunction: IO_L16P_T2_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[12]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[12]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[12]}] -set_property PACKAGE_PIN AE8 [get_ports {ddr3_dq_b[12]}] - -# PadFunction: IO_L18N_T2_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[13]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[13]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[13]}] -set_property PACKAGE_PIN AF8 [get_ports {ddr3_dq_b[13]}] - -# PadFunction: IO_L16N_T2_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[14]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[14]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[14]}] -set_property PACKAGE_PIN AE7 [get_ports {ddr3_dq_b[14]}] - -# PadFunction: IO_L14P_T2_SRCC_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[15]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[15]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[15]}] -set_property PACKAGE_PIN AF7 [get_ports {ddr3_dq_b[15]}] - -# PadFunction: IO_L7P_T1_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[16]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[16]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[16]}] -set_property PACKAGE_PIN AF4 [get_ports {ddr3_dq_b[16]}] - -# PadFunction: IO_L12N_T1_MRCC_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[17]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[17]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[17]}] -set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq_b[17]}] - -# PadFunction: IO_L10P_T1_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[18]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[18]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[18]}] -set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq_b[18]}] - -# PadFunction: IO_L11N_T1_SRCC_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[19]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[19]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[19]}] -set_property PACKAGE_PIN AG5 [get_ports {ddr3_dq_b[19]}] - -# PadFunction: IO_L8P_T1_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[20]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[20]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[20]}] -set_property PACKAGE_PIN AD5 [get_ports {ddr3_dq_b[20]}] - -# PadFunction: IO_L11P_T1_SRCC_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[21]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[21]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[21]}] -set_property PACKAGE_PIN AG6 [get_ports {ddr3_dq_b[21]}] - -# PadFunction: IO_L8N_T1_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[22]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[22]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[22]}] -set_property PACKAGE_PIN AD4 [get_ports {ddr3_dq_b[22]}] - -# PadFunction: IO_L10N_T1_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[23]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[23]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[23]}] -set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq_b[23]}] - -# PadFunction: IO_L1P_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[24]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[24]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[24]}] -set_property PACKAGE_PIN AG1 [get_ports {ddr3_dq_b[24]}] - -# PadFunction: IO_L5N_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[25]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[25]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[25]}] -set_property PACKAGE_PIN AG2 [get_ports {ddr3_dq_b[25]}] - -# PadFunction: IO_L2N_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[26]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[26]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[26]}] -set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq_b[26]}] - -# PadFunction: IO_L5P_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[27]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[27]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[27]}] -set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq_b[27]}] - -# PadFunction: IO_L4P_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[28]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[28]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[28]}] -set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq_b[28]}] - -# PadFunction: IO_L6P_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[29]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[29]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[29]}] -set_property PACKAGE_PIN AH3 [get_ports {ddr3_dq_b[29]}] - -# PadFunction: IO_L2P_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[30]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[30]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[30]}] -set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq_b[30]}] - -# PadFunction: IO_L4N_T0_33 -set_property SLEW FAST [get_ports {ddr3_dq_b[31]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[31]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[31]}] -set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq_b[31]}] - -# PadFunction: IO_L5N_T0_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[15]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[15]}] -set_property PACKAGE_PIN AP3 [get_ports {ddr3_addr_o[15]}] - -# PadFunction: IO_L15N_T2_DQS_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[14]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[14]}] -set_property PACKAGE_PIN AK8 [get_ports {ddr3_addr_o[14]}] - -# PadFunction: IO_L14P_T2_SRCC_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[13]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[13]}] -set_property PACKAGE_PIN AM7 [get_ports {ddr3_addr_o[13]}] - -# PadFunction: IO_L9N_T1_DQS_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[12]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[12]}] -set_property PACKAGE_PIN AP5 [get_ports {ddr3_addr_o[12]}] - -# PadFunction: IO_L15P_T2_DQS_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[11]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[11]}] -set_property PACKAGE_PIN AJ8 [get_ports {ddr3_addr_o[11]}] - -# PadFunction: IO_L3N_T0_DQS_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[10]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[10]}] -set_property PACKAGE_PIN AN2 [get_ports {ddr3_addr_o[10]}] - -# PadFunction: IO_L10P_T1_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[9]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[9]}] -set_property PACKAGE_PIN AL4 [get_ports {ddr3_addr_o[9]}] - -# PadFunction: IO_L12N_T1_MRCC_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[8]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[8]}] -set_property PACKAGE_PIN AK6 [get_ports {ddr3_addr_o[8]}] - -# PadFunction: IO_L9P_T1_DQS_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[7]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[7]}] -set_property PACKAGE_PIN AP6 [get_ports {ddr3_addr_o[7]}] - -# PadFunction: IO_L8N_T1_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[6]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[6]}] -set_property PACKAGE_PIN AK5 [get_ports {ddr3_addr_o[6]}] - -# PadFunction: IO_L6P_T0_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[5]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[5]}] -set_property PACKAGE_PIN AK3 [get_ports {ddr3_addr_o[5]}] - -# PadFunction: IO_L7P_T1_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[4]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[4]}] -set_property PACKAGE_PIN AN4 [get_ports {ddr3_addr_o[4]}] - -# PadFunction: IO_L14N_T2_SRCC_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[3]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[3]}] -set_property PACKAGE_PIN AM6 [get_ports {ddr3_addr_o[3]}] - -# PadFunction: IO_L10N_T1_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[2]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[2]}] -set_property PACKAGE_PIN AM4 [get_ports {ddr3_addr_o[2]}] - -# PadFunction: IO_L12P_T1_MRCC_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[1]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[1]}] -set_property PACKAGE_PIN AJ6 [get_ports {ddr3_addr_o[1]}] - -# PadFunction: IO_L7N_T1_32 -set_property SLEW FAST [get_ports {ddr3_addr_o[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[0]}] -set_property PACKAGE_PIN AP4 [get_ports {ddr3_addr_o[0]}] - -# PadFunction: IO_L2N_T0_32 -set_property SLEW FAST [get_ports {ddr3_ba_o[2]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba_o[2]}] -set_property PACKAGE_PIN AK1 [get_ports {ddr3_ba_o[2]}] - -# PadFunction: IO_L2P_T0_32 -set_property SLEW FAST [get_ports {ddr3_ba_o[1]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba_o[1]}] -set_property PACKAGE_PIN AK2 [get_ports {ddr3_ba_o[1]}] - -# PadFunction: IO_L3P_T0_DQS_32 -set_property SLEW FAST [get_ports {ddr3_ba_o[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba_o[0]}] -set_property PACKAGE_PIN AM2 [get_ports {ddr3_ba_o[0]}] - -# PadFunction: IO_L1P_T0_32 -set_property SLEW FAST [get_ports ddr3_ras_n_o] -set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n_o] -set_property PACKAGE_PIN AN1 [get_ports ddr3_ras_n_o] - -# PadFunction: IO_L4P_T0_32 -set_property SLEW FAST [get_ports ddr3_cas_n_o] -set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n_o] -set_property PACKAGE_PIN AL2 [get_ports ddr3_cas_n_o] - -# PadFunction: IO_L4N_T0_32 -set_property SLEW FAST [get_ports ddr3_we_n_o] -set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n_o] -set_property PACKAGE_PIN AM1 [get_ports ddr3_we_n_o] - -# PadFunction: IO_0_32 -set_property SLEW FAST [get_ports ddr3_reset_n_o] -set_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n_o] -set_property PACKAGE_PIN AJ9 [get_ports ddr3_reset_n_o] - -# PadFunction: IO_L8P_T1_32 -set_property SLEW FAST [get_ports {ddr3_cke_o[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke_o[0]}] -set_property PACKAGE_PIN AJ5 [get_ports {ddr3_cke_o[0]}] - -# PadFunction: IO_L1N_T0_32 -set_property SLEW FAST [get_ports {ddr3_odt_o[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt_o[0]}] -set_property PACKAGE_PIN AP1 [get_ports {ddr3_odt_o[0]}] - -# PadFunction: IO_L5P_T0_32 -set_property SLEW FAST [get_ports {ddr3_cs_n_o[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n_o[0]}] -set_property PACKAGE_PIN AN3 [get_ports {ddr3_cs_n_o[0]}] - -# PadFunction: IO_L24P_T3_33 -set_property SLEW FAST [get_ports {ddr3_dm_o[0]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[0]}] -set_property PACKAGE_PIN AD10 [get_ports {ddr3_dm_o[0]}] - -# PadFunction: IO_L17N_T2_33 -set_property SLEW FAST [get_ports {ddr3_dm_o[1]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[1]}] -set_property PACKAGE_PIN AH6 [get_ports {ddr3_dm_o[1]}] - -# PadFunction: IO_L7N_T1_33 -set_property SLEW FAST [get_ports {ddr3_dm_o[2]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[2]}] -set_property PACKAGE_PIN AG4 [get_ports {ddr3_dm_o[2]}] - -# PadFunction: IO_L1N_T0_33 -set_property SLEW FAST [get_ports {ddr3_dm_o[3]}] -set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[3]}] -set_property PACKAGE_PIN AH1 [get_ports {ddr3_dm_o[3]}] - -# PadFunction: IO_L21P_T3_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_p_b[0]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[0]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[0]}] - -# PadFunction: IO_L21N_T3_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_n_b[0]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[0]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[0]}] -set_property PACKAGE_PIN AG9 [get_ports {ddr3_dqs_n_b[0]}] - -# PadFunction: IO_L15P_T2_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_p_b[1]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[1]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[1]}] - -# PadFunction: IO_L15N_T2_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_n_b[1]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[1]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[1]}] -set_property PACKAGE_PIN AD8 [get_ports {ddr3_dqs_n_b[1]}] - -# PadFunction: IO_L9P_T1_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_p_b[2]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[2]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[2]}] - -# PadFunction: IO_L9N_T1_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_n_b[2]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[2]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[2]}] -set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dqs_n_b[2]}] - -# PadFunction: IO_L3P_T0_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_p_b[3]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[3]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[3]}] - -# PadFunction: IO_L3N_T0_DQS_33 -set_property SLEW FAST [get_ports {ddr3_dqs_n_b[3]}] -set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[3]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[3]}] -set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dqs_n_b[3]}] - -# PadFunction: IO_L11P_T1_SRCC_32 -set_property SLEW FAST [get_ports {ddr3_ck_p_o[0]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p_o[0]}] - -# PadFunction: IO_L11N_T1_SRCC_32 -set_property SLEW FAST [get_ports {ddr3_ck_n_o[0]}] -set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n_o[0]}] -set_property PACKAGE_PIN AM5 [get_ports {ddr3_ck_n_o[0]}] - - - -set_property LOC PHASER_OUT_PHY_X1Y3 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out] -set_property LOC PHASER_OUT_PHY_X1Y2 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out] -set_property LOC PHASER_OUT_PHY_X1Y1 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out] -set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out] -set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out] -set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out] -set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out] - -## set_property LOC PHASER_IN_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] -## set_property LOC PHASER_IN_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] -## set_property LOC PHASER_IN_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] -set_property LOC PHASER_IN_PHY_X1Y7 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in] -set_property LOC PHASER_IN_PHY_X1Y6 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in] -set_property LOC PHASER_IN_PHY_X1Y5 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in] -set_property LOC PHASER_IN_PHY_X1Y4 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in] - - - -set_property LOC OUT_FIFO_X1Y3 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo] -set_property LOC OUT_FIFO_X1Y2 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo] -set_property LOC OUT_FIFO_X1Y1 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo] -set_property LOC OUT_FIFO_X1Y7 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo] -set_property LOC OUT_FIFO_X1Y6 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo] -set_property LOC OUT_FIFO_X1Y5 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo] -set_property LOC OUT_FIFO_X1Y4 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo] - -set_property LOC IN_FIFO_X1Y7 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo] -set_property LOC IN_FIFO_X1Y6 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo] -set_property LOC IN_FIFO_X1Y5 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo] -set_property LOC IN_FIFO_X1Y4 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo] - -set_property LOC PHY_CONTROL_X1Y0 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i] -set_property LOC PHY_CONTROL_X1Y1 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i] - -set_property LOC PHASER_REF_X1Y0 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i] -set_property LOC PHASER_REF_X1Y1 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i] - -set_property LOC OLOGIC_X1Y93 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/slave_ts.oserdes_slave_ts] -set_property LOC OLOGIC_X1Y81 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/slave_ts.oserdes_slave_ts] -set_property LOC OLOGIC_X1Y69 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/slave_ts.oserdes_slave_ts] -set_property LOC OLOGIC_X1Y57 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/slave_ts.oserdes_slave_ts] - -set_property LOC PLLE2_ADV_X1Y0 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_ddr3_infrastructure/plle2_i] -set_property LOC MMCME2_ADV_X1Y0 [get_cells cmp_xwb_bpm_pcie_a7/cmp_wb_bpm_pcie_a7/cmp_bpm_pcie_a7/u_ddr_core/u_ddr_core_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i] - - -set_multicycle_path -setup -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 6 - -set_multicycle_path -hold -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] 5 - -#set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] # -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] # -setup 6 - -#set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] # -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] # -hold 5 - -#set_max_delay -from [get_cells -hier -filter {NAME =~ */u_phase_detector && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *neg_edge_samp*}] 2.500000 -#set_max_delay -from [get_cells -hier -filter {NAME =~ */u_phase_detector && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *pos_edge_samp*}] 2.500000 - -set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] - -set_multicycle_path -setup -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 2 -set_multicycle_path -hold -start -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] 1 - -set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20.000 -set_max_delay -datapath_only -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] 5.000 -#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 -#set_max_delay -from [get_cells -hier rstdiv0_sync_r1*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 - -set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20.000 -#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*rst_r1*}] 20 diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py deleted file mode 100644 index 90e2ed93..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/Manifest.py +++ /dev/null @@ -1,12 +0,0 @@ -files = [ "dbe_bpm_dsp.vhd", - "sys_pll.vhd", - "clk_gen.vhd", - "dbe_bpm_dsp.ucf", - "position_calc_core.ucf", - "dbe_bpm_dsp.xcf" ]; - -modules = { "local" : - ["../../.." - ] - }; - diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope.cpj b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope.cpj deleted file mode 100644 index 7b712305..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope.cpj +++ /dev/null @@ -1,13503 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Thu Jun 27 14:32:54 BRT 2013 -avoidUserRegDevice1=2,3,4 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109364250093 -mdiAreaHeight=0.7103448275862069 -mdiAreaHeightLast=0.6528735632183909 -mdiCount=21 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice10=1 -mdiDevice11=1 -mdiDevice12=1 -mdiDevice13=1 -mdiDevice14=1 -mdiDevice15=1 -mdiDevice16=1 -mdiDevice17=1 -mdiDevice18=1 -mdiDevice19=1 -mdiDevice2=1 -mdiDevice20=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiDevice6=1 -mdiDevice7=1 -mdiDevice8=1 -mdiDevice9=1 -mdiType0=5 -mdiType1=1 -mdiType10=1 -mdiType11=5 -mdiType12=0 -mdiType13=1 -mdiType14=5 -mdiType15=0 -mdiType16=1 -mdiType17=5 -mdiType18=0 -mdiType19=1 -mdiType2=0 -mdiType20=5 -mdiType3=0 -mdiType4=1 -mdiType5=5 -mdiType6=0 -mdiType7=1 -mdiType8=5 -mdiType9=0 -mdiUnit0=0 -mdiUnit1=0 -mdiUnit10=3 -mdiUnit11=3 -mdiUnit12=4 -mdiUnit13=4 -mdiUnit14=4 -mdiUnit15=5 -mdiUnit16=5 -mdiUnit17=5 -mdiUnit18=6 -mdiUnit19=6 -mdiUnit2=0 -mdiUnit20=6 -mdiUnit3=1 -mdiUnit4=1 -mdiUnit5=1 -mdiUnit6=2 -mdiUnit7=2 -mdiUnit8=2 -mdiUnit9=3 -navigatorHeight=0.16551724137931034 -navigatorHeightLast=0.16551724137931034 -navigatorWidth=0.13258286429018137 -navigatorWidthLast=0.13258286429018137 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.44878048 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=0.7079388 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5219512 -unit.1.0.1.WIDTH1=0.7079388 -unit.1.0.1.X1=0.0 -unit.1.0.1.Y1=0.34796748 -unit.1.0.2.HEIGHT2=0.39219016 -unit.1.0.2.WIDTH2=0.92604005 -unit.1.0.2.X2=0.07395994 -unit.1.0.2.Y2=0.55348045 -unit.1.0.5.HEIGHT5=0.8601626 -unit.1.0.5.WIDTH5=0.8667152 -unit.1.0.5.X5=0.011653314 -unit.1.0.5.Y5=0.01300813 -unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXX0XXXXXXXX -unit.1.0.MFBitsA3=XXXXXXXXXXXXXXXXXX01XXXXXXXXXXXX -unit.1.0.MFBitsB0=00000000000000000000000000000000 -unit.1.0.MFBitsB1=00000000000000000000000000000000 -unit.1.0.MFBitsB2=00000000000000000000000000000000 -unit.1.0.MFBitsB3=00000000000000000000000000000000 -unit.1.0.MFCompareA0=0 -unit.1.0.MFCompareA1=0 -unit.1.0.MFCompareA2=0 -unit.1.0.MFCompareA3=0 -unit.1.0.MFCompareB0=999 -unit.1.0.MFCompareB1=999 -unit.1.0.MFCompareB2=999 -unit.1.0.MFCompareB3=999 -unit.1.0.MFCount=4 -unit.1.0.MFDisplay0=0 -unit.1.0.MFDisplay1=0 -unit.1.0.MFDisplay2=0 -unit.1.0.MFDisplay3=0 -unit.1.0.MFEventType0=3 -unit.1.0.MFEventType1=3 -unit.1.0.MFEventType2=3 -unit.1.0.MFEventType3=3 -unit.1.0.RunMode=SINGLE RUN -unit.1.0.SQCondition=All Data -unit.1.0.SQContiguous0=0 -unit.1.0.SequencerOn=0 -unit.1.0.TCActive=0 -unit.1.0.TCAdvanced0=0 -unit.1.0.TCCondition0_0=M2 -unit.1.0.TCCondition0_1= -unit.1.0.TCConditionType0=0 -unit.1.0.TCCount=1 -unit.1.0.TCEventCount0=1 -unit.1.0.TCEventType0=3 -unit.1.0.TCName0=TriggerCondition0 -unit.1.0.TCOutputEnable0=0 -unit.1.0.TCOutputHigh0=1 -unit.1.0.TCOutputMode0=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.coretype=ILA -unit.1.0.eventCount0=1 -unit.1.0.eventCount1=1 -unit.1.0.eventCount2=1 -unit.1.0.eventCount3=1 -unit.1.0.export.format=2 -unit.1.0.export.signals=Bus Plot Buses -unit.1.0.export.unitName=DEV\:1 MyDevice1 (XC6VLX240T) UNIT\:0 MyILA0 (ILA) -unit.1.0.listing.count=0 -unit.1.0.plotBusColor0=-16777092 -unit.1.0.plotBusColor1=-3407821 -unit.1.0.plotBusColor10=-16777092 -unit.1.0.plotBusColor11=-16777092 -unit.1.0.plotBusColor12=-16777092 -unit.1.0.plotBusColor13=-16777092 -unit.1.0.plotBusColor14=-16777092 -unit.1.0.plotBusColor2=-6710785 -unit.1.0.plotBusColor3=-3355648 -unit.1.0.plotBusColor4=-16777092 -unit.1.0.plotBusColor5=-16777092 -unit.1.0.plotBusColor6=-16777092 -unit.1.0.plotBusColor7=-16777092 -unit.1.0.plotBusColor8=-16777092 -unit.1.0.plotBusColor9=-16777092 -unit.1.0.plotBusCount=4 -unit.1.0.plotBusName0=adc_data_ch0 -unit.1.0.plotBusName1=adc_data_ch1 -unit.1.0.plotBusName10=fmc516_debug_valid -unit.1.0.plotBusName11=fmc_adc_valid -unit.1.0.plotBusName12=fmc_lmk_lock -unit.1.0.plotBusName13=fmc_mmcm_lock -unit.1.0.plotBusName14=fmc_rst_adcs_n -unit.1.0.plotBusName2=adc_data_ch2 -unit.1.0.plotBusName3=adc_data_ch3 -unit.1.0.plotBusName4=fmc516_ch1_clk_dly -unit.1.0.plotBusName5=fmc516_ch1_clk_load -unit.1.0.plotBusName6=fmc516_ch1_data_dly -unit.1.0.plotBusName7=fmc516_ch1_data_load -unit.1.0.plotBusName8=fmc516_debug_dull -unit.1.0.plotBusName9=fmc516_debug_empty -unit.1.0.plotBusX=adc_data_ch0 -unit.1.0.plotBusY=adc_data_ch0 -unit.1.0.plotDataTimeMode=1 -unit.1.0.plotDisplayMode=line -unit.1.0.plotMaxX=1047.7522935779816 -unit.1.0.plotMaxY=1487.0 -unit.1.0.plotMinX=605.2752293577981 -unit.1.0.plotMinY=-1371.0 -unit.1.0.plotSelectedBus=0 -unit.1.0.port.-1.b.0.alias=adc_data_ch0 -unit.1.0.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.1.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.0.name=DataPort -unit.1.0.port.-1.b.0.orderindex=-1 -unit.1.0.port.-1.b.0.radix=Signed -unit.1.0.port.-1.b.0.signedOffset=0.0 -unit.1.0.port.-1.b.0.signedPrecision=0 -unit.1.0.port.-1.b.0.signedScaleFactor=1.0 -unit.1.0.port.-1.b.0.tokencount=0 -unit.1.0.port.-1.b.0.unsignedOffset=0.0 -unit.1.0.port.-1.b.0.unsignedPrecision=0 -unit.1.0.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.0.visible=1 -unit.1.0.port.-1.b.1.alias=adc_data_ch1 -unit.1.0.port.-1.b.1.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.-1.b.1.color=java.awt.Color[r\=204,g\=0,b\=51] -unit.1.0.port.-1.b.1.name=DataPort -unit.1.0.port.-1.b.1.orderindex=-1 -unit.1.0.port.-1.b.1.radix=Signed -unit.1.0.port.-1.b.1.signedOffset=0.0 -unit.1.0.port.-1.b.1.signedPrecision=0 -unit.1.0.port.-1.b.1.signedScaleFactor=1.0 -unit.1.0.port.-1.b.1.tokencount=0 -unit.1.0.port.-1.b.1.unsignedOffset=0.0 -unit.1.0.port.-1.b.1.unsignedPrecision=0 -unit.1.0.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.1.visible=1 -unit.1.0.port.-1.b.10.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.10.channellist=82 -unit.1.0.port.-1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.10.name=DataPort -unit.1.0.port.-1.b.10.orderindex=-1 -unit.1.0.port.-1.b.10.radix=Hex -unit.1.0.port.-1.b.10.signedOffset=0.0 -unit.1.0.port.-1.b.10.signedPrecision=0 -unit.1.0.port.-1.b.10.signedScaleFactor=1.0 -unit.1.0.port.-1.b.10.tokencount=0 -unit.1.0.port.-1.b.10.unsignedOffset=0.0 -unit.1.0.port.-1.b.10.unsignedPrecision=0 -unit.1.0.port.-1.b.10.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.10.visible=1 -unit.1.0.port.-1.b.11.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.11.channellist=82 -unit.1.0.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.11.name=DataPort -unit.1.0.port.-1.b.11.orderindex=-1 -unit.1.0.port.-1.b.11.radix=Hex -unit.1.0.port.-1.b.11.signedOffset=0.0 -unit.1.0.port.-1.b.11.signedPrecision=0 -unit.1.0.port.-1.b.11.signedScaleFactor=1.0 -unit.1.0.port.-1.b.11.tokencount=0 -unit.1.0.port.-1.b.11.unsignedOffset=0.0 -unit.1.0.port.-1.b.11.unsignedPrecision=0 -unit.1.0.port.-1.b.11.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.11.visible=1 -unit.1.0.port.-1.b.12.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.12.channellist=82 -unit.1.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.12.name=DataPort -unit.1.0.port.-1.b.12.orderindex=-1 -unit.1.0.port.-1.b.12.radix=Hex -unit.1.0.port.-1.b.12.signedOffset=0.0 -unit.1.0.port.-1.b.12.signedPrecision=0 -unit.1.0.port.-1.b.12.signedScaleFactor=1.0 -unit.1.0.port.-1.b.12.tokencount=0 -unit.1.0.port.-1.b.12.unsignedOffset=0.0 -unit.1.0.port.-1.b.12.unsignedPrecision=0 -unit.1.0.port.-1.b.12.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.12.visible=1 -unit.1.0.port.-1.b.13.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.13.channellist=82 -unit.1.0.port.-1.b.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.13.name=DataPort -unit.1.0.port.-1.b.13.orderindex=-1 -unit.1.0.port.-1.b.13.radix=Hex -unit.1.0.port.-1.b.13.signedOffset=0.0 -unit.1.0.port.-1.b.13.signedPrecision=0 -unit.1.0.port.-1.b.13.signedScaleFactor=1.0 -unit.1.0.port.-1.b.13.tokencount=0 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-unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 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-unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=MyILA0 -unit.1.0.waveform.count=4 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=adc_data_ch3 -unit.1.0.waveform.posn.0.radix=3 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-unit.1.0.waveform.posn.8.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.37398374 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.6715222 -unit.1.1.0.X0=0.036416605 -unit.1.1.0.Y0=0.0 -unit.1.1.1.HEIGHT1=0.8487805 -unit.1.1.1.WIDTH1=0.90167516 -unit.1.1.1.X1=0.060451567 -unit.1.1.1.Y1=0.17560975 -unit.1.1.5.HEIGHT5=0.7804878 -unit.1.1.5.WIDTH5=0.9533867 -unit.1.1.5.X5=0.029133284 -unit.1.1.5.Y5=0.15772358 -unit.1.1.MFBitsA0=XXXXX1XX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 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-unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=0 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=0 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=0 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=0 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=0 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=0 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=8 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.port.4.b.0.alias= -unit.1.1.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.b.0.name=TriggerPort4 -unit.1.1.port.4.b.0.orderindex=-1 -unit.1.1.port.4.b.0.radix=Hex -unit.1.1.port.4.b.0.signedOffset=0.0 -unit.1.1.port.4.b.0.signedPrecision=0 -unit.1.1.port.4.b.0.signedScaleFactor=1.0 -unit.1.1.port.4.b.0.unsignedOffset=0.0 -unit.1.1.port.4.b.0.unsignedPrecision=0 -unit.1.1.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.4.b.0.visible=1 -unit.1.1.port.4.buscount=1 -unit.1.1.port.4.channelcount=32 -unit.1.1.port.4.s.0.alias= -unit.1.1.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.0.name=TriggerPort4[0] -unit.1.1.port.4.s.0.orderindex=-1 -unit.1.1.port.4.s.0.visible=1 -unit.1.1.port.4.s.1.alias= -unit.1.1.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.1.name=TriggerPort4[1] -unit.1.1.port.4.s.1.orderindex=-1 -unit.1.1.port.4.s.1.visible=1 -unit.1.1.port.4.s.10.alias= -unit.1.1.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.10.name=TriggerPort4[10] -unit.1.1.port.4.s.10.orderindex=-1 -unit.1.1.port.4.s.10.visible=1 -unit.1.1.port.4.s.11.alias= -unit.1.1.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.11.name=TriggerPort4[11] -unit.1.1.port.4.s.11.orderindex=-1 -unit.1.1.port.4.s.11.visible=1 -unit.1.1.port.4.s.12.alias= -unit.1.1.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.12.name=TriggerPort4[12] -unit.1.1.port.4.s.12.orderindex=-1 -unit.1.1.port.4.s.12.visible=1 -unit.1.1.port.4.s.13.alias= -unit.1.1.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.13.name=TriggerPort4[13] -unit.1.1.port.4.s.13.orderindex=-1 -unit.1.1.port.4.s.13.visible=1 -unit.1.1.port.4.s.14.alias= -unit.1.1.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.14.name=TriggerPort4[14] -unit.1.1.port.4.s.14.orderindex=-1 -unit.1.1.port.4.s.14.visible=1 -unit.1.1.port.4.s.15.alias= -unit.1.1.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.15.name=TriggerPort4[15] -unit.1.1.port.4.s.15.orderindex=-1 -unit.1.1.port.4.s.15.visible=1 -unit.1.1.port.4.s.16.alias= -unit.1.1.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.16.name=TriggerPort4[16] -unit.1.1.port.4.s.16.orderindex=-1 -unit.1.1.port.4.s.16.visible=1 -unit.1.1.port.4.s.17.alias= -unit.1.1.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.17.name=TriggerPort4[17] -unit.1.1.port.4.s.17.orderindex=-1 -unit.1.1.port.4.s.17.visible=1 -unit.1.1.port.4.s.18.alias= -unit.1.1.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.18.name=TriggerPort4[18] -unit.1.1.port.4.s.18.orderindex=-1 -unit.1.1.port.4.s.18.visible=1 -unit.1.1.port.4.s.19.alias= -unit.1.1.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.19.name=TriggerPort4[19] -unit.1.1.port.4.s.19.orderindex=-1 -unit.1.1.port.4.s.19.visible=1 -unit.1.1.port.4.s.2.alias= -unit.1.1.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.2.name=TriggerPort4[2] -unit.1.1.port.4.s.2.orderindex=-1 -unit.1.1.port.4.s.2.visible=1 -unit.1.1.port.4.s.20.alias= -unit.1.1.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.20.name=TriggerPort4[20] -unit.1.1.port.4.s.20.orderindex=-1 -unit.1.1.port.4.s.20.visible=1 -unit.1.1.port.4.s.21.alias= -unit.1.1.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.21.name=TriggerPort4[21] -unit.1.1.port.4.s.21.orderindex=-1 -unit.1.1.port.4.s.21.visible=1 -unit.1.1.port.4.s.22.alias= -unit.1.1.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.22.name=TriggerPort4[22] -unit.1.1.port.4.s.22.orderindex=-1 -unit.1.1.port.4.s.22.visible=1 -unit.1.1.port.4.s.23.alias= -unit.1.1.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.23.name=TriggerPort4[23] -unit.1.1.port.4.s.23.orderindex=-1 -unit.1.1.port.4.s.23.visible=1 -unit.1.1.port.4.s.24.alias= -unit.1.1.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.24.name=TriggerPort4[24] -unit.1.1.port.4.s.24.orderindex=-1 -unit.1.1.port.4.s.24.visible=1 -unit.1.1.port.4.s.25.alias= -unit.1.1.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.25.name=TriggerPort4[25] -unit.1.1.port.4.s.25.orderindex=-1 -unit.1.1.port.4.s.25.visible=1 -unit.1.1.port.4.s.26.alias= -unit.1.1.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.26.name=TriggerPort4[26] -unit.1.1.port.4.s.26.orderindex=-1 -unit.1.1.port.4.s.26.visible=1 -unit.1.1.port.4.s.27.alias= -unit.1.1.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.27.name=TriggerPort4[27] -unit.1.1.port.4.s.27.orderindex=-1 -unit.1.1.port.4.s.27.visible=1 -unit.1.1.port.4.s.28.alias= -unit.1.1.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.28.name=TriggerPort4[28] -unit.1.1.port.4.s.28.orderindex=-1 -unit.1.1.port.4.s.28.visible=1 -unit.1.1.port.4.s.29.alias= -unit.1.1.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.29.name=TriggerPort4[29] -unit.1.1.port.4.s.29.orderindex=-1 -unit.1.1.port.4.s.29.visible=1 -unit.1.1.port.4.s.3.alias= -unit.1.1.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.3.name=TriggerPort4[3] -unit.1.1.port.4.s.3.orderindex=-1 -unit.1.1.port.4.s.3.visible=1 -unit.1.1.port.4.s.30.alias= -unit.1.1.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.30.name=TriggerPort4[30] -unit.1.1.port.4.s.30.orderindex=-1 -unit.1.1.port.4.s.30.visible=1 -unit.1.1.port.4.s.31.alias= -unit.1.1.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.31.name=TriggerPort4[31] -unit.1.1.port.4.s.31.orderindex=-1 -unit.1.1.port.4.s.31.visible=1 -unit.1.1.port.4.s.4.alias= -unit.1.1.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.4.name=TriggerPort4[4] -unit.1.1.port.4.s.4.orderindex=-1 -unit.1.1.port.4.s.4.visible=1 -unit.1.1.port.4.s.5.alias= -unit.1.1.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.5.name=TriggerPort4[5] -unit.1.1.port.4.s.5.orderindex=-1 -unit.1.1.port.4.s.5.visible=1 -unit.1.1.port.4.s.6.alias= -unit.1.1.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.6.name=TriggerPort4[6] -unit.1.1.port.4.s.6.orderindex=-1 -unit.1.1.port.4.s.6.visible=1 -unit.1.1.port.4.s.7.alias= -unit.1.1.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.7.name=TriggerPort4[7] -unit.1.1.port.4.s.7.orderindex=-1 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-unit.1.1.waveform.posn.95.name=DataPort[127] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=127 -unit.1.1.waveform.posn.96.name=DataPort[127] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal -unit.1.2.0.HEIGHT0=0.37398374 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 -unit.1.2.0.TriggerRow2=1 -unit.1.2.0.WIDTH0=0.6554989 -unit.1.2.0.X0=0.052439913 -unit.1.2.0.Y0=0.0 -unit.1.2.1.HEIGHT1=0.7804878 -unit.1.2.1.WIDTH1=0.603059 -unit.1.2.1.X1=0.0050983247 -unit.1.2.1.Y1=0.12682927 -unit.1.2.5.HEIGHT5=0.85203254 -unit.1.2.5.WIDTH5=0.68536055 -unit.1.2.5.X5=0.0036416606 -unit.1.2.5.Y5=0.06666667 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-unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=8 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 -unit.1.2.port.3.s.27.alias= -unit.1.2.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.27.name=TriggerPort3[27] -unit.1.2.port.3.s.27.orderindex=-1 -unit.1.2.port.3.s.27.visible=1 -unit.1.2.port.3.s.28.alias= -unit.1.2.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.28.name=TriggerPort3[28] -unit.1.2.port.3.s.28.orderindex=-1 -unit.1.2.port.3.s.28.visible=1 -unit.1.2.port.3.s.29.alias= -unit.1.2.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.29.name=TriggerPort3[29] -unit.1.2.port.3.s.29.orderindex=-1 -unit.1.2.port.3.s.29.visible=1 -unit.1.2.port.3.s.3.alias= -unit.1.2.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.3.name=TriggerPort3[3] -unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.port.4.b.0.alias= -unit.1.2.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.b.0.name=TriggerPort4 -unit.1.2.port.4.b.0.orderindex=-1 -unit.1.2.port.4.b.0.radix=Hex -unit.1.2.port.4.b.0.signedOffset=0.0 -unit.1.2.port.4.b.0.signedPrecision=0 -unit.1.2.port.4.b.0.signedScaleFactor=1.0 -unit.1.2.port.4.b.0.unsignedOffset=0.0 -unit.1.2.port.4.b.0.unsignedPrecision=0 -unit.1.2.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.4.b.0.visible=1 -unit.1.2.port.4.buscount=1 -unit.1.2.port.4.channelcount=32 -unit.1.2.port.4.s.0.alias= -unit.1.2.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.0.name=TriggerPort4[0] -unit.1.2.port.4.s.0.orderindex=-1 -unit.1.2.port.4.s.0.visible=1 -unit.1.2.port.4.s.1.alias= -unit.1.2.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.1.name=TriggerPort4[1] -unit.1.2.port.4.s.1.orderindex=-1 -unit.1.2.port.4.s.1.visible=1 -unit.1.2.port.4.s.10.alias= -unit.1.2.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.10.name=TriggerPort4[10] -unit.1.2.port.4.s.10.orderindex=-1 -unit.1.2.port.4.s.10.visible=1 -unit.1.2.port.4.s.11.alias= -unit.1.2.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.11.name=TriggerPort4[11] -unit.1.2.port.4.s.11.orderindex=-1 -unit.1.2.port.4.s.11.visible=1 -unit.1.2.port.4.s.12.alias= -unit.1.2.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.12.name=TriggerPort4[12] -unit.1.2.port.4.s.12.orderindex=-1 -unit.1.2.port.4.s.12.visible=1 -unit.1.2.port.4.s.13.alias= -unit.1.2.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.13.name=TriggerPort4[13] -unit.1.2.port.4.s.13.orderindex=-1 -unit.1.2.port.4.s.13.visible=1 -unit.1.2.port.4.s.14.alias= -unit.1.2.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.14.name=TriggerPort4[14] -unit.1.2.port.4.s.14.orderindex=-1 -unit.1.2.port.4.s.14.visible=1 -unit.1.2.port.4.s.15.alias= -unit.1.2.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.15.name=TriggerPort4[15] -unit.1.2.port.4.s.15.orderindex=-1 -unit.1.2.port.4.s.15.visible=1 -unit.1.2.port.4.s.16.alias= -unit.1.2.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.16.name=TriggerPort4[16] -unit.1.2.port.4.s.16.orderindex=-1 -unit.1.2.port.4.s.16.visible=1 -unit.1.2.port.4.s.17.alias= -unit.1.2.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.17.name=TriggerPort4[17] -unit.1.2.port.4.s.17.orderindex=-1 -unit.1.2.port.4.s.17.visible=1 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-unit.1.2.port.4.s.30.name=TriggerPort4[30] -unit.1.2.port.4.s.30.orderindex=-1 -unit.1.2.port.4.s.30.visible=1 -unit.1.2.port.4.s.31.alias= -unit.1.2.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.31.name=TriggerPort4[31] -unit.1.2.port.4.s.31.orderindex=-1 -unit.1.2.port.4.s.31.visible=1 -unit.1.2.port.4.s.4.alias= -unit.1.2.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.4.name=TriggerPort4[4] -unit.1.2.port.4.s.4.orderindex=-1 -unit.1.2.port.4.s.4.visible=1 -unit.1.2.port.4.s.5.alias= -unit.1.2.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.5.name=TriggerPort4[5] -unit.1.2.port.4.s.5.orderindex=-1 -unit.1.2.port.4.s.5.visible=1 -unit.1.2.port.4.s.6.alias= -unit.1.2.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.6.name=TriggerPort4[6] -unit.1.2.port.4.s.6.orderindex=-1 -unit.1.2.port.4.s.6.visible=1 -unit.1.2.port.4.s.7.alias= -unit.1.2.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.7.name=TriggerPort4[7] -unit.1.2.port.4.s.7.orderindex=-1 -unit.1.2.port.4.s.7.visible=1 -unit.1.2.port.4.s.8.alias= -unit.1.2.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.8.name=TriggerPort4[8] -unit.1.2.port.4.s.8.orderindex=-1 -unit.1.2.port.4.s.8.visible=1 -unit.1.2.port.4.s.9.alias= -unit.1.2.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.9.name=TriggerPort4[9] -unit.1.2.port.4.s.9.orderindex=-1 -unit.1.2.port.4.s.9.visible=1 -unit.1.2.portcount=5 -unit.1.2.rep_trigger.clobber=1 -unit.1.2.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.2.rep_trigger.filename=waveform -unit.1.2.rep_trigger.format=ASCII -unit.1.2.rep_trigger.loggingEnabled=0 -unit.1.2.rep_trigger.signals=All Signals/Buses -unit.1.2.samplesPerTrigger=1 -unit.1.2.triggerCapture=1 -unit.1.2.triggerNSamplesTS=0 -unit.1.2.triggerPosition=0 -unit.1.2.triggerWindowCount=1 -unit.1.2.triggerWindowDepth=4096 -unit.1.2.triggerWindowTS=0 -unit.1.2.username=MyILA2 -unit.1.2.waveform.count=33 -unit.1.2.waveform.posn.0.channel=2147483646 -unit.1.2.waveform.posn.0.name=dsp_tbt_amp_ch3 -unit.1.2.waveform.posn.0.radix=3 -unit.1.2.waveform.posn.0.type=bus -unit.1.2.waveform.posn.1.channel=2147483646 -unit.1.2.waveform.posn.1.name=dsp_tbt_amp_ch2 -unit.1.2.waveform.posn.1.radix=3 -unit.1.2.waveform.posn.1.type=bus -unit.1.2.waveform.posn.10.channel=7 -unit.1.2.waveform.posn.10.name=DataPort[7] -unit.1.2.waveform.posn.10.radix=3 -unit.1.2.waveform.posn.10.type=signal -unit.1.2.waveform.posn.100.channel=127 -unit.1.2.waveform.posn.100.name=DataPort[127] -unit.1.2.waveform.posn.100.type=signal -unit.1.2.waveform.posn.101.channel=127 -unit.1.2.waveform.posn.101.name=DataPort[127] -unit.1.2.waveform.posn.101.type=signal -unit.1.2.waveform.posn.102.channel=127 -unit.1.2.waveform.posn.102.name=DataPort[127] -unit.1.2.waveform.posn.102.type=signal -unit.1.2.waveform.posn.103.channel=127 -unit.1.2.waveform.posn.103.name=DataPort[127] -unit.1.2.waveform.posn.103.type=signal -unit.1.2.waveform.posn.104.channel=127 -unit.1.2.waveform.posn.104.name=DataPort[127] -unit.1.2.waveform.posn.104.type=signal -unit.1.2.waveform.posn.105.channel=127 -unit.1.2.waveform.posn.105.name=DataPort[127] -unit.1.2.waveform.posn.105.type=signal -unit.1.2.waveform.posn.106.channel=127 -unit.1.2.waveform.posn.106.name=DataPort[127] -unit.1.2.waveform.posn.106.type=signal -unit.1.2.waveform.posn.107.channel=127 -unit.1.2.waveform.posn.107.name=DataPort[127] -unit.1.2.waveform.posn.107.type=signal -unit.1.2.waveform.posn.108.channel=127 -unit.1.2.waveform.posn.108.name=DataPort[127] -unit.1.2.waveform.posn.108.type=signal -unit.1.2.waveform.posn.109.channel=127 -unit.1.2.waveform.posn.109.name=DataPort[127] -unit.1.2.waveform.posn.109.type=signal -unit.1.2.waveform.posn.11.channel=2147483646 -unit.1.2.waveform.posn.11.name=dsp_tbt_amp_ch0 -unit.1.2.waveform.posn.11.radix=3 -unit.1.2.waveform.posn.11.type=bus -unit.1.2.waveform.posn.110.channel=127 -unit.1.2.waveform.posn.110.name=DataPort[127] -unit.1.2.waveform.posn.110.type=signal -unit.1.2.waveform.posn.111.channel=127 -unit.1.2.waveform.posn.111.name=DataPort[127] -unit.1.2.waveform.posn.111.type=signal -unit.1.2.waveform.posn.112.channel=127 -unit.1.2.waveform.posn.112.name=DataPort[127] -unit.1.2.waveform.posn.112.type=signal -unit.1.2.waveform.posn.113.channel=127 -unit.1.2.waveform.posn.113.name=DataPort[127] -unit.1.2.waveform.posn.113.type=signal -unit.1.2.waveform.posn.114.channel=127 -unit.1.2.waveform.posn.114.name=DataPort[127] -unit.1.2.waveform.posn.114.type=signal -unit.1.2.waveform.posn.115.channel=127 -unit.1.2.waveform.posn.115.name=DataPort[127] -unit.1.2.waveform.posn.115.type=signal -unit.1.2.waveform.posn.116.channel=127 -unit.1.2.waveform.posn.116.name=DataPort[127] -unit.1.2.waveform.posn.116.type=signal -unit.1.2.waveform.posn.117.channel=127 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-unit.1.2.waveform.posn.16.type=signal -unit.1.2.waveform.posn.17.channel=38 -unit.1.2.waveform.posn.17.name=DataPort[38] -unit.1.2.waveform.posn.17.type=signal -unit.1.2.waveform.posn.18.channel=39 -unit.1.2.waveform.posn.18.name=DataPort[39] -unit.1.2.waveform.posn.18.type=signal -unit.1.2.waveform.posn.19.channel=65 -unit.1.2.waveform.posn.19.name=DataPort[65] -unit.1.2.waveform.posn.19.type=signal -unit.1.2.waveform.posn.2.channel=2147483646 -unit.1.2.waveform.posn.2.name=dsp_tbt_amp_ch1 -unit.1.2.waveform.posn.2.radix=3 -unit.1.2.waveform.posn.2.type=bus -unit.1.2.waveform.posn.20.channel=66 -unit.1.2.waveform.posn.20.name=DataPort[66] -unit.1.2.waveform.posn.20.type=signal -unit.1.2.waveform.posn.21.channel=67 -unit.1.2.waveform.posn.21.name=DataPort[67] -unit.1.2.waveform.posn.21.type=signal -unit.1.2.waveform.posn.22.channel=68 -unit.1.2.waveform.posn.22.name=DataPort[68] -unit.1.2.waveform.posn.22.type=signal -unit.1.2.waveform.posn.23.channel=69 -unit.1.2.waveform.posn.23.name=DataPort[69] -unit.1.2.waveform.posn.23.radix=3 -unit.1.2.waveform.posn.23.type=signal -unit.1.2.waveform.posn.24.channel=70 -unit.1.2.waveform.posn.24.name=DataPort[70] -unit.1.2.waveform.posn.24.radix=3 -unit.1.2.waveform.posn.24.type=signal -unit.1.2.waveform.posn.25.channel=71 -unit.1.2.waveform.posn.25.name=DataPort[71] -unit.1.2.waveform.posn.25.type=signal -unit.1.2.waveform.posn.26.channel=97 -unit.1.2.waveform.posn.26.name=DataPort[97] -unit.1.2.waveform.posn.26.type=signal -unit.1.2.waveform.posn.27.channel=98 -unit.1.2.waveform.posn.27.name=DataPort[98] -unit.1.2.waveform.posn.27.type=signal -unit.1.2.waveform.posn.28.channel=99 -unit.1.2.waveform.posn.28.name=DataPort[99] -unit.1.2.waveform.posn.28.type=signal -unit.1.2.waveform.posn.29.channel=100 -unit.1.2.waveform.posn.29.name=DataPort[100] -unit.1.2.waveform.posn.29.type=signal -unit.1.2.waveform.posn.3.channel=0 -unit.1.2.waveform.posn.3.name=DataPort[0] -unit.1.2.waveform.posn.3.type=signal -unit.1.2.waveform.posn.30.channel=101 -unit.1.2.waveform.posn.30.name=DataPort[101] -unit.1.2.waveform.posn.30.type=signal -unit.1.2.waveform.posn.31.channel=102 -unit.1.2.waveform.posn.31.name=DataPort[102] -unit.1.2.waveform.posn.31.radix=3 -unit.1.2.waveform.posn.31.type=signal -unit.1.2.waveform.posn.32.channel=103 -unit.1.2.waveform.posn.32.name=DataPort[103] -unit.1.2.waveform.posn.32.radix=3 -unit.1.2.waveform.posn.32.type=signal -unit.1.2.waveform.posn.33.channel=127 -unit.1.2.waveform.posn.33.name=DataPort[127] -unit.1.2.waveform.posn.33.type=signal -unit.1.2.waveform.posn.34.channel=127 -unit.1.2.waveform.posn.34.name=DataPort[127] -unit.1.2.waveform.posn.34.type=signal -unit.1.2.waveform.posn.35.channel=127 -unit.1.2.waveform.posn.35.name=DataPort[127] -unit.1.2.waveform.posn.35.type=signal -unit.1.2.waveform.posn.36.channel=127 -unit.1.2.waveform.posn.36.name=DataPort[127] -unit.1.2.waveform.posn.36.type=signal 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-unit.1.2.waveform.posn.8.type=signal -unit.1.2.waveform.posn.80.channel=127 -unit.1.2.waveform.posn.80.name=DataPort[127] -unit.1.2.waveform.posn.80.type=signal -unit.1.2.waveform.posn.81.channel=127 -unit.1.2.waveform.posn.81.name=DataPort[127] -unit.1.2.waveform.posn.81.type=signal -unit.1.2.waveform.posn.82.channel=127 -unit.1.2.waveform.posn.82.name=DataPort[127] -unit.1.2.waveform.posn.82.type=signal -unit.1.2.waveform.posn.83.channel=127 -unit.1.2.waveform.posn.83.name=DataPort[127] -unit.1.2.waveform.posn.83.type=signal -unit.1.2.waveform.posn.84.channel=127 -unit.1.2.waveform.posn.84.name=DataPort[127] -unit.1.2.waveform.posn.84.type=signal -unit.1.2.waveform.posn.85.channel=127 -unit.1.2.waveform.posn.85.name=DataPort[127] -unit.1.2.waveform.posn.85.type=signal -unit.1.2.waveform.posn.86.channel=127 -unit.1.2.waveform.posn.86.name=DataPort[127] -unit.1.2.waveform.posn.86.type=signal -unit.1.2.waveform.posn.87.channel=127 -unit.1.2.waveform.posn.87.name=DataPort[127] -unit.1.2.waveform.posn.87.type=signal -unit.1.2.waveform.posn.88.channel=127 -unit.1.2.waveform.posn.88.name=DataPort[127] -unit.1.2.waveform.posn.88.type=signal -unit.1.2.waveform.posn.89.channel=127 -unit.1.2.waveform.posn.89.name=DataPort[127] -unit.1.2.waveform.posn.89.type=signal -unit.1.2.waveform.posn.9.channel=6 -unit.1.2.waveform.posn.9.name=DataPort[6] -unit.1.2.waveform.posn.9.radix=3 -unit.1.2.waveform.posn.9.type=signal -unit.1.2.waveform.posn.90.channel=127 -unit.1.2.waveform.posn.90.name=DataPort[127] -unit.1.2.waveform.posn.90.type=signal -unit.1.2.waveform.posn.91.channel=127 -unit.1.2.waveform.posn.91.name=DataPort[127] -unit.1.2.waveform.posn.91.type=signal -unit.1.2.waveform.posn.92.channel=127 -unit.1.2.waveform.posn.92.name=DataPort[127] -unit.1.2.waveform.posn.92.type=signal -unit.1.2.waveform.posn.93.channel=127 -unit.1.2.waveform.posn.93.name=DataPort[127] -unit.1.2.waveform.posn.93.type=signal -unit.1.2.waveform.posn.94.channel=127 -unit.1.2.waveform.posn.94.name=DataPort[127] -unit.1.2.waveform.posn.94.type=signal -unit.1.2.waveform.posn.95.channel=127 -unit.1.2.waveform.posn.95.name=DataPort[127] -unit.1.2.waveform.posn.95.type=signal -unit.1.2.waveform.posn.96.channel=127 -unit.1.2.waveform.posn.96.name=DataPort[127] -unit.1.2.waveform.posn.96.type=signal -unit.1.2.waveform.posn.97.channel=127 -unit.1.2.waveform.posn.97.name=DataPort[127] -unit.1.2.waveform.posn.97.type=signal -unit.1.2.waveform.posn.98.channel=127 -unit.1.2.waveform.posn.98.name=DataPort[127] -unit.1.2.waveform.posn.98.type=signal -unit.1.2.waveform.posn.99.channel=127 -unit.1.2.waveform.posn.99.name=DataPort[127] -unit.1.2.waveform.posn.99.type=signal -unit.1.3.0.HEIGHT0=0.4699187 -unit.1.3.0.TriggerRow0=1 -unit.1.3.0.TriggerRow1=1 -unit.1.3.0.TriggerRow2=1 -unit.1.3.0.WIDTH0=0.7079388 -unit.1.3.0.X0=0.0 -unit.1.3.0.Y0=0.0 -unit.1.3.1.HEIGHT1=0.66178864 -unit.1.3.1.WIDTH1=0.7079388 -unit.1.3.1.X1=0.0 -unit.1.3.1.Y1=0.25691056 -unit.1.3.5.HEIGHT5=0.7804878 -unit.1.3.5.WIDTH5=0.94901675 -unit.1.3.5.X5=0.020393299 -unit.1.3.5.Y5=0.05691057 -unit.1.3.MFBitsA0=X1XXXXXX -unit.1.3.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsB0=00000000 -unit.1.3.MFBitsB1=00000000000000000000000000000000 -unit.1.3.MFBitsB2=00000000000000000000000000000000 -unit.1.3.MFBitsB3=00000000000000000000000000000000 -unit.1.3.MFBitsB4=00000000000000000000000000000000 -unit.1.3.MFCompareA0=0 -unit.1.3.MFCompareA1=0 -unit.1.3.MFCompareA2=0 -unit.1.3.MFCompareA3=0 -unit.1.3.MFCompareA4=0 -unit.1.3.MFCompareB0=999 -unit.1.3.MFCompareB1=999 -unit.1.3.MFCompareB2=999 -unit.1.3.MFCompareB3=999 -unit.1.3.MFCompareB4=999 -unit.1.3.MFCount=5 -unit.1.3.MFDisplay0=0 -unit.1.3.MFDisplay1=0 -unit.1.3.MFDisplay2=0 -unit.1.3.MFDisplay3=0 -unit.1.3.MFDisplay4=0 -unit.1.3.MFEventType0=3 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-unit.1.3.port.-1.s.66.name=DataPort[66] -unit.1.3.port.-1.s.66.orderindex=-1 -unit.1.3.port.-1.s.66.visible=1 -unit.1.3.port.-1.s.67.alias= -unit.1.3.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.67.name=DataPort[67] -unit.1.3.port.-1.s.67.orderindex=-1 -unit.1.3.port.-1.s.67.visible=1 -unit.1.3.port.-1.s.68.alias= -unit.1.3.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.68.name=DataPort[68] -unit.1.3.port.-1.s.68.orderindex=-1 -unit.1.3.port.-1.s.68.visible=1 -unit.1.3.port.-1.s.69.alias= -unit.1.3.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.69.name=DataPort[69] -unit.1.3.port.-1.s.69.orderindex=-1 -unit.1.3.port.-1.s.69.visible=1 -unit.1.3.port.-1.s.7.alias= -unit.1.3.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.7.name=DataPort[7] -unit.1.3.port.-1.s.7.orderindex=-1 -unit.1.3.port.-1.s.7.visible=1 -unit.1.3.port.-1.s.70.alias= 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-unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.3.waveform.posn.15.name=DataPort[38] -unit.1.3.waveform.posn.15.type=signal -unit.1.3.waveform.posn.16.channel=39 -unit.1.3.waveform.posn.16.name=DataPort[39] -unit.1.3.waveform.posn.16.type=signal -unit.1.3.waveform.posn.17.channel=66 -unit.1.3.waveform.posn.17.name=DataPort[66] -unit.1.3.waveform.posn.17.type=signal -unit.1.3.waveform.posn.18.channel=67 -unit.1.3.waveform.posn.18.name=DataPort[67] -unit.1.3.waveform.posn.18.radix=1 -unit.1.3.waveform.posn.18.type=signal -unit.1.3.waveform.posn.19.channel=68 -unit.1.3.waveform.posn.19.name=DataPort[68] -unit.1.3.waveform.posn.19.type=signal -unit.1.3.waveform.posn.2.channel=2147483646 -unit.1.3.waveform.posn.2.name=dsp_x_tbt -unit.1.3.waveform.posn.2.radix=3 -unit.1.3.waveform.posn.2.type=bus -unit.1.3.waveform.posn.20.channel=69 -unit.1.3.waveform.posn.20.name=DataPort[69] -unit.1.3.waveform.posn.20.type=signal -unit.1.3.waveform.posn.21.channel=70 -unit.1.3.waveform.posn.21.name=DataPort[70] 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-unit.1.3.waveform.posn.9.type=signal -unit.1.3.waveform.posn.90.channel=127 -unit.1.3.waveform.posn.90.name=DataPort[127] -unit.1.3.waveform.posn.90.type=signal -unit.1.3.waveform.posn.91.channel=127 -unit.1.3.waveform.posn.91.name=DataPort[127] -unit.1.3.waveform.posn.91.type=signal -unit.1.3.waveform.posn.92.channel=127 -unit.1.3.waveform.posn.92.name=DataPort[127] -unit.1.3.waveform.posn.92.type=signal -unit.1.3.waveform.posn.93.channel=127 -unit.1.3.waveform.posn.93.name=DataPort[127] -unit.1.3.waveform.posn.93.type=signal -unit.1.3.waveform.posn.94.channel=127 -unit.1.3.waveform.posn.94.name=DataPort[127] -unit.1.3.waveform.posn.94.type=signal -unit.1.3.waveform.posn.95.channel=127 -unit.1.3.waveform.posn.95.name=DataPort[127] -unit.1.3.waveform.posn.95.type=signal -unit.1.3.waveform.posn.96.channel=127 -unit.1.3.waveform.posn.96.name=DataPort[127] -unit.1.3.waveform.posn.96.type=signal -unit.1.3.waveform.posn.97.channel=127 -unit.1.3.waveform.posn.97.name=DataPort[127] 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-unit.1.4.port.-1.s.80.orderindex=-1 -unit.1.4.port.-1.s.80.visible=0 -unit.1.4.port.-1.s.81.alias= -unit.1.4.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.81.name=DataPort[81] -unit.1.4.port.-1.s.81.orderindex=-1 -unit.1.4.port.-1.s.81.visible=0 -unit.1.4.port.-1.s.82.alias= -unit.1.4.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.82.name=DataPort[82] -unit.1.4.port.-1.s.82.orderindex=-1 -unit.1.4.port.-1.s.82.visible=0 -unit.1.4.port.-1.s.83.alias= -unit.1.4.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.83.name=DataPort[83] -unit.1.4.port.-1.s.83.orderindex=-1 -unit.1.4.port.-1.s.83.visible=0 -unit.1.4.port.-1.s.84.alias= -unit.1.4.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.84.name=DataPort[84] -unit.1.4.port.-1.s.84.orderindex=-1 -unit.1.4.port.-1.s.84.visible=0 -unit.1.4.port.-1.s.85.alias= -unit.1.4.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.85.name=DataPort[85] -unit.1.4.port.-1.s.85.orderindex=-1 -unit.1.4.port.-1.s.85.visible=0 -unit.1.4.port.-1.s.86.alias= -unit.1.4.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.86.name=DataPort[86] -unit.1.4.port.-1.s.86.orderindex=-1 -unit.1.4.port.-1.s.86.visible=0 -unit.1.4.port.-1.s.87.alias= -unit.1.4.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.87.name=DataPort[87] -unit.1.4.port.-1.s.87.orderindex=-1 -unit.1.4.port.-1.s.87.visible=0 -unit.1.4.port.-1.s.88.alias= -unit.1.4.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.88.name=DataPort[88] -unit.1.4.port.-1.s.88.orderindex=-1 -unit.1.4.port.-1.s.88.visible=0 -unit.1.4.port.-1.s.89.alias= -unit.1.4.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.89.name=DataPort[89] -unit.1.4.port.-1.s.89.orderindex=-1 -unit.1.4.port.-1.s.89.visible=0 -unit.1.4.port.-1.s.9.alias= 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-unit.1.4.port.0.s.5.visible=1 -unit.1.4.port.0.s.6.alias= -unit.1.4.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.6.name=TriggerPort0[6] -unit.1.4.port.0.s.6.orderindex=-1 -unit.1.4.port.0.s.6.visible=1 -unit.1.4.port.0.s.7.alias= -unit.1.4.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.7.name=TriggerPort0[7] -unit.1.4.port.0.s.7.orderindex=-1 -unit.1.4.port.0.s.7.visible=1 -unit.1.4.port.1.b.0.alias= -unit.1.4.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex -unit.1.4.port.1.b.0.signedOffset=0.0 -unit.1.4.port.1.b.0.signedPrecision=0 -unit.1.4.port.1.b.0.signedScaleFactor=1.0 -unit.1.4.port.1.b.0.unsignedOffset=0.0 -unit.1.4.port.1.b.0.unsignedPrecision=0 -unit.1.4.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.1.b.0.visible=1 -unit.1.4.port.1.buscount=1 -unit.1.4.port.1.channelcount=32 -unit.1.4.port.1.s.0.alias= -unit.1.4.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.0.name=TriggerPort1[0] -unit.1.4.port.1.s.0.orderindex=-1 -unit.1.4.port.1.s.0.visible=1 -unit.1.4.port.1.s.1.alias= -unit.1.4.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.1.name=TriggerPort1[1] -unit.1.4.port.1.s.1.orderindex=-1 -unit.1.4.port.1.s.1.visible=1 -unit.1.4.port.1.s.10.alias= -unit.1.4.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.10.name=TriggerPort1[10] -unit.1.4.port.1.s.10.orderindex=-1 -unit.1.4.port.1.s.10.visible=1 -unit.1.4.port.1.s.11.alias= -unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 -unit.1.4.port.1.s.16.alias= -unit.1.4.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.16.name=TriggerPort1[16] -unit.1.4.port.1.s.16.orderindex=-1 -unit.1.4.port.1.s.16.visible=1 -unit.1.4.port.1.s.17.alias= -unit.1.4.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.17.name=TriggerPort1[17] -unit.1.4.port.1.s.17.orderindex=-1 -unit.1.4.port.1.s.17.visible=1 -unit.1.4.port.1.s.18.alias= -unit.1.4.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.18.name=TriggerPort1[18] -unit.1.4.port.1.s.18.orderindex=-1 -unit.1.4.port.1.s.18.visible=1 -unit.1.4.port.1.s.19.alias= -unit.1.4.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.19.name=TriggerPort1[19] -unit.1.4.port.1.s.19.orderindex=-1 -unit.1.4.port.1.s.19.visible=1 -unit.1.4.port.1.s.2.alias= -unit.1.4.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.2.name=TriggerPort1[2] -unit.1.4.port.1.s.2.orderindex=-1 -unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.18.name=TriggerPort3[18] -unit.1.4.port.3.s.18.orderindex=-1 -unit.1.4.port.3.s.18.visible=1 -unit.1.4.port.3.s.19.alias= -unit.1.4.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.19.name=TriggerPort3[19] -unit.1.4.port.3.s.19.orderindex=-1 -unit.1.4.port.3.s.19.visible=1 -unit.1.4.port.3.s.2.alias= -unit.1.4.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.2.name=TriggerPort3[2] -unit.1.4.port.3.s.2.orderindex=-1 -unit.1.4.port.3.s.2.visible=1 -unit.1.4.port.3.s.20.alias= -unit.1.4.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.20.name=TriggerPort3[20] -unit.1.4.port.3.s.20.orderindex=-1 -unit.1.4.port.3.s.20.visible=1 -unit.1.4.port.3.s.21.alias= -unit.1.4.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.21.name=TriggerPort3[21] -unit.1.4.port.3.s.21.orderindex=-1 -unit.1.4.port.3.s.21.visible=1 -unit.1.4.port.3.s.22.alias= -unit.1.4.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.22.name=TriggerPort3[22] -unit.1.4.port.3.s.22.orderindex=-1 -unit.1.4.port.3.s.22.visible=1 -unit.1.4.port.3.s.23.alias= -unit.1.4.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.23.name=TriggerPort3[23] -unit.1.4.port.3.s.23.orderindex=-1 -unit.1.4.port.3.s.23.visible=1 -unit.1.4.port.3.s.24.alias= -unit.1.4.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.24.name=TriggerPort3[24] -unit.1.4.port.3.s.24.orderindex=-1 -unit.1.4.port.3.s.24.visible=1 -unit.1.4.port.3.s.25.alias= -unit.1.4.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.25.name=TriggerPort3[25] -unit.1.4.port.3.s.25.orderindex=-1 -unit.1.4.port.3.s.25.visible=1 -unit.1.4.port.3.s.26.alias= -unit.1.4.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.26.name=TriggerPort3[26] -unit.1.4.port.3.s.26.orderindex=-1 -unit.1.4.port.3.s.26.visible=1 -unit.1.4.port.3.s.27.alias= -unit.1.4.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.27.name=TriggerPort3[27] -unit.1.4.port.3.s.27.orderindex=-1 -unit.1.4.port.3.s.27.visible=1 -unit.1.4.port.3.s.28.alias= -unit.1.4.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.28.name=TriggerPort3[28] -unit.1.4.port.3.s.28.orderindex=-1 -unit.1.4.port.3.s.28.visible=1 -unit.1.4.port.3.s.29.alias= -unit.1.4.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.29.name=TriggerPort3[29] -unit.1.4.port.3.s.29.orderindex=-1 -unit.1.4.port.3.s.29.visible=1 -unit.1.4.port.3.s.3.alias= -unit.1.4.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.3.name=TriggerPort3[3] -unit.1.4.port.3.s.3.orderindex=-1 -unit.1.4.port.3.s.3.visible=1 -unit.1.4.port.3.s.30.alias= -unit.1.4.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.30.name=TriggerPort3[30] -unit.1.4.port.3.s.30.orderindex=-1 -unit.1.4.port.3.s.30.visible=1 -unit.1.4.port.3.s.31.alias= -unit.1.4.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.31.name=TriggerPort3[31] -unit.1.4.port.3.s.31.orderindex=-1 -unit.1.4.port.3.s.31.visible=1 -unit.1.4.port.3.s.4.alias= -unit.1.4.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.4.name=TriggerPort3[4] -unit.1.4.port.3.s.4.orderindex=-1 -unit.1.4.port.3.s.4.visible=1 -unit.1.4.port.3.s.5.alias= -unit.1.4.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.5.name=TriggerPort3[5] -unit.1.4.port.3.s.5.orderindex=-1 -unit.1.4.port.3.s.5.visible=1 -unit.1.4.port.3.s.6.alias= -unit.1.4.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.6.name=TriggerPort3[6] -unit.1.4.port.3.s.6.orderindex=-1 -unit.1.4.port.3.s.6.visible=1 -unit.1.4.port.3.s.7.alias= -unit.1.4.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.7.name=TriggerPort3[7] -unit.1.4.port.3.s.7.orderindex=-1 -unit.1.4.port.3.s.7.visible=1 -unit.1.4.port.3.s.8.alias= -unit.1.4.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.8.name=TriggerPort3[8] -unit.1.4.port.3.s.8.orderindex=-1 -unit.1.4.port.3.s.8.visible=1 -unit.1.4.port.3.s.9.alias= -unit.1.4.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.9.name=TriggerPort3[9] -unit.1.4.port.3.s.9.orderindex=-1 -unit.1.4.port.3.s.9.visible=1 -unit.1.4.port.4.b.0.alias= -unit.1.4.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.b.0.name=TriggerPort4 -unit.1.4.port.4.b.0.orderindex=-1 -unit.1.4.port.4.b.0.radix=Hex -unit.1.4.port.4.b.0.signedOffset=0.0 -unit.1.4.port.4.b.0.signedPrecision=0 -unit.1.4.port.4.b.0.signedScaleFactor=1.0 -unit.1.4.port.4.b.0.unsignedOffset=0.0 -unit.1.4.port.4.b.0.unsignedPrecision=0 -unit.1.4.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.4.b.0.visible=1 -unit.1.4.port.4.buscount=1 -unit.1.4.port.4.channelcount=32 -unit.1.4.port.4.s.0.alias= -unit.1.4.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.0.name=TriggerPort4[0] -unit.1.4.port.4.s.0.orderindex=-1 -unit.1.4.port.4.s.0.visible=1 -unit.1.4.port.4.s.1.alias= -unit.1.4.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.1.name=TriggerPort4[1] -unit.1.4.port.4.s.1.orderindex=-1 -unit.1.4.port.4.s.1.visible=1 -unit.1.4.port.4.s.10.alias= -unit.1.4.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.10.name=TriggerPort4[10] -unit.1.4.port.4.s.10.orderindex=-1 -unit.1.4.port.4.s.10.visible=1 -unit.1.4.port.4.s.11.alias= -unit.1.4.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.11.name=TriggerPort4[11] -unit.1.4.port.4.s.11.orderindex=-1 -unit.1.4.port.4.s.11.visible=1 -unit.1.4.port.4.s.12.alias= -unit.1.4.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.12.name=TriggerPort4[12] -unit.1.4.port.4.s.12.orderindex=-1 -unit.1.4.port.4.s.12.visible=1 -unit.1.4.port.4.s.13.alias= -unit.1.4.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.13.name=TriggerPort4[13] -unit.1.4.port.4.s.13.orderindex=-1 -unit.1.4.port.4.s.13.visible=1 -unit.1.4.port.4.s.14.alias= -unit.1.4.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.14.name=TriggerPort4[14] -unit.1.4.port.4.s.14.orderindex=-1 -unit.1.4.port.4.s.14.visible=1 -unit.1.4.port.4.s.15.alias= -unit.1.4.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.15.name=TriggerPort4[15] -unit.1.4.port.4.s.15.orderindex=-1 -unit.1.4.port.4.s.15.visible=1 -unit.1.4.port.4.s.16.alias= -unit.1.4.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.16.name=TriggerPort4[16] -unit.1.4.port.4.s.16.orderindex=-1 -unit.1.4.port.4.s.16.visible=1 -unit.1.4.port.4.s.17.alias= -unit.1.4.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.17.name=TriggerPort4[17] -unit.1.4.port.4.s.17.orderindex=-1 -unit.1.4.port.4.s.17.visible=1 -unit.1.4.port.4.s.18.alias= -unit.1.4.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.18.name=TriggerPort4[18] -unit.1.4.port.4.s.18.orderindex=-1 -unit.1.4.port.4.s.18.visible=1 -unit.1.4.port.4.s.19.alias= -unit.1.4.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.19.name=TriggerPort4[19] -unit.1.4.port.4.s.19.orderindex=-1 -unit.1.4.port.4.s.19.visible=1 -unit.1.4.port.4.s.2.alias= -unit.1.4.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.2.name=TriggerPort4[2] -unit.1.4.port.4.s.2.orderindex=-1 -unit.1.4.port.4.s.2.visible=1 -unit.1.4.port.4.s.20.alias= -unit.1.4.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.20.name=TriggerPort4[20] -unit.1.4.port.4.s.20.orderindex=-1 -unit.1.4.port.4.s.20.visible=1 -unit.1.4.port.4.s.21.alias= -unit.1.4.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.21.name=TriggerPort4[21] -unit.1.4.port.4.s.21.orderindex=-1 -unit.1.4.port.4.s.21.visible=1 -unit.1.4.port.4.s.22.alias= -unit.1.4.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.22.name=TriggerPort4[22] -unit.1.4.port.4.s.22.orderindex=-1 -unit.1.4.port.4.s.22.visible=1 -unit.1.4.port.4.s.23.alias= -unit.1.4.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.23.name=TriggerPort4[23] -unit.1.4.port.4.s.23.orderindex=-1 -unit.1.4.port.4.s.23.visible=1 -unit.1.4.port.4.s.24.alias= -unit.1.4.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.24.name=TriggerPort4[24] -unit.1.4.port.4.s.24.orderindex=-1 -unit.1.4.port.4.s.24.visible=1 -unit.1.4.port.4.s.25.alias= -unit.1.4.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.25.name=TriggerPort4[25] -unit.1.4.port.4.s.25.orderindex=-1 -unit.1.4.port.4.s.25.visible=1 -unit.1.4.port.4.s.26.alias= -unit.1.4.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.26.name=TriggerPort4[26] -unit.1.4.port.4.s.26.orderindex=-1 -unit.1.4.port.4.s.26.visible=1 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-unit.1.5.port.-1.s.90.alias= -unit.1.5.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.90.name=DataPort[90] -unit.1.5.port.-1.s.90.orderindex=-1 -unit.1.5.port.-1.s.90.visible=0 -unit.1.5.port.-1.s.91.alias= -unit.1.5.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.91.name=DataPort[91] -unit.1.5.port.-1.s.91.orderindex=-1 -unit.1.5.port.-1.s.91.visible=0 -unit.1.5.port.-1.s.92.alias= -unit.1.5.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.92.name=DataPort[92] -unit.1.5.port.-1.s.92.orderindex=-1 -unit.1.5.port.-1.s.92.visible=0 -unit.1.5.port.-1.s.93.alias= -unit.1.5.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.93.name=DataPort[93] -unit.1.5.port.-1.s.93.orderindex=-1 -unit.1.5.port.-1.s.93.visible=0 -unit.1.5.port.-1.s.94.alias= -unit.1.5.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.94.name=DataPort[94] -unit.1.5.port.-1.s.94.orderindex=-1 -unit.1.5.port.-1.s.94.visible=0 -unit.1.5.port.-1.s.95.alias= -unit.1.5.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.95.name=DataPort[95] -unit.1.5.port.-1.s.95.orderindex=-1 -unit.1.5.port.-1.s.95.visible=0 -unit.1.5.port.-1.s.96.alias= -unit.1.5.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.96.name=DataPort[96] -unit.1.5.port.-1.s.96.orderindex=-1 -unit.1.5.port.-1.s.96.visible=0 -unit.1.5.port.-1.s.97.alias= -unit.1.5.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.97.name=DataPort[97] -unit.1.5.port.-1.s.97.orderindex=-1 -unit.1.5.port.-1.s.97.visible=0 -unit.1.5.port.-1.s.98.alias= -unit.1.5.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.98.name=DataPort[98] -unit.1.5.port.-1.s.98.orderindex=-1 -unit.1.5.port.-1.s.98.visible=1 -unit.1.5.port.-1.s.99.alias= -unit.1.5.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.99.name=DataPort[99] -unit.1.5.port.-1.s.99.orderindex=-1 -unit.1.5.port.-1.s.99.visible=1 -unit.1.5.port.0.b.0.alias= -unit.1.5.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.5.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.b.0.name=TriggerPort0 -unit.1.5.port.0.b.0.orderindex=-1 -unit.1.5.port.0.b.0.radix=Hex -unit.1.5.port.0.b.0.signedOffset=0.0 -unit.1.5.port.0.b.0.signedPrecision=0 -unit.1.5.port.0.b.0.signedScaleFactor=1.0 -unit.1.5.port.0.b.0.unsignedOffset=0.0 -unit.1.5.port.0.b.0.unsignedPrecision=0 -unit.1.5.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.0.b.0.visible=1 -unit.1.5.port.0.buscount=1 -unit.1.5.port.0.channelcount=8 -unit.1.5.port.0.s.0.alias= -unit.1.5.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.0.name=TriggerPort0[0] -unit.1.5.port.0.s.0.orderindex=-1 -unit.1.5.port.0.s.0.visible=1 -unit.1.5.port.0.s.1.alias= -unit.1.5.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.1.name=TriggerPort0[1] -unit.1.5.port.0.s.1.orderindex=-1 -unit.1.5.port.0.s.1.visible=1 -unit.1.5.port.0.s.2.alias= -unit.1.5.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.2.name=TriggerPort0[2] -unit.1.5.port.0.s.2.orderindex=-1 -unit.1.5.port.0.s.2.visible=1 -unit.1.5.port.0.s.3.alias= -unit.1.5.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.3.name=TriggerPort0[3] -unit.1.5.port.0.s.3.orderindex=-1 -unit.1.5.port.0.s.3.visible=1 -unit.1.5.port.0.s.4.alias= -unit.1.5.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.4.name=TriggerPort0[4] -unit.1.5.port.0.s.4.orderindex=-1 -unit.1.5.port.0.s.4.visible=1 -unit.1.5.port.0.s.5.alias= -unit.1.5.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.5.name=TriggerPort0[5] -unit.1.5.port.0.s.5.orderindex=-1 -unit.1.5.port.0.s.5.visible=1 -unit.1.5.port.0.s.6.alias= -unit.1.5.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.6.name=TriggerPort0[6] -unit.1.5.port.0.s.6.orderindex=-1 -unit.1.5.port.0.s.6.visible=1 -unit.1.5.port.0.s.7.alias= -unit.1.5.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.7.name=TriggerPort0[7] -unit.1.5.port.0.s.7.orderindex=-1 -unit.1.5.port.0.s.7.visible=1 -unit.1.5.port.1.b.0.alias= -unit.1.5.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.b.0.name=TriggerPort1 -unit.1.5.port.1.b.0.orderindex=-1 -unit.1.5.port.1.b.0.radix=Hex -unit.1.5.port.1.b.0.signedOffset=0.0 -unit.1.5.port.1.b.0.signedPrecision=0 -unit.1.5.port.1.b.0.signedScaleFactor=1.0 -unit.1.5.port.1.b.0.unsignedOffset=0.0 -unit.1.5.port.1.b.0.unsignedPrecision=0 -unit.1.5.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.1.b.0.visible=1 -unit.1.5.port.1.buscount=1 -unit.1.5.port.1.channelcount=32 -unit.1.5.port.1.s.0.alias= -unit.1.5.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.0.name=TriggerPort1[0] -unit.1.5.port.1.s.0.orderindex=-1 -unit.1.5.port.1.s.0.visible=1 -unit.1.5.port.1.s.1.alias= -unit.1.5.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.1.name=TriggerPort1[1] -unit.1.5.port.1.s.1.orderindex=-1 -unit.1.5.port.1.s.1.visible=1 -unit.1.5.port.1.s.10.alias= -unit.1.5.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.10.name=TriggerPort1[10] -unit.1.5.port.1.s.10.orderindex=-1 -unit.1.5.port.1.s.10.visible=1 -unit.1.5.port.1.s.11.alias= -unit.1.5.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.11.name=TriggerPort1[11] -unit.1.5.port.1.s.11.orderindex=-1 -unit.1.5.port.1.s.11.visible=1 -unit.1.5.port.1.s.12.alias= -unit.1.5.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.12.name=TriggerPort1[12] -unit.1.5.port.1.s.12.orderindex=-1 -unit.1.5.port.1.s.12.visible=1 -unit.1.5.port.1.s.13.alias= -unit.1.5.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.13.name=TriggerPort1[13] -unit.1.5.port.1.s.13.orderindex=-1 -unit.1.5.port.1.s.13.visible=1 -unit.1.5.port.1.s.14.alias= -unit.1.5.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.14.name=TriggerPort1[14] -unit.1.5.port.1.s.14.orderindex=-1 -unit.1.5.port.1.s.14.visible=1 -unit.1.5.port.1.s.15.alias= -unit.1.5.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.15.name=TriggerPort1[15] -unit.1.5.port.1.s.15.orderindex=-1 -unit.1.5.port.1.s.15.visible=1 -unit.1.5.port.1.s.16.alias= -unit.1.5.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.16.name=TriggerPort1[16] -unit.1.5.port.1.s.16.orderindex=-1 -unit.1.5.port.1.s.16.visible=1 -unit.1.5.port.1.s.17.alias= -unit.1.5.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.17.name=TriggerPort1[17] -unit.1.5.port.1.s.17.orderindex=-1 -unit.1.5.port.1.s.17.visible=1 -unit.1.5.port.1.s.18.alias= -unit.1.5.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.18.name=TriggerPort1[18] -unit.1.5.port.1.s.18.orderindex=-1 -unit.1.5.port.1.s.18.visible=1 -unit.1.5.port.1.s.19.alias= -unit.1.5.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.19.name=TriggerPort1[19] -unit.1.5.port.1.s.19.orderindex=-1 -unit.1.5.port.1.s.19.visible=1 -unit.1.5.port.1.s.2.alias= -unit.1.5.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.2.name=TriggerPort1[2] -unit.1.5.port.1.s.2.orderindex=-1 -unit.1.5.port.1.s.2.visible=1 -unit.1.5.port.1.s.20.alias= -unit.1.5.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.20.name=TriggerPort1[20] -unit.1.5.port.1.s.20.orderindex=-1 -unit.1.5.port.1.s.20.visible=1 -unit.1.5.port.1.s.21.alias= -unit.1.5.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.21.name=TriggerPort1[21] -unit.1.5.port.1.s.21.orderindex=-1 -unit.1.5.port.1.s.21.visible=1 -unit.1.5.port.1.s.22.alias= -unit.1.5.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.22.name=TriggerPort1[22] -unit.1.5.port.1.s.22.orderindex=-1 -unit.1.5.port.1.s.22.visible=1 -unit.1.5.port.1.s.23.alias= -unit.1.5.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.23.name=TriggerPort1[23] -unit.1.5.port.1.s.23.orderindex=-1 -unit.1.5.port.1.s.23.visible=1 -unit.1.5.port.1.s.24.alias= -unit.1.5.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.24.name=TriggerPort1[24] -unit.1.5.port.1.s.24.orderindex=-1 -unit.1.5.port.1.s.24.visible=1 -unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 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-unit.1.5.port.3.s.2.visible=1 -unit.1.5.port.3.s.20.alias= -unit.1.5.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.20.name=TriggerPort3[20] -unit.1.5.port.3.s.20.orderindex=-1 -unit.1.5.port.3.s.20.visible=1 -unit.1.5.port.3.s.21.alias= -unit.1.5.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.21.name=TriggerPort3[21] -unit.1.5.port.3.s.21.orderindex=-1 -unit.1.5.port.3.s.21.visible=1 -unit.1.5.port.3.s.22.alias= -unit.1.5.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.22.name=TriggerPort3[22] -unit.1.5.port.3.s.22.orderindex=-1 -unit.1.5.port.3.s.22.visible=1 -unit.1.5.port.3.s.23.alias= -unit.1.5.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.23.name=TriggerPort3[23] -unit.1.5.port.3.s.23.orderindex=-1 -unit.1.5.port.3.s.23.visible=1 -unit.1.5.port.3.s.24.alias= -unit.1.5.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.24.name=TriggerPort3[24] -unit.1.5.port.3.s.24.orderindex=-1 -unit.1.5.port.3.s.24.visible=1 -unit.1.5.port.3.s.25.alias= -unit.1.5.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.25.name=TriggerPort3[25] -unit.1.5.port.3.s.25.orderindex=-1 -unit.1.5.port.3.s.25.visible=1 -unit.1.5.port.3.s.26.alias= -unit.1.5.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.26.name=TriggerPort3[26] -unit.1.5.port.3.s.26.orderindex=-1 -unit.1.5.port.3.s.26.visible=1 -unit.1.5.port.3.s.27.alias= -unit.1.5.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.27.name=TriggerPort3[27] -unit.1.5.port.3.s.27.orderindex=-1 -unit.1.5.port.3.s.27.visible=1 -unit.1.5.port.3.s.28.alias= -unit.1.5.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.28.name=TriggerPort3[28] -unit.1.5.port.3.s.28.orderindex=-1 -unit.1.5.port.3.s.28.visible=1 -unit.1.5.port.3.s.29.alias= -unit.1.5.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.5.port.3.s.5.name=TriggerPort3[5] -unit.1.5.port.3.s.5.orderindex=-1 -unit.1.5.port.3.s.5.visible=1 -unit.1.5.port.3.s.6.alias= -unit.1.5.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.6.name=TriggerPort3[6] -unit.1.5.port.3.s.6.orderindex=-1 -unit.1.5.port.3.s.6.visible=1 -unit.1.5.port.3.s.7.alias= -unit.1.5.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.7.name=TriggerPort3[7] -unit.1.5.port.3.s.7.orderindex=-1 -unit.1.5.port.3.s.7.visible=1 -unit.1.5.port.3.s.8.alias= -unit.1.5.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.8.name=TriggerPort3[8] -unit.1.5.port.3.s.8.orderindex=-1 -unit.1.5.port.3.s.8.visible=1 -unit.1.5.port.3.s.9.alias= -unit.1.5.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.9.name=TriggerPort3[9] -unit.1.5.port.3.s.9.orderindex=-1 -unit.1.5.port.3.s.9.visible=1 -unit.1.5.port.4.b.0.alias= -unit.1.5.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.b.0.name=TriggerPort4 -unit.1.5.port.4.b.0.orderindex=-1 -unit.1.5.port.4.b.0.radix=Hex -unit.1.5.port.4.b.0.signedOffset=0.0 -unit.1.5.port.4.b.0.signedPrecision=0 -unit.1.5.port.4.b.0.signedScaleFactor=1.0 -unit.1.5.port.4.b.0.unsignedOffset=0.0 -unit.1.5.port.4.b.0.unsignedPrecision=0 -unit.1.5.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.4.b.0.visible=1 -unit.1.5.port.4.buscount=1 -unit.1.5.port.4.channelcount=32 -unit.1.5.port.4.s.0.alias= -unit.1.5.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.0.name=TriggerPort4[0] -unit.1.5.port.4.s.0.orderindex=-1 -unit.1.5.port.4.s.0.visible=1 -unit.1.5.port.4.s.1.alias= -unit.1.5.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.1.name=TriggerPort4[1] -unit.1.5.port.4.s.1.orderindex=-1 -unit.1.5.port.4.s.1.visible=1 -unit.1.5.port.4.s.10.alias= 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-unit.1.5.waveform.posn.18.name=DataPort[70] -unit.1.5.waveform.posn.18.type=signal -unit.1.5.waveform.posn.19.channel=71 -unit.1.5.waveform.posn.19.name=DataPort[71] -unit.1.5.waveform.posn.19.type=signal -unit.1.5.waveform.posn.2.channel=2 -unit.1.5.waveform.posn.2.name=DataPort[2] -unit.1.5.waveform.posn.2.type=signal -unit.1.5.waveform.posn.20.channel=98 -unit.1.5.waveform.posn.20.name=DataPort[98] -unit.1.5.waveform.posn.20.type=signal -unit.1.5.waveform.posn.21.channel=99 -unit.1.5.waveform.posn.21.name=DataPort[99] -unit.1.5.waveform.posn.21.type=signal -unit.1.5.waveform.posn.22.channel=100 -unit.1.5.waveform.posn.22.name=DataPort[100] -unit.1.5.waveform.posn.22.type=signal -unit.1.5.waveform.posn.23.channel=101 -unit.1.5.waveform.posn.23.name=DataPort[101] -unit.1.5.waveform.posn.23.type=signal -unit.1.5.waveform.posn.24.channel=102 -unit.1.5.waveform.posn.24.name=DataPort[102] -unit.1.5.waveform.posn.24.type=signal -unit.1.5.waveform.posn.25.channel=103 -unit.1.5.waveform.posn.25.name=DataPort[103] -unit.1.5.waveform.posn.25.type=signal -unit.1.5.waveform.posn.26.channel=130 -unit.1.5.waveform.posn.26.name=DataPort[130] -unit.1.5.waveform.posn.26.type=signal -unit.1.5.waveform.posn.27.channel=131 -unit.1.5.waveform.posn.27.name=DataPort[131] -unit.1.5.waveform.posn.27.type=signal -unit.1.5.waveform.posn.28.channel=132 -unit.1.5.waveform.posn.28.name=DataPort[132] -unit.1.5.waveform.posn.28.type=signal -unit.1.5.waveform.posn.29.channel=133 -unit.1.5.waveform.posn.29.name=DataPort[133] -unit.1.5.waveform.posn.29.type=signal -unit.1.5.waveform.posn.3.channel=3 -unit.1.5.waveform.posn.3.name=DataPort[3] -unit.1.5.waveform.posn.3.type=signal -unit.1.5.waveform.posn.30.channel=134 -unit.1.5.waveform.posn.30.name=DataPort[134] -unit.1.5.waveform.posn.30.type=signal -unit.1.5.waveform.posn.31.channel=135 -unit.1.5.waveform.posn.31.name=DataPort[135] -unit.1.5.waveform.posn.31.type=signal -unit.1.5.waveform.posn.32.channel=2147483646 -unit.1.5.waveform.posn.32.name=dsp_q_fofb -unit.1.5.waveform.posn.32.radix=3 -unit.1.5.waveform.posn.32.type=bus -unit.1.5.waveform.posn.33.channel=2147483646 -unit.1.5.waveform.posn.33.name=dsp_sum_fofb -unit.1.5.waveform.posn.33.radix=3 -unit.1.5.waveform.posn.33.type=bus -unit.1.5.waveform.posn.34.channel=2147483646 -unit.1.5.waveform.posn.34.name=dsp_x_fofb -unit.1.5.waveform.posn.34.radix=3 -unit.1.5.waveform.posn.34.type=bus -unit.1.5.waveform.posn.35.channel=2147483646 -unit.1.5.waveform.posn.35.name=dsp_y_fofb -unit.1.5.waveform.posn.35.radix=3 -unit.1.5.waveform.posn.35.type=bus -unit.1.5.waveform.posn.36.channel=2147483646 -unit.1.5.waveform.posn.36.name=dsp_y_fofb -unit.1.5.waveform.posn.36.radix=3 -unit.1.5.waveform.posn.36.type=bus -unit.1.5.waveform.posn.37.channel=2147483646 -unit.1.5.waveform.posn.37.name=dsp_y_fofb -unit.1.5.waveform.posn.37.radix=3 -unit.1.5.waveform.posn.37.type=bus -unit.1.5.waveform.posn.38.channel=2147483646 -unit.1.5.waveform.posn.38.name=dsp_y_fofb -unit.1.5.waveform.posn.38.radix=3 -unit.1.5.waveform.posn.38.type=bus -unit.1.5.waveform.posn.39.channel=2147483646 -unit.1.5.waveform.posn.39.name=dsp_y_fofb -unit.1.5.waveform.posn.39.radix=3 -unit.1.5.waveform.posn.39.type=bus -unit.1.5.waveform.posn.4.channel=4 -unit.1.5.waveform.posn.4.name=DataPort[4] -unit.1.5.waveform.posn.4.type=signal -unit.1.5.waveform.posn.40.channel=2147483646 -unit.1.5.waveform.posn.40.name=dsp_y_fofb -unit.1.5.waveform.posn.40.radix=3 -unit.1.5.waveform.posn.40.type=bus -unit.1.5.waveform.posn.41.channel=2147483646 -unit.1.5.waveform.posn.41.name=dsp_y_fofb -unit.1.5.waveform.posn.41.radix=3 -unit.1.5.waveform.posn.41.type=bus -unit.1.5.waveform.posn.42.channel=2147483646 -unit.1.5.waveform.posn.42.name=dsp_y_fofb -unit.1.5.waveform.posn.42.radix=3 -unit.1.5.waveform.posn.42.type=bus -unit.1.5.waveform.posn.43.channel=2147483646 -unit.1.5.waveform.posn.43.name=dsp_y_fofb -unit.1.5.waveform.posn.43.radix=3 -unit.1.5.waveform.posn.43.type=bus -unit.1.5.waveform.posn.44.channel=2147483646 -unit.1.5.waveform.posn.44.name=dsp_y_fofb -unit.1.5.waveform.posn.44.radix=3 -unit.1.5.waveform.posn.44.type=bus -unit.1.5.waveform.posn.45.channel=2147483646 -unit.1.5.waveform.posn.45.name=dsp_y_fofb -unit.1.5.waveform.posn.45.radix=3 -unit.1.5.waveform.posn.45.type=bus -unit.1.5.waveform.posn.46.channel=2147483646 -unit.1.5.waveform.posn.46.name=dsp_y_fofb -unit.1.5.waveform.posn.46.radix=3 -unit.1.5.waveform.posn.46.type=bus -unit.1.5.waveform.posn.5.channel=5 -unit.1.5.waveform.posn.5.name=DataPort[5] -unit.1.5.waveform.posn.5.type=signal -unit.1.5.waveform.posn.6.channel=6 -unit.1.5.waveform.posn.6.name=DataPort[6] -unit.1.5.waveform.posn.6.type=signal -unit.1.5.waveform.posn.7.channel=7 -unit.1.5.waveform.posn.7.name=DataPort[7] -unit.1.5.waveform.posn.7.type=signal -unit.1.5.waveform.posn.8.channel=34 -unit.1.5.waveform.posn.8.name=DataPort[34] -unit.1.5.waveform.posn.8.type=signal -unit.1.5.waveform.posn.9.channel=35 -unit.1.5.waveform.posn.9.name=DataPort[35] -unit.1.5.waveform.posn.9.type=signal -unit.1.6.0.HEIGHT0=0.37398374 -unit.1.6.0.TriggerRow0=1 -unit.1.6.0.TriggerRow1=1 -unit.1.6.0.TriggerRow2=1 -unit.1.6.0.WIDTH0=0.63801897 -unit.1.6.0.X0=0.069919884 -unit.1.6.0.Y0=0.0 -unit.1.6.1.HEIGHT1=0.7804878 -unit.1.6.1.WIDTH1=0.58557904 -unit.1.6.1.X1=0.024763292 -unit.1.6.1.Y1=0.068292685 -unit.1.6.5.HEIGHT5=0.7804878 -unit.1.6.5.WIDTH5=0.8550619 -unit.1.6.5.X5=0.076474875 -unit.1.6.5.Y5=0.037398376 -unit.1.6.MFBitsA0=XXXXX1XX -unit.1.6.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsB0=00000000 -unit.1.6.MFBitsB1=00000000000000000000000000000000 -unit.1.6.MFBitsB2=00000000000000000000000000000000 -unit.1.6.MFBitsB3=00000000000000000000000000000000 -unit.1.6.MFBitsB4=00000000000000000000000000000000 -unit.1.6.MFCompareA0=0 -unit.1.6.MFCompareA1=0 -unit.1.6.MFCompareA2=0 -unit.1.6.MFCompareA3=0 -unit.1.6.MFCompareA4=0 -unit.1.6.MFCompareB0=999 -unit.1.6.MFCompareB1=999 -unit.1.6.MFCompareB2=999 -unit.1.6.MFCompareB3=999 -unit.1.6.MFCompareB4=999 -unit.1.6.MFCount=5 -unit.1.6.MFDisplay0=0 -unit.1.6.MFDisplay1=0 -unit.1.6.MFDisplay2=0 -unit.1.6.MFDisplay3=0 -unit.1.6.MFDisplay4=0 -unit.1.6.MFEventType0=3 -unit.1.6.MFEventType1=3 -unit.1.6.MFEventType2=3 -unit.1.6.MFEventType3=3 -unit.1.6.MFEventType4=3 -unit.1.6.RunMode=SINGLE RUN -unit.1.6.SQCondition=M0 -unit.1.6.SQContiguous0=0 -unit.1.6.SequencerOn=0 -unit.1.6.TCActive=0 -unit.1.6.TCAdvanced0=0 -unit.1.6.TCCondition0_0=M0 -unit.1.6.TCCondition0_1= -unit.1.6.TCConditionType0=0 -unit.1.6.TCCount=1 -unit.1.6.TCEventCount0=1 -unit.1.6.TCEventType0=3 -unit.1.6.TCName0=TriggerCondition0 -unit.1.6.TCOutputEnable0=0 -unit.1.6.TCOutputHigh0=1 -unit.1.6.TCOutputMode0=0 -unit.1.6.browser_tree_state=1 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.coretype=ILA -unit.1.6.eventCount0=1 -unit.1.6.eventCount1=1 -unit.1.6.eventCount2=1 -unit.1.6.eventCount3=1 -unit.1.6.eventCount4=1 -unit.1.6.plotBusColor0=-10066177 -unit.1.6.plotBusColor1=-3355648 -unit.1.6.plotBusColor2=-16776961 -unit.1.6.plotBusColor3=-52429 -unit.1.6.plotBusCount=4 -unit.1.6.plotBusName0=dsp_q_monit -unit.1.6.plotBusName1=dsp_sum_monit -unit.1.6.plotBusName2=dsp_x_monit -unit.1.6.plotBusName3=dsp_y_monit -unit.1.6.plotBusX=dsp_q_monit -unit.1.6.plotBusY=dsp_sum_monit -unit.1.6.plotDataTimeMode=1 -unit.1.6.plotDisplayMode=line -unit.1.6.plotMaxX=0.0 -unit.1.6.plotMaxY=0.0 -unit.1.6.plotMinX=0.0 -unit.1.6.plotMinY=0.0 -unit.1.6.plotSelectedBus=0 -unit.1.6.port.-1.b.0.alias=dsp_q_monit -unit.1.6.port.-1.b.0.channellist=72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 -unit.1.6.port.-1.b.0.color=java.awt.Color[r\=102,g\=102,b\=255] -unit.1.6.port.-1.b.0.name=DataPort -unit.1.6.port.-1.b.0.orderindex=-1 -unit.1.6.port.-1.b.0.radix=Signed -unit.1.6.port.-1.b.0.signedOffset=0.0 -unit.1.6.port.-1.b.0.signedPrecision=0 -unit.1.6.port.-1.b.0.signedScaleFactor=1.0 -unit.1.6.port.-1.b.0.tokencount=0 -unit.1.6.port.-1.b.0.unsignedOffset=0.0 -unit.1.6.port.-1.b.0.unsignedPrecision=0 -unit.1.6.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.0.visible=1 -unit.1.6.port.-1.b.1.alias=dsp_sum_monit -unit.1.6.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 -unit.1.6.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.6.port.-1.b.1.name=DataPort -unit.1.6.port.-1.b.1.orderindex=-1 -unit.1.6.port.-1.b.1.radix=Signed -unit.1.6.port.-1.b.1.signedOffset=0.0 -unit.1.6.port.-1.b.1.signedPrecision=0 -unit.1.6.port.-1.b.1.signedScaleFactor=1.0 -unit.1.6.port.-1.b.1.tokencount=0 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-unit.1.6.port.-1.b.3.color=java.awt.Color[r\=255,g\=51,b\=51] -unit.1.6.port.-1.b.3.name=DataPort -unit.1.6.port.-1.b.3.orderindex=-1 -unit.1.6.port.-1.b.3.radix=Signed -unit.1.6.port.-1.b.3.signedOffset=0.0 -unit.1.6.port.-1.b.3.signedPrecision=0 -unit.1.6.port.-1.b.3.signedScaleFactor=1.0 -unit.1.6.port.-1.b.3.tokencount=0 -unit.1.6.port.-1.b.3.unsignedOffset=0.0 -unit.1.6.port.-1.b.3.unsignedPrecision=0 -unit.1.6.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.3.visible=1 -unit.1.6.port.-1.buscount=4 -unit.1.6.port.-1.channelcount=136 -unit.1.6.port.-1.s.0.alias= -unit.1.6.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.0.name=DataPort[0] -unit.1.6.port.-1.s.0.orderindex=-1 -unit.1.6.port.-1.s.0.visible=1 -unit.1.6.port.-1.s.1.alias= -unit.1.6.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.1.name=DataPort[1] -unit.1.6.port.-1.s.1.orderindex=-1 -unit.1.6.port.-1.s.1.visible=1 -unit.1.6.port.-1.s.10.alias= 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-unit.1.6.port.-1.s.108.name=DataPort[108] -unit.1.6.port.-1.s.108.orderindex=-1 -unit.1.6.port.-1.s.108.visible=0 -unit.1.6.port.-1.s.109.alias= -unit.1.6.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.109.name=DataPort[109] -unit.1.6.port.-1.s.109.orderindex=-1 -unit.1.6.port.-1.s.109.visible=0 -unit.1.6.port.-1.s.11.alias= -unit.1.6.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.11.name=DataPort[11] -unit.1.6.port.-1.s.11.orderindex=-1 -unit.1.6.port.-1.s.11.visible=0 -unit.1.6.port.-1.s.110.alias= -unit.1.6.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.110.name=DataPort[110] -unit.1.6.port.-1.s.110.orderindex=-1 -unit.1.6.port.-1.s.110.visible=0 -unit.1.6.port.-1.s.111.alias= -unit.1.6.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.111.name=DataPort[111] -unit.1.6.port.-1.s.111.orderindex=-1 -unit.1.6.port.-1.s.111.visible=0 -unit.1.6.port.-1.s.112.alias= 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-unit.1.6.port.0.s.6.orderindex=-1 -unit.1.6.port.0.s.6.visible=1 -unit.1.6.port.0.s.7.alias= -unit.1.6.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.7.name=TriggerPort0[7] -unit.1.6.port.0.s.7.orderindex=-1 -unit.1.6.port.0.s.7.visible=1 -unit.1.6.port.1.b.0.alias= -unit.1.6.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.b.0.name=TriggerPort1 -unit.1.6.port.1.b.0.orderindex=-1 -unit.1.6.port.1.b.0.radix=Hex -unit.1.6.port.1.b.0.signedOffset=0.0 -unit.1.6.port.1.b.0.signedPrecision=0 -unit.1.6.port.1.b.0.signedScaleFactor=1.0 -unit.1.6.port.1.b.0.unsignedOffset=0.0 -unit.1.6.port.1.b.0.unsignedPrecision=0 -unit.1.6.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.1.b.0.visible=1 -unit.1.6.port.1.buscount=1 -unit.1.6.port.1.channelcount=32 -unit.1.6.port.1.s.0.alias= -unit.1.6.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.0.name=TriggerPort1[0] -unit.1.6.port.1.s.0.orderindex=-1 -unit.1.6.port.1.s.0.visible=1 -unit.1.6.port.1.s.1.alias= -unit.1.6.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.1.name=TriggerPort1[1] -unit.1.6.port.1.s.1.orderindex=-1 -unit.1.6.port.1.s.1.visible=1 -unit.1.6.port.1.s.10.alias= -unit.1.6.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.10.name=TriggerPort1[10] -unit.1.6.port.1.s.10.orderindex=-1 -unit.1.6.port.1.s.10.visible=1 -unit.1.6.port.1.s.11.alias= -unit.1.6.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.11.name=TriggerPort1[11] -unit.1.6.port.1.s.11.orderindex=-1 -unit.1.6.port.1.s.11.visible=1 -unit.1.6.port.1.s.12.alias= -unit.1.6.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.12.name=TriggerPort1[12] -unit.1.6.port.1.s.12.orderindex=-1 -unit.1.6.port.1.s.12.visible=1 -unit.1.6.port.1.s.13.alias= -unit.1.6.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.13.name=TriggerPort1[13] -unit.1.6.port.1.s.13.orderindex=-1 -unit.1.6.port.1.s.13.visible=1 -unit.1.6.port.1.s.14.alias= -unit.1.6.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.14.name=TriggerPort1[14] -unit.1.6.port.1.s.14.orderindex=-1 -unit.1.6.port.1.s.14.visible=1 -unit.1.6.port.1.s.15.alias= -unit.1.6.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.15.name=TriggerPort1[15] -unit.1.6.port.1.s.15.orderindex=-1 -unit.1.6.port.1.s.15.visible=1 -unit.1.6.port.1.s.16.alias= -unit.1.6.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.16.name=TriggerPort1[16] -unit.1.6.port.1.s.16.orderindex=-1 -unit.1.6.port.1.s.16.visible=1 -unit.1.6.port.1.s.17.alias= -unit.1.6.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.17.name=TriggerPort1[17] -unit.1.6.port.1.s.17.orderindex=-1 -unit.1.6.port.1.s.17.visible=1 -unit.1.6.port.1.s.18.alias= -unit.1.6.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.18.name=TriggerPort1[18] -unit.1.6.port.1.s.18.orderindex=-1 -unit.1.6.port.1.s.18.visible=1 -unit.1.6.port.1.s.19.alias= -unit.1.6.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.19.name=TriggerPort1[19] -unit.1.6.port.1.s.19.orderindex=-1 -unit.1.6.port.1.s.19.visible=1 -unit.1.6.port.1.s.2.alias= -unit.1.6.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.2.name=TriggerPort1[2] -unit.1.6.port.1.s.2.orderindex=-1 -unit.1.6.port.1.s.2.visible=1 -unit.1.6.port.1.s.20.alias= -unit.1.6.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.20.name=TriggerPort1[20] -unit.1.6.port.1.s.20.orderindex=-1 -unit.1.6.port.1.s.20.visible=1 -unit.1.6.port.1.s.21.alias= -unit.1.6.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.21.name=TriggerPort1[21] -unit.1.6.port.1.s.21.orderindex=-1 -unit.1.6.port.1.s.21.visible=1 -unit.1.6.port.1.s.22.alias= -unit.1.6.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.22.name=TriggerPort1[22] -unit.1.6.port.1.s.22.orderindex=-1 -unit.1.6.port.1.s.22.visible=1 -unit.1.6.port.1.s.23.alias= -unit.1.6.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.23.name=TriggerPort1[23] -unit.1.6.port.1.s.23.orderindex=-1 -unit.1.6.port.1.s.23.visible=1 -unit.1.6.port.1.s.24.alias= -unit.1.6.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.24.name=TriggerPort1[24] -unit.1.6.port.1.s.24.orderindex=-1 -unit.1.6.port.1.s.24.visible=1 -unit.1.6.port.1.s.25.alias= -unit.1.6.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.25.name=TriggerPort1[25] -unit.1.6.port.1.s.25.orderindex=-1 -unit.1.6.port.1.s.25.visible=1 -unit.1.6.port.1.s.26.alias= -unit.1.6.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.26.name=TriggerPort1[26] -unit.1.6.port.1.s.26.orderindex=-1 -unit.1.6.port.1.s.26.visible=1 -unit.1.6.port.1.s.27.alias= -unit.1.6.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.27.name=TriggerPort1[27] -unit.1.6.port.1.s.27.orderindex=-1 -unit.1.6.port.1.s.27.visible=1 -unit.1.6.port.1.s.28.alias= -unit.1.6.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.28.name=TriggerPort1[28] -unit.1.6.port.1.s.28.orderindex=-1 -unit.1.6.port.1.s.28.visible=1 -unit.1.6.port.1.s.29.alias= -unit.1.6.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.29.name=TriggerPort1[29] -unit.1.6.port.1.s.29.orderindex=-1 -unit.1.6.port.1.s.29.visible=1 -unit.1.6.port.1.s.3.alias= -unit.1.6.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.3.name=TriggerPort1[3] -unit.1.6.port.1.s.3.orderindex=-1 -unit.1.6.port.1.s.3.visible=1 -unit.1.6.port.1.s.30.alias= -unit.1.6.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.30.name=TriggerPort1[30] -unit.1.6.port.1.s.30.orderindex=-1 -unit.1.6.port.1.s.30.visible=1 -unit.1.6.port.1.s.31.alias= -unit.1.6.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.31.name=TriggerPort1[31] -unit.1.6.port.1.s.31.orderindex=-1 -unit.1.6.port.1.s.31.visible=1 -unit.1.6.port.1.s.4.alias= -unit.1.6.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.4.name=TriggerPort1[4] -unit.1.6.port.1.s.4.orderindex=-1 -unit.1.6.port.1.s.4.visible=1 -unit.1.6.port.1.s.5.alias= -unit.1.6.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.5.name=TriggerPort1[5] -unit.1.6.port.1.s.5.orderindex=-1 -unit.1.6.port.1.s.5.visible=1 -unit.1.6.port.1.s.6.alias= -unit.1.6.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.6.name=TriggerPort1[6] -unit.1.6.port.1.s.6.orderindex=-1 -unit.1.6.port.1.s.6.visible=1 -unit.1.6.port.1.s.7.alias= -unit.1.6.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.7.name=TriggerPort1[7] -unit.1.6.port.1.s.7.orderindex=-1 -unit.1.6.port.1.s.7.visible=1 -unit.1.6.port.1.s.8.alias= -unit.1.6.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.8.name=TriggerPort1[8] -unit.1.6.port.1.s.8.orderindex=-1 -unit.1.6.port.1.s.8.visible=1 -unit.1.6.port.1.s.9.alias= -unit.1.6.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.9.name=TriggerPort1[9] -unit.1.6.port.1.s.9.orderindex=-1 -unit.1.6.port.1.s.9.visible=1 -unit.1.6.port.2.b.0.alias= -unit.1.6.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.b.0.name=TriggerPort2 -unit.1.6.port.2.b.0.orderindex=-1 -unit.1.6.port.2.b.0.radix=Hex -unit.1.6.port.2.b.0.signedOffset=0.0 -unit.1.6.port.2.b.0.signedPrecision=0 -unit.1.6.port.2.b.0.signedScaleFactor=1.0 -unit.1.6.port.2.b.0.unsignedOffset=0.0 -unit.1.6.port.2.b.0.unsignedPrecision=0 -unit.1.6.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.2.b.0.visible=1 -unit.1.6.port.2.buscount=1 -unit.1.6.port.2.channelcount=32 -unit.1.6.port.2.s.0.alias= -unit.1.6.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.0.name=TriggerPort2[0] -unit.1.6.port.2.s.0.orderindex=-1 -unit.1.6.port.2.s.0.visible=1 -unit.1.6.port.2.s.1.alias= -unit.1.6.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.1.name=TriggerPort2[1] -unit.1.6.port.2.s.1.orderindex=-1 -unit.1.6.port.2.s.1.visible=1 -unit.1.6.port.2.s.10.alias= -unit.1.6.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.10.name=TriggerPort2[10] -unit.1.6.port.2.s.10.orderindex=-1 -unit.1.6.port.2.s.10.visible=1 -unit.1.6.port.2.s.11.alias= -unit.1.6.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.11.name=TriggerPort2[11] -unit.1.6.port.2.s.11.orderindex=-1 -unit.1.6.port.2.s.11.visible=1 -unit.1.6.port.2.s.12.alias= -unit.1.6.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.12.name=TriggerPort2[12] -unit.1.6.port.2.s.12.orderindex=-1 -unit.1.6.port.2.s.12.visible=1 -unit.1.6.port.2.s.13.alias= -unit.1.6.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.13.name=TriggerPort2[13] -unit.1.6.port.2.s.13.orderindex=-1 -unit.1.6.port.2.s.13.visible=1 -unit.1.6.port.2.s.14.alias= -unit.1.6.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.14.name=TriggerPort2[14] -unit.1.6.port.2.s.14.orderindex=-1 -unit.1.6.port.2.s.14.visible=1 -unit.1.6.port.2.s.15.alias= -unit.1.6.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.15.name=TriggerPort2[15] -unit.1.6.port.2.s.15.orderindex=-1 -unit.1.6.port.2.s.15.visible=1 -unit.1.6.port.2.s.16.alias= -unit.1.6.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.16.name=TriggerPort2[16] -unit.1.6.port.2.s.16.orderindex=-1 -unit.1.6.port.2.s.16.visible=1 -unit.1.6.port.2.s.17.alias= -unit.1.6.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.17.name=TriggerPort2[17] -unit.1.6.port.2.s.17.orderindex=-1 -unit.1.6.port.2.s.17.visible=1 -unit.1.6.port.2.s.18.alias= -unit.1.6.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.18.name=TriggerPort2[18] -unit.1.6.port.2.s.18.orderindex=-1 -unit.1.6.port.2.s.18.visible=1 -unit.1.6.port.2.s.19.alias= -unit.1.6.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.19.name=TriggerPort2[19] -unit.1.6.port.2.s.19.orderindex=-1 -unit.1.6.port.2.s.19.visible=1 -unit.1.6.port.2.s.2.alias= -unit.1.6.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.2.name=TriggerPort2[2] -unit.1.6.port.2.s.2.orderindex=-1 -unit.1.6.port.2.s.2.visible=1 -unit.1.6.port.2.s.20.alias= -unit.1.6.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.20.name=TriggerPort2[20] -unit.1.6.port.2.s.20.orderindex=-1 -unit.1.6.port.2.s.20.visible=1 -unit.1.6.port.2.s.21.alias= -unit.1.6.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.21.name=TriggerPort2[21] -unit.1.6.port.2.s.21.orderindex=-1 -unit.1.6.port.2.s.21.visible=1 -unit.1.6.port.2.s.22.alias= -unit.1.6.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.22.name=TriggerPort2[22] -unit.1.6.port.2.s.22.orderindex=-1 -unit.1.6.port.2.s.22.visible=1 -unit.1.6.port.2.s.23.alias= -unit.1.6.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.23.name=TriggerPort2[23] -unit.1.6.port.2.s.23.orderindex=-1 -unit.1.6.port.2.s.23.visible=1 -unit.1.6.port.2.s.24.alias= -unit.1.6.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.24.name=TriggerPort2[24] -unit.1.6.port.2.s.24.orderindex=-1 -unit.1.6.port.2.s.24.visible=1 -unit.1.6.port.2.s.25.alias= -unit.1.6.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.25.name=TriggerPort2[25] -unit.1.6.port.2.s.25.orderindex=-1 -unit.1.6.port.2.s.25.visible=1 -unit.1.6.port.2.s.26.alias= -unit.1.6.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.26.name=TriggerPort2[26] -unit.1.6.port.2.s.26.orderindex=-1 -unit.1.6.port.2.s.26.visible=1 -unit.1.6.port.2.s.27.alias= -unit.1.6.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.27.name=TriggerPort2[27] -unit.1.6.port.2.s.27.orderindex=-1 -unit.1.6.port.2.s.27.visible=1 -unit.1.6.port.2.s.28.alias= -unit.1.6.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.28.name=TriggerPort2[28] -unit.1.6.port.2.s.28.orderindex=-1 -unit.1.6.port.2.s.28.visible=1 -unit.1.6.port.2.s.29.alias= -unit.1.6.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.29.name=TriggerPort2[29] -unit.1.6.port.2.s.29.orderindex=-1 -unit.1.6.port.2.s.29.visible=1 -unit.1.6.port.2.s.3.alias= -unit.1.6.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.3.name=TriggerPort2[3] -unit.1.6.port.2.s.3.orderindex=-1 -unit.1.6.port.2.s.3.visible=1 -unit.1.6.port.2.s.30.alias= -unit.1.6.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.30.name=TriggerPort2[30] -unit.1.6.port.2.s.30.orderindex=-1 -unit.1.6.port.2.s.30.visible=1 -unit.1.6.port.2.s.31.alias= -unit.1.6.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.31.name=TriggerPort2[31] -unit.1.6.port.2.s.31.orderindex=-1 -unit.1.6.port.2.s.31.visible=1 -unit.1.6.port.2.s.4.alias= -unit.1.6.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.4.name=TriggerPort2[4] -unit.1.6.port.2.s.4.orderindex=-1 -unit.1.6.port.2.s.4.visible=1 -unit.1.6.port.2.s.5.alias= -unit.1.6.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.5.name=TriggerPort2[5] -unit.1.6.port.2.s.5.orderindex=-1 -unit.1.6.port.2.s.5.visible=1 -unit.1.6.port.2.s.6.alias= -unit.1.6.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.6.name=TriggerPort2[6] -unit.1.6.port.2.s.6.orderindex=-1 -unit.1.6.port.2.s.6.visible=1 -unit.1.6.port.2.s.7.alias= -unit.1.6.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.7.name=TriggerPort2[7] -unit.1.6.port.2.s.7.orderindex=-1 -unit.1.6.port.2.s.7.visible=1 -unit.1.6.port.2.s.8.alias= -unit.1.6.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.8.name=TriggerPort2[8] -unit.1.6.port.2.s.8.orderindex=-1 -unit.1.6.port.2.s.8.visible=1 -unit.1.6.port.2.s.9.alias= -unit.1.6.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.9.name=TriggerPort2[9] -unit.1.6.port.2.s.9.orderindex=-1 -unit.1.6.port.2.s.9.visible=1 -unit.1.6.port.3.b.0.alias= -unit.1.6.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.b.0.name=TriggerPort3 -unit.1.6.port.3.b.0.orderindex=-1 -unit.1.6.port.3.b.0.radix=Hex -unit.1.6.port.3.b.0.signedOffset=0.0 -unit.1.6.port.3.b.0.signedPrecision=0 -unit.1.6.port.3.b.0.signedScaleFactor=1.0 -unit.1.6.port.3.b.0.unsignedOffset=0.0 -unit.1.6.port.3.b.0.unsignedPrecision=0 -unit.1.6.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.3.b.0.visible=1 -unit.1.6.port.3.buscount=1 -unit.1.6.port.3.channelcount=32 -unit.1.6.port.3.s.0.alias= -unit.1.6.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.0.name=TriggerPort3[0] -unit.1.6.port.3.s.0.orderindex=-1 -unit.1.6.port.3.s.0.visible=1 -unit.1.6.port.3.s.1.alias= -unit.1.6.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.1.name=TriggerPort3[1] -unit.1.6.port.3.s.1.orderindex=-1 -unit.1.6.port.3.s.1.visible=1 -unit.1.6.port.3.s.10.alias= -unit.1.6.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.10.name=TriggerPort3[10] -unit.1.6.port.3.s.10.orderindex=-1 -unit.1.6.port.3.s.10.visible=1 -unit.1.6.port.3.s.11.alias= -unit.1.6.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.11.name=TriggerPort3[11] -unit.1.6.port.3.s.11.orderindex=-1 -unit.1.6.port.3.s.11.visible=1 -unit.1.6.port.3.s.12.alias= -unit.1.6.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.12.name=TriggerPort3[12] -unit.1.6.port.3.s.12.orderindex=-1 -unit.1.6.port.3.s.12.visible=1 -unit.1.6.port.3.s.13.alias= -unit.1.6.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.13.name=TriggerPort3[13] -unit.1.6.port.3.s.13.orderindex=-1 -unit.1.6.port.3.s.13.visible=1 -unit.1.6.port.3.s.14.alias= -unit.1.6.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.14.name=TriggerPort3[14] -unit.1.6.port.3.s.14.orderindex=-1 -unit.1.6.port.3.s.14.visible=1 -unit.1.6.port.3.s.15.alias= -unit.1.6.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.15.name=TriggerPort3[15] -unit.1.6.port.3.s.15.orderindex=-1 -unit.1.6.port.3.s.15.visible=1 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-unit.1.6.port.3.s.2.visible=1 -unit.1.6.port.3.s.20.alias= -unit.1.6.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.20.name=TriggerPort3[20] -unit.1.6.port.3.s.20.orderindex=-1 -unit.1.6.port.3.s.20.visible=1 -unit.1.6.port.3.s.21.alias= -unit.1.6.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.21.name=TriggerPort3[21] -unit.1.6.port.3.s.21.orderindex=-1 -unit.1.6.port.3.s.21.visible=1 -unit.1.6.port.3.s.22.alias= -unit.1.6.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.22.name=TriggerPort3[22] -unit.1.6.port.3.s.22.orderindex=-1 -unit.1.6.port.3.s.22.visible=1 -unit.1.6.port.3.s.23.alias= -unit.1.6.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.23.name=TriggerPort3[23] -unit.1.6.port.3.s.23.orderindex=-1 -unit.1.6.port.3.s.23.visible=1 -unit.1.6.port.3.s.24.alias= -unit.1.6.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.24.name=TriggerPort3[24] -unit.1.6.port.3.s.24.orderindex=-1 -unit.1.6.port.3.s.24.visible=1 -unit.1.6.port.3.s.25.alias= -unit.1.6.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.25.name=TriggerPort3[25] -unit.1.6.port.3.s.25.orderindex=-1 -unit.1.6.port.3.s.25.visible=1 -unit.1.6.port.3.s.26.alias= -unit.1.6.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.26.name=TriggerPort3[26] -unit.1.6.port.3.s.26.orderindex=-1 -unit.1.6.port.3.s.26.visible=1 -unit.1.6.port.3.s.27.alias= -unit.1.6.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.27.name=TriggerPort3[27] -unit.1.6.port.3.s.27.orderindex=-1 -unit.1.6.port.3.s.27.visible=1 -unit.1.6.port.3.s.28.alias= -unit.1.6.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.28.name=TriggerPort3[28] -unit.1.6.port.3.s.28.orderindex=-1 -unit.1.6.port.3.s.28.visible=1 -unit.1.6.port.3.s.29.alias= -unit.1.6.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.29.name=TriggerPort3[29] -unit.1.6.port.3.s.29.orderindex=-1 -unit.1.6.port.3.s.29.visible=1 -unit.1.6.port.3.s.3.alias= -unit.1.6.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.3.name=TriggerPort3[3] -unit.1.6.port.3.s.3.orderindex=-1 -unit.1.6.port.3.s.3.visible=1 -unit.1.6.port.3.s.30.alias= -unit.1.6.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.30.name=TriggerPort3[30] -unit.1.6.port.3.s.30.orderindex=-1 -unit.1.6.port.3.s.30.visible=1 -unit.1.6.port.3.s.31.alias= -unit.1.6.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.31.name=TriggerPort3[31] -unit.1.6.port.3.s.31.orderindex=-1 -unit.1.6.port.3.s.31.visible=1 -unit.1.6.port.3.s.4.alias= -unit.1.6.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.4.name=TriggerPort3[4] -unit.1.6.port.3.s.4.orderindex=-1 -unit.1.6.port.3.s.4.visible=1 -unit.1.6.port.3.s.5.alias= -unit.1.6.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.5.name=TriggerPort3[5] -unit.1.6.port.3.s.5.orderindex=-1 -unit.1.6.port.3.s.5.visible=1 -unit.1.6.port.3.s.6.alias= -unit.1.6.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.6.name=TriggerPort3[6] -unit.1.6.port.3.s.6.orderindex=-1 -unit.1.6.port.3.s.6.visible=1 -unit.1.6.port.3.s.7.alias= -unit.1.6.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.7.name=TriggerPort3[7] -unit.1.6.port.3.s.7.orderindex=-1 -unit.1.6.port.3.s.7.visible=1 -unit.1.6.port.3.s.8.alias= -unit.1.6.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.8.name=TriggerPort3[8] -unit.1.6.port.3.s.8.orderindex=-1 -unit.1.6.port.3.s.8.visible=1 -unit.1.6.port.3.s.9.alias= -unit.1.6.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.9.name=TriggerPort3[9] -unit.1.6.port.3.s.9.orderindex=-1 -unit.1.6.port.3.s.9.visible=1 -unit.1.6.port.4.b.0.alias= -unit.1.6.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.b.0.name=TriggerPort4 -unit.1.6.port.4.b.0.orderindex=-1 -unit.1.6.port.4.b.0.radix=Hex -unit.1.6.port.4.b.0.signedOffset=0.0 -unit.1.6.port.4.b.0.signedPrecision=0 -unit.1.6.port.4.b.0.signedScaleFactor=1.0 -unit.1.6.port.4.b.0.unsignedOffset=0.0 -unit.1.6.port.4.b.0.unsignedPrecision=0 -unit.1.6.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.4.b.0.visible=1 -unit.1.6.port.4.buscount=1 -unit.1.6.port.4.channelcount=32 -unit.1.6.port.4.s.0.alias= -unit.1.6.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.0.name=TriggerPort4[0] -unit.1.6.port.4.s.0.orderindex=-1 -unit.1.6.port.4.s.0.visible=1 -unit.1.6.port.4.s.1.alias= -unit.1.6.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.1.name=TriggerPort4[1] -unit.1.6.port.4.s.1.orderindex=-1 -unit.1.6.port.4.s.1.visible=1 -unit.1.6.port.4.s.10.alias= -unit.1.6.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.10.name=TriggerPort4[10] -unit.1.6.port.4.s.10.orderindex=-1 -unit.1.6.port.4.s.10.visible=1 -unit.1.6.port.4.s.11.alias= -unit.1.6.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.11.name=TriggerPort4[11] -unit.1.6.port.4.s.11.orderindex=-1 -unit.1.6.port.4.s.11.visible=1 -unit.1.6.port.4.s.12.alias= -unit.1.6.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.12.name=TriggerPort4[12] -unit.1.6.port.4.s.12.orderindex=-1 -unit.1.6.port.4.s.12.visible=1 -unit.1.6.port.4.s.13.alias= -unit.1.6.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.13.name=TriggerPort4[13] -unit.1.6.port.4.s.13.orderindex=-1 -unit.1.6.port.4.s.13.visible=1 -unit.1.6.port.4.s.14.alias= -unit.1.6.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.14.name=TriggerPort4[14] -unit.1.6.port.4.s.14.orderindex=-1 -unit.1.6.port.4.s.14.visible=1 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-unit.1.6.waveform.posn.43.name=dsp_y_monit -unit.1.6.waveform.posn.43.radix=3 -unit.1.6.waveform.posn.43.type=bus -unit.1.6.waveform.posn.44.channel=2147483646 -unit.1.6.waveform.posn.44.name=dsp_y_monit -unit.1.6.waveform.posn.44.radix=3 -unit.1.6.waveform.posn.44.type=bus -unit.1.6.waveform.posn.45.channel=2147483646 -unit.1.6.waveform.posn.45.name=dsp_y_monit -unit.1.6.waveform.posn.45.radix=3 -unit.1.6.waveform.posn.45.type=bus -unit.1.6.waveform.posn.46.channel=2147483646 -unit.1.6.waveform.posn.46.name=dsp_y_monit -unit.1.6.waveform.posn.46.radix=3 -unit.1.6.waveform.posn.46.type=bus -unit.1.6.waveform.posn.5.channel=5 -unit.1.6.waveform.posn.5.name=DataPort[5] -unit.1.6.waveform.posn.5.type=signal -unit.1.6.waveform.posn.6.channel=6 -unit.1.6.waveform.posn.6.name=DataPort[6] -unit.1.6.waveform.posn.6.type=signal -unit.1.6.waveform.posn.7.channel=7 -unit.1.6.waveform.posn.7.name=DataPort[7] -unit.1.6.waveform.posn.7.type=signal -unit.1.6.waveform.posn.8.channel=34 -unit.1.6.waveform.posn.8.name=DataPort[34] -unit.1.6.waveform.posn.8.type=signal -unit.1.6.waveform.posn.9.channel=35 -unit.1.6.waveform.posn.9.name=DataPort[35] -unit.1.6.waveform.posn.9.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope_130m_postition_large_fofb_amp_buffers.cpj b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope_130m_postition_large_fofb_amp_buffers.cpj deleted file mode 100755 index 761d0349..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope_130m_postition_large_fofb_amp_buffers.cpj +++ /dev/null @@ -1,30261 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Wed Oct 02 16:41:20 BRT 2013 -avoidUserRegDevice1=2,3,4 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109364250093 -mdiAreaHeight=0.7057471264367816 -mdiAreaHeightLast=0.7057471264367816 -mdiCount=26 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice10=1 -mdiDevice11=1 -mdiDevice12=1 -mdiDevice13=1 -mdiDevice14=1 -mdiDevice15=1 -mdiDevice16=1 -mdiDevice17=1 -mdiDevice18=1 -mdiDevice19=1 -mdiDevice2=1 -mdiDevice20=1 -mdiDevice21=1 -mdiDevice22=1 -mdiDevice23=1 -mdiDevice24=1 -mdiDevice25=1 -mdiDevice26=1 -mdiDevice27=1 -mdiDevice28=1 -mdiDevice29=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiDevice6=1 -mdiDevice7=1 -mdiDevice8=1 -mdiDevice9=1 -mdiType0=5 -mdiType1=5 -mdiType10=0 -mdiType11=1 -mdiType12=5 -mdiType13=0 -mdiType14=1 -mdiType15=5 -mdiType16=0 -mdiType17=1 -mdiType18=5 -mdiType19=0 -mdiType2=0 -mdiType20=5 -mdiType21=0 -mdiType22=1 -mdiType23=0 -mdiType24=6 -mdiType25=6 -mdiType26=0 -mdiType27=6 -mdiType28=6 -mdiType29=6 -mdiType3=1 -mdiType4=5 -mdiType5=0 -mdiType6=1 -mdiType7=5 -mdiType8=0 -mdiType9=5 -mdiUnit0=8 -mdiUnit1=0 -mdiUnit10=4 -mdiUnit11=4 -mdiUnit12=4 -mdiUnit13=5 -mdiUnit14=5 -mdiUnit15=5 -mdiUnit16=6 -mdiUnit17=6 -mdiUnit18=6 -mdiUnit19=7 -mdiUnit2=1 -mdiUnit20=7 -mdiUnit21=8 -mdiUnit22=8 -mdiUnit23=0 -mdiUnit24=11 -mdiUnit25=12 -mdiUnit26=0 -mdiUnit27=12 -mdiUnit28=11 -mdiUnit29=12 -mdiUnit3=1 -mdiUnit4=1 -mdiUnit5=2 -mdiUnit6=2 -mdiUnit7=2 -mdiUnit8=3 -mdiUnit9=3 -navigatorHeight=0.23218390804597702 -navigatorHeightLast=0.1425287356321839 -navigatorWidth=0.15947467166979362 -navigatorWidthLast=0.09193245778611632 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.45171848 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=0.71428573 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5253683 -unit.1.0.1.WIDTH1=0.71428573 -unit.1.0.1.X1=0.0 -unit.1.0.1.Y1=0.34697217 -unit.1.0.2.HEIGHT2=0.39219016 -unit.1.0.2.WIDTH2=0.92604005 -unit.1.0.2.X2=0.07395994 -unit.1.0.2.Y2=0.55348045 -unit.1.0.5.HEIGHT5=0.9983633 -unit.1.0.5.WIDTH5=1.0744361 -unit.1.0.5.X5=0.004511278 -unit.1.0.5.Y5=0.011456628 -unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXX0XXXXXXXX -unit.1.0.MFBitsA3=XXXXXXXXXXXXXXXXXX01XXXXXXXXXXXX -unit.1.0.MFBitsB0=00000000000000000000000000000000 -unit.1.0.MFBitsB1=00000000000000000000000000000000 -unit.1.0.MFBitsB2=00000000000000000000000000000000 -unit.1.0.MFBitsB3=00000000000000000000000000000000 -unit.1.0.MFCompareA0=0 -unit.1.0.MFCompareA1=0 -unit.1.0.MFCompareA2=0 -unit.1.0.MFCompareA3=0 -unit.1.0.MFCompareB0=999 -unit.1.0.MFCompareB1=999 -unit.1.0.MFCompareB2=999 -unit.1.0.MFCompareB3=999 -unit.1.0.MFCount=4 -unit.1.0.MFDisplay0=0 -unit.1.0.MFDisplay1=0 -unit.1.0.MFDisplay2=0 -unit.1.0.MFDisplay3=0 -unit.1.0.MFEventType0=3 -unit.1.0.MFEventType1=3 -unit.1.0.MFEventType2=3 -unit.1.0.MFEventType3=3 -unit.1.0.RunMode=SINGLE RUN -unit.1.0.SQCondition=All Data -unit.1.0.SQContiguous0=0 -unit.1.0.SequencerOn=0 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-unit.1.0.export.unitName=DEV\:1 MyDevice1 (XC6VLX240T) UNIT\:0 MyILA0 (ILA) -unit.1.0.listing.count=0 -unit.1.0.plotBusColor0=-16777092 -unit.1.0.plotBusColor1=-3407821 -unit.1.0.plotBusColor10=-16777092 -unit.1.0.plotBusColor11=-16777092 -unit.1.0.plotBusColor12=-16777092 -unit.1.0.plotBusColor13=-16777092 -unit.1.0.plotBusColor14=-16777092 -unit.1.0.plotBusColor2=-6710785 -unit.1.0.plotBusColor3=-3355648 -unit.1.0.plotBusColor4=-16777092 -unit.1.0.plotBusColor5=-16777092 -unit.1.0.plotBusColor6=-16777092 -unit.1.0.plotBusColor7=-16777092 -unit.1.0.plotBusColor8=-16777092 -unit.1.0.plotBusColor9=-16777092 -unit.1.0.plotBusCount=4 -unit.1.0.plotBusName0=adc_data_ch0 -unit.1.0.plotBusName1=adc_data_ch1 -unit.1.0.plotBusName10=fmc516_debug_valid -unit.1.0.plotBusName11=fmc_adc_valid -unit.1.0.plotBusName12=fmc_lmk_lock -unit.1.0.plotBusName13=fmc_mmcm_lock -unit.1.0.plotBusName14=fmc_rst_adcs_n -unit.1.0.plotBusName2=adc_data_ch2 -unit.1.0.plotBusName3=adc_data_ch3 -unit.1.0.plotBusName4=fmc516_ch1_clk_dly -unit.1.0.plotBusName5=fmc516_ch1_clk_load -unit.1.0.plotBusName6=fmc516_ch1_data_dly -unit.1.0.plotBusName7=fmc516_ch1_data_load -unit.1.0.plotBusName8=fmc516_debug_dull -unit.1.0.plotBusName9=fmc516_debug_empty -unit.1.0.plotBusX=adc_data_ch0 -unit.1.0.plotBusY=adc_data_ch0 -unit.1.0.plotDataTimeMode=1 -unit.1.0.plotDisplayMode=line -unit.1.0.plotMaxX=0.0 -unit.1.0.plotMaxY=0.0 -unit.1.0.plotMinX=0.0 -unit.1.0.plotMinY=0.0 -unit.1.0.plotSelectedBus=f -unit.1.0.port.-1.b.0.alias=adc_data_ch0 -unit.1.0.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.1.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.0.name=DataPort -unit.1.0.port.-1.b.0.orderindex=-1 -unit.1.0.port.-1.b.0.radix=Signed -unit.1.0.port.-1.b.0.signedOffset=0.0 -unit.1.0.port.-1.b.0.signedPrecision=0 -unit.1.0.port.-1.b.0.signedScaleFactor=1.0 -unit.1.0.port.-1.b.0.tokencount=0 -unit.1.0.port.-1.b.0.unsignedOffset=0.0 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-unit.1.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.9.name=DataPort[9] -unit.1.0.port.-1.s.9.orderindex=-1 -unit.1.0.port.-1.s.9.visible=0 -unit.1.0.port.-1.s.90.alias= -unit.1.0.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.90.name=DataPort[90] -unit.1.0.port.-1.s.90.orderindex=-1 -unit.1.0.port.-1.s.90.visible=1 -unit.1.0.port.-1.s.91.alias= -unit.1.0.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.91.name=DataPort[91] -unit.1.0.port.-1.s.91.orderindex=-1 -unit.1.0.port.-1.s.91.visible=1 -unit.1.0.port.-1.s.92.alias= -unit.1.0.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.92.name=DataPort[92] -unit.1.0.port.-1.s.92.orderindex=-1 -unit.1.0.port.-1.s.92.visible=1 -unit.1.0.port.-1.s.93.alias= -unit.1.0.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.93.name=DataPort[93] -unit.1.0.port.-1.s.93.orderindex=-1 -unit.1.0.port.-1.s.93.visible=1 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-unit.1.0.port.-1.s.98.visible=1 -unit.1.0.port.-1.s.99.alias= -unit.1.0.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.99.name=DataPort[99] -unit.1.0.port.-1.s.99.orderindex=-1 -unit.1.0.port.-1.s.99.visible=1 -unit.1.0.port.0.b.0.alias= -unit.1.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.b.0.name=TriggerPort0 -unit.1.0.port.0.b.0.orderindex=-1 -unit.1.0.port.0.b.0.radix=Hex -unit.1.0.port.0.b.0.signedOffset=0.0 -unit.1.0.port.0.b.0.signedPrecision=0 -unit.1.0.port.0.b.0.signedScaleFactor=1.0 -unit.1.0.port.0.b.0.unsignedOffset=0.0 -unit.1.0.port.0.b.0.unsignedPrecision=0 -unit.1.0.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.0.b.0.visible=1 -unit.1.0.port.0.buscount=1 -unit.1.0.port.0.channelcount=32 -unit.1.0.port.0.s.0.alias= -unit.1.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= -unit.1.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.10.name=TriggerPort0[10] -unit.1.0.port.0.s.10.orderindex=-1 -unit.1.0.port.0.s.10.visible=1 -unit.1.0.port.0.s.11.alias= -unit.1.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.11.name=TriggerPort0[11] -unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= 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-unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/D\:\\home\\lerwys\\Repos\\bpm-sw\\hdl\\top\\ml_605\\dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=adc_data -unit.1.0.waveform.count=4 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=adc_data_ch3 -unit.1.0.waveform.posn.0.radix=3 -unit.1.0.waveform.posn.0.type=bus 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-unit.1.0.waveform.posn.119.name=DataPort[127] -unit.1.0.waveform.posn.119.type=signal -unit.1.0.waveform.posn.12.channel=2147483646 -unit.1.0.waveform.posn.12.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.12.radix=1 -unit.1.0.waveform.posn.12.type=bus -unit.1.0.waveform.posn.120.channel=127 -unit.1.0.waveform.posn.120.name=DataPort[127] -unit.1.0.waveform.posn.120.type=signal -unit.1.0.waveform.posn.121.channel=127 -unit.1.0.waveform.posn.121.name=DataPort[127] -unit.1.0.waveform.posn.121.type=signal -unit.1.0.waveform.posn.122.channel=127 -unit.1.0.waveform.posn.122.name=DataPort[127] -unit.1.0.waveform.posn.122.type=signal -unit.1.0.waveform.posn.123.channel=127 -unit.1.0.waveform.posn.123.name=DataP -unit.1.0.waveform.posn.13.channel=2147483646 -unit.1.0.waveform.posn.13.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.13.radix=1 -unit.1.0.waveform.posn.13.type=bus -unit.1.0.waveform.posn.2.channel=2147483646 -unit.1.0.waveform.posn.2.name=adc_data_ch1 -unit.1.0.waveform.posn.2.radix=3 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-unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.44517186 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.6789474 -unit.1.1.0.X0=0.036842104 -unit.1.1.0.Y0=0.0 -unit.1.1.1.HEIGHT1=0.85106385 -unit.1.1.1.WIDTH1=0.54661655 -unit.1.1.1.X1=0.25263157 -unit.1.1.1.Y1=0.65466446 -unit.1.1.5.HEIGHT5=1.0 -unit.1.1.5.WIDTH5=1.0 -unit.1.1.5.X5=0.0 -unit.1.1.5.Y5=0.0 -unit.1.1.MFBitsA0=1XXXXXXX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 -unit.1.1.MFBitsB2=00000000000000000000000000000000 -unit.1.1.MFBitsB3=00000000000000000000000000000000 -unit.1.1.MFBitsB4=00000000000000000000000000000000 -unit.1.1.MFCompareA0=0 -unit.1.1.MFCompareA1=0 -unit.1.1.MFCompareA2=0 -unit.1.1.MFCompareA3=0 -unit.1.1.MFCompareA4=0 -unit.1.1.MFCompareB0=999 -unit.1.1.MFCompareB1=999 -unit.1.1.MFCompareB2=999 -unit.1.1.MFCompareB3=999 -unit.1.1.MFCompareB4=999 -unit.1.1.MFCount=5 -unit.1.1.MFDisplay0=0 -unit.1.1.MFDisplay1=0 -unit.1.1.MFDisplay2=0 -unit.1.1.MFDisplay3=0 -unit.1.1.MFDisplay4=0 -unit.1.1.MFEventType0=3 -unit.1.1.MFEventType1=3 -unit.1.1.MFEventType2=3 -unit.1.1.MFEventType3=3 -unit.1.1.MFEventType4=3 -unit.1.1.RunMode=SINGLE RUN -unit.1.1.SQCondition=M0 -unit.1.1.SQContiguous0=0 -unit.1.1.SequencerOn=0 -unit.1.1.TCActive=0 -unit.1.1.TCAdvanced0=0 -unit.1.1.TCCondition0_0=M0 -unit.1.1.TCCondition0_1= -unit.1.1.TCConditionType0=0 -unit.1.1.TCCount=1 -unit.1.1.TCEventCount0=1 -unit.1.1.TCEventType0=3 -unit.1.1.TCName0=TriggerCondition0 -unit.1.1.TCOutputEnable0=0 -unit.1.1.TCOutputHigh0=1 -unit.1.1.TCOutputMode0=0 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.coretype=ILA -unit.1.1.eventCount0=1 -unit.1.1.eventCount1=1 -unit.1.1.eventCount2=1 -unit.1.1.eventCount3=1 -unit.1.1.eventCount4=1 -unit.1.1.plotBusColor0=-16777092 -unit.1.1.plotBusColor1=-3407770 -unit.1.1.plotBusColor2=-6723841 -unit.1.1.plotBusColor3=-6711040 -unit.1.1.plotBusCount=4 -unit.1.1.plotBusName0=dsp_bpf_ch0 -unit.1.1.plotBusName1=dsp_bpf_ch2 -unit.1.1.plotBusName2=dsp_mix_ch0_i -unit.1.1.plotBusName3=dsp_mix_ch2_i -unit.1.1.plotBusX=dsp_bpf_ch0 -unit.1.1.plotBusY=dsp_bpf_ch0 -unit.1.1.plotDataTimeMode=1 -unit.1.1.plotDisplayMode=line -unit.1.1.plotMaxX=0.0 -unit.1.1.plotMaxY=0.0 -unit.1.1.plotMinX=0.0 -unit.1.1.plotMinY=0.0 -unit.1.1.plotSelectedBus=c -unit.1.1.port.-1.b.0.alias=dsp_bpf_ch0 -unit.1.1.port.-1.b.0.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.b.0.name=DataPort -unit.1.1.port.-1.b.0.orderindex=-1 -unit.1.1.port.-1.b.0.radix=Signed -unit.1.1.port.-1.b.0.signedOffset=0.0 -unit.1.1.port.-1.b.0.signedPrecision=0 -unit.1.1.port.-1.b.0.signedScaleFactor=1.0 -unit.1.1.port.-1.b.0.tokencount=0 -unit.1.1.port.-1.b.0.unsignedOffset=0.0 -unit.1.1.port.-1.b.0.unsignedPrecision=0 -unit.1.1.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.0.visible=1 -unit.1.1.port.-1.b.1.alias=dsp_bpf_ch2 -unit.1.1.port.-1.b.1.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.1.port.-1.b.1.color=java.awt.Color[r\=204,g\=0,b\=102] -unit.1.1.port.-1.b.1.name=DataPort -unit.1.1.port.-1.b.1.orderindex=-1 -unit.1.1.port.-1.b.1.radix=Signed -unit.1.1.port.-1.b.1.signedOffset=0.0 -unit.1.1.port.-1.b.1.signedPrecision=0 -unit.1.1.port.-1.b.1.signedScaleFactor=1.0 -unit.1.1.port.-1.b.1.tokencount=0 -unit.1.1.port.-1.b.1.unsignedOffset=0.0 -unit.1.1.port.-1.b.1.unsignedPrecision=0 -unit.1.1.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.1.visible=1 -unit.1.1.port.-1.b.2.alias=dsp_mix_ch0_i -unit.1.1.port.-1.b.2.channellist=72 73 74 76 75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.1.port.-1.b.2.color=java.awt.Color[r\=153,g\=102,b\=255] -unit.1.1.port.-1.b.2.name=DataPort -unit.1.1.port.-1.b.2.orderindex=-1 -unit.1.1.port.-1.b.2.radix=Signed -unit.1.1.port.-1.b.2.signedOffset=0.0 -unit.1.1.port.-1.b.2.signedPrecision=0 -unit.1.1.port.-1.b.2.signedScaleFactor=1.0 -unit.1.1.port.-1.b.2.tokencount=0 -unit.1.1.port.-1.b.2.unsignedOffset=0.0 -unit.1.1.port.-1.b.2.unsignedPrecision=0 -unit.1.1.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.2.visible=1 -unit.1.1.port.-1.b.3.alias=dsp_mix_ch2_i -unit.1.1.port.-1.b.3.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 -unit.1.1.port.-1.b.3.color=java.awt.Color[r\=153,g\=153,b\=0] -unit.1.1.port.-1.b.3.name=DataPort -unit.1.1.port.-1.b.3.orderindex=-1 -unit.1.1.port.-1.b.3.radix=Signed -unit.1.1.port.-1.b.3.signedOffset=0.0 -unit.1.1.port.-1.b.3.signedPrecision=0 -unit.1.1.port.-1.b.3.signedScaleFactor=1.0 -unit.1.1.port.-1.b.3.tokencount=0 -unit.1.1.port.-1.b.3.unsignedOffset=0.0 -unit.1.1.port.-1.b.3.unsignedPrecision=0 -unit.1.1.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.3.visible=1 -unit.1.1.port.-1.buscount=4 -unit.1.1.port.-1.channelcount=136 -unit.1.1.port.-1.s.0.alias= -unit.1.1.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.0.name=DataPort[0] -unit.1.1.port.-1.s.0.orderindex=-1 -unit.1.1.port.-1.s.0.visible=1 -unit.1.1.port.-1.s.1.alias= -unit.1.1.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.1.name=DataPort[1] -unit.1.1.port.-1.s.1.orderindex=-1 -unit.1.1.port.-1.s.1.visible=1 -unit.1.1.port.-1.s.10.alias= -unit.1.1.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.10.name=DataPort[10] -unit.1.1.port.-1.s.10.orderindex=-1 -unit.1.1.port.-1.s.10.visible=0 -unit.1.1.port.-1.s.100.alias= -unit.1.1.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.100.name=DataPort[100] -unit.1.1.port.-1.s.100.orderindex=-1 -unit.1.1.port.-1.s.100.visible=1 -unit.1.1.port.-1.s.101.alias= -unit.1.1.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.101.name=DataPort[101] -unit.1.1.port.-1.s.101.orderindex=-1 -unit.1.1.port.-1.s.101.visible=1 -unit.1.1.port.-1.s.102.alias= -unit.1.1.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.102.name=DataPort[102] -unit.1.1.port.-1.s.102.orderindex=-1 -unit.1.1.port.-1.s.102.visible=1 -unit.1.1.port.-1.s.103.alias= -unit.1.1.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.103.name=DataPort[103] -unit.1.1.port.-1.s.103.orderindex=-1 -unit.1.1.port.-1.s.103.visible=1 -unit.1.1.port.-1.s.104.alias= -unit.1.1.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.104.name=DataPort[104] -unit.1.1.port.-1.s.104.orderindex=-1 -unit.1.1.port.-1.s.104.visible=0 -unit.1.1.port.-1.s.105.alias= -unit.1.1.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.105.name=DataPort[105] -unit.1.1.port.-1.s.105.orderindex=-1 -unit.1.1.port.-1.s.105.visible=0 -unit.1.1.port.-1.s.106.alias= -unit.1.1.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.106.name=DataPort[106] -unit.1.1.port.-1.s.106.orderindex=-1 -unit.1.1.port.-1.s.106.visible=0 -unit.1.1.port.-1.s.107.alias= -unit.1.1.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.107.name=DataPort[107] -unit.1.1.port.-1.s.107.orderindex=-1 -unit.1.1.port.-1.s.107.visible=0 -unit.1.1.port.-1.s.108.alias= -unit.1.1.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.108.name=DataPort[108] -unit.1.1.port.-1.s.108.orderindex=-1 -unit.1.1.port.-1.s.108.visible=0 -unit.1.1.port.-1.s.109.alias= -unit.1.1.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.109.name=DataPort[109] -unit.1.1.port.-1.s.109.orderindex=-1 -unit.1.1.port.-1.s.109.visible=0 -unit.1.1.port.-1.s.11.alias= -unit.1.1.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.11.name=DataPort[11] -unit.1.1.port.-1.s.11.orderindex=-1 -unit.1.1.port.-1.s.11.visible=0 -unit.1.1.port.-1.s.110.alias= -unit.1.1.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.110.name=DataPort[110] -unit.1.1.port.-1.s.110.orderindex=-1 -unit.1.1.port.-1.s.110.visible=0 -unit.1.1.port.-1.s.111.alias= -unit.1.1.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.111.name=DataPort[111] -unit.1.1.port.-1.s.111.orderindex=-1 -unit.1.1.port.-1.s.111.visible=0 -unit.1.1.port.-1.s.112.alias= -unit.1.1.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.112.name=DataPort[112] -unit.1.1.port.-1.s.112.orderindex=-1 -unit.1.1.port.-1.s.112.visible=0 -unit.1.1.port.-1.s.113.alias= -unit.1.1.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.113.name=DataPort[113] -unit.1.1.port.-1.s.113.orderindex=-1 -unit.1.1.port.-1.s.113.visible=0 -unit.1.1.port.-1.s.114.alias= -unit.1.1.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.114.name=DataPort[114] -unit.1.1.port.-1.s.114.orderindex=-1 -unit.1.1.port.-1.s.114.visible=0 -unit.1.1.port.-1.s.115.alias= -unit.1.1.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.115.name=DataPort[115] -unit.1.1.port.-1.s.115.orderindex=-1 -unit.1.1.port.-1.s.115.visible=0 -unit.1.1.port.-1.s.116.alias= -unit.1.1.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.116.name=DataPort[116] -unit.1.1.port.-1.s.116.orderindex=-1 -unit.1.1.port.-1.s.116.visible=0 -unit.1.1.port.-1.s.117.alias= -unit.1.1.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.117.name=DataPort[117] -unit.1.1.port.-1.s.117.orderindex=-1 -unit.1.1.port.-1.s.117.visible=0 -unit.1.1.port.-1.s.118.alias= -unit.1.1.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.118.name=DataPort[118] -unit.1.1.port.-1.s.118.orderindex=-1 -unit.1.1.port.-1.s.118.visible=0 -unit.1.1.port.-1.s.119.alias= -unit.1.1.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.119.name=DataPort[119] -unit.1.1.port.-1.s.119.orderindex=-1 -unit.1.1.port.-1.s.119.visible=0 -unit.1.1.port.-1.s.12.alias= -unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=0 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=0 -unit.1.1.port.-1.s.121.alias= -unit.1.1.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.121.name=DataPort[121] -unit.1.1.port.-1.s.121.orderindex=-1 -unit.1.1.port.-1.s.121.visible=0 -unit.1.1.port.-1.s.122.alias= -unit.1.1.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.122.name=DataPort[122] -unit.1.1.port.-1.s.122.orderindex=-1 -unit.1.1.port.-1.s.122.visible=0 -unit.1.1.port.-1.s.123.alias= -unit.1.1.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.123.name=DataPort[123] -unit.1.1.port.-1.s.123.orderindex=-1 -unit.1.1.port.-1.s.123.visible=0 -unit.1.1.port.-1.s.124.alias= -unit.1.1.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.124.name=DataPort[124] -unit.1.1.port.-1.s.124.orderindex=-1 -unit.1.1.port.-1.s.124.visible=0 -unit.1.1.port.-1.s.125.alias= -unit.1.1.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.125.name=DataPort[125] -unit.1.1.port.-1.s.125.orderindex=-1 -unit.1.1.port.-1.s.125.visible=0 -unit.1.1.port.-1.s.126.alias= -unit.1.1.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.126.name=DataPort[126] -unit.1.1.port.-1.s.126.orderindex=-1 -unit.1.1.port.-1.s.126.visible=0 -unit.1.1.port.-1.s.127.alias= -unit.1.1.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.127.name=DataPort[127] -unit.1.1.port.-1.s.127.orderindex=-1 -unit.1.1.port.-1.s.127.visible=0 -unit.1.1.port.-1.s.128.alias= -unit.1.1.port.-1.s.128.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.128.name=DataPort[128] -unit.1.1.port.-1.s.128.orderindex=-1 -unit.1.1.port.-1.s.128.visible=1 -unit.1.1.port.-1.s.129.alias= -unit.1.1.port.-1.s.129.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.129.name=DataPort[129] -unit.1.1.port.-1.s.129.orderindex=-1 -unit.1.1.port.-1.s.129.visible=1 -unit.1.1.port.-1.s.13.alias= -unit.1.1.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.13.name=DataPort[13] -unit.1.1.port.-1.s.13.orderindex=-1 -unit.1.1.port.-1.s.13.visible=0 -unit.1.1.port.-1.s.130.alias= -unit.1.1.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.130.name=DataPort[130] -unit.1.1.port.-1.s.130.orderindex=-1 -unit.1.1.port.-1.s.130.visible=1 -unit.1.1.port.-1.s.131.alias= -unit.1.1.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.131.name=DataPort[131] -unit.1.1.port.-1.s.131.orderindex=-1 -unit.1.1.port.-1.s.131.visible=1 -unit.1.1.port.-1.s.132.alias= -unit.1.1.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.132.name=DataPort[132] -unit.1.1.port.-1.s.132.orderindex=-1 -unit.1.1.port.-1.s.132.visible=1 -unit.1.1.port.-1.s.133.alias= -unit.1.1.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.133.name=DataPort[133] -unit.1.1.port.-1.s.133.orderindex=-1 -unit.1.1.port.-1.s.133.visible=1 -unit.1.1.port.-1.s.134.alias= -unit.1.1.port.-1.s.134.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.134.name=DataPort[134] -unit.1.1.port.-1.s.134.orderindex=-1 -unit.1.1.port.-1.s.134.visible=1 -unit.1.1.port.-1.s.135.alias= -unit.1.1.port.-1.s.135.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.135.name=DataPort[135] -unit.1.1.port.-1.s.135.orderindex=-1 -unit.1.1.port.-1.s.135.visible=1 -unit.1.1.port.-1.s.14.alias= -unit.1.1.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.14.name=DataPort[14] -unit.1.1.port.-1.s.14.orderindex=-1 -unit.1.1.port.-1.s.14.visible=0 -unit.1.1.port.-1.s.15.alias= -unit.1.1.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.15.name=DataPort[15] -unit.1.1.port.-1.s.15.orderindex=-1 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-unit.1.1.port.-1.s.63.orderindex=-1 -unit.1.1.port.-1.s.63.visible=0 -unit.1.1.port.-1.s.64.alias= -unit.1.1.port.-1.s.64.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.64.name=DataPort[64] -unit.1.1.port.-1.s.64.orderindex=-1 -unit.1.1.port.-1.s.64.visible=1 -unit.1.1.port.-1.s.65.alias= -unit.1.1.port.-1.s.65.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.65.name=DataPort[65] -unit.1.1.port.-1.s.65.orderindex=-1 -unit.1.1.port.-1.s.65.visible=1 -unit.1.1.port.-1.s.66.alias= -unit.1.1.port.-1.s.66.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.66.name=DataPort[66] -unit.1.1.port.-1.s.66.orderindex=-1 -unit.1.1.port.-1.s.66.visible=1 -unit.1.1.port.-1.s.67.alias= -unit.1.1.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.67.name=DataPort[67] -unit.1.1.port.-1.s.67.orderindex=-1 -unit.1.1.port.-1.s.67.visible=1 -unit.1.1.port.-1.s.68.alias= -unit.1.1.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.68.name=DataPort[68] -unit.1.1.port.-1.s.68.orderindex=-1 -unit.1.1.port.-1.s.68.visible=1 -unit.1.1.port.-1.s.69.alias= -unit.1.1.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.69.name=DataPort[69] -unit.1.1.port.-1.s.69.orderindex=-1 -unit.1.1.port.-1.s.69.visible=1 -unit.1.1.port.-1.s.7.alias= -unit.1.1.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.7.name=DataPort[7] -unit.1.1.port.-1.s.7.orderindex=-1 -unit.1.1.port.-1.s.7.visible=1 -unit.1.1.port.-1.s.70.alias= -unit.1.1.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.70.name=DataPort[70] -unit.1.1.port.-1.s.70.orderindex=-1 -unit.1.1.port.-1.s.70.visible=1 -unit.1.1.port.-1.s.71.alias= -unit.1.1.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.71.name=DataPort[71] -unit.1.1.port.-1.s.71.orderindex=-1 -unit.1.1.port.-1.s.71.visible=1 -unit.1.1.port.-1.s.72.alias= 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-unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=0 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=0 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=0 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=0 -unit.1.1.port.-1.s.94.alias= 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-unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] 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-unit.1.1.waveform.posn.38.type=signal -unit.1.1.waveform.posn.39.channel=131 -unit.1.1.waveform.posn.39.name=DataPort[131] -unit.1.1.waveform.posn.39.type=signal -unit.1.1.waveform.posn.4.channel=0 -unit.1.1.waveform.posn.4.name=DataPort[0] -unit.1.1.waveform.posn.4.type=signal -unit.1.1.waveform.posn.40.channel=132 -unit.1.1.waveform.posn.40.name=DataPort[132] -unit.1.1.waveform.posn.40.type=signal -unit.1.1.waveform.posn.41.channel=133 -unit.1.1.waveform.posn.41.name=DataPort[133] -unit.1.1.waveform.posn.41.type=signal -unit.1.1.waveform.posn.42.channel=134 -unit.1.1.waveform.posn.42.name=DataPort[134] -unit.1.1.waveform.posn.42.type=signal -unit.1.1.waveform.posn.43.channel=135 -unit.1.1.waveform.posn.43.name=DataPort[135] -unit.1.1.waveform.posn.43.type=signal -unit.1.1.waveform.posn.44.channel=7 -unit.1.1.waveform.posn.44.name=DataPort[7] -unit.1.1.waveform.posn.44.type=signal -unit.1.1.waveform.posn.45.channel=7 -unit.1.1.waveform.posn.45.name=DataPort[7] -unit.1.1.waveform.posn.45.type=signal -unit.1.1.waveform.posn.46.channel=7 -unit.1.1.waveform.posn.46.name=DataPort[7] -unit.1.1.waveform.posn.46.type=signal -unit.1.1.waveform.posn.47.channel=7 -unit.1.1.waveform.posn.47.name=DataPort[7] -unit.1.1.waveform.posn.47.type=signal -unit.1.1.waveform.posn.48.channel=7 -unit.1.1.waveform.posn.48.name=DataPort[7] -unit.1.1.waveform.posn.48.type=signal -unit.1.1.waveform.posn.49.channel=7 -unit.1.1.waveform.posn.49.name=DataPort[7] -unit.1.1.waveform.posn.49.type=signal -unit.1.1.waveform.posn.5.channel=1 -unit.1.1.waveform.posn.5.name=DataPort[1] -unit.1.1.waveform.posn.5.type=signal -unit.1.1.waveform.posn.50.channel=7 -unit.1.1.waveform.posn.50.name=DataPort[7] -unit.1.1.waveform.posn.50.type=signal -unit.1.1.waveform.posn.51.channel=7 -unit.1.1.waveform.posn.51.name=DataPort[7] -unit.1.1.waveform.posn.51.type=signal -unit.1.1.waveform.posn.52.channel=135 -unit.1.1.waveform.posn.52.name=DataPort[135] -unit.1.1.waveform.posn.52.type=signal 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-unit.1.1.waveform.posn.89.name=DataPort[127] -unit.1.1.waveform.posn.89.type=signal -unit.1.1.waveform.posn.9.channel=5 -unit.1.1.waveform.posn.9.name=DataPort[5] -unit.1.1.waveform.posn.9.radix=3 -unit.1.1.waveform.posn.9.type=signal -unit.1.1.waveform.posn.90.channel=127 -unit.1.1.waveform.posn.90.name=DataPort[127] -unit.1.1.waveform.posn.90.type=signal -unit.1.1.waveform.posn.91.channel=127 -unit.1.1.waveform.posn.91.name=DataPort[127] -unit.1.1.waveform.posn.91.type=signal -unit.1.1.waveform.posn.92.channel=127 -unit.1.1.waveform.posn.92.name=DataPort[127] -unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=127 -unit.1.1.waveform.posn.93.name=DataPort[127] -unit.1.1.waveform.posn.93.type=signal -unit.1.1.waveform.posn.94.channel=127 -unit.1.1.waveform.posn.94.name=DataPort[127] -unit.1.1.waveform.posn.94.type=signal -unit.1.1.waveform.posn.95.channel=127 -unit.1.1.waveform.posn.95.name=DataPort[127] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=127 -unit.1.1.waveform.posn.96.name=DataPort[127] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal -unit.1.10.0.HEIGHT0=0.47790506 -unit.1.10.0.TriggerRow0=1 -unit.1.10.0.TriggerRow1=1 -unit.1.10.0.TriggerRow2=1 -unit.1.10.0.WIDTH0=0.79774433 -unit.1.10.0.X0=0.20225564 -unit.1.10.0.Y0=0.0 -unit.1.10.5.HEIGHT5=1.0 -unit.1.10.5.WIDTH5=1.0 -unit.1.10.5.X5=0.0 -unit.1.10.5.Y5=0.0 -unit.1.10.MFBitsA0=1XXXXXXX -unit.1.10.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.10.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.10.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 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-unit.1.10.port.-1.s.65.name=DataPort[65] -unit.1.10.port.-1.s.65.orderindex=-1 -unit.1.10.port.-1.s.65.visible=1 -unit.1.10.port.-1.s.66.alias= -unit.1.10.port.-1.s.66.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.66.name=DataPort[66] -unit.1.10.port.-1.s.66.orderindex=-1 -unit.1.10.port.-1.s.66.visible=1 -unit.1.10.port.-1.s.67.alias= -unit.1.10.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.67.name=DataPort[67] -unit.1.10.port.-1.s.67.orderindex=-1 -unit.1.10.port.-1.s.67.visible=1 -unit.1.10.port.-1.s.68.alias= -unit.1.10.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.68.name=DataPort[68] -unit.1.10.port.-1.s.68.orderindex=-1 -unit.1.10.port.-1.s.68.visible=1 -unit.1.10.port.-1.s.69.alias= -unit.1.10.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.69.name=DataPort[69] -unit.1.10.port.-1.s.69.orderindex=-1 -unit.1.10.port.-1.s.69.visible=1 -unit.1.10.port.-1.s.7.alias= -unit.1.10.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.7.name=DataPort[7] -unit.1.10.port.-1.s.7.orderindex=-1 -unit.1.10.port.-1.s.7.visible=1 -unit.1.10.port.-1.s.70.alias= -unit.1.10.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.70.name=DataPort[70] -unit.1.10.port.-1.s.70.orderindex=-1 -unit.1.10.port.-1.s.70.visible=1 -unit.1.10.port.-1.s.71.alias= -unit.1.10.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.71.name=DataPort[71] -unit.1.10.port.-1.s.71.orderindex=-1 -unit.1.10.port.-1.s.71.visible=1 -unit.1.10.port.-1.s.72.alias= -unit.1.10.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.72.name=DataPort[72] -unit.1.10.port.-1.s.72.orderindex=-1 -unit.1.10.port.-1.s.72.visible=0 -unit.1.10.port.-1.s.73.alias= -unit.1.10.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.73.name=DataPort[73] -unit.1.10.port.-1.s.73.orderindex=-1 -unit.1.10.port.-1.s.73.visible=0 -unit.1.10.port.-1.s.74.alias= -unit.1.10.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.74.name=DataPort[74] -unit.1.10.port.-1.s.74.orderindex=-1 -unit.1.10.port.-1.s.74.visible=0 -unit.1.10.port.-1.s.75.alias= -unit.1.10.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.75.name=DataPort[75] -unit.1.10.port.-1.s.75.orderindex=-1 -unit.1.10.port.-1.s.75.visible=0 -unit.1.10.port.-1.s.76.alias= -unit.1.10.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.76.name=DataPort[76] -unit.1.10.port.-1.s.76.orderindex=-1 -unit.1.10.port.-1.s.76.visible=0 -unit.1.10.port.-1.s.77.alias= -unit.1.10.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.77.name=DataPort[77] -unit.1.10.port.-1.s.77.orderindex=-1 -unit.1.10.port.-1.s.77.visible=0 -unit.1.10.port.-1.s.78.alias= -unit.1.10.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.78.name=DataPort[78] -unit.1.10.port.-1.s.78.orderindex=-1 -unit.1.10.port.-1.s.78.visible=0 -unit.1.10.port.-1.s.79.alias= -unit.1.10.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.79.name=DataPort[79] -unit.1.10.port.-1.s.79.orderindex=-1 -unit.1.10.port.-1.s.79.visible=0 -unit.1.10.port.-1.s.8.alias= -unit.1.10.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.8.name=DataPort[8] -unit.1.10.port.-1.s.8.orderindex=-1 -unit.1.10.port.-1.s.8.visible=0 -unit.1.10.port.-1.s.80.alias= -unit.1.10.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.80.name=DataPort[80] -unit.1.10.port.-1.s.80.orderindex=-1 -unit.1.10.port.-1.s.80.visible=0 -unit.1.10.port.-1.s.81.alias= -unit.1.10.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.81.name=DataPort[81] -unit.1.10.port.-1.s.81.orderindex=-1 -unit.1.10.port.-1.s.81.visible=0 -unit.1.10.port.-1.s.82.alias= -unit.1.10.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.82.name=DataPort[82] -unit.1.10.port.-1.s.82.orderindex=-1 -unit.1.10.port.-1.s.82.visible=0 -unit.1.10.port.-1.s.83.alias= -unit.1.10.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.83.name=DataPort[83] -unit.1.10.port.-1.s.83.orderindex=-1 -unit.1.10.port.-1.s.83.visible=0 -unit.1.10.port.-1.s.84.alias= -unit.1.10.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.84.name=DataPort[84] -unit.1.10.port.-1.s.84.orderindex=-1 -unit.1.10.port.-1.s.84.visible=0 -unit.1.10.port.-1.s.85.alias= -unit.1.10.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.85.name=DataPort[85] -unit.1.10.port.-1.s.85.orderindex=-1 -unit.1.10.port.-1.s.85.visible=0 -unit.1.10.port.-1.s.86.alias= -unit.1.10.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.86.name=DataPort[86] -unit.1.10.port.-1.s.86.orderindex=-1 -unit.1.10.port.-1.s.86.visible=0 -unit.1.10.port.-1.s.87.alias= -unit.1.10.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.87.name=DataPort[87] -unit.1.10.port.-1.s.87.orderindex=-1 -unit.1.10.port.-1.s.87.visible=0 -unit.1.10.port.-1.s.88.alias= -unit.1.10.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.88.name=DataPort[88] -unit.1.10.port.-1.s.88.orderindex=-1 -unit.1.10.port.-1.s.88.visible=0 -unit.1.10.port.-1.s.89.alias= -unit.1.10.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.89.name=DataPort[89] -unit.1.10.port.-1.s.89.orderindex=-1 -unit.1.10.port.-1.s.89.visible=0 -unit.1.10.port.-1.s.9.alias= -unit.1.10.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.9.name=DataPort[9] -unit.1.10.port.-1.s.9.orderindex=-1 -unit.1.10.port.-1.s.9.visible=0 -unit.1.10.port.-1.s.90.alias= -unit.1.10.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.90.name=DataPort[90] -unit.1.10.port.-1.s.90.orderindex=-1 -unit.1.10.port.-1.s.90.visible=0 -unit.1.10.port.-1.s.91.alias= -unit.1.10.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.91.name=DataPort[91] -unit.1.10.port.-1.s.91.orderindex=-1 -unit.1.10.port.-1.s.91.visible=0 -unit.1.10.port.-1.s.92.alias= -unit.1.10.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.92.name=DataPort[92] -unit.1.10.port.-1.s.92.orderindex=-1 -unit.1.10.port.-1.s.92.visible=0 -unit.1.10.port.-1.s.93.alias= -unit.1.10.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.93.name=DataPort[93] -unit.1.10.port.-1.s.93.orderindex=-1 -unit.1.10.port.-1.s.93.visible=0 -unit.1.10.port.-1.s.94.alias= -unit.1.10.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.94.name=DataPort[94] -unit.1.10.port.-1.s.94.orderindex=-1 -unit.1.10.port.-1.s.94.visible=0 -unit.1.10.port.-1.s.95.alias= -unit.1.10.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.95.name=DataPort[95] -unit.1.10.port.-1.s.95.orderindex=-1 -unit.1.10.port.-1.s.95.visible=0 -unit.1.10.port.-1.s.96.alias= -unit.1.10.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.96.name=DataPort[96] -unit.1.10.port.-1.s.96.orderindex=-1 -unit.1.10.port.-1.s.96.visible=1 -unit.1.10.port.-1.s.97.alias= -unit.1.10.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.97.name=DataPort[97] -unit.1.10.port.-1.s.97.orderindex=-1 -unit.1.10.port.-1.s.97.visible=1 -unit.1.10.port.-1.s.98.alias= -unit.1.10.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.98.name=DataPort[98] -unit.1.10.port.-1.s.98.orderindex=-1 -unit.1.10.port.-1.s.98.visible=1 -unit.1.10.port.-1.s.99.alias= -unit.1.10.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.-1.s.99.name=DataPort[99] -unit.1.10.port.-1.s.99.orderindex=-1 -unit.1.10.port.-1.s.99.visible=1 -unit.1.10.port.0.b.0.alias= -unit.1.10.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.10.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.b.0.name=TriggerPort0 -unit.1.10.port.0.b.0.orderindex=-1 -unit.1.10.port.0.b.0.radix=Hex -unit.1.10.port.0.b.0.signedOffset=0.0 -unit.1.10.port.0.b.0.signedPrecision=0 -unit.1.10.port.0.b.0.signedScaleFactor=1.0 -unit.1.10.port.0.b.0.unsignedOffset=0.0 -unit.1.10.port.0.b.0.unsignedPrecision=0 -unit.1.10.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.0.b.0.visible=1 -unit.1.10.port.0.buscount=1 -unit.1.10.port.0.channelcount=8 -unit.1.10.port.0.s.0.alias= -unit.1.10.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.0.name=TriggerPort0[0] -unit.1.10.port.0.s.0.orderindex=-1 -unit.1.10.port.0.s.0.visible=1 -unit.1.10.port.0.s.1.alias= -unit.1.10.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.1.name=TriggerPort0[1] -unit.1.10.port.0.s.1.orderindex=-1 -unit.1.10.port.0.s.1.visible=1 -unit.1.10.port.0.s.2.alias= -unit.1.10.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.2.name=TriggerPort0[2] -unit.1.10.port.0.s.2.orderindex=-1 -unit.1.10.port.0.s.2.visible=1 -unit.1.10.port.0.s.3.alias= -unit.1.10.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.3.name=TriggerPort0[3] -unit.1.10.port.0.s.3.orderindex=-1 -unit.1.10.port.0.s.3.visible=1 -unit.1.10.port.0.s.4.alias= -unit.1.10.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.4.name=TriggerPort0[4] -unit.1.10.port.0.s.4.orderindex=-1 -unit.1.10.port.0.s.4.visible=1 -unit.1.10.port.0.s.5.alias= -unit.1.10.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.5.name=TriggerPort0[5] -unit.1.10.port.0.s.5.orderindex=-1 -unit.1.10.port.0.s.5.visible=1 -unit.1.10.port.0.s.6.alias= -unit.1.10.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.6.name=TriggerPort0[6] -unit.1.10.port.0.s.6.orderindex=-1 -unit.1.10.port.0.s.6.visible=1 -unit.1.10.port.0.s.7.alias= -unit.1.10.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.7.name=TriggerPort0[7] -unit.1.10.port.0.s.7.orderindex=-1 -unit.1.10.port.0.s.7.visible=1 -unit.1.10.port.1.b.0.alias= -unit.1.10.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.b.0.name=TriggerPort1 -unit.1.10.port.1.b.0.orderindex=-1 -unit.1.10.port.1.b.0.radix=Hex -unit.1.10.port.1.b.0.signedOffset=0.0 -unit.1.10.port.1.b.0.signedPrecision=0 -unit.1.10.port.1.b.0.signedScaleFactor=1.0 -unit.1.10.port.1.b.0.unsignedOffset=0.0 -unit.1.10.port.1.b.0.unsignedPrecision=0 -unit.1.10.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.1.b.0.visible=1 -unit.1.10.port.1.buscount=1 -unit.1.10.port.1.channelcount=32 -unit.1.10.port.1.s.0.alias= -unit.1.10.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.0.name=TriggerPort1[0] -unit.1.10.port.1.s.0.orderindex=-1 -unit.1.10.port.1.s.0.visible=1 -unit.1.10.port.1.s.1.alias= -unit.1.10.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.1.name=TriggerPort1[1] -unit.1.10.port.1.s.1.orderindex=-1 -unit.1.10.port.1.s.1.visible=1 -unit.1.10.port.1.s.10.alias= -unit.1.10.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.10.name=TriggerPort1[10] -unit.1.10.port.1.s.10.orderindex=-1 -unit.1.10.port.1.s.10.visible=1 -unit.1.10.port.1.s.11.alias= -unit.1.10.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.11.name=TriggerPort1[11] -unit.1.10.port.1.s.11.orderindex=-1 -unit.1.10.port.1.s.11.visible=1 -unit.1.10.port.1.s.12.alias= -unit.1.10.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.12.name=TriggerPort1[12] -unit.1.10.port.1.s.12.orderindex=-1 -unit.1.10.port.1.s.12.visible=1 -unit.1.10.port.1.s.13.alias= -unit.1.10.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.13.name=TriggerPort1[13] -unit.1.10.port.1.s.13.orderindex=-1 -unit.1.10.port.1.s.13.visible=1 -unit.1.10.port.1.s.14.alias= -unit.1.10.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.14.name=TriggerPort1[14] -unit.1.10.port.1.s.14.orderindex=-1 -unit.1.10.port.1.s.14.visible=1 -unit.1.10.port.1.s.15.alias= -unit.1.10.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.15.name=TriggerPort1[15] -unit.1.10.port.1.s.15.orderindex=-1 -unit.1.10.port.1.s.15.visible=1 -unit.1.10.port.1.s.16.alias= -unit.1.10.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.16.name=TriggerPort1[16] -unit.1.10.port.1.s.16.orderindex=-1 -unit.1.10.port.1.s.16.visible=1 -unit.1.10.port.1.s.17.alias= -unit.1.10.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.17.name=TriggerPort1[17] -unit.1.10.port.1.s.17.orderindex=-1 -unit.1.10.port.1.s.17.visible=1 -unit.1.10.port.1.s.18.alias= -unit.1.10.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.18.name=TriggerPort1[18] -unit.1.10.port.1.s.18.orderindex=-1 -unit.1.10.port.1.s.18.visible=1 -unit.1.10.port.1.s.19.alias= -unit.1.10.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.19.name=TriggerPort1[19] -unit.1.10.port.1.s.19.orderindex=-1 -unit.1.10.port.1.s.19.visible=1 -unit.1.10.port.1.s.2.alias= -unit.1.10.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.2.name=TriggerPort1[2] -unit.1.10.port.1.s.2.orderindex=-1 -unit.1.10.port.1.s.2.visible=1 -unit.1.10.port.1.s.20.alias= -unit.1.10.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.20.name=TriggerPort1[20] -unit.1.10.port.1.s.20.orderindex=-1 -unit.1.10.port.1.s.20.visible=1 -unit.1.10.port.1.s.21.alias= -unit.1.10.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.21.name=TriggerPort1[21] -unit.1.10.port.1.s.21.orderindex=-1 -unit.1.10.port.1.s.21.visible=1 -unit.1.10.port.1.s.22.alias= -unit.1.10.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.22.name=TriggerPort1[22] -unit.1.10.port.1.s.22.orderindex=-1 -unit.1.10.port.1.s.22.visible=1 -unit.1.10.port.1.s.23.alias= -unit.1.10.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.23.name=TriggerPort1[23] -unit.1.10.port.1.s.23.orderindex=-1 -unit.1.10.port.1.s.23.visible=1 -unit.1.10.port.1.s.24.alias= -unit.1.10.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.24.name=TriggerPort1[24] -unit.1.10.port.1.s.24.orderindex=-1 -unit.1.10.port.1.s.24.visible=1 -unit.1.10.port.1.s.25.alias= -unit.1.10.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.25.name=TriggerPort1[25] -unit.1.10.port.1.s.25.orderindex=-1 -unit.1.10.port.1.s.25.visible=1 -unit.1.10.port.1.s.26.alias= -unit.1.10.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.26.name=TriggerPort1[26] -unit.1.10.port.1.s.26.orderindex=-1 -unit.1.10.port.1.s.26.visible=1 -unit.1.10.port.1.s.27.alias= -unit.1.10.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.27.name=TriggerPort1[27] -unit.1.10.port.1.s.27.orderindex=-1 -unit.1.10.port.1.s.27.visible=1 -unit.1.10.port.1.s.28.alias= -unit.1.10.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.28.name=TriggerPort1[28] -unit.1.10.port.1.s.28.orderindex=-1 -unit.1.10.port.1.s.28.visible=1 -unit.1.10.port.1.s.29.alias= -unit.1.10.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.29.name=TriggerPort1[29] -unit.1.10.port.1.s.29.orderindex=-1 -unit.1.10.port.1.s.29.visible=1 -unit.1.10.port.1.s.3.alias= -unit.1.10.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.3.name=TriggerPort1[3] -unit.1.10.port.1.s.3.orderindex=-1 -unit.1.10.port.1.s.3.visible=1 -unit.1.10.port.1.s.30.alias= -unit.1.10.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.30.name=TriggerPort1[30] -unit.1.10.port.1.s.30.orderindex=-1 -unit.1.10.port.1.s.30.visible=1 -unit.1.10.port.1.s.31.alias= -unit.1.10.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.31.name=TriggerPort1[31] -unit.1.10.port.1.s.31.orderindex=-1 -unit.1.10.port.1.s.31.visible=1 -unit.1.10.port.1.s.4.alias= -unit.1.10.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.4.name=TriggerPort1[4] -unit.1.10.port.1.s.4.orderindex=-1 -unit.1.10.port.1.s.4.visible=1 -unit.1.10.port.1.s.5.alias= -unit.1.10.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.5.name=TriggerPort1[5] -unit.1.10.port.1.s.5.orderindex=-1 -unit.1.10.port.1.s.5.visible=1 -unit.1.10.port.1.s.6.alias= -unit.1.10.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.6.name=TriggerPort1[6] -unit.1.10.port.1.s.6.orderindex=-1 -unit.1.10.port.1.s.6.visible=1 -unit.1.10.port.1.s.7.alias= -unit.1.10.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.7.name=TriggerPort1[7] -unit.1.10.port.1.s.7.orderindex=-1 -unit.1.10.port.1.s.7.visible=1 -unit.1.10.port.1.s.8.alias= -unit.1.10.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.8.name=TriggerPort1[8] -unit.1.10.port.1.s.8.orderindex=-1 -unit.1.10.port.1.s.8.visible=1 -unit.1.10.port.1.s.9.alias= -unit.1.10.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.9.name=TriggerPort1[9] -unit.1.10.port.1.s.9.orderindex=-1 -unit.1.10.port.1.s.9.visible=1 -unit.1.10.port.2.b.0.alias= -unit.1.10.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.b.0.name=TriggerPort2 -unit.1.10.port.2.b.0.orderindex=-1 -unit.1.10.port.2.b.0.radix=Hex -unit.1.10.port.2.b.0.signedOffset=0.0 -unit.1.10.port.2.b.0.signedPrecision=0 -unit.1.10.port.2.b.0.signedScaleFactor=1.0 -unit.1.10.port.2.b.0.unsignedOffset=0.0 -unit.1.10.port.2.b.0.unsignedPrecision=0 -unit.1.10.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.2.b.0.visible=1 -unit.1.10.port.2.buscount=1 -unit.1.10.port.2.channelcount=32 -unit.1.10.port.2.s.0.alias= -unit.1.10.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.0.name=TriggerPort2[0] -unit.1.10.port.2.s.0.orderindex=-1 -unit.1.10.port.2.s.0.visible=1 -unit.1.10.port.2.s.1.alias= -unit.1.10.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.1.name=TriggerPort2[1] -unit.1.10.port.2.s.1.orderindex=-1 -unit.1.10.port.2.s.1.visible=1 -unit.1.10.port.2.s.10.alias= -unit.1.10.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.10.name=TriggerPort2[10] -unit.1.10.port.2.s.10.orderindex=-1 -unit.1.10.port.2.s.10.visible=1 -unit.1.10.port.2.s.11.alias= -unit.1.10.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.11.name=TriggerPort2[11] -unit.1.10.port.2.s.11.orderindex=-1 -unit.1.10.port.2.s.11.visible=1 -unit.1.10.port.2.s.12.alias= -unit.1.10.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.12.name=TriggerPort2[12] -unit.1.10.port.2.s.12.orderindex=-1 -unit.1.10.port.2.s.12.visible=1 -unit.1.10.port.2.s.13.alias= -unit.1.10.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.13.name=TriggerPort2[13] -unit.1.10.port.2.s.13.orderindex=-1 -unit.1.10.port.2.s.13.visible=1 -unit.1.10.port.2.s.14.alias= -unit.1.10.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.14.name=TriggerPort2[14] -unit.1.10.port.2.s.14.orderindex=-1 -unit.1.10.port.2.s.14.visible=1 -unit.1.10.port.2.s.15.alias= -unit.1.10.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.15.name=TriggerPort2[15] -unit.1.10.port.2.s.15.orderindex=-1 -unit.1.10.port.2.s.15.visible=1 -unit.1.10.port.2.s.16.alias= -unit.1.10.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.16.name=TriggerPort2[16] -unit.1.10.port.2.s.16.orderindex=-1 -unit.1.10.port.2.s.16.visible=1 -unit.1.10.port.2.s.17.alias= -unit.1.10.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.17.name=TriggerPort2[17] -unit.1.10.port.2.s.17.orderindex=-1 -unit.1.10.port.2.s.17.visible=1 -unit.1.10.port.2.s.18.alias= -unit.1.10.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.18.name=TriggerPort2[18] -unit.1.10.port.2.s.18.orderindex=-1 -unit.1.10.port.2.s.18.visible=1 -unit.1.10.port.2.s.19.alias= -unit.1.10.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.19.name=TriggerPort2[19] -unit.1.10.port.2.s.19.orderindex=-1 -unit.1.10.port.2.s.19.visible=1 -unit.1.10.port.2.s.2.alias= -unit.1.10.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.2.name=TriggerPort2[2] -unit.1.10.port.2.s.2.orderindex=-1 -unit.1.10.port.2.s.2.visible=1 -unit.1.10.port.2.s.20.alias= -unit.1.10.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.20.name=TriggerPort2[20] -unit.1.10.port.2.s.20.orderindex=-1 -unit.1.10.port.2.s.20.visible=1 -unit.1.10.port.2.s.21.alias= -unit.1.10.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.21.name=TriggerPort2[21] -unit.1.10.port.2.s.21.orderindex=-1 -unit.1.10.port.2.s.21.visible=1 -unit.1.10.port.2.s.22.alias= -unit.1.10.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.22.name=TriggerPort2[22] -unit.1.10.port.2.s.22.orderindex=-1 -unit.1.10.port.2.s.22.visible=1 -unit.1.10.port.2.s.23.alias= -unit.1.10.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.23.name=TriggerPort2[23] -unit.1.10.port.2.s.23.orderindex=-1 -unit.1.10.port.2.s.23.visible=1 -unit.1.10.port.2.s.24.alias= -unit.1.10.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.24.name=TriggerPort2[24] -unit.1.10.port.2.s.24.orderindex=-1 -unit.1.10.port.2.s.24.visible=1 -unit.1.10.port.2.s.25.alias= -unit.1.10.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.25.name=TriggerPort2[25] -unit.1.10.port.2.s.25.orderindex=-1 -unit.1.10.port.2.s.25.visible=1 -unit.1.10.port.2.s.26.alias= -unit.1.10.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.26.name=TriggerPort2[26] -unit.1.10.port.2.s.26.orderindex=-1 -unit.1.10.port.2.s.26.visible=1 -unit.1.10.port.2.s.27.alias= -unit.1.10.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.27.name=TriggerPort2[27] -unit.1.10.port.2.s.27.orderindex=-1 -unit.1.10.port.2.s.27.visible=1 -unit.1.10.port.2.s.28.alias= -unit.1.10.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.28.name=TriggerPort2[28] -unit.1.10.port.2.s.28.orderindex=-1 -unit.1.10.port.2.s.28.visible=1 -unit.1.10.port.2.s.29.alias= -unit.1.10.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.29.name=TriggerPort2[29] -unit.1.10.port.2.s.29.orderindex=-1 -unit.1.10.port.2.s.29.visible=1 -unit.1.10.port.2.s.3.alias= -unit.1.10.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.3.name=TriggerPort2[3] -unit.1.10.port.2.s.3.orderindex=-1 -unit.1.10.port.2.s.3.visible=1 -unit.1.10.port.2.s.30.alias= -unit.1.10.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.30.name=TriggerPort2[30] -unit.1.10.port.2.s.30.orderindex=-1 -unit.1.10.port.2.s.30.visible=1 -unit.1.10.port.2.s.31.alias= -unit.1.10.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.31.name=TriggerPort2[31] -unit.1.10.port.2.s.31.orderindex=-1 -unit.1.10.port.2.s.31.visible=1 -unit.1.10.port.2.s.4.alias= -unit.1.10.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.4.name=TriggerPort2[4] -unit.1.10.port.2.s.4.orderindex=-1 -unit.1.10.port.2.s.4.visible=1 -unit.1.10.port.2.s.5.alias= -unit.1.10.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.5.name=TriggerPort2[5] -unit.1.10.port.2.s.5.orderindex=-1 -unit.1.10.port.2.s.5.visible=1 -unit.1.10.port.2.s.6.alias= -unit.1.10.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.6.name=TriggerPort2[6] -unit.1.10.port.2.s.6.orderindex=-1 -unit.1.10.port.2.s.6.visible=1 -unit.1.10.port.2.s.7.alias= -unit.1.10.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.7.name=TriggerPort2[7] -unit.1.10.port.2.s.7.orderindex=-1 -unit.1.10.port.2.s.7.visible=1 -unit.1.10.port.2.s.8.alias= -unit.1.10.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.8.name=TriggerPort2[8] -unit.1.10.port.2.s.8.orderindex=-1 -unit.1.10.port.2.s.8.visible=1 -unit.1.10.port.2.s.9.alias= -unit.1.10.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.9.name=TriggerPort2[9] -unit.1.10.port.2.s.9.orderindex=-1 -unit.1.10.port.2.s.9.visible=1 -unit.1.10.port.3.b.0.alias= -unit.1.10.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.b.0.name=TriggerPort3 -unit.1.10.port.3.b.0.orderindex=-1 -unit.1.10.port.3.b.0.radix=Hex -unit.1.10.port.3.b.0.signedOffset=0.0 -unit.1.10.port.3.b.0.signedPrecision=0 -unit.1.10.port.3.b.0.signedScaleFactor=1.0 -unit.1.10.port.3.b.0.unsignedOffset=0.0 -unit.1.10.port.3.b.0.unsignedPrecision=0 -unit.1.10.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.3.b.0.visible=1 -unit.1.10.port.3.buscount=1 -unit.1.10.port.3.channelcount=32 -unit.1.10.port.3.s.0.alias= -unit.1.10.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.0.name=TriggerPort3[0] -unit.1.10.port.3.s.0.orderindex=-1 -unit.1.10.port.3.s.0.visible=1 -unit.1.10.port.3.s.1.alias= -unit.1.10.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.1.name=TriggerPort3[1] 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-unit.1.11.vio.posn.226.channel=255 -unit.1.11.vio.posn.226.name=AsyncOut[255] -unit.1.11.vio.posn.226.port=1 -unit.1.11.vio.posn.226.type=signal -unit.1.11.vio.posn.227.channel=255 -unit.1.11.vio.posn.227.name=AsyncOut[255] -unit.1.11.vio.posn.227.port=1 -unit.1.11.vio.posn.227.type=signal -unit.1.11.vio.posn.228.channel=255 -unit.1.11.vio.posn.228.name=AsyncOut[255] -unit.1.11.vio.posn.228.port=1 -unit.1.11.vio.posn.228.type=signal -unit.1.11.vio.posn.229.channel=255 -unit.1.11.vio.posn.229.name=AsyncOut[255] -unit.1.11.vio.posn.229.port=1 -unit.1.11.vio.posn.229.type=signal -unit.1.11.vio.posn.23.channel=2147483646 -unit.1.11.vio.posn.23.name=un_cross_gain_db -unit.1.11.vio.posn.23.port=1 -unit.1.11.vio.posn.23.radix=1 -unit.1.11.vio.posn.23.type=bus -unit.1.11.vio.posn.230.channel=255 -unit.1.11.vio.posn.230.name=AsyncOut[255] -unit.1.11.vio.posn.230.port=1 -unit.1.11.vio.posn.230.type=signal -unit.1.11.vio.posn.231.channel=255 -unit.1.11.vio.posn.231.name=AsyncOut[255] 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-unit.1.11.vio.posn.238.name=AsyncOut[255] -unit.1.11.vio.posn.238.port=1 -unit.1.11.vio.posn.238.type=signal -unit.1.11.vio.posn.239.channel=255 -unit.1.11.vio.posn.239.name=AsyncOut[255] -unit.1.11.vio.posn.239.port=1 -unit.1.11.vio.posn.239.type=signal -unit.1.11.vio.posn.24.channel=2147483646 -unit.1.11.vio.posn.24.name=un_cross_gain_db -unit.1.11.vio.posn.24.port=1 -unit.1.11.vio.posn.24.radix=1 -unit.1.11.vio.posn.24.type=bus -unit.1.11.vio.posn.240.channel=255 -unit.1.11.vio.posn.240.name=AsyncOut[255] -unit.1.11.vio.posn.240.port=1 -unit.1.11.vio.posn.240.type=signal -unit.1.11.vio.posn.241.channel=255 -unit.1.11.vio.posn.241.name=AsyncOut[255] -unit.1.11.vio.posn.241.port=1 -unit.1.11.vio.posn.241.type=signal -unit.1.11.vio.posn.242.channel=255 -unit.1.11.vio.posn.242.name=AsyncOut[255] -unit.1.11.vio.posn.242.port=1 -unit.1.11.vio.posn.242.type=signal -unit.1.11.vio.posn.243.channel=255 -unit.1.11.vio.posn.243.name=AsyncOut[255] -unit.1.11.vio.posn.243.port=1 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-unit.1.11.vio.posn.26.channel=2147483646 -unit.1.11.vio.posn.26.name=un_cross_gain_db -unit.1.11.vio.posn.26.port=1 -unit.1.11.vio.posn.26.radix=1 -unit.1.11.vio.posn.26.type=bus -unit.1.11.vio.posn.27.channel=2147483646 -unit.1.11.vio.posn.27.name=un_cross_gain_db -unit.1.11.vio.posn.27.port=1 -unit.1.11.vio.posn.27.radix=1 -unit.1.11.vio.posn.27.type=bus -unit.1.11.vio.posn.28.channel=2147483646 -unit.1.11.vio.posn.28.name=un_cross_gain_db -unit.1.11.vio.posn.28.port=1 -unit.1.11.vio.posn.28.radix=1 -unit.1.11.vio.posn.28.type=bus -unit.1.11.vio.posn.29.channel=2147483646 -unit.1.11.vio.posn.29.name=un_cross_gain_db -unit.1.11.vio.posn.29.port=1 -unit.1.11.vio.posn.29.radix=1 -unit.1.11.vio.posn.29.type=bus -unit.1.11.vio.posn.3.channel=2147483646 -unit.1.11.vio.posn.3.name=dds_sine_gain_ch2 -unit.1.11.vio.posn.3.port=1 -unit.1.11.vio.posn.3.radix=1 -unit.1.11.vio.posn.3.type=bus -unit.1.11.vio.posn.30.channel=2147483646 -unit.1.11.vio.posn.30.name=un_cross_gain_db -unit.1.11.vio.posn.30.port=1 -unit.1.11.vio.posn.30.radix=1 -unit.1.11.vio.posn.30.type=bus -unit.1.11.vio.posn.31.channel=2147483646 -unit.1.11.vio.posn.31.name=un_cross_gain_db -unit.1.11.vio.posn.31.port=1 -unit.1.11.vio.posn.31.radix=1 -unit.1.11.vio.posn.31.type=bus -unit.1.11.vio.posn.32.channel=2147483646 -unit.1.11.vio.posn.32.name=un_cross_gain_db -unit.1.11.vio.posn.32.port=1 -unit.1.11.vio.posn.32.radix=1 -unit.1.11.vio.posn.32.type=bus -unit.1.11.vio.posn.33.channel=2147483646 -unit.1.11.vio.posn.33.name=un_cross_gain_db -unit.1.11.vio.posn.33.port=1 -unit.1.11.vio.posn.33.radix=1 -unit.1.11.vio.posn.33.type=bus -unit.1.11.vio.posn.34.channel=2147483646 -unit.1.11.vio.posn.34.name=un_cross_gain_db -unit.1.11.vio.posn.34.port=1 -unit.1.11.vio.posn.34.radix=1 -unit.1.11.vio.posn.34.type=bus -unit.1.11.vio.posn.35.channel=2147483646 -unit.1.11.vio.posn.35.name=un_cross_gain_db -unit.1.11.vio.posn.35.port=1 -unit.1.11.vio.posn.35.radix=1 -unit.1.11.vio.posn.35.type=bus -unit.1.11.vio.posn.36.channel=2147483646 -unit.1.11.vio.posn.36.name=un_cross_gain_db -unit.1.11.vio.posn.36.port=1 -unit.1.11.vio.posn.36.radix=1 -unit.1.11.vio.posn.36.type=bus -unit.1.11.vio.posn.37.channel=2147483646 -unit.1.11.vio.posn.37.name=un_cross_gain_db -unit.1.11.vio.posn.37.port=1 -unit.1.11.vio.posn.37.radix=1 -unit.1.11.vio.posn.37.type=bus -unit.1.11.vio.posn.38.channel=2147483646 -unit.1.11.vio.posn.38.name=un_cross_gain_db -unit.1.11.vio.posn.38.port=1 -unit.1.11.vio.posn.38.radix=1 -unit.1.11.vio.posn.38.type=bus -unit.1.11.vio.posn.39.channel=2147483646 -unit.1.11.vio.posn.39.name=un_cross_gain_db -unit.1.11.vio.posn.39.port=1 -unit.1.11.vio.posn.39.radix=1 -unit.1.11.vio.posn.39.type=bus -unit.1.11.vio.posn.4.channel=2147483646 -unit.1.11.vio.posn.4.name=dds_sine_gain_ch1 -unit.1.11.vio.posn.4.port=1 -unit.1.11.vio.posn.4.radix=1 -unit.1.11.vio.posn.4.type=bus -unit.1.11.vio.posn.40.channel=2147483646 -unit.1.11.vio.posn.40.name=un_cross_gain_db -unit.1.11.vio.posn.40.port=1 -unit.1.11.vio.posn.40.radix=1 -unit.1.11.vio.posn.40.type=bus -unit.1.11.vio.posn.41.channel=2147483646 -unit.1.11.vio.posn.41.name=un_cross_gain_db -unit.1.11.vio.posn.41.port=1 -unit.1.11.vio.posn.41.radix=1 -unit.1.11.vio.posn.41.type=bus -unit.1.11.vio.posn.42.channel=2147483646 -unit.1.11.vio.posn.42.name=un_cross_gain_db -unit.1.11.vio.posn.42.port=1 -unit.1.11.vio.posn.42.radix=1 -unit.1.11.vio.posn.42.type=bus -unit.1.11.vio.posn.43.channel=2147483646 -unit.1.11.vio.posn.43.name=un_cross_gain_db -unit.1.11.vio.posn.43.port=1 -unit.1.11.vio.posn.43.radix=1 -unit.1.11.vio.posn.43.type=bus -unit.1.11.vio.posn.44.channel=2147483646 -unit.1.11.vio.posn.44.name=un_cross_gain_db -unit.1.11.vio.posn.44.port=1 -unit.1.11.vio.posn.44.radix=1 -unit.1.11.vio.posn.44.type=bus -unit.1.11.vio.posn.45.channel=255 -unit.1.11.vio.posn.45.name=AsyncOut[255] -unit.1.11.vio.posn.45.port=1 -unit.1.11.vio.posn.45.type=signal -unit.1.11.vio.posn.46.channel=255 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-unit.1.11.vio.posn.51.port=1 -unit.1.11.vio.posn.51.type=signal -unit.1.11.vio.posn.52.channel=255 -unit.1.11.vio.posn.52.name=AsyncOut[255] -unit.1.11.vio.posn.52.port=1 -unit.1.11.vio.posn.52.type=signal -unit.1.11.vio.posn.53.channel=255 -unit.1.11.vio.posn.53.name=AsyncOut[255] -unit.1.11.vio.posn.53.port=1 -unit.1.11.vio.posn.53.type=signal -unit.1.11.vio.posn.54.channel=255 -unit.1.11.vio.posn.54.name=AsyncOut[255] -unit.1.11.vio.posn.54.port=1 -unit.1.11.vio.posn.54.type=signal -unit.1.11.vio.posn.55.channel=255 -unit.1.11.vio.posn.55.name=AsyncOut[255] -unit.1.11.vio.posn.55.port=1 -unit.1.11.vio.posn.55.type=signal -unit.1.11.vio.posn.56.channel=255 -unit.1.11.vio.posn.56.name=AsyncOut[255] -unit.1.11.vio.posn.56.port=1 -unit.1.11.vio.posn.56.type=signal -unit.1.11.vio.posn.57.channel=255 -unit.1.11.vio.posn.57.name=AsyncOut[255] -unit.1.11.vio.posn.57.port=1 -unit.1.11.vio.posn.57.type=signal -unit.1.11.vio.posn.58.channel=255 -unit.1.11.vio.posn.58.name=AsyncOut[255] -unit.1.11.vio.posn.58.port=1 -unit.1.11.vio.posn.58.type=signal -unit.1.11.vio.posn.59.channel=255 -unit.1.11.vio.posn.59.name=AsyncOut[255] -unit.1.11.vio.posn.59.port=1 -unit.1.11.vio.posn.59.type=signal -unit.1.11.vio.posn.6.channel=2147483646 -unit.1.11.vio.posn.6.name=adc_synth_data_en -unit.1.11.vio.posn.6.port=1 -unit.1.11.vio.posn.6.radix=1 -unit.1.11.vio.posn.6.type=bus -unit.1.11.vio.posn.60.channel=255 -unit.1.11.vio.posn.60.name=AsyncOut[255] -unit.1.11.vio.posn.60.port=1 -unit.1.11.vio.posn.60.radix=1 -unit.1.11.vio.posn.60.type=signal -unit.1.11.vio.posn.61.channel=255 -unit.1.11.vio.posn.61.name=AsyncOut[255] -unit.1.11.vio.posn.61.port=1 -unit.1.11.vio.posn.61.radix=1 -unit.1.11.vio.posn.61.type=signal -unit.1.11.vio.posn.62.channel=255 -unit.1.11.vio.posn.62.name=AsyncOut[255] -unit.1.11.vio.posn.62.port=1 -unit.1.11.vio.posn.62.type=signal -unit.1.11.vio.posn.63.channel=255 -unit.1.11.vio.posn.63.name=AsyncOut[255] -unit.1.11.vio.posn.63.port=1 -unit.1.11.vio.posn.63.type=signal -unit.1.11.vio.posn.64.channel=255 -unit.1.11.vio.posn.64.name=AsyncOut[255] -unit.1.11.vio.posn.64.port=1 -unit.1.11.vio.posn.64.type=signal -unit.1.11.vio.posn.65.channel=255 -unit.1.11.vio.posn.65.name=AsyncOut[255] -unit.1.11.vio.posn.65.port=1 -unit.1.11.vio.posn.65.type=signal -unit.1.11.vio.posn.66.channel=255 -unit.1.11.vio.posn.66.name=AsyncOut[255] -unit.1.11.vio.posn.66.port=1 -unit.1.11.vio.posn.66.type=signal -unit.1.11.vio.posn.67.channel=255 -unit.1.11.vio.posn.67.name=AsyncOut[255] -unit.1.11.vio.posn.67.port=1 -unit.1.11.vio.posn.67.type=signal -unit.1.11.vio.posn.68.channel=255 -unit.1.11.vio.posn.68.name=AsyncOut[255] -unit.1.11.vio.posn.68.port=1 -unit.1.11.vio.posn.68.type=signal -unit.1.11.vio.posn.69.channel=255 -unit.1.11.vio.posn.69.name=AsyncOut[255] -unit.1.11.vio.posn.69.port=1 -unit.1.11.vio.posn.69.type=signal -unit.1.11.vio.posn.7.channel=2147483646 -unit.1.11.vio.posn.7.name=un_cross_gain_aa -unit.1.11.vio.posn.7.port=1 -unit.1.11.vio.posn.7.radix=4 -unit.1.11.vio.posn.7.type=bus -unit.1.11.vio.posn.70.channel=255 -unit.1.11.vio.posn.70.name=AsyncOut[255] -unit.1.11.vio.posn.70.port=1 -unit.1.11.vio.posn.70.type=signal -unit.1.11.vio.posn.71.channel=255 -unit.1.11.vio.posn.71.name=AsyncOut[255] -unit.1.11.vio.posn.71.port=1 -unit.1.11.vio.posn.71.type=signal -unit.1.11.vio.posn.72.channel=255 -unit.1.11.vio.posn.72.name=AsyncOut[255] -unit.1.11.vio.posn.72.port=1 -unit.1.11.vio.posn.72.type=signal -unit.1.11.vio.posn.73.channel=255 -unit.1.11.vio.posn.73.name=AsyncOut[255] -unit.1.11.vio.posn.73.port=1 -unit.1.11.vio.posn.73.type=signal -unit.1.11.vio.posn.74.channel=255 -unit.1.11.vio.posn.74.name=AsyncOut[255] -unit.1.11.vio.posn.74.port=1 -unit.1.11.vio.posn.74.type=signal -unit.1.11.vio.posn.75.channel=255 -unit.1.11.vio.posn.75.name=AsyncOut[255] -unit.1.11.vio.posn.75.port=1 -unit.1.11.vio.posn.75.radix=1 -unit.1.11.vio.posn.75.type=signal -unit.1.11.vio.posn.76.channel=255 -unit.1.11.vio.posn.76.name=AsyncOut[255] -unit.1.11.vio.posn.76.port=1 -unit.1.11.vio.posn.76.radix=1 -unit.1.11.vio.posn.76.type=signal -unit.1.11.vio.posn.77.channel=255 -unit.1.11.vio.posn.77.name=AsyncOut[255] -unit.1.11.vio.posn.77.port=1 -unit.1.11.vio.posn.77.type=signal -unit.1.11.vio.posn.78.channel=255 -unit.1.11.vio.posn.78.name=AsyncOut[255] -unit.1.11.vio.posn.78.port=1 -unit.1.11.vio.posn.78.type=signal -unit.1.11.vio.posn.79.channel=255 -unit.1.11.vio.posn.79.name=AsyncOut[255] -unit.1.11.vio.posn.79.port=1 -unit.1.11.vio.posn.79.type=signal -unit.1.11.vio.posn.8.channel=2147483646 -unit.1.11.vio.posn.8.name=un_cross_gain_bb -unit.1.11.vio.posn.8.port=1 -unit.1.11.vio.posn.8.radix=4 -unit.1.11.vio.posn.8.type=bus -unit.1.11.vio.posn.80.channel=255 -unit.1.11.vio.posn.80.name=AsyncOut[255] -unit.1.11.vio.posn.80.port=1 -unit.1.11.vio.posn.80.type=signal -unit.1.11.vio.posn.81.channel=255 -unit.1.11.vio.posn.81.name=AsyncOut[255] -unit.1.11.vio.posn.81.port=1 -unit.1.11.vio.posn.81.type=signal -unit.1.11.vio.posn.82.channel=255 -unit.1.11.vio.posn.82.name=AsyncOut[255] -unit.1.11.vio.posn.82.port=1 -unit.1.11.vio.posn.82.type=signal -unit.1.11.vio.posn.83.channel=255 -unit.1.11.vio.posn.83.name=AsyncOut[255] -unit.1.11.vio.posn.83.port=1 -unit.1.11.vio.posn.83.type=signal -unit.1.11.vio.posn.84.channel=255 -unit.1.11.vio.posn.84.name=AsyncOut[255] -unit.1.11.vio.posn.84.port=1 -unit.1.11.vio.posn.84.type=signal -unit.1.11.vio.posn.85.channel=255 -unit.1.11.vio.posn.85.name=AsyncOut[255] -unit.1.11.vio.posn.85.port=1 -unit.1.11.vio.posn.85.type=signal -unit.1.11.vio.posn.86.channel=255 -unit.1.11.vio.posn.86.name=AsyncOut[255] -unit.1.11.vio.posn.86.port=1 -unit.1.11.vio.posn.86.type=signal -unit.1.11.vio.posn.87.channel=255 -unit.1.11.vio.posn.87.name=AsyncOut[255] -unit.1.11.vio.posn.87.port=1 -unit.1.11.vio.posn.87.radix=1 -unit.1.11.vio.posn.87.type=signal -unit.1.11.vio.posn.88.channel=255 -unit.1.11.vio.posn.88.name=AsyncOut[255] -unit.1.11.vio.posn.88.port=1 -unit.1.11.vio.posn.88.radix=1 -unit.1.11.vio.posn.88.type=signal -unit.1.11.vio.posn.89.channel=255 -unit.1.11.vio.posn.89.name=AsyncOut[255] -unit.1.11.vio.posn.89.port=1 -unit.1.11.vio.posn.89.type=signal -unit.1.11.vio.posn.9.channel=2147483646 -unit.1.11.vio.posn.9.name=un_cross_gain_cc -unit.1.11.vio.posn.9.port=1 -unit.1.11.vio.posn.9.radix=4 -unit.1.11.vio.posn.9.type=bus -unit.1.11.vio.posn.90.channel=255 -unit.1.11.vio.posn.90.name=AsyncOut[255] -unit.1.11.vio.posn.90.port=1 -unit.1.11.vio.posn.90.type=signal -unit.1.11.vio.posn.91.channel=255 -unit.1.11.vio.posn.91.name=AsyncOut[255] -unit.1.11.vio.posn.91.port=1 -unit.1.11.vio.posn.91.type=signal -unit.1.11.vio.posn.92.channel=255 -unit.1.11.vio.posn.92.name=AsyncOut[255] -unit.1.11.vio.posn.92.port=1 -unit.1.11.vio.posn.92.type=signal -unit.1.11.vio.posn.93.channel=255 -unit.1.11.vio.posn.93.name=AsyncOut[255] -unit.1.11.vio.posn.93.port=1 -unit.1.11.vio.posn.93.type=signal -unit.1.11.vio.posn.94.channel=255 -unit.1.11.vio.posn.94.name=AsyncOut[255] -unit.1.11.vio.posn.94.port=1 -unit.1.11.vio.posn.94.type=signal -unit.1.11.vio.posn.95.channel=255 -unit.1.11.vio.posn.95.name=AsyncOut[255] -unit.1.11.vio.posn.95.port=1 -unit.1.11.vio.posn.95.type=signal -unit.1.11.vio.posn.96.channel=255 -unit.1.11.vio.posn.96.name=AsyncOut[255] -unit.1.11.vio.posn.96.port=1 -unit.1.11.vio.posn.96.type=signal -unit.1.11.vio.posn.97.channel=255 -unit.1.11.vio.posn.97.name=AsyncOut[255] -unit.1.11.vio.posn.97.port=1 -unit.1.11.vio.posn.97.type=signal -unit.1.11.vio.posn.98.channel=255 -unit.1.11.vio.posn.98.name=AsyncOut[255] -unit.1.11.vio.posn.98.port=1 -unit.1.11.vio.posn.98.type=signal -unit.1.11.vio.posn.99.channel=255 -unit.1.11.vio.posn.99.name=AsyncOut[255] -unit.1.11.vio.posn.99.port=1 -unit.1.11.vio.posn.99.radix=1 -unit.1.11.vio.posn.99.type=signal -unit.1.11.vio.readperiod=0 -unit.1.12.6.HEIGHT6=0.8134206 -unit.1.12.6.WIDTH6=0.63909775 -unit.1.12.6.X6=0.028571429 -unit.1.12.6.Y6=0.045826513 -unit.1.12.browser_tree_state=1 -unit.1.12.browser_tree_state=0 -unit.1.12.browser_tree_state=0 -unit.1.12.coretype=VIO -unit.1.12.port.-1.buscount=0 -unit.1.12.port.-1.channelcount=0 -unit.1.12.port.0.buscount=0 -unit.1.12.port.0.channelcount=0 -unit.1.12.port.1.b.0.alias=dsp_dds_config_valid_ch0 -unit.1.12.port.1.b.0.channellist=240 -unit.1.12.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.0.display=0 -unit.1.12.port.1.b.0.name=AsyncOut -unit.1.12.port.1.b.0.orderindex=-1 -unit.1.12.port.1.b.0.radix=Hex -unit.1.12.port.1.b.0.signedOffset=0.0 -unit.1.12.port.1.b.0.signedPrecision=0 -unit.1.12.port.1.b.0.signedScaleFactor=1.0 -unit.1.12.port.1.b.0.tokencount=0 -unit.1.12.port.1.b.0.unsignedOffset=0.0 -unit.1.12.port.1.b.0.unsignedPrecision=0 -unit.1.12.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.0.value=0 -unit.1.12.port.1.b.0.visible=1 -unit.1.12.port.1.b.1.alias=dsp_dds_config_valid_ch1 -unit.1.12.port.1.b.1.channellist=241 -unit.1.12.port.1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.1.display=0 -unit.1.12.port.1.b.1.name=AsyncOut -unit.1.12.port.1.b.1.orderindex=-1 -unit.1.12.port.1.b.1.radix=Hex -unit.1.12.port.1.b.1.signedOffset=0.0 -unit.1.12.port.1.b.1.signedPrecision=0 -unit.1.12.port.1.b.1.signedScaleFactor=1.0 -unit.1.12.port.1.b.1.tokencount=0 -unit.1.12.port.1.b.1.unsignedOffset=0.0 -unit.1.12.port.1.b.1.unsignedPrecision=0 -unit.1.12.port.1.b.1.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.1.value=0 -unit.1.12.port.1.b.1.visible=1 -unit.1.12.port.1.b.10.alias=dsp_dds_poff_ch2 -unit.1.12.port.1.b.10.channellist=180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 -unit.1.12.port.1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.10.display=0 -unit.1.12.port.1.b.10.name=AsyncOut -unit.1.12.port.1.b.10.orderindex=-1 -unit.1.12.port.1.b.10.radix=Hex -unit.1.12.port.1.b.10.signedOffset=0.0 -unit.1.12.port.1.b.10.signedPrecision=0 -unit.1.12.port.1.b.10.signedScaleFactor=1.0 -unit.1.12.port.1.b.10.tokencount=0 -unit.1.12.port.1.b.10.unsignedOffset=0.0 -unit.1.12.port.1.b.10.unsignedPrecision=0 -unit.1.12.port.1.b.10.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.10.value=00000000 -unit.1.12.port.1.b.10.visible=1 -unit.1.12.port.1.b.11.alias=dsp_dds_poff_ch3 -unit.1.12.port.1.b.11.channellist=210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 -unit.1.12.port.1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.11.display=0 -unit.1.12.port.1.b.11.name=AsyncOut -unit.1.12.port.1.b.11.orderindex=-1 -unit.1.12.port.1.b.11.radix=Hex -unit.1.12.port.1.b.11.signedOffset=0.0 -unit.1.12.port.1.b.11.signedPrecision=0 -unit.1.12.port.1.b.11.signedScaleFactor=1.0 -unit.1.12.port.1.b.11.tokencount=0 -unit.1.12.port.1.b.11.unsignedOffset=0.0 -unit.1.12.port.1.b.11.unsignedPrecision=0 -unit.1.12.port.1.b.11.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.11.value=00000000 -unit.1.12.port.1.b.11.visible=1 -unit.1.12.port.1.b.2.alias=dsp_dds_config_valid_ch2 -unit.1.12.port.1.b.2.channellist=242 -unit.1.12.port.1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.2.display=0 -unit.1.12.port.1.b.2.name=AsyncOut -unit.1.12.port.1.b.2.orderindex=-1 -unit.1.12.port.1.b.2.radix=Hex -unit.1.12.port.1.b.2.signedOffset=0.0 -unit.1.12.port.1.b.2.signedPrecision=0 -unit.1.12.port.1.b.2.signedScaleFactor=1.0 -unit.1.12.port.1.b.2.tokencount=0 -unit.1.12.port.1.b.2.unsignedOffset=0.0 -unit.1.12.port.1.b.2.unsignedPrecision=0 -unit.1.12.port.1.b.2.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.2.value=0 -unit.1.12.port.1.b.2.visible=1 -unit.1.12.port.1.b.3.alias=dsp_dds_config_valid_ch3 -unit.1.12.port.1.b.3.channellist=243 -unit.1.12.port.1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.3.display=0 -unit.1.12.port.1.b.3.name=AsyncOut -unit.1.12.port.1.b.3.orderindex=-1 -unit.1.12.port.1.b.3.radix=Hex -unit.1.12.port.1.b.3.signedOffset=0.0 -unit.1.12.port.1.b.3.signedPrecision=0 -unit.1.12.port.1.b.3.signedScaleFactor=1.0 -unit.1.12.port.1.b.3.tokencount=0 -unit.1.12.port.1.b.3.unsignedOffset=0.0 -unit.1.12.port.1.b.3.unsignedPrecision=0 -unit.1.12.port.1.b.3.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.3.value=0 -unit.1.12.port.1.b.3.visible=1 -unit.1.12.port.1.b.4.alias=dsp_dds_pinc_ch0 -unit.1.12.port.1.b.4.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 -unit.1.12.port.1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.4.display=0 -unit.1.12.port.1.b.4.name=AsyncOut -unit.1.12.port.1.b.4.orderindex=-1 -unit.1.12.port.1.b.4.radix=Unsigned -unit.1.12.port.1.b.4.signedOffset=0.0 -unit.1.12.port.1.b.4.signedPrecision=0 -unit.1.12.port.1.b.4.signedScaleFactor=1.0 -unit.1.12.port.1.b.4.tokencount=0 -unit.1.12.port.1.b.4.unsignedOffset=0.0 -unit.1.12.port.1.b.4.unsignedPrecision=0 -unit.1.12.port.1.b.4.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.4.value=245366784 -unit.1.12.port.1.b.4.visible=1 -unit.1.12.port.1.b.5.alias=dsp_dds_pinc_ch1 -unit.1.12.port.1.b.5.channellist=30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 -unit.1.12.port.1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.5.display=0 -unit.1.12.port.1.b.5.name=AsyncOut -unit.1.12.port.1.b.5.orderindex=-1 -unit.1.12.port.1.b.5.radix=Unsigned -unit.1.12.port.1.b.5.signedOffset=0.0 -unit.1.12.port.1.b.5.signedPrecision=0 -unit.1.12.port.1.b.5.signedScaleFactor=1.0 -unit.1.12.port.1.b.5.tokencount=0 -unit.1.12.port.1.b.5.unsignedOffset=0.0 -unit.1.12.port.1.b.5.unsignedPrecision=0 -unit.1.12.port.1.b.5.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.5.value=245366784 -unit.1.12.port.1.b.5.visible=1 -unit.1.12.port.1.b.6.alias=dsp_dds_pinc_ch2 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-unit.1.12.port.1.s.9.value=0 -unit.1.12.port.1.s.9.visible=0 -unit.1.12.port.1.s.90.alias= -unit.1.12.port.1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.90.display=0 -unit.1.12.port.1.s.90.name=AsyncOut[90] -unit.1.12.port.1.s.90.orderindex=-1 -unit.1.12.port.1.s.90.persistence=0 -unit.1.12.port.1.s.90.value=0 -unit.1.12.port.1.s.90.visible=0 -unit.1.12.port.1.s.91.alias= -unit.1.12.port.1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.91.display=0 -unit.1.12.port.1.s.91.name=AsyncOut[91] -unit.1.12.port.1.s.91.orderindex=-1 -unit.1.12.port.1.s.91.persistence=0 -unit.1.12.port.1.s.91.value=0 -unit.1.12.port.1.s.91.visible=0 -unit.1.12.port.1.s.92.alias= -unit.1.12.port.1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.92.display=0 -unit.1.12.port.1.s.92.name=AsyncOut[92] -unit.1.12.port.1.s.92.orderindex=-1 -unit.1.12.port.1.s.92.persistence=0 -unit.1.12.port.1.s.92.value=0 -unit.1.12.port.1.s.92.visible=0 -unit.1.12.port.1.s.93.alias= -unit.1.12.port.1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.93.display=0 -unit.1.12.port.1.s.93.name=AsyncOut[93] -unit.1.12.port.1.s.93.orderindex=-1 -unit.1.12.port.1.s.93.persistence=0 -unit.1.12.port.1.s.93.value=0 -unit.1.12.port.1.s.93.visible=0 -unit.1.12.port.1.s.94.alias= -unit.1.12.port.1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.94.display=0 -unit.1.12.port.1.s.94.name=AsyncOut[94] -unit.1.12.port.1.s.94.orderindex=-1 -unit.1.12.port.1.s.94.persistence=0 -unit.1.12.port.1.s.94.value=0 -unit.1.12.port.1.s.94.visible=0 -unit.1.12.port.1.s.95.alias= -unit.1.12.port.1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.95.display=0 -unit.1.12.port.1.s.95.name=AsyncOut[95] -unit.1.12.port.1.s.95.orderindex=-1 -unit.1.12.port.1.s.95.persistence=0 -unit.1.12.port.1.s.95.value=0 -unit.1.12.port.1.s.95.visible=0 -unit.1.12.port.1.s.96.alias= -unit.1.12.port.1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.96.display=0 -unit.1.12.port.1.s.96.name=AsyncOut[96] -unit.1.12.port.1.s.96.orderindex=-1 -unit.1.12.port.1.s.96.persistence=0 -unit.1.12.port.1.s.96.value=0 -unit.1.12.port.1.s.96.visible=0 -unit.1.12.port.1.s.97.alias= -unit.1.12.port.1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.97.display=0 -unit.1.12.port.1.s.97.name=AsyncOut[97] -unit.1.12.port.1.s.97.orderindex=-1 -unit.1.12.port.1.s.97.persistence=0 -unit.1.12.port.1.s.97.value=0 -unit.1.12.port.1.s.97.visible=0 -unit.1.12.port.1.s.98.alias= -unit.1.12.port.1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.98.display=0 -unit.1.12.port.1.s.98.name=AsyncOut[98] -unit.1.12.port.1.s.98.orderindex=-1 -unit.1.12.port.1.s.98.persistence=0 -unit.1.12.port.1.s.98.value=0 -unit.1.12.port.1.s.98.visible=0 -unit.1.12.port.1.s.99.alias= -unit.1.12.port.1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.s.99.display=0 -unit.1.12.port.1.s.99.name=AsyncOut[99] -unit.1.12.port.1.s.99.orderindex=-1 -unit.1.12.port.1.s.99.persistence=0 -unit.1.12.port.1.s.99.value=0 -unit.1.12.port.1.s.99.visible=0 -unit.1.12.port.2.buscount=0 -unit.1.12.port.2.channelcount=0 -unit.1.12.portcount=3 -unit.1.12.username=MyVIO12 -unit.1.12.vio.count=12 -unit.1.12.vio.posn.0.channel=2147483646 -unit.1.12.vio.posn.0.name=dsp_dds_pinc_ch0 -unit.1.12.vio.posn.0.port=1 -unit.1.12.vio.posn.0.radix=4 -unit.1.12.vio.posn.0.type=bus -unit.1.12.vio.posn.1.channel=2147483646 -unit.1.12.vio.posn.1.name=dsp_dds_pinc_ch1 -unit.1.12.vio.posn.1.port=1 -unit.1.12.vio.posn.1.radix=4 -unit.1.12.vio.posn.1.type=bus -unit.1.12.vio.posn.10.channel=2147483646 -unit.1.12.vio.posn.10.name=dsp_dds_config_valid_ch2 -unit.1.12.vio.posn.10.port=1 -unit.1.12.vio.posn.10.radix=1 -unit.1.12.vio.posn.10.type=bus -unit.1.12.vio.posn.11.channel=2147483646 -unit.1.12.vio.posn.11.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.11.port=1 -unit.1.12.vio.posn.11.radix=1 -unit.1.12.vio.posn.11.type=bus -unit.1.12.vio.posn.12.channel=2147483646 -unit.1.12.vio.posn.12.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.12.port=1 -unit.1.12.vio.posn.12.radix=1 -unit.1.12.vio.posn.12.type=bus -unit.1.12.vio.posn.13.channel=2147483646 -unit.1.12.vio.posn.13.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.13.port=1 -unit.1.12.vio.posn.13.radix=1 -unit.1.12.vio.posn.13.type=bus -unit.1.12.vio.posn.14.channel=2147483646 -unit.1.12.vio.posn.14.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.14.port=1 -unit.1.12.vio.posn.14.radix=1 -unit.1.12.vio.posn.14.type=bus -unit.1.12.vio.posn.15.channel=2147483646 -unit.1.12.vio.posn.15.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.15.port=1 -unit.1.12.vio.posn.15.radix=1 -unit.1.12.vio.posn.15.type=bus -unit.1.12.vio.posn.16.channel=2147483646 -unit.1.12.vio.posn.16.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.16.port=1 -unit.1.12.vio.posn.16.radix=1 -unit.1.12.vio.posn.16.type=bus -unit.1.12.vio.posn.17.channel=2147483646 -unit.1.12.vio.posn.17.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.17.port=1 -unit.1.12.vio.posn.17.radix=1 -unit.1.12.vio.posn.17.type=bus -unit.1.12.vio.posn.18.channel=2147483646 -unit.1.12.vio.posn.18.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.18.port=1 -unit.1.12.vio.posn.18.radix=1 -unit.1.12.vio.posn.18.type=bus -unit.1.12.vio.posn.19.channel=2147483646 -unit.1.12.vio.posn.19.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.19.port=1 -unit.1.12.vio.posn.19.radix=1 -unit.1.12.vio.posn.19.type=bus -unit.1.12.vio.posn.2.channel=2147483646 -unit.1.12.vio.posn.2.name=dsp_dds_pinc_ch2 -unit.1.12.vio.posn.2.port=1 -unit.1.12.vio.posn.2.radix=4 -unit.1.12.vio.posn.2.type=bus -unit.1.12.vio.posn.20.channel=2147483646 -unit.1.12.vio.posn.20.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.20.port=1 -unit.1.12.vio.posn.20.radix=1 -unit.1.12.vio.posn.20.type=bus -unit.1.12.vio.posn.21.channel=2147483646 -unit.1.12.vio.posn.21.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.21.port=1 -unit.1.12.vio.posn.21.radix=1 -unit.1.12.vio.posn.21.type=bus -unit.1.12.vio.posn.22.channel=2147483646 -unit.1.12.vio.posn.22.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.22.port=1 -unit.1.12.vio.posn.22.radix=1 -unit.1.12.vio.posn.22.type=bus -unit.1.12.vio.posn.23.channel=2147483646 -unit.1.12.vio.posn.23.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.23.port=1 -unit.1.12.vio.posn.23.radix=1 -unit.1.12.vio.posn.23.type=bus -unit.1.12.vio.posn.24.channel=2147483646 -unit.1.12.vio.posn.24.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.24.port=1 -unit.1.12.vio.posn.24.radix=1 -unit.1.12.vio.posn.24.type=bus -unit.1.12.vio.posn.25.channel=2147483646 -unit.1.12.vio.posn.25.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.25.port=1 -unit.1.12.vio.posn.25.radix=1 -unit.1.12.vio.posn.25.type=bus -unit.1.12.vio.posn.26.channel=2147483646 -unit.1.12.vio.posn.26.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.26.port=1 -unit.1.12.vio.posn.26.radix=1 -unit.1.12.vio.posn.26.type=bus -unit.1.12.vio.posn.27.channel=2147483646 -unit.1.12.vio.posn.27.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.27.port=1 -unit.1.12.vio.posn.27.radix=1 -unit.1.12.vio.posn.27.type=bus -unit.1.12.vio.posn.3.channel=2147483646 -unit.1.12.vio.posn.3.name=dsp_dds_pinc_ch3 -unit.1.12.vio.posn.3.port=1 -unit.1.12.vio.posn.3.radix=4 -unit.1.12.vio.posn.3.type=bus -unit.1.12.vio.posn.4.channel=2147483646 -unit.1.12.vio.posn.4.name=dsp_dds_poff_ch0 -unit.1.12.vio.posn.4.port=1 -unit.1.12.vio.posn.4.radix=1 -unit.1.12.vio.posn.4.type=bus -unit.1.12.vio.posn.5.channel=2147483646 -unit.1.12.vio.posn.5.name=dsp_dds_poff_ch1 -unit.1.12.vio.posn.5.port=1 -unit.1.12.vio.posn.5.radix=1 -unit.1.12.vio.posn.5.type=bus -unit.1.12.vio.posn.6.channel=2147483646 -unit.1.12.vio.posn.6.name=dsp_dds_poff_ch2 -unit.1.12.vio.posn.6.port=1 -unit.1.12.vio.posn.6.radix=1 -unit.1.12.vio.posn.6.type=bus -unit.1.12.vio.posn.7.channel=2147483646 -unit.1.12.vio.posn.7.name=dsp_dds_poff_ch3 -unit.1.12.vio.posn.7.port=1 -unit.1.12.vio.posn.7.radix=1 -unit.1.12.vio.posn.7.type=bus -unit.1.12.vio.posn.8.channel=2147483646 -unit.1.12.vio.posn.8.name=dsp_dds_config_valid_ch0 -unit.1.12.vio.posn.8.port=1 -unit.1.12.vio.posn.8.radix=1 -unit.1.12.vio.posn.8.type=bus -unit.1.12.vio.posn.9.channel=2147483646 -unit.1.12.vio.posn.9.name=dsp_dds_config_valid_ch1 -unit.1.12.vio.posn.9.port=1 -unit.1.12.vio.posn.9.radix=1 -unit.1.12.vio.posn.9.type=bus -unit.1.12.vio.readperiod=0 -unit.1.2.0.HEIGHT0=0.44517186 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 -unit.1.2.0.TriggerRow2=1 -unit.1.2.0.WIDTH0=0.6631579 -unit.1.2.0.X0=0.05263158 -unit.1.2.0.Y0=0.0 -unit.1.2.1.HEIGHT1=0.7839607 -unit.1.2.1.WIDTH1=0.6097744 -unit.1.2.1.X1=0.004511278 -unit.1.2.1.Y1=0.12765957 -unit.1.2.5.HEIGHT5=1.0 -unit.1.2.5.WIDTH5=1.0 -unit.1.2.5.X5=0.0 -unit.1.2.5.Y5=0.0 -unit.1.2.MFBitsA0=1XXXXXXX -unit.1.2.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsB0=00000000 -unit.1.2.MFBitsB1=00000000000000000000000000000000 -unit.1.2.MFBitsB2=00000000000000000000000000000000 -unit.1.2.MFBitsB3=00000000000000000000000000000000 -unit.1.2.MFBitsB4=00000000000000000000000000000000 -unit.1.2.MFCompareA0=0 -unit.1.2.MFCompareA1=0 -unit.1.2.MFCompareA2=0 -unit.1.2.MFCompareA3=0 -unit.1.2.MFCompareA4=0 -unit.1.2.MFCompareB0=999 -unit.1.2.MFCompareB1=999 -unit.1.2.MFCompareB2=999 -unit.1.2.MFCompareB3=999 -unit.1.2.MFCompareB4=999 -unit.1.2.MFCount=5 -unit.1.2.MFDisplay0=0 -unit.1.2.MFDisplay1=0 -unit.1.2.MFDisplay2=0 -unit.1.2.MFDisplay3=0 -unit.1.2.MFDisplay4=0 -unit.1.2.MFEventType0=3 -unit.1.2.MFEventType1=3 -unit.1.2.MFEventType2=3 -unit.1.2.MFEventType3=3 -unit.1.2.MFEventType4=3 -unit.1.2.RunMode=SINGLE RUN -unit.1.2.SQCondition=M0 -unit.1.2.SQContiguous0=0 -unit.1.2.SequencerOn=0 -unit.1.2.TCActive=0 -unit.1.2.TCAdvanced0=0 -unit.1.2.TCCondition0_0=M0 -unit.1.2.TCCondition0_1= -unit.1.2.TCConditionType0=0 -unit.1.2.TCCount=1 -unit.1.2.TCEventCount0=1 -unit.1.2.TCEventType0=3 -unit.1.2.TCName0=TriggerCondition0 -unit.1.2.TCOutputEnable0=0 -unit.1.2.TCOutputHigh0=1 -unit.1.2.TCOutputMode0=0 -unit.1.2.browser_tree_state=1 -unit.1.2.browser_tree_state=1 -unit.1.2.browser_tree_state=0 -unit.1.2.browser_tree_state=0 -unit.1.2.browser_tree_state=0 -unit.1.2.coretype=ILA -unit.1.2.eventCount0=1 -unit.1.2.eventCount1=1 -unit.1.2.eventCount2=1 -unit.1.2.eventCount3=1 -unit.1.2.eventCount4=1 -unit.1.2.plotBusColor0=-16737844 -unit.1.2.plotBusColor1=-6711040 -unit.1.2.plotBusColor2=-65536 -unit.1.2.plotBusColor3=-16777012 -unit.1.2.plotBusCount=4 -unit.1.2.plotBusName0=dsp_tbt_amp_ch0 -unit.1.2.plotBusName1=dsp_tbt_amp_ch1 -unit.1.2.plotBusName2=dsp_tbt_amp_ch2 -unit.1.2.plotBusName3=dsp_tbt_amp_ch3 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-unit.1.2.port.-1.s.67.alias= -unit.1.2.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.67.name=DataPort[67] -unit.1.2.port.-1.s.67.orderindex=-1 -unit.1.2.port.-1.s.67.visible=1 -unit.1.2.port.-1.s.68.alias= -unit.1.2.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.68.name=DataPort[68] -unit.1.2.port.-1.s.68.orderindex=-1 -unit.1.2.port.-1.s.68.visible=1 -unit.1.2.port.-1.s.69.alias= -unit.1.2.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.69.name=DataPort[69] -unit.1.2.port.-1.s.69.orderindex=-1 -unit.1.2.port.-1.s.69.visible=1 -unit.1.2.port.-1.s.7.alias= -unit.1.2.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.7.name=DataPort[7] -unit.1.2.port.-1.s.7.orderindex=-1 -unit.1.2.port.-1.s.7.visible=1 -unit.1.2.port.-1.s.70.alias= -unit.1.2.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.70.name=DataPort[70] -unit.1.2.port.-1.s.70.orderindex=-1 -unit.1.2.port.-1.s.70.visible=1 -unit.1.2.port.-1.s.71.alias= -unit.1.2.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.71.name=DataPort[71] -unit.1.2.port.-1.s.71.orderindex=-1 -unit.1.2.port.-1.s.71.visible=1 -unit.1.2.port.-1.s.72.alias= -unit.1.2.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.72.name=DataPort[72] -unit.1.2.port.-1.s.72.orderindex=-1 -unit.1.2.port.-1.s.72.visible=0 -unit.1.2.port.-1.s.73.alias= -unit.1.2.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.73.name=DataPort[73] -unit.1.2.port.-1.s.73.orderindex=-1 -unit.1.2.port.-1.s.73.visible=0 -unit.1.2.port.-1.s.74.alias= -unit.1.2.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.74.name=DataPort[74] -unit.1.2.port.-1.s.74.orderindex=-1 -unit.1.2.port.-1.s.74.visible=0 -unit.1.2.port.-1.s.75.alias= -unit.1.2.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.75.name=DataPort[75] -unit.1.2.port.-1.s.75.orderindex=-1 -unit.1.2.port.-1.s.75.visible=0 -unit.1.2.port.-1.s.76.alias= -unit.1.2.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.76.name=DataPort[76] -unit.1.2.port.-1.s.76.orderindex=-1 -unit.1.2.port.-1.s.76.visible=0 -unit.1.2.port.-1.s.77.alias= -unit.1.2.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.77.name=DataPort[77] -unit.1.2.port.-1.s.77.orderindex=-1 -unit.1.2.port.-1.s.77.visible=0 -unit.1.2.port.-1.s.78.alias= -unit.1.2.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.78.name=DataPort[78] -unit.1.2.port.-1.s.78.orderindex=-1 -unit.1.2.port.-1.s.78.visible=0 -unit.1.2.port.-1.s.79.alias= -unit.1.2.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.79.name=DataPort[79] -unit.1.2.port.-1.s.79.orderindex=-1 -unit.1.2.port.-1.s.79.visible=0 -unit.1.2.port.-1.s.8.alias= -unit.1.2.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.8.name=DataPort[8] -unit.1.2.port.-1.s.8.orderindex=-1 -unit.1.2.port.-1.s.8.visible=0 -unit.1.2.port.-1.s.80.alias= -unit.1.2.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.80.name=DataPort[80] -unit.1.2.port.-1.s.80.orderindex=-1 -unit.1.2.port.-1.s.80.visible=0 -unit.1.2.port.-1.s.81.alias= -unit.1.2.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.81.name=DataPort[81] -unit.1.2.port.-1.s.81.orderindex=-1 -unit.1.2.port.-1.s.81.visible=0 -unit.1.2.port.-1.s.82.alias= -unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=0 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=0 -unit.1.2.port.-1.s.84.alias= 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-unit.1.2.port.-1.s.89.alias= -unit.1.2.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.89.name=DataPort[89] -unit.1.2.port.-1.s.89.orderindex=-1 -unit.1.2.port.-1.s.89.visible=0 -unit.1.2.port.-1.s.9.alias= -unit.1.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.9.name=DataPort[9] -unit.1.2.port.-1.s.9.orderindex=-1 -unit.1.2.port.-1.s.9.visible=0 -unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=0 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=0 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 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-unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex -unit.1.2.port.0.b.0.signedOffset=0.0 -unit.1.2.port.0.b.0.signedPrecision=0 -unit.1.2.port.0.b.0.signedScaleFactor=1.0 -unit.1.2.port.0.b.0.unsignedOffset=0.0 -unit.1.2.port.0.b.0.unsignedPrecision=0 -unit.1.2.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.0.b.0.visible=1 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-unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 -unit.1.2.port.3.s.27.alias= -unit.1.2.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.27.name=TriggerPort3[27] -unit.1.2.port.3.s.27.orderindex=-1 -unit.1.2.port.3.s.27.visible=1 -unit.1.2.port.3.s.28.alias= -unit.1.2.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.28.name=TriggerPort3[28] -unit.1.2.port.3.s.28.orderindex=-1 -unit.1.2.port.3.s.28.visible=1 -unit.1.2.port.3.s.29.alias= -unit.1.2.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.29.name=TriggerPort3[29] -unit.1.2.port.3.s.29.orderindex=-1 -unit.1.2.port.3.s.29.visible=1 -unit.1.2.port.3.s.3.alias= -unit.1.2.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.3.name=TriggerPort3[3] -unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.port.4.b.0.alias= -unit.1.2.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.b.0.name=TriggerPort4 -unit.1.2.port.4.b.0.orderindex=-1 -unit.1.2.port.4.b.0.radix=Hex -unit.1.2.port.4.b.0.signedOffset=0.0 -unit.1.2.port.4.b.0.signedPrecision=0 -unit.1.2.port.4.b.0.signedScaleFactor=1.0 -unit.1.2.port.4.b.0.unsignedOffset=0.0 -unit.1.2.port.4.b.0.unsignedPrecision=0 -unit.1.2.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.4.b.0.visible=1 -unit.1.2.port.4.buscount=1 -unit.1.2.port.4.channelcount=32 -unit.1.2.port.4.s.0.alias= -unit.1.2.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.0.name=TriggerPort4[0] -unit.1.2.port.4.s.0.orderindex=-1 -unit.1.2.port.4.s.0.visible=1 -unit.1.2.port.4.s.1.alias= -unit.1.2.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.1.name=TriggerPort4[1] -unit.1.2.port.4.s.1.orderindex=-1 -unit.1.2.port.4.s.1.visible=1 -unit.1.2.port.4.s.10.alias= -unit.1.2.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.10.name=TriggerPort4[10] -unit.1.2.port.4.s.10.orderindex=-1 -unit.1.2.port.4.s.10.visible=1 -unit.1.2.port.4.s.11.alias= -unit.1.2.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.11.name=TriggerPort4[11] -unit.1.2.port.4.s.11.orderindex=-1 -unit.1.2.port.4.s.11.visible=1 -unit.1.2.port.4.s.12.alias= -unit.1.2.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.12.name=TriggerPort4[12] -unit.1.2.port.4.s.12.orderindex=-1 -unit.1.2.port.4.s.12.visible=1 -unit.1.2.port.4.s.13.alias= -unit.1.2.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.13.name=TriggerPort4[13] -unit.1.2.port.4.s.13.orderindex=-1 -unit.1.2.port.4.s.13.visible=1 -unit.1.2.port.4.s.14.alias= -unit.1.2.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.14.name=TriggerPort4[14] -unit.1.2.port.4.s.14.orderindex=-1 -unit.1.2.port.4.s.14.visible=1 -unit.1.2.port.4.s.15.alias= -unit.1.2.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.15.name=TriggerPort4[15] -unit.1.2.port.4.s.15.orderindex=-1 -unit.1.2.port.4.s.15.visible=1 -unit.1.2.port.4.s.16.alias= -unit.1.2.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.16.name=TriggerPort4[16] -unit.1.2.port.4.s.16.orderindex=-1 -unit.1.2.port.4.s.16.visible=1 -unit.1.2.port.4.s.17.alias= -unit.1.2.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.17.name=TriggerPort4[17] -unit.1.2.port.4.s.17.orderindex=-1 -unit.1.2.port.4.s.17.visible=1 -unit.1.2.port.4.s.18.alias= -unit.1.2.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.18.name=TriggerPort4[18] -unit.1.2.port.4.s.18.orderindex=-1 -unit.1.2.port.4.s.18.visible=1 -unit.1.2.port.4.s.19.alias= -unit.1.2.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.19.name=TriggerPort4[19] -unit.1.2.port.4.s.19.orderindex=-1 -unit.1.2.port.4.s.19.visible=1 -unit.1.2.port.4.s.2.alias= -unit.1.2.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.2.name=TriggerPort4[2] -unit.1.2.port.4.s.2.orderindex=-1 -unit.1.2.port.4.s.2.visible=1 -unit.1.2.port.4.s.20.alias= -unit.1.2.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.20.name=TriggerPort4[20] -unit.1.2.port.4.s.20.orderindex=-1 -unit.1.2.port.4.s.20.visible=1 -unit.1.2.port.4.s.21.alias= -unit.1.2.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.21.name=TriggerPort4[21] -unit.1.2.port.4.s.21.orderindex=-1 -unit.1.2.port.4.s.21.visible=1 -unit.1.2.port.4.s.22.alias= -unit.1.2.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.22.name=TriggerPort4[22] -unit.1.2.port.4.s.22.orderindex=-1 -unit.1.2.port.4.s.22.visible=1 -unit.1.2.port.4.s.23.alias= -unit.1.2.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.23.name=TriggerPort4[23] -unit.1.2.port.4.s.23.orderindex=-1 -unit.1.2.port.4.s.23.visible=1 -unit.1.2.port.4.s.24.alias= -unit.1.2.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.24.name=TriggerPort4[24] -unit.1.2.port.4.s.24.orderindex=-1 -unit.1.2.port.4.s.24.visible=1 -unit.1.2.port.4.s.25.alias= -unit.1.2.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.25.name=TriggerPort4[25] -unit.1.2.port.4.s.25.orderindex=-1 -unit.1.2.port.4.s.25.visible=1 -unit.1.2.port.4.s.26.alias= -unit.1.2.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.26.name=TriggerPort4[26] -unit.1.2.port.4.s.26.orderindex=-1 -unit.1.2.port.4.s.26.visible=1 -unit.1.2.port.4.s.27.alias= -unit.1.2.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.27.name=TriggerPort4[27] -unit.1.2.port.4.s.27.orderindex=-1 -unit.1.2.port.4.s.27.visible=1 -unit.1.2.port.4.s.28.alias= -unit.1.2.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.28.name=TriggerPort4[28] -unit.1.2.port.4.s.28.orderindex=-1 -unit.1.2.port.4.s.28.visible=1 -unit.1.2.port.4.s.29.alias= -unit.1.2.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.29.name=TriggerPort4[29] -unit.1.2.port.4.s.29.orderindex=-1 -unit.1.2.port.4.s.29.visible=1 -unit.1.2.port.4.s.3.alias= -unit.1.2.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.3.name=TriggerPort4[3] -unit.1.2.port.4.s.3.orderindex=-1 -unit.1.2.port.4.s.3.visible=1 -unit.1.2.port.4.s.30.alias= -unit.1.2.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.30.name=TriggerPort4[30] -unit.1.2.port.4.s.30.orderindex=-1 -unit.1.2.port.4.s.30.visible=1 -unit.1.2.port.4.s.31.alias= -unit.1.2.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.31.name=TriggerPort4[31] -unit.1.2.port.4.s.31.orderindex=-1 -unit.1.2.port.4.s.31.visible=1 -unit.1.2.port.4.s.4.alias= -unit.1.2.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.4.name=TriggerPort4[4] -unit.1.2.port.4.s.4.orderindex=-1 -unit.1.2.port.4.s.4.visible=1 -unit.1.2.port.4.s.5.alias= -unit.1.2.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.5.name=TriggerPort4[5] -unit.1.2.port.4.s.5.orderindex=-1 -unit.1.2.port.4.s.5.visible=1 -unit.1.2.port.4.s.6.alias= -unit.1.2.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.6.name=TriggerPort4[6] -unit.1.2.port.4.s.6.orderindex=-1 -unit.1.2.port.4.s.6.visible=1 -unit.1.2.port.4.s.7.alias= -unit.1.2.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.7.name=TriggerPort4[7] -unit.1.2.port.4.s.7.orderindex=-1 -unit.1.2.port.4.s.7.visible=1 -unit.1.2.port.4.s.8.alias= -unit.1.2.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.8.name=TriggerPort4[8] -unit.1.2.port.4.s.8.orderindex=-1 -unit.1.2.port.4.s.8.visible=1 -unit.1.2.port.4.s.9.alias= -unit.1.2.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.9.name=TriggerPort4[9] -unit.1.2.port.4.s.9.orderindex=-1 -unit.1.2.port.4.s.9.visible=1 -unit.1.2.portcount=5 -unit.1.2.rep_trigger.clobber=1 -unit.1.2.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/C\:\\Documents and Settings\\lucas.russo\\Desktop\\position_test\\logs -unit.1.2.rep_trigger.filename=dsp_monit_pos -unit.1.2.rep_trigger.format=ASCII -unit.1.2.rep_trigger.loggingEnabled=0 -unit.1.2.rep_trigger.signals=Waveform Signals/Buses -unit.1.2.samplesPerTrigger=1 -unit.1.2.triggerCapture=1 -unit.1.2.triggerNSamplesTS=0 -unit.1.2.triggerPosition=0 -unit.1.2.triggerWindowCount=1 -unit.1.2.triggerWindowDepth=1024 -unit.1.2.triggerWindowTS=0 -unit.1.2.username=tbt_amp -unit.1.2.waveform.count=32 -unit.1.2.waveform.posn.0.channel=2147483646 -unit.1.2.waveform.posn.0.name=dsp_tbt_amp_ch1 -unit.1.2.waveform.posn.0.radix=3 -unit.1.2.waveform.posn.0.type=bus -unit.1.2.waveform.posn.1.channel=2147483646 -unit.1.2.waveform.posn.1.name=dsp_tbt_amp_ch3 -unit.1.2.waveform.posn.1.radix=3 -unit.1.2.waveform.posn.1.type=bus -unit.1.2.waveform.posn.10.channel=7 -unit.1.2.waveform.posn.10.name=DataPort[7] -unit.1.2.waveform.posn.10.radix=3 -unit.1.2.waveform.posn.10.type=signal -unit.1.2.waveform.posn.100.channel=127 -unit.1.2.waveform.posn.100.name=DataPort[127] -unit.1.2.waveform.posn.100.type=signal -unit.1.2.waveform.posn.101.channel=127 -unit.1.2.waveform.posn.101.name=DataPort[127] -unit.1.2.waveform.posn.101.type=signal -unit.1.2.waveform.posn.102.channel=127 -unit.1.2.waveform.posn.102.name=DataPort[127] -unit.1.2.waveform.posn.102.type=signal -unit.1.2.waveform.posn.103.channel=127 -unit.1.2.waveform.posn.103.name=DataPort[127] -unit.1.2.waveform.posn.103.type=signal -unit.1.2.waveform.posn.104.channel=127 -unit.1.2.waveform.posn.104.name=DataPort[127] -unit.1.2.waveform.posn.104.type=signal -unit.1.2.waveform.posn.105.channel=127 -unit.1.2.waveform.posn.105.name=DataPort[127] -unit.1.2.waveform.posn.105.type=signal -unit.1.2.waveform.posn.106.channel=127 -unit.1.2.waveform.posn.106.name=DataPort[127] -unit.1.2.waveform.posn.106.type=signal -unit.1.2.waveform.posn.107.channel=127 -unit.1.2.waveform.posn.107.name=DataPort[127] -unit.1.2.waveform.posn.107.type=signal -unit.1.2.waveform.posn.108.channel=127 -unit.1.2.waveform.posn.108.name=DataPort[127] -unit.1.2.waveform.posn.108.type=signal -unit.1.2.waveform.posn.109.channel=127 -unit.1.2.waveform.posn.109.name=DataPort[127] -unit.1.2.waveform.posn.109.type=signal -unit.1.2.waveform.posn.11.channel=33 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-unit.1.2.waveform.posn.123.name=DataPort[127] -unit.1.2.waveform.posn.123.type=signal -unit.1.2.waveform.posn.124.channel=127 -unit.1.2.waveform.posn.124.name=DataPort[127] -unit.1.2.waveform.posn.124.type=signal -unit.1.2.waveform.posn.125.channel=127 -unit.1.2.waveform.posn.125.name=DataPort[127] -unit.1.2.waveform.posn.125.type=signal -unit.1.2.waveform.posn.126.channel=127 -unit.1.2.waveform.posn.126.name=DataPort[127] -unit.1.2.waveform.posn.126.type=signal -unit.1.2.waveform.posn.127.channel=127 -unit.1.2.waveform.posn.127.name=DataPort[127] -unit.1.2.waveform.posn.127.type=signal -unit.1.2.waveform.posn.13.channel=35 -unit.1.2.waveform.posn.13.name=DataPort[35] -unit.1.2.waveform.posn.13.type=signal -unit.1.2.waveform.posn.14.channel=36 -unit.1.2.waveform.posn.14.name=DataPort[36] -unit.1.2.waveform.posn.14.type=signal -unit.1.2.waveform.posn.15.channel=37 -unit.1.2.waveform.posn.15.name=DataPort[37] -unit.1.2.waveform.posn.15.type=signal -unit.1.2.waveform.posn.16.channel=38 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-unit.1.3.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.b.2.name=DataPort -unit.1.3.port.-1.b.2.orderindex=-1 -unit.1.3.port.-1.b.2.radix=Signed -unit.1.3.port.-1.b.2.signedOffset=0.0 -unit.1.3.port.-1.b.2.signedPrecision=0 -unit.1.3.port.-1.b.2.signedScaleFactor=1.0 -unit.1.3.port.-1.b.2.tokencount=0 -unit.1.3.port.-1.b.2.unsignedOffset=0.0 -unit.1.3.port.-1.b.2.unsignedPrecision=0 -unit.1.3.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.3.port.-1.b.2.visible=1 -unit.1.3.port.-1.b.3.alias=dsp_y_tbt -unit.1.3.port.-1.b.3.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 -unit.1.3.port.-1.b.3.color=java.awt.Color[r\=255,g\=0,b\=0] -unit.1.3.port.-1.b.3.name=DataPort -unit.1.3.port.-1.b.3.orderindex=-1 -unit.1.3.port.-1.b.3.radix=Signed -unit.1.3.port.-1.b.3.signedOffset=0.0 -unit.1.3.port.-1.b.3.signedPrecision=0 -unit.1.3.port.-1.b.3.signedScaleFactor=1.0 -unit.1.3.port.-1.b.3.tokencount=0 -unit.1.3.port.-1.b.3.unsignedOffset=0.0 -unit.1.3.port.-1.b.3.unsignedPrecision=0 -unit.1.3.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.3.port.-1.b.3.visible=1 -unit.1.3.port.-1.buscount=4 -unit.1.3.port.-1.channelcount=136 -unit.1.3.port.-1.s.0.alias= -unit.1.3.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.0.name=DataPort[0] -unit.1.3.port.-1.s.0.orderindex=-1 -unit.1.3.port.-1.s.0.visible=1 -unit.1.3.port.-1.s.1.alias= -unit.1.3.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.1.name=DataPort[1] -unit.1.3.port.-1.s.1.orderindex=-1 -unit.1.3.port.-1.s.1.visible=1 -unit.1.3.port.-1.s.10.alias= -unit.1.3.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.10.name=DataPort[10] -unit.1.3.port.-1.s.10.orderindex=-1 -unit.1.3.port.-1.s.10.visible=0 -unit.1.3.port.-1.s.100.alias= -unit.1.3.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.100.name=DataPort[100] -unit.1.3.port.-1.s.100.orderindex=-1 -unit.1.3.port.-1.s.100.visible=1 -unit.1.3.port.-1.s.101.alias= -unit.1.3.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.101.name=DataPort[101] -unit.1.3.port.-1.s.101.orderindex=-1 -unit.1.3.port.-1.s.101.visible=1 -unit.1.3.port.-1.s.102.alias= -unit.1.3.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.102.name=DataPort[102] -unit.1.3.port.-1.s.102.orderindex=-1 -unit.1.3.port.-1.s.102.visible=1 -unit.1.3.port.-1.s.103.alias= -unit.1.3.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.103.name=DataPort[103] -unit.1.3.port.-1.s.103.orderindex=-1 -unit.1.3.port.-1.s.103.visible=1 -unit.1.3.port.-1.s.104.alias= -unit.1.3.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.104.name=DataPort[104] -unit.1.3.port.-1.s.104.orderindex=-1 -unit.1.3.port.-1.s.104.visible=0 -unit.1.3.port.-1.s.105.alias= -unit.1.3.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.105.name=DataPort[105] -unit.1.3.port.-1.s.105.orderindex=-1 -unit.1.3.port.-1.s.105.visible=0 -unit.1.3.port.-1.s.106.alias= -unit.1.3.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.106.name=DataPort[106] -unit.1.3.port.-1.s.106.orderindex=-1 -unit.1.3.port.-1.s.106.visible=0 -unit.1.3.port.-1.s.107.alias= -unit.1.3.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.107.name=DataPort[107] -unit.1.3.port.-1.s.107.orderindex=-1 -unit.1.3.port.-1.s.107.visible=0 -unit.1.3.port.-1.s.108.alias= -unit.1.3.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.108.name=DataPort[108] -unit.1.3.port.-1.s.108.orderindex=-1 -unit.1.3.port.-1.s.108.visible=0 -unit.1.3.port.-1.s.109.alias= -unit.1.3.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.109.name=DataPort[109] -unit.1.3.port.-1.s.109.orderindex=-1 -unit.1.3.port.-1.s.109.visible=0 -unit.1.3.port.-1.s.11.alias= -unit.1.3.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.11.name=DataPort[11] -unit.1.3.port.-1.s.11.orderindex=-1 -unit.1.3.port.-1.s.11.visible=0 -unit.1.3.port.-1.s.110.alias= -unit.1.3.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.110.name=DataPort[110] -unit.1.3.port.-1.s.110.orderindex=-1 -unit.1.3.port.-1.s.110.visible=0 -unit.1.3.port.-1.s.111.alias= -unit.1.3.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.111.name=DataPort[111] -unit.1.3.port.-1.s.111.orderindex=-1 -unit.1.3.port.-1.s.111.visible=0 -unit.1.3.port.-1.s.112.alias= -unit.1.3.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.112.name=DataPort[112] -unit.1.3.port.-1.s.112.orderindex=-1 -unit.1.3.port.-1.s.112.visible=0 -unit.1.3.port.-1.s.113.alias= -unit.1.3.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.113.name=DataPort[113] -unit.1.3.port.-1.s.113.orderindex=-1 -unit.1.3.port.-1.s.113.visible=0 -unit.1.3.port.-1.s.114.alias= -unit.1.3.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.114.name=DataPort[114] -unit.1.3.port.-1.s.114.orderindex=-1 -unit.1.3.port.-1.s.114.visible=0 -unit.1.3.port.-1.s.115.alias= -unit.1.3.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.115.name=DataPort[115] -unit.1.3.port.-1.s.115.orderindex=-1 -unit.1.3.port.-1.s.115.visible=0 -unit.1.3.port.-1.s.116.alias= -unit.1.3.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.116.name=DataPort[116] -unit.1.3.port.-1.s.116.orderindex=-1 -unit.1.3.port.-1.s.116.visible=0 -unit.1.3.port.-1.s.117.alias= -unit.1.3.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.117.name=DataPort[117] -unit.1.3.port.-1.s.117.orderindex=-1 -unit.1.3.port.-1.s.117.visible=0 -unit.1.3.port.-1.s.118.alias= -unit.1.3.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.118.name=DataPort[118] -unit.1.3.port.-1.s.118.orderindex=-1 -unit.1.3.port.-1.s.118.visible=0 -unit.1.3.port.-1.s.119.alias= -unit.1.3.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.119.name=DataPort[119] -unit.1.3.port.-1.s.119.orderindex=-1 -unit.1.3.port.-1.s.119.visible=0 -unit.1.3.port.-1.s.12.alias= -unit.1.3.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.12.name=DataPort[12] -unit.1.3.port.-1.s.12.orderindex=-1 -unit.1.3.port.-1.s.12.visible=0 -unit.1.3.port.-1.s.120.alias= -unit.1.3.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.120.name=DataPort[120] -unit.1.3.port.-1.s.120.orderindex=-1 -unit.1.3.port.-1.s.120.visible=0 -unit.1.3.port.-1.s.121.alias= -unit.1.3.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.121.name=DataPort[121] -unit.1.3.port.-1.s.121.orderindex=-1 -unit.1.3.port.-1.s.121.visible=0 -unit.1.3.port.-1.s.122.alias= -unit.1.3.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.122.name=DataPort[122] -unit.1.3.port.-1.s.122.orderindex=-1 -unit.1.3.port.-1.s.122.visible=0 -unit.1.3.port.-1.s.123.alias= -unit.1.3.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.123.name=DataPort[123] -unit.1.3.port.-1.s.123.orderindex=-1 -unit.1.3.port.-1.s.123.visible=0 -unit.1.3.port.-1.s.124.alias= -unit.1.3.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.124.name=DataPort[124] -unit.1.3.port.-1.s.124.orderindex=-1 -unit.1.3.port.-1.s.124.visible=0 -unit.1.3.port.-1.s.125.alias= -unit.1.3.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.125.name=DataPort[125] -unit.1.3.port.-1.s.125.orderindex=-1 -unit.1.3.port.-1.s.125.visible=0 -unit.1.3.port.-1.s.126.alias= -unit.1.3.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.126.name=DataPort[126] -unit.1.3.port.-1.s.126.orderindex=-1 -unit.1.3.port.-1.s.126.visible=0 -unit.1.3.port.-1.s.127.alias= -unit.1.3.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.127.name=DataPort[127] -unit.1.3.port.-1.s.127.orderindex=-1 -unit.1.3.port.-1.s.127.visible=0 -unit.1.3.port.-1.s.128.alias= -unit.1.3.port.-1.s.128.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.128.name=DataPort[128] -unit.1.3.port.-1.s.128.orderindex=-1 -unit.1.3.port.-1.s.128.visible=0 -unit.1.3.port.-1.s.129.alias= -unit.1.3.port.-1.s.129.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.129.name=DataPort[129] -unit.1.3.port.-1.s.129.orderindex=-1 -unit.1.3.port.-1.s.129.visible=0 -unit.1.3.port.-1.s.13.alias= -unit.1.3.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.13.name=DataPort[13] -unit.1.3.port.-1.s.13.orderindex=-1 -unit.1.3.port.-1.s.13.visible=0 -unit.1.3.port.-1.s.130.alias= -unit.1.3.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.130.name=DataPort[130] -unit.1.3.port.-1.s.130.orderindex=-1 -unit.1.3.port.-1.s.130.visible=1 -unit.1.3.port.-1.s.131.alias= -unit.1.3.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.131.name=DataPort[131] -unit.1.3.port.-1.s.131.orderindex=-1 -unit.1.3.port.-1.s.131.visible=1 -unit.1.3.port.-1.s.132.alias= -unit.1.3.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.132.name=DataPort[132] -unit.1.3.port.-1.s.132.orderindex=-1 -unit.1.3.port.-1.s.132.visible=1 -unit.1.3.port.-1.s.133.alias= -unit.1.3.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.133.name=DataPort[133] -unit.1.3.port.-1.s.133.orderindex=-1 -unit.1.3.port.-1.s.133.visible=1 -unit.1.3.port.-1.s.134.alias= -unit.1.3.port.-1.s.134.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.134.name=DataPort[134] -unit.1.3.port.-1.s.134.orderindex=-1 -unit.1.3.port.-1.s.134.visible=1 -unit.1.3.port.-1.s.135.alias= -unit.1.3.port.-1.s.135.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.135.name=DataPort[135] -unit.1.3.port.-1.s.135.orderindex=-1 -unit.1.3.port.-1.s.135.visible=1 -unit.1.3.port.-1.s.14.alias= -unit.1.3.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.14.name=DataPort[14] -unit.1.3.port.-1.s.14.orderindex=-1 -unit.1.3.port.-1.s.14.visible=0 -unit.1.3.port.-1.s.15.alias= -unit.1.3.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.15.name=DataPort[15] -unit.1.3.port.-1.s.15.orderindex=-1 -unit.1.3.port.-1.s.15.visible=0 -unit.1.3.port.-1.s.16.alias= -unit.1.3.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.16.name=DataPort[16] -unit.1.3.port.-1.s.16.orderindex=-1 -unit.1.3.port.-1.s.16.visible=0 -unit.1.3.port.-1.s.17.alias= -unit.1.3.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.17.name=DataPort[17] -unit.1.3.port.-1.s.17.orderindex=-1 -unit.1.3.port.-1.s.17.visible=0 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-unit.1.3.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.79.name=DataPort[79] -unit.1.3.port.-1.s.79.orderindex=-1 -unit.1.3.port.-1.s.79.visible=0 -unit.1.3.port.-1.s.8.alias= -unit.1.3.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.8.name=DataPort[8] -unit.1.3.port.-1.s.8.orderindex=-1 -unit.1.3.port.-1.s.8.visible=0 -unit.1.3.port.-1.s.80.alias= -unit.1.3.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.80.name=DataPort[80] -unit.1.3.port.-1.s.80.orderindex=-1 -unit.1.3.port.-1.s.80.visible=0 -unit.1.3.port.-1.s.81.alias= -unit.1.3.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.81.name=DataPort[81] -unit.1.3.port.-1.s.81.orderindex=-1 -unit.1.3.port.-1.s.81.visible=0 -unit.1.3.port.-1.s.82.alias= -unit.1.3.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.82.name=DataPort[82] -unit.1.3.port.-1.s.82.orderindex=-1 -unit.1.3.port.-1.s.82.visible=0 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-unit.1.3.port.-1.s.96.name=DataPort[96] -unit.1.3.port.-1.s.96.orderindex=-1 -unit.1.3.port.-1.s.96.visible=0 -unit.1.3.port.-1.s.97.alias= -unit.1.3.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.97.name=DataPort[97] -unit.1.3.port.-1.s.97.orderindex=-1 -unit.1.3.port.-1.s.97.visible=0 -unit.1.3.port.-1.s.98.alias= -unit.1.3.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.98.name=DataPort[98] -unit.1.3.port.-1.s.98.orderindex=-1 -unit.1.3.port.-1.s.98.visible=1 -unit.1.3.port.-1.s.99.alias= -unit.1.3.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.99.name=DataPort[99] -unit.1.3.port.-1.s.99.orderindex=-1 -unit.1.3.port.-1.s.99.visible=1 -unit.1.3.port.0.b.0.alias= -unit.1.3.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.3.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.b.0.name=TriggerPort0 -unit.1.3.port.0.b.0.orderindex=-1 -unit.1.3.port.0.b.0.radix=Hex -unit.1.3.port.0.b.0.signedOffset=0.0 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-unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.port.4.b.0.alias= -unit.1.3.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.b.0.name=TriggerPort4 -unit.1.3.port.4.b.0.orderindex=-1 -unit.1.3.port.4.b.0.radix=Hex -unit.1.3.port.4.b.0.signedOffset=0.0 -unit.1.3.port.4.b.0.signedPrecision=0 -unit.1.3.port.4.b.0.signedScaleFactor=1.0 -unit.1.3.port.4.b.0.unsignedOffset=0.0 -unit.1.3.port.4.b.0.unsignedPrecision=0 -unit.1.3.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.4.b.0.visible=1 -unit.1.3.port.4.buscount=1 -unit.1.3.port.4.channelcount=32 -unit.1.3.port.4.s.0.alias= -unit.1.3.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.0.name=TriggerPort4[0] -unit.1.3.port.4.s.0.orderindex=-1 -unit.1.3.port.4.s.0.visible=1 -unit.1.3.port.4.s.1.alias= -unit.1.3.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.1.name=TriggerPort4[1] -unit.1.3.port.4.s.1.orderindex=-1 -unit.1.3.port.4.s.1.visible=1 -unit.1.3.port.4.s.10.alias= -unit.1.3.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.10.name=TriggerPort4[10] -unit.1.3.port.4.s.10.orderindex=-1 -unit.1.3.port.4.s.10.visible=1 -unit.1.3.port.4.s.11.alias= -unit.1.3.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.11.name=TriggerPort4[11] -unit.1.3.port.4.s.11.orderindex=-1 -unit.1.3.port.4.s.11.visible=1 -unit.1.3.port.4.s.12.alias= -unit.1.3.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.12.name=TriggerPort4[12] -unit.1.3.port.4.s.12.orderindex=-1 -unit.1.3.port.4.s.12.visible=1 -unit.1.3.port.4.s.13.alias= -unit.1.3.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.13.name=TriggerPort4[13] -unit.1.3.port.4.s.13.orderindex=-1 -unit.1.3.port.4.s.13.visible=1 -unit.1.3.port.4.s.14.alias= -unit.1.3.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.14.name=TriggerPort4[14] -unit.1.3.port.4.s.14.orderindex=-1 -unit.1.3.port.4.s.14.visible=1 -unit.1.3.port.4.s.15.alias= -unit.1.3.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.15.name=TriggerPort4[15] -unit.1.3.port.4.s.15.orderindex=-1 -unit.1.3.port.4.s.15.visible=1 -unit.1.3.port.4.s.16.alias= -unit.1.3.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.16.name=TriggerPort4[16] -unit.1.3.port.4.s.16.orderindex=-1 -unit.1.3.port.4.s.16.visible=1 -unit.1.3.port.4.s.17.alias= -unit.1.3.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.17.name=TriggerPort4[17] -unit.1.3.port.4.s.17.orderindex=-1 -unit.1.3.port.4.s.17.visible=1 -unit.1.3.port.4.s.18.alias= -unit.1.3.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.18.name=TriggerPort4[18] -unit.1.3.port.4.s.18.orderindex=-1 -unit.1.3.port.4.s.18.visible=1 -unit.1.3.port.4.s.19.alias= -unit.1.3.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.19.name=TriggerPort4[19] -unit.1.3.port.4.s.19.orderindex=-1 -unit.1.3.port.4.s.19.visible=1 -unit.1.3.port.4.s.2.alias= -unit.1.3.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.2.name=TriggerPort4[2] -unit.1.3.port.4.s.2.orderindex=-1 -unit.1.3.port.4.s.2.visible=1 -unit.1.3.port.4.s.20.alias= -unit.1.3.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.20.name=TriggerPort4[20] -unit.1.3.port.4.s.20.orderindex=-1 -unit.1.3.port.4.s.20.visible=1 -unit.1.3.port.4.s.21.alias= -unit.1.3.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.21.name=TriggerPort4[21] -unit.1.3.port.4.s.21.orderindex=-1 -unit.1.3.port.4.s.21.visible=1 -unit.1.3.port.4.s.22.alias= -unit.1.3.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.22.name=TriggerPort4[22] -unit.1.3.port.4.s.22.orderindex=-1 -unit.1.3.port.4.s.22.visible=1 -unit.1.3.port.4.s.23.alias= -unit.1.3.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.23.name=TriggerPort4[23] -unit.1.3.port.4.s.23.orderindex=-1 -unit.1.3.port.4.s.23.visible=1 -unit.1.3.port.4.s.24.alias= -unit.1.3.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.24.name=TriggerPort4[24] -unit.1.3.port.4.s.24.orderindex=-1 -unit.1.3.port.4.s.24.visible=1 -unit.1.3.port.4.s.25.alias= -unit.1.3.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.25.name=TriggerPort4[25] -unit.1.3.port.4.s.25.orderindex=-1 -unit.1.3.port.4.s.25.visible=1 -unit.1.3.port.4.s.26.alias= -unit.1.3.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.26.name=TriggerPort4[26] -unit.1.3.port.4.s.26.orderindex=-1 -unit.1.3.port.4.s.26.visible=1 -unit.1.3.port.4.s.27.alias= -unit.1.3.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.27.name=TriggerPort4[27] -unit.1.3.port.4.s.27.orderindex=-1 -unit.1.3.port.4.s.27.visible=1 -unit.1.3.port.4.s.28.alias= -unit.1.3.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.28.name=TriggerPort4[28] -unit.1.3.port.4.s.28.orderindex=-1 -unit.1.3.port.4.s.28.visible=1 -unit.1.3.port.4.s.29.alias= -unit.1.3.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.29.name=TriggerPort4[29] -unit.1.3.port.4.s.29.orderindex=-1 -unit.1.3.port.4.s.29.visible=1 -unit.1.3.port.4.s.3.alias= -unit.1.3.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.3.name=TriggerPort4[3] -unit.1.3.port.4.s.3.orderindex=-1 -unit.1.3.port.4.s.3.visible=1 -unit.1.3.port.4.s.30.alias= -unit.1.3.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.30.name=TriggerPort4[30] -unit.1.3.port.4.s.30.orderindex=-1 -unit.1.3.port.4.s.30.visible=1 -unit.1.3.port.4.s.31.alias= -unit.1.3.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.31.name=TriggerPort4[31] -unit.1.3.port.4.s.31.orderindex=-1 -unit.1.3.port.4.s.31.visible=1 -unit.1.3.port.4.s.4.alias= -unit.1.3.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.4.name=TriggerPort4[4] -unit.1.3.port.4.s.4.orderindex=-1 -unit.1.3.port.4.s.4.visible=1 -unit.1.3.port.4.s.5.alias= -unit.1.3.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.5.name=TriggerPort4[5] -unit.1.3.port.4.s.5.orderindex=-1 -unit.1.3.port.4.s.5.visible=1 -unit.1.3.port.4.s.6.alias= -unit.1.3.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.6.name=TriggerPort4[6] -unit.1.3.port.4.s.6.orderindex=-1 -unit.1.3.port.4.s.6.visible=1 -unit.1.3.port.4.s.7.alias= -unit.1.3.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.7.name=TriggerPort4[7] -unit.1.3.port.4.s.7.orderindex=-1 -unit.1.3.port.4.s.7.visible=1 -unit.1.3.port.4.s.8.alias= -unit.1.3.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.8.name=TriggerPort4[8] -unit.1.3.port.4.s.8.orderindex=-1 -unit.1.3.port.4.s.8.visible=1 -unit.1.3.port.4.s.9.alias= -unit.1.3.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.9.name=TriggerPort4[9] -unit.1.3.port.4.s.9.orderindex=-1 -unit.1.3.port.4.s.9.visible=1 -unit.1.3.portcount=5 -unit.1.3.rep_trigger.clobber=1 -unit.1.3.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/D\:\\home\\lerwys\\Repos\\bpm-sw\\hdl\\top\\ml_605\\dbe_bpm_fmc516 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-unit.1.4.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.84.name=DataPort[84] -unit.1.4.port.-1.s.84.orderindex=-1 -unit.1.4.port.-1.s.84.visible=0 -unit.1.4.port.-1.s.85.alias= -unit.1.4.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.85.name=DataPort[85] -unit.1.4.port.-1.s.85.orderindex=-1 -unit.1.4.port.-1.s.85.visible=0 -unit.1.4.port.-1.s.86.alias= -unit.1.4.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.86.name=DataPort[86] -unit.1.4.port.-1.s.86.orderindex=-1 -unit.1.4.port.-1.s.86.visible=0 -unit.1.4.port.-1.s.87.alias= -unit.1.4.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.87.name=DataPort[87] -unit.1.4.port.-1.s.87.orderindex=-1 -unit.1.4.port.-1.s.87.visible=0 -unit.1.4.port.-1.s.88.alias= -unit.1.4.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.88.name=DataPort[88] -unit.1.4.port.-1.s.88.orderindex=-1 -unit.1.4.port.-1.s.88.visible=0 -unit.1.4.port.-1.s.89.alias= -unit.1.4.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.89.name=DataPort[89] -unit.1.4.port.-1.s.89.orderindex=-1 -unit.1.4.port.-1.s.89.visible=0 -unit.1.4.port.-1.s.9.alias= -unit.1.4.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.9.name=DataPort[9] -unit.1.4.port.-1.s.9.orderindex=-1 -unit.1.4.port.-1.s.9.visible=0 -unit.1.4.port.-1.s.90.alias= -unit.1.4.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.90.name=DataPort[90] -unit.1.4.port.-1.s.90.orderindex=-1 -unit.1.4.port.-1.s.90.visible=0 -unit.1.4.port.-1.s.91.alias= -unit.1.4.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.91.name=DataPort[91] -unit.1.4.port.-1.s.91.orderindex=-1 -unit.1.4.port.-1.s.91.visible=0 -unit.1.4.port.-1.s.92.alias= -unit.1.4.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.92.name=DataPort[92] -unit.1.4.port.-1.s.92.orderindex=-1 -unit.1.4.port.-1.s.92.visible=0 -unit.1.4.port.-1.s.93.alias= -unit.1.4.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.93.name=DataPort[93] -unit.1.4.port.-1.s.93.orderindex=-1 -unit.1.4.port.-1.s.93.visible=0 -unit.1.4.port.-1.s.94.alias= -unit.1.4.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.94.name=DataPort[94] -unit.1.4.port.-1.s.94.orderindex=-1 -unit.1.4.port.-1.s.94.visible=0 -unit.1.4.port.-1.s.95.alias= -unit.1.4.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.95.name=DataPort[95] -unit.1.4.port.-1.s.95.orderindex=-1 -unit.1.4.port.-1.s.95.visible=0 -unit.1.4.port.-1.s.96.alias= -unit.1.4.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.96.name=DataPort[96] -unit.1.4.port.-1.s.96.orderindex=-1 -unit.1.4.port.-1.s.96.visible=0 -unit.1.4.port.-1.s.97.alias= -unit.1.4.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.97.name=DataPort[97] -unit.1.4.port.-1.s.97.orderindex=-1 -unit.1.4.port.-1.s.97.visible=0 -unit.1.4.port.-1.s.98.alias= -unit.1.4.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.98.name=DataPort[98] -unit.1.4.port.-1.s.98.orderindex=-1 -unit.1.4.port.-1.s.98.visible=0 -unit.1.4.port.-1.s.99.alias= -unit.1.4.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.99.name=DataPort[99] -unit.1.4.port.-1.s.99.orderindex=-1 -unit.1.4.port.-1.s.99.visible=0 -unit.1.4.port.0.b.0.alias= -unit.1.4.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.4.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.b.0.name=TriggerPort0 -unit.1.4.port.0.b.0.orderindex=-1 -unit.1.4.port.0.b.0.radix=Hex -unit.1.4.port.0.b.0.signedOffset=0.0 -unit.1.4.port.0.b.0.signedPrecision=0 -unit.1.4.port.0.b.0.signedScaleFactor=1.0 -unit.1.4.port.0.b.0.unsignedOffset=0.0 -unit.1.4.port.0.b.0.unsignedPrecision=0 -unit.1.4.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.0.b.0.visible=1 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-unit.1.4.port.0.s.4.orderindex=-1 -unit.1.4.port.0.s.4.visible=1 -unit.1.4.port.0.s.5.alias= -unit.1.4.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.5.name=TriggerPort0[5] -unit.1.4.port.0.s.5.orderindex=-1 -unit.1.4.port.0.s.5.visible=1 -unit.1.4.port.0.s.6.alias= -unit.1.4.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.6.name=TriggerPort0[6] -unit.1.4.port.0.s.6.orderindex=-1 -unit.1.4.port.0.s.6.visible=1 -unit.1.4.port.0.s.7.alias= -unit.1.4.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.7.name=TriggerPort0[7] -unit.1.4.port.0.s.7.orderindex=-1 -unit.1.4.port.0.s.7.visible=1 -unit.1.4.port.1.b.0.alias= -unit.1.4.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex 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-unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 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-unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.4.rep_trigger.signals=All Signals/Buses -unit.1.4.samplesPerTrigger=1 -unit.1.4.triggerCapture=1 -unit.1.4.triggerNSamplesTS=0 -unit.1.4.triggerPosition=0 -unit.1.4.triggerWindowCount=1 -unit.1.4.triggerWindowDepth=1024 -unit.1.4.triggerWindowTS=0 -unit.1.4.username=fofb_amp -unit.1.4.waveform.count=4 -unit.1.4.waveform.posn.0.channel=2147483646 -unit.1.4.waveform.posn.0.name=dsp_fofb_amp_ch0 -unit.1.4.waveform.posn.0.radix=3 -unit.1.4.waveform.posn.0.type=bus -unit.1.4.waveform.posn.1.channel=2147483646 -unit.1.4.waveform.posn.1.name=dsp_fofb_amp_ch1 -unit.1.4.waveform.posn.1.radix=3 -unit.1.4.waveform.posn.1.type=bus -unit.1.4.waveform.posn.10.channel=103 -unit.1.4.waveform.posn.10.name=DataPort[103] -unit.1.4.waveform.posn.10.type=signal -unit.1.4.waveform.posn.11.channel=103 -unit.1.4.waveform.posn.11.name=DataPort[103] -unit.1.4.waveform.posn.11.type=signal -unit.1.4.waveform.posn.12.channel=103 -unit.1.4.waveform.posn.12.name=DataPort[103] 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-unit.1.4.waveform.posn.2.radix=3 -unit.1.4.waveform.posn.2.type=bus -unit.1.4.waveform.posn.20.channel=103 -unit.1.4.waveform.posn.20.name=DataPort[103] -unit.1.4.waveform.posn.20.type=signal -unit.1.4.waveform.posn.21.channel=103 -unit.1.4.waveform.posn.21.name=DataPort[103] -unit.1.4.waveform.posn.21.type=signal -unit.1.4.waveform.posn.22.channel=103 -unit.1.4.waveform.posn.22.name=DataPort[103] -unit.1.4.waveform.posn.22.type=signal -unit.1.4.waveform.posn.23.channel=103 -unit.1.4.waveform.posn.23.name=DataPort[103] -unit.1.4.waveform.posn.23.type=signal -unit.1.4.waveform.posn.24.channel=103 -unit.1.4.waveform.posn.24.name=DataPort[103] -unit.1.4.waveform.posn.24.type=signal -unit.1.4.waveform.posn.25.channel=103 -unit.1.4.waveform.posn.25.name=DataPort[103] -unit.1.4.waveform.posn.25.type=signal -unit.1.4.waveform.posn.26.channel=103 -unit.1.4.waveform.posn.26.name=DataPort[103] -unit.1.4.waveform.posn.26.type=signal -unit.1.4.waveform.posn.27.channel=103 -unit.1.4.waveform.posn.27.name=DataPort[103] -unit.1.4.waveform.posn.27.type=signal -unit.1.4.waveform.posn.28.channel=103 -unit.1.4.waveform.posn.28.name=DataPort[103] -unit.1.4.waveform.posn.28.type=signal -unit.1.4.waveform.posn.29.channel=2147483646 -unit.1.4.waveform.posn.29.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.29.radix=3 -unit.1.4.waveform.posn.29.type=bus -unit.1.4.waveform.posn.3.channel=2147483646 -unit.1.4.waveform.posn.3.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.3.radix=3 -unit.1.4.waveform.posn.3.type=bus -unit.1.4.waveform.posn.30.channel=2147483646 -unit.1.4.waveform.posn.30.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.30.radix=3 -unit.1.4.waveform.posn.30.type=bus -unit.1.4.waveform.posn.31.channel=2147483646 -unit.1.4.waveform.posn.31.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.31.radix=3 -unit.1.4.waveform.posn.31.type=bus -unit.1.4.waveform.posn.32.channel=2147483646 -unit.1.4.waveform.posn.32.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.32.radix=3 -unit.1.4.waveform.posn.32.type=bus -unit.1.4.waveform.posn.33.channel=133 -unit.1.4.waveform.posn.33.name=DataPort[133] -unit.1.4.waveform.posn.33.type=signal -unit.1.4.waveform.posn.34.channel=134 -unit.1.4.waveform.posn.34.name=DataPort[134] -unit.1.4.waveform.posn.34.type=signal -unit.1.4.waveform.posn.35.channel=135 -unit.1.4.waveform.posn.35.name=DataPort[135] -unit.1.4.waveform.posn.35.type=signal -unit.1.4.waveform.posn.36.channel=2147483646 -unit.1.4.waveform.posn.36.name=dsp_fofb_amp_ch0 -unit.1.4.waveform.posn.36.radix=3 -unit.1.4.waveform.posn.36.type=bus -unit.1.4.waveform.posn.37.channel=2147483646 -unit.1.4.waveform.posn.37.name=dsp_fofb_amp_ch1 -unit.1.4.waveform.posn.37.radix=3 -unit.1.4.waveform.posn.37.type=bus -unit.1.4.waveform.posn.38.channel=2147483646 -unit.1.4.waveform.posn.38.name=dsp_fofb_amp_ch2 -unit.1.4.waveform.posn.38.radix=3 -unit.1.4.waveform.posn.38.type=bus -unit.1.4.waveform.posn.39.channel=2147483646 -unit.1.4.waveform.posn.39.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.39.radix=3 -unit.1.4.waveform.posn.39.type=bus -unit.1.4.waveform.posn.4.channel=103 -unit.1.4.waveform.posn.4.name=DataPort[103] -unit.1.4.waveform.posn.4.type=signal -unit.1.4.waveform.posn.5.channel=103 -unit.1.4.waveform.posn.5.name=DataPort[103] -unit.1.4.waveform.posn.5.type=signal -unit.1.4.waveform.posn.6.channel=103 -unit.1.4.waveform.posn.6.name=DataPort[103] -unit.1.4.waveform.posn.6.type=signal -unit.1.4.waveform.posn.7.channel=103 -unit.1.4.waveform.posn.7.name=DataPort[103] -unit.1.4.waveform.posn.7.type=signal -unit.1.4.waveform.posn.8.channel=103 -unit.1.4.waveform.posn.8.name=DataPort[103] -unit.1.4.waveform.posn.8.type=signal -unit.1.4.waveform.posn.9.channel=103 -unit.1.4.waveform.posn.9.name=DataPort[103] -unit.1.4.waveform.posn.9.type=signal -unit.1.5.0.HEIGHT0=0.5826514 -unit.1.5.0.TriggerRow0=1 -unit.1.5.0.TriggerRow1=1 -unit.1.5.0.TriggerRow2=1 -unit.1.5.0.WIDTH0=0.67969924 -unit.1.5.0.X0=0.034586467 -unit.1.5.0.Y0=0.0 -unit.1.5.1.HEIGHT1=0.7839607 -unit.1.5.1.WIDTH1=0.6263158 -unit.1.5.1.X1=0.018796992 -unit.1.5.1.Y1=0.055646483 -unit.1.5.5.HEIGHT5=0.9361702 -unit.1.5.5.WIDTH5=1.137594 -unit.1.5.5.X5=0.029323308 -unit.1.5.5.Y5=0.014729951 -unit.1.5.MFBitsA0=1XXXXXXX -unit.1.5.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsB0=00000000 -unit.1.5.MFBitsB1=00000000000000000000000000000000 -unit.1.5.MFBitsB2=00000000000000000000000000000000 -unit.1.5.MFBitsB3=00000000000000000000000000000000 -unit.1.5.MFBitsB4=00000000000000000000000000000000 -unit.1.5.MFCompareA0=0 -unit.1.5.MFCompareA1=0 -unit.1.5.MFCompareA2=0 -unit.1.5.MFCompareA3=0 -unit.1.5.MFCompareA4=0 -unit.1.5.MFCompareB0=999 -unit.1.5.MFCompareB1=999 -unit.1.5.MFCompareB2=999 -unit.1.5.MFCompareB3=999 -unit.1.5.MFCompareB4=999 -unit.1.5.MFCount=5 -unit.1.5.MFDisplay0=0 -unit.1.5.MFDisplay1=0 -unit.1.5.MFDisplay2=0 -unit.1.5.MFDisplay3=0 -unit.1.5.MFDisplay4=0 -unit.1.5.MFEventType0=3 -unit.1.5.MFEventType1=3 -unit.1.5.MFEventType2=3 -unit.1.5.MFEventType3=3 -unit.1.5.MFEventType4=3 -unit.1.5.RunMode=SINGLE RUN -unit.1.5.SQCondition=M0 -unit.1.5.SQContiguous0=0 -unit.1.5.SequencerOn=0 -unit.1.5.TCActive=0 -unit.1.5.TCAdvanced0=0 -unit.1.5.TCCondition0_0=M0 -unit.1.5.TCCondition0_1= -unit.1.5.TCConditionType0=0 -unit.1.5.TCCount=1 -unit.1.5.TCEventCount0=1 -unit.1.5.TCEventType0=3 -unit.1.5.TCName0=TriggerCondition0 -unit.1.5.TCOutputEnable0=0 -unit.1.5.TCOutputHigh0=1 -unit.1.5.TCOutputMode0=0 -unit.1.5.browser_tree_state=1 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=1 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.coretype=ILA -unit.1.5.eventCount0=1 -unit.1.5.eventCount1=1 -unit.1.5.eventCount2=1 -unit.1.5.eventCount3=1 -unit.1.5.eventCount4=1 -unit.1.5.plotBusColor0=-10066177 -unit.1.5.plotBusColor1=-3355648 -unit.1.5.plotBusColor2=-16777012 -unit.1.5.plotBusColor3=-52429 -unit.1.5.plotBusCount=4 -unit.1.5.plotBusName0=dsp_q_fofb -unit.1.5.plotBusName1=dsp_sum_fofb -unit.1.5.plotBusName2=dsp_x_fofb -unit.1.5.plotBusName3=dsp_y_fofb -unit.1.5.plotBusX=dsp_q_fofb -unit.1.5.plotBusY=dsp_sum_fofb -unit.1.5.plotDataTimeMode=1 -unit.1.5.plotDisplayMode=line -unit.1.5.plotMaxX=0.0 -unit.1.5.plotMaxY=0.0 -unit.1.5.plotMinX=0.0 -unit.1.5.plotMinY=0.0 -unit.1.5.plotSelectedBus=8 -unit.1.5.port.-1.b.0.alias=dsp_q_fofb -unit.1.5.port.-1.b.0.channellist=72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 -unit.1.5.port.-1.b.0.color=java.awt.Color[r\=102,g\=102,b\=255] -unit.1.5.port.-1.b.0.name=DataPort -unit.1.5.port.-1.b.0.orderindex=-1 -unit.1.5.port.-1.b.0.radix=Signed -unit.1.5.port.-1.b.0.signedOffset=0.0 -unit.1.5.port.-1.b.0.signedPrecision=0 -unit.1.5.port.-1.b.0.signedScaleFactor=1.0 -unit.1.5.port.-1.b.0.tokencount=0 -unit.1.5.port.-1.b.0.unsignedOffset=0.0 -unit.1.5.port.-1.b.0.unsignedPrecision=0 -unit.1.5.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.0.visible=1 -unit.1.5.port.-1.b.1.alias=dsp_sum_fofb -unit.1.5.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 -unit.1.5.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.5.port.-1.b.1.name=DataPort -unit.1.5.port.-1.b.1.orderindex=-1 -unit.1.5.port.-1.b.1.radix=Signed -unit.1.5.port.-1.b.1.signedOffset=0.0 -unit.1.5.port.-1.b.1.signedPrecision=0 -unit.1.5.port.-1.b.1.signedScaleFactor=1.0 -unit.1.5.port.-1.b.1.tokencount=0 -unit.1.5.port.-1.b.1.unsignedOffset=0.0 -unit.1.5.port.-1.b.1.unsignedPrecision=0 -unit.1.5.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.1.visible=1 -unit.1.5.port.-1.b.2.alias=dsp_x_fofb -unit.1.5.port.-1.b.2.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 -unit.1.5.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=204] -unit.1.5.port.-1.b.2.name=DataPort -unit.1.5.port.-1.b.2.orderindex=-1 -unit.1.5.port.-1.b.2.radix=Signed -unit.1.5.port.-1.b.2.signedOffset=0.0 -unit.1.5.port.-1.b.2.signedPrecision=0 -unit.1.5.port.-1.b.2.signedScaleFactor=1.0 -unit.1.5.port.-1.b.2.tokencount=0 -unit.1.5.port.-1.b.2.unsignedOffset=0.0 -unit.1.5.port.-1.b.2.unsignedPrecision=0 -unit.1.5.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.2.visible=1 -unit.1.5.port.-1.b.3.alias=dsp_y_fofb -unit.1.5.port.-1.b.3.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 -unit.1.5.port.-1.b.3.color=java.awt.Color[r\=255,g\=51,b\=51] -unit.1.5.port.-1.b.3.name=DataPort -unit.1.5.port.-1.b.3.orderindex=-1 -unit.1.5.port.-1.b.3.radix=Signed -unit.1.5.port.-1.b.3.signedOffset=0.0 -unit.1.5.port.-1.b.3.signedPrecision=0 -unit.1.5.port.-1.b.3.signedScaleFactor=1.0 -unit.1.5.port.-1.b.3.tokencount=0 -unit.1.5.port.-1.b.3.unsignedOffset=0.0 -unit.1.5.port.-1.b.3.unsignedPrecision=0 -unit.1.5.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.3.visible=1 -unit.1.5.port.-1.buscount=4 -unit.1.5.port.-1.channelcount=136 -unit.1.5.port.-1.s.0.alias= -unit.1.5.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.0.name=DataPort[0] -unit.1.5.port.-1.s.0.orderindex=-1 -unit.1.5.port.-1.s.0.visible=1 -unit.1.5.port.-1.s.1.alias= -unit.1.5.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.1.name=DataPort[1] -unit.1.5.port.-1.s.1.orderindex=-1 -unit.1.5.port.-1.s.1.visible=1 -unit.1.5.port.-1.s.10.alias= -unit.1.5.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.10.name=DataPort[10] -unit.1.5.port.-1.s.10.orderindex=-1 -unit.1.5.port.-1.s.10.visible=0 -unit.1.5.port.-1.s.100.alias= -unit.1.5.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.100.name=DataPort[100] -unit.1.5.port.-1.s.100.orderindex=-1 -unit.1.5.port.-1.s.100.visible=1 -unit.1.5.port.-1.s.101.alias= -unit.1.5.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.101.name=DataPort[101] -unit.1.5.port.-1.s.101.orderindex=-1 -unit.1.5.port.-1.s.101.visible=1 -unit.1.5.port.-1.s.102.alias= -unit.1.5.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.102.name=DataPort[102] -unit.1.5.port.-1.s.102.orderindex=-1 -unit.1.5.port.-1.s.102.visible=1 -unit.1.5.port.-1.s.103.alias= -unit.1.5.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.103.name=DataPort[103] -unit.1.5.port.-1.s.103.orderindex=-1 -unit.1.5.port.-1.s.103.visible=1 -unit.1.5.port.-1.s.104.alias= -unit.1.5.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.104.name=DataPort[104] -unit.1.5.port.-1.s.104.orderindex=-1 -unit.1.5.port.-1.s.104.visible=0 -unit.1.5.port.-1.s.105.alias= -unit.1.5.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.105.name=DataPort[105] -unit.1.5.port.-1.s.105.orderindex=-1 -unit.1.5.port.-1.s.105.visible=0 -unit.1.5.port.-1.s.106.alias= -unit.1.5.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.106.name=DataPort[106] -unit.1.5.port.-1.s.106.orderindex=-1 -unit.1.5.port.-1.s.106.visible=0 -unit.1.5.port.-1.s.107.alias= -unit.1.5.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.107.name=DataPort[107] -unit.1.5.port.-1.s.107.orderindex=-1 -unit.1.5.port.-1.s.107.visible=0 -unit.1.5.port.-1.s.108.alias= -unit.1.5.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.108.name=DataPort[108] -unit.1.5.port.-1.s.108.orderindex=-1 -unit.1.5.port.-1.s.108.visible=0 -unit.1.5.port.-1.s.109.alias= -unit.1.5.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.109.name=DataPort[109] -unit.1.5.port.-1.s.109.orderindex=-1 -unit.1.5.port.-1.s.109.visible=0 -unit.1.5.port.-1.s.11.alias= -unit.1.5.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.5.port.0.s.3.orderindex=-1 -unit.1.5.port.0.s.3.visible=1 -unit.1.5.port.0.s.4.alias= -unit.1.5.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.4.name=TriggerPort0[4] -unit.1.5.port.0.s.4.orderindex=-1 -unit.1.5.port.0.s.4.visible=1 -unit.1.5.port.0.s.5.alias= -unit.1.5.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.5.name=TriggerPort0[5] -unit.1.5.port.0.s.5.orderindex=-1 -unit.1.5.port.0.s.5.visible=1 -unit.1.5.port.0.s.6.alias= -unit.1.5.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.6.name=TriggerPort0[6] -unit.1.5.port.0.s.6.orderindex=-1 -unit.1.5.port.0.s.6.visible=1 -unit.1.5.port.0.s.7.alias= -unit.1.5.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.7.name=TriggerPort0[7] -unit.1.5.port.0.s.7.orderindex=-1 -unit.1.5.port.0.s.7.visible=1 -unit.1.5.port.1.b.0.alias= -unit.1.5.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.b.0.name=TriggerPort1 -unit.1.5.port.1.b.0.orderindex=-1 -unit.1.5.port.1.b.0.radix=Hex -unit.1.5.port.1.b.0.signedOffset=0.0 -unit.1.5.port.1.b.0.signedPrecision=0 -unit.1.5.port.1.b.0.signedScaleFactor=1.0 -unit.1.5.port.1.b.0.unsignedOffset=0.0 -unit.1.5.port.1.b.0.unsignedPrecision=0 -unit.1.5.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.1.b.0.visible=1 -unit.1.5.port.1.buscount=1 -unit.1.5.port.1.channelcount=32 -unit.1.5.port.1.s.0.alias= -unit.1.5.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.0.name=TriggerPort1[0] -unit.1.5.port.1.s.0.orderindex=-1 -unit.1.5.port.1.s.0.visible=1 -unit.1.5.port.1.s.1.alias= -unit.1.5.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.1.name=TriggerPort1[1] -unit.1.5.port.1.s.1.orderindex=-1 -unit.1.5.port.1.s.1.visible=1 -unit.1.5.port.1.s.10.alias= -unit.1.5.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.10.name=TriggerPort1[10] -unit.1.5.port.1.s.10.orderindex=-1 -unit.1.5.port.1.s.10.visible=1 -unit.1.5.port.1.s.11.alias= -unit.1.5.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.11.name=TriggerPort1[11] -unit.1.5.port.1.s.11.orderindex=-1 -unit.1.5.port.1.s.11.visible=1 -unit.1.5.port.1.s.12.alias= -unit.1.5.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.12.name=TriggerPort1[12] -unit.1.5.port.1.s.12.orderindex=-1 -unit.1.5.port.1.s.12.visible=1 -unit.1.5.port.1.s.13.alias= -unit.1.5.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.13.name=TriggerPort1[13] -unit.1.5.port.1.s.13.orderindex=-1 -unit.1.5.port.1.s.13.visible=1 -unit.1.5.port.1.s.14.alias= -unit.1.5.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.14.name=TriggerPort1[14] -unit.1.5.port.1.s.14.orderindex=-1 -unit.1.5.port.1.s.14.visible=1 -unit.1.5.port.1.s.15.alias= -unit.1.5.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.15.name=TriggerPort1[15] -unit.1.5.port.1.s.15.orderindex=-1 -unit.1.5.port.1.s.15.visible=1 -unit.1.5.port.1.s.16.alias= -unit.1.5.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.16.name=TriggerPort1[16] -unit.1.5.port.1.s.16.orderindex=-1 -unit.1.5.port.1.s.16.visible=1 -unit.1.5.port.1.s.17.alias= -unit.1.5.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.17.name=TriggerPort1[17] -unit.1.5.port.1.s.17.orderindex=-1 -unit.1.5.port.1.s.17.visible=1 -unit.1.5.port.1.s.18.alias= -unit.1.5.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.18.name=TriggerPort1[18] -unit.1.5.port.1.s.18.orderindex=-1 -unit.1.5.port.1.s.18.visible=1 -unit.1.5.port.1.s.19.alias= -unit.1.5.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.19.name=TriggerPort1[19] -unit.1.5.port.1.s.19.orderindex=-1 -unit.1.5.port.1.s.19.visible=1 -unit.1.5.port.1.s.2.alias= -unit.1.5.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.2.name=TriggerPort1[2] -unit.1.5.port.1.s.2.orderindex=-1 -unit.1.5.port.1.s.2.visible=1 -unit.1.5.port.1.s.20.alias= -unit.1.5.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.20.name=TriggerPort1[20] -unit.1.5.port.1.s.20.orderindex=-1 -unit.1.5.port.1.s.20.visible=1 -unit.1.5.port.1.s.21.alias= -unit.1.5.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.21.name=TriggerPort1[21] -unit.1.5.port.1.s.21.orderindex=-1 -unit.1.5.port.1.s.21.visible=1 -unit.1.5.port.1.s.22.alias= -unit.1.5.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.22.name=TriggerPort1[22] -unit.1.5.port.1.s.22.orderindex=-1 -unit.1.5.port.1.s.22.visible=1 -unit.1.5.port.1.s.23.alias= -unit.1.5.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.23.name=TriggerPort1[23] -unit.1.5.port.1.s.23.orderindex=-1 -unit.1.5.port.1.s.23.visible=1 -unit.1.5.port.1.s.24.alias= -unit.1.5.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.24.name=TriggerPort1[24] -unit.1.5.port.1.s.24.orderindex=-1 -unit.1.5.port.1.s.24.visible=1 -unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 -unit.1.5.port.3.s.16.alias= -unit.1.5.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.16.name=TriggerPort3[16] -unit.1.5.port.3.s.16.orderindex=-1 -unit.1.5.port.3.s.16.visible=1 -unit.1.5.port.3.s.17.alias= -unit.1.5.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.17.name=TriggerPort3[17] -unit.1.5.port.3.s.17.orderindex=-1 -unit.1.5.port.3.s.17.visible=1 -unit.1.5.port.3.s.18.alias= -unit.1.5.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.18.name=TriggerPort3[18] -unit.1.5.port.3.s.18.orderindex=-1 -unit.1.5.port.3.s.18.visible=1 -unit.1.5.port.3.s.19.alias= -unit.1.5.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.19.name=TriggerPort3[19] -unit.1.5.port.3.s.19.orderindex=-1 -unit.1.5.port.3.s.19.visible=1 -unit.1.5.port.3.s.2.alias= -unit.1.5.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.2.name=TriggerPort3[2] -unit.1.5.port.3.s.2.orderindex=-1 -unit.1.5.port.3.s.2.visible=1 -unit.1.5.port.3.s.20.alias= -unit.1.5.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.20.name=TriggerPort3[20] -unit.1.5.port.3.s.20.orderindex=-1 -unit.1.5.port.3.s.20.visible=1 -unit.1.5.port.3.s.21.alias= -unit.1.5.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.21.name=TriggerPort3[21] -unit.1.5.port.3.s.21.orderindex=-1 -unit.1.5.port.3.s.21.visible=1 -unit.1.5.port.3.s.22.alias= -unit.1.5.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.22.name=TriggerPort3[22] -unit.1.5.port.3.s.22.orderindex=-1 -unit.1.5.port.3.s.22.visible=1 -unit.1.5.port.3.s.23.alias= -unit.1.5.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.23.name=TriggerPort3[23] -unit.1.5.port.3.s.23.orderindex=-1 -unit.1.5.port.3.s.23.visible=1 -unit.1.5.port.3.s.24.alias= -unit.1.5.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.24.name=TriggerPort3[24] -unit.1.5.port.3.s.24.orderindex=-1 -unit.1.5.port.3.s.24.visible=1 -unit.1.5.port.3.s.25.alias= -unit.1.5.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.25.name=TriggerPort3[25] -unit.1.5.port.3.s.25.orderindex=-1 -unit.1.5.port.3.s.25.visible=1 -unit.1.5.port.3.s.26.alias= -unit.1.5.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.26.name=TriggerPort3[26] -unit.1.5.port.3.s.26.orderindex=-1 -unit.1.5.port.3.s.26.visible=1 -unit.1.5.port.3.s.27.alias= -unit.1.5.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.27.name=TriggerPort3[27] -unit.1.5.port.3.s.27.orderindex=-1 -unit.1.5.port.3.s.27.visible=1 -unit.1.5.port.3.s.28.alias= -unit.1.5.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.28.name=TriggerPort3[28] -unit.1.5.port.3.s.28.orderindex=-1 -unit.1.5.port.3.s.28.visible=1 -unit.1.5.port.3.s.29.alias= -unit.1.5.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.29.name=TriggerPort3[29] -unit.1.5.port.3.s.29.orderindex=-1 -unit.1.5.port.3.s.29.visible=1 -unit.1.5.port.3.s.3.alias= -unit.1.5.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.3.name=TriggerPort3[3] -unit.1.5.port.3.s.3.orderindex=-1 -unit.1.5.port.3.s.3.visible=1 -unit.1.5.port.3.s.30.alias= -unit.1.5.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.30.name=TriggerPort3[30] -unit.1.5.port.3.s.30.orderindex=-1 -unit.1.5.port.3.s.30.visible=1 -unit.1.5.port.3.s.31.alias= -unit.1.5.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.31.name=TriggerPort3[31] -unit.1.5.port.3.s.31.orderindex=-1 -unit.1.5.port.3.s.31.visible=1 -unit.1.5.port.3.s.4.alias= -unit.1.5.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.4.name=TriggerPort3[4] -unit.1.5.port.3.s.4.orderindex=-1 -unit.1.5.port.3.s.4.visible=1 -unit.1.5.port.3.s.5.alias= -unit.1.5.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.5.name=TriggerPort3[5] -unit.1.5.port.3.s.5.orderindex=-1 -unit.1.5.port.3.s.5.visible=1 -unit.1.5.port.3.s.6.alias= -unit.1.5.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.6.name=TriggerPort3[6] -unit.1.5.port.3.s.6.orderindex=-1 -unit.1.5.port.3.s.6.visible=1 -unit.1.5.port.3.s.7.alias= -unit.1.5.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.7.name=TriggerPort3[7] -unit.1.5.port.3.s.7.orderindex=-1 -unit.1.5.port.3.s.7.visible=1 -unit.1.5.port.3.s.8.alias= -unit.1.5.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.8.name=TriggerPort3[8] -unit.1.5.port.3.s.8.orderindex=-1 -unit.1.5.port.3.s.8.visible=1 -unit.1.5.port.3.s.9.alias= -unit.1.5.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.9.name=TriggerPort3[9] -unit.1.5.port.3.s.9.orderindex=-1 -unit.1.5.port.3.s.9.visible=1 -unit.1.5.port.4.b.0.alias= -unit.1.5.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.b.0.name=TriggerPort4 -unit.1.5.port.4.b.0.orderindex=-1 -unit.1.5.port.4.b.0.radix=Hex -unit.1.5.port.4.b.0.signedOffset=0.0 -unit.1.5.port.4.b.0.signedPrecision=0 -unit.1.5.port.4.b.0.signedScaleFactor=1.0 -unit.1.5.port.4.b.0.unsignedOffset=0.0 -unit.1.5.port.4.b.0.unsignedPrecision=0 -unit.1.5.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.4.b.0.visible=1 -unit.1.5.port.4.buscount=1 -unit.1.5.port.4.channelcount=32 -unit.1.5.port.4.s.0.alias= -unit.1.5.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.0.name=TriggerPort4[0] -unit.1.5.port.4.s.0.orderindex=-1 -unit.1.5.port.4.s.0.visible=1 -unit.1.5.port.4.s.1.alias= -unit.1.5.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.1.name=TriggerPort4[1] -unit.1.5.port.4.s.1.orderindex=-1 -unit.1.5.port.4.s.1.visible=1 -unit.1.5.port.4.s.10.alias= -unit.1.5.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.10.name=TriggerPort4[10] -unit.1.5.port.4.s.10.orderindex=-1 -unit.1.5.port.4.s.10.visible=1 -unit.1.5.port.4.s.11.alias= -unit.1.5.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.11.name=TriggerPort4[11] -unit.1.5.port.4.s.11.orderindex=-1 -unit.1.5.port.4.s.11.visible=1 -unit.1.5.port.4.s.12.alias= -unit.1.5.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.12.name=TriggerPort4[12] -unit.1.5.port.4.s.12.orderindex=-1 -unit.1.5.port.4.s.12.visible=1 -unit.1.5.port.4.s.13.alias= -unit.1.5.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.13.name=TriggerPort4[13] -unit.1.5.port.4.s.13.orderindex=-1 -unit.1.5.port.4.s.13.visible=1 -unit.1.5.port.4.s.14.alias= -unit.1.5.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.14.name=TriggerPort4[14] -unit.1.5.port.4.s.14.orderindex=-1 -unit.1.5.port.4.s.14.visible=1 -unit.1.5.port.4.s.15.alias= -unit.1.5.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.15.name=TriggerPort4[15] -unit.1.5.port.4.s.15.orderindex=-1 -unit.1.5.port.4.s.15.visible=1 -unit.1.5.port.4.s.16.alias= -unit.1.5.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.16.name=TriggerPort4[16] -unit.1.5.port.4.s.16.orderindex=-1 -unit.1.5.port.4.s.16.visible=1 -unit.1.5.port.4.s.17.alias= -unit.1.5.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.17.name=TriggerPort4[17] -unit.1.5.port.4.s.17.orderindex=-1 -unit.1.5.port.4.s.17.visible=1 -unit.1.5.port.4.s.18.alias= -unit.1.5.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.18.name=TriggerPort4[18] -unit.1.5.port.4.s.18.orderindex=-1 -unit.1.5.port.4.s.18.visible=1 -unit.1.5.port.4.s.19.alias= -unit.1.5.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.19.name=TriggerPort4[19] -unit.1.5.port.4.s.19.orderindex=-1 -unit.1.5.port.4.s.19.visible=1 -unit.1.5.port.4.s.2.alias= -unit.1.5.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.2.name=TriggerPort4[2] -unit.1.5.port.4.s.2.orderindex=-1 -unit.1.5.port.4.s.2.visible=1 -unit.1.5.port.4.s.20.alias= -unit.1.5.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.20.name=TriggerPort4[20] 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-unit.1.5.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.3.name=TriggerPort4[3] -unit.1.5.port.4.s.3.orderindex=-1 -unit.1.5.port.4.s.3.visible=1 -unit.1.5.port.4.s.30.alias= -unit.1.5.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.30.name=TriggerPort4[30] -unit.1.5.port.4.s.30.orderindex=-1 -unit.1.5.port.4.s.30.visible=1 -unit.1.5.port.4.s.31.alias= -unit.1.5.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.31.name=TriggerPort4[31] -unit.1.5.port.4.s.31.orderindex=-1 -unit.1.5.port.4.s.31.visible=1 -unit.1.5.port.4.s.4.alias= -unit.1.5.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.4.name=TriggerPort4[4] -unit.1.5.port.4.s.4.orderindex=-1 -unit.1.5.port.4.s.4.visible=1 -unit.1.5.port.4.s.5.alias= -unit.1.5.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.5.name=TriggerPort4[5] -unit.1.5.port.4.s.5.orderindex=-1 -unit.1.5.port.4.s.5.visible=1 -unit.1.5.port.4.s.6.alias= -unit.1.5.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.6.name=TriggerPort4[6] -unit.1.5.port.4.s.6.orderindex=-1 -unit.1.5.port.4.s.6.visible=1 -unit.1.5.port.4.s.7.alias= -unit.1.5.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.7.name=TriggerPort4[7] -unit.1.5.port.4.s.7.orderindex=-1 -unit.1.5.port.4.s.7.visible=1 -unit.1.5.port.4.s.8.alias= -unit.1.5.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.8.name=TriggerPort4[8] -unit.1.5.port.4.s.8.orderindex=-1 -unit.1.5.port.4.s.8.visible=1 -unit.1.5.port.4.s.9.alias= -unit.1.5.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.9.name=TriggerPort4[9] -unit.1.5.port.4.s.9.orderindex=-1 -unit.1.5.port.4.s.9.visible=1 -unit.1.5.portcount=5 -unit.1.5.rep_trigger.clobber=1 -unit.1.5.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/D\:\\home\\lerwys\\Repos\\fmc-adc-hdl\\chipscope\\fmc130m\\acq -unit.1.5.rep_trigger.filename=dsp_acq -unit.1.5.rep_trigger.format=ASCII -unit.1.5.rep_trigger.loggingEnabled=0 -unit.1.5.rep_trigger.signals=Bus Plot Buses -unit.1.5.samplesPerTrigger=1 -unit.1.5.triggerCapture=1 -unit.1.5.triggerNSamplesTS=0 -unit.1.5.triggerPosition=0 -unit.1.5.triggerWindowCount=1 -unit.1.5.triggerWindowDepth=1024 -unit.1.5.triggerWindowTS=0 -unit.1.5.username=fofb_pos -unit.1.5.waveform.count=36 -unit.1.5.waveform.posn.0.channel=0 -unit.1.5.waveform.posn.0.name=DataPort[0] -unit.1.5.waveform.posn.0.type=signal -unit.1.5.waveform.posn.1.channel=1 -unit.1.5.waveform.posn.1.name=DataPort[1] -unit.1.5.waveform.posn.1.type=signal -unit.1.5.waveform.posn.10.channel=36 -unit.1.5.waveform.posn.10.name=DataPort[36] -unit.1.5.waveform.posn.10.type=signal -unit.1.5.waveform.posn.11.channel=37 -unit.1.5.waveform.posn.11.name=DataPort[37] -unit.1.5.waveform.posn.11.type=signal -unit.1.5.waveform.posn.12.channel=38 -unit.1.5.waveform.posn.12.name=DataPort[38] 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-unit.1.5.waveform.posn.4.name=DataPort[4] -unit.1.5.waveform.posn.4.type=signal -unit.1.5.waveform.posn.40.channel=2147483646 -unit.1.5.waveform.posn.40.name=dsp_y_fofb -unit.1.5.waveform.posn.40.radix=3 -unit.1.5.waveform.posn.40.type=bus -unit.1.5.waveform.posn.41.channel=2147483646 -unit.1.5.waveform.posn.41.name=dsp_y_fofb -unit.1.5.waveform.posn.41.radix=3 -unit.1.5.waveform.posn.41.type=bus -unit.1.5.waveform.posn.42.channel=2147483646 -unit.1.5.waveform.posn.42.name=dsp_y_fofb -unit.1.5.waveform.posn.42.radix=3 -unit.1.5.waveform.posn.42.type=bus -unit.1.5.waveform.posn.43.channel=2147483646 -unit.1.5.waveform.posn.43.name=dsp_y_fofb -unit.1.5.waveform.posn.43.radix=3 -unit.1.5.waveform.posn.43.type=bus -unit.1.5.waveform.posn.44.channel=2147483646 -unit.1.5.waveform.posn.44.name=dsp_y_fofb -unit.1.5.waveform.posn.44.radix=3 -unit.1.5.waveform.posn.44.type=bus -unit.1.5.waveform.posn.45.channel=2147483646 -unit.1.5.waveform.posn.45.name=dsp_y_fofb -unit.1.5.waveform.posn.45.radix=3 -unit.1.5.waveform.posn.45.type=bus -unit.1.5.waveform.posn.46.channel=2147483646 -unit.1.5.waveform.posn.46.name=dsp_y_fofb -unit.1.5.waveform.posn.46.radix=3 -unit.1.5.waveform.posn.46.type=bus -unit.1.5.waveform.posn.5.channel=5 -unit.1.5.waveform.posn.5.name=DataPort[5] -unit.1.5.waveform.posn.5.type=signal -unit.1.5.waveform.posn.6.channel=6 -unit.1.5.waveform.posn.6.name=DataPort[6] -unit.1.5.waveform.posn.6.type=signal -unit.1.5.waveform.posn.7.channel=7 -unit.1.5.waveform.posn.7.name=DataPort[7] -unit.1.5.waveform.posn.7.type=signal -unit.1.5.waveform.posn.8.channel=34 -unit.1.5.waveform.posn.8.name=DataPort[34] -unit.1.5.waveform.posn.8.type=signal -unit.1.5.waveform.posn.9.channel=35 -unit.1.5.waveform.posn.9.name=DataPort[35] -unit.1.5.waveform.posn.9.type=signal -unit.1.6.0.HEIGHT0=0.44517186 -unit.1.6.0.TriggerRow0=1 -unit.1.6.0.TriggerRow1=1 -unit.1.6.0.TriggerRow2=1 -unit.1.6.0.WIDTH0=0.77894735 -unit.1.6.0.X0=0.071428575 -unit.1.6.0.Y0=0.0 -unit.1.6.1.HEIGHT1=1.0 -unit.1.6.1.WIDTH1=0.9887218 -unit.1.6.1.X1=0.0 -unit.1.6.1.Y1=0.0 -unit.1.6.5.HEIGHT5=1.0 -unit.1.6.5.WIDTH5=1.0 -unit.1.6.5.X5=0.0 -unit.1.6.5.Y5=0.0 -unit.1.6.MFBitsA0=1XXXXXXX -unit.1.6.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsB0=00000000 -unit.1.6.MFBitsB1=00000000000000000000000000000000 -unit.1.6.MFBitsB2=00000000000000000000000000000000 -unit.1.6.MFBitsB3=00000000000000000000000000000000 -unit.1.6.MFBitsB4=00000000000000000000000000000000 -unit.1.6.MFCompareA0=0 -unit.1.6.MFCompareA1=0 -unit.1.6.MFCompareA2=0 -unit.1.6.MFCompareA3=0 -unit.1.6.MFCompareA4=0 -unit.1.6.MFCompareB0=999 -unit.1.6.MFCompareB1=999 -unit.1.6.MFCompareB2=999 -unit.1.6.MFCompareB3=999 -unit.1.6.MFCompareB4=999 -unit.1.6.MFCount=5 -unit.1.6.MFDisplay0=0 -unit.1.6.MFDisplay1=0 -unit.1.6.MFDisplay2=0 -unit.1.6.MFDisplay3=0 -unit.1.6.MFDisplay4=0 -unit.1.6.MFEventType0=3 -unit.1.6.MFEventType1=3 -unit.1.6.MFEventType2=3 -unit.1.6.MFEventType3=3 -unit.1.6.MFEventType4=3 -unit.1.6.RunMode=SINGLE RUN -unit.1.6.SQCondition=M0 -unit.1.6.SQContiguous0=0 -unit.1.6.SequencerOn=0 -unit.1.6.TCActive=0 -unit.1.6.TCAdvanced0=0 -unit.1.6.TCCondition0_0=M0 -unit.1.6.TCCondition0_1= -unit.1.6.TCConditionType0=0 -unit.1.6.TCCount=1 -unit.1.6.TCEventCount0=1 -unit.1.6.TCEventType0=3 -unit.1.6.TCName0=TriggerCondition0 -unit.1.6.TCOutputEnable0=0 -unit.1.6.TCOutputHigh0=1 -unit.1.6.TCOutputMode0=0 -unit.1.6.browser_tree_state=1 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=1 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.coretype=ILA -unit.1.6.eventCount0=1 -unit.1.6.eventCount1=1 -unit.1.6.eventCount2=1 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-unit.1.6.port.0.s.7.name=TriggerPort0[7] -unit.1.6.port.0.s.7.orderindex=-1 -unit.1.6.port.0.s.7.visible=1 -unit.1.6.port.1.b.0.alias= -unit.1.6.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.b.0.name=TriggerPort1 -unit.1.6.port.1.b.0.orderindex=-1 -unit.1.6.port.1.b.0.radix=Hex -unit.1.6.port.1.b.0.signedOffset=0.0 -unit.1.6.port.1.b.0.signedPrecision=0 -unit.1.6.port.1.b.0.signedScaleFactor=1.0 -unit.1.6.port.1.b.0.unsignedOffset=0.0 -unit.1.6.port.1.b.0.unsignedPrecision=0 -unit.1.6.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.1.b.0.visible=1 -unit.1.6.port.1.buscount=1 -unit.1.6.port.1.channelcount=32 -unit.1.6.port.1.s.0.alias= -unit.1.6.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.0.name=TriggerPort1[0] -unit.1.6.port.1.s.0.orderindex=-1 -unit.1.6.port.1.s.0.visible=1 -unit.1.6.port.1.s.1.alias= -unit.1.6.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.1.name=TriggerPort1[1] -unit.1.6.port.1.s.1.orderindex=-1 -unit.1.6.port.1.s.1.visible=1 -unit.1.6.port.1.s.10.alias= -unit.1.6.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.10.name=TriggerPort1[10] -unit.1.6.port.1.s.10.orderindex=-1 -unit.1.6.port.1.s.10.visible=1 -unit.1.6.port.1.s.11.alias= -unit.1.6.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.11.name=TriggerPort1[11] -unit.1.6.port.1.s.11.orderindex=-1 -unit.1.6.port.1.s.11.visible=1 -unit.1.6.port.1.s.12.alias= -unit.1.6.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.12.name=TriggerPort1[12] -unit.1.6.port.1.s.12.orderindex=-1 -unit.1.6.port.1.s.12.visible=1 -unit.1.6.port.1.s.13.alias= -unit.1.6.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.13.name=TriggerPort1[13] -unit.1.6.port.1.s.13.orderindex=-1 -unit.1.6.port.1.s.13.visible=1 -unit.1.6.port.1.s.14.alias= -unit.1.6.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.14.name=TriggerPort1[14] -unit.1.6.port.1.s.14.orderindex=-1 -unit.1.6.port.1.s.14.visible=1 -unit.1.6.port.1.s.15.alias= -unit.1.6.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.15.name=TriggerPort1[15] -unit.1.6.port.1.s.15.orderindex=-1 -unit.1.6.port.1.s.15.visible=1 -unit.1.6.port.1.s.16.alias= -unit.1.6.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.16.name=TriggerPort1[16] -unit.1.6.port.1.s.16.orderindex=-1 -unit.1.6.port.1.s.16.visible=1 -unit.1.6.port.1.s.17.alias= -unit.1.6.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.17.name=TriggerPort1[17] -unit.1.6.port.1.s.17.orderindex=-1 -unit.1.6.port.1.s.17.visible=1 -unit.1.6.port.1.s.18.alias= -unit.1.6.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.18.name=TriggerPort1[18] -unit.1.6.port.1.s.18.orderindex=-1 -unit.1.6.port.1.s.18.visible=1 -unit.1.6.port.1.s.19.alias= -unit.1.6.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.19.name=TriggerPort1[19] -unit.1.6.port.1.s.19.orderindex=-1 -unit.1.6.port.1.s.19.visible=1 -unit.1.6.port.1.s.2.alias= -unit.1.6.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.2.name=TriggerPort1[2] -unit.1.6.port.1.s.2.orderindex=-1 -unit.1.6.port.1.s.2.visible=1 -unit.1.6.port.1.s.20.alias= -unit.1.6.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.20.name=TriggerPort1[20] -unit.1.6.port.1.s.20.orderindex=-1 -unit.1.6.port.1.s.20.visible=1 -unit.1.6.port.1.s.21.alias= -unit.1.6.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.21.name=TriggerPort1[21] -unit.1.6.port.1.s.21.orderindex=-1 -unit.1.6.port.1.s.21.visible=1 -unit.1.6.port.1.s.22.alias= -unit.1.6.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.22.name=TriggerPort1[22] -unit.1.6.port.1.s.22.orderindex=-1 -unit.1.6.port.1.s.22.visible=1 -unit.1.6.port.1.s.23.alias= -unit.1.6.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.23.name=TriggerPort1[23] -unit.1.6.port.1.s.23.orderindex=-1 -unit.1.6.port.1.s.23.visible=1 -unit.1.6.port.1.s.24.alias= -unit.1.6.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.24.name=TriggerPort1[24] -unit.1.6.port.1.s.24.orderindex=-1 -unit.1.6.port.1.s.24.visible=1 -unit.1.6.port.1.s.25.alias= -unit.1.6.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.25.name=TriggerPort1[25] -unit.1.6.port.1.s.25.orderindex=-1 -unit.1.6.port.1.s.25.visible=1 -unit.1.6.port.1.s.26.alias= -unit.1.6.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.26.name=TriggerPort1[26] -unit.1.6.port.1.s.26.orderindex=-1 -unit.1.6.port.1.s.26.visible=1 -unit.1.6.port.1.s.27.alias= -unit.1.6.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.27.name=TriggerPort1[27] -unit.1.6.port.1.s.27.orderindex=-1 -unit.1.6.port.1.s.27.visible=1 -unit.1.6.port.1.s.28.alias= -unit.1.6.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.28.name=TriggerPort1[28] -unit.1.6.port.1.s.28.orderindex=-1 -unit.1.6.port.1.s.28.visible=1 -unit.1.6.port.1.s.29.alias= -unit.1.6.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.29.name=TriggerPort1[29] -unit.1.6.port.1.s.29.orderindex=-1 -unit.1.6.port.1.s.29.visible=1 -unit.1.6.port.1.s.3.alias= -unit.1.6.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.3.name=TriggerPort1[3] -unit.1.6.port.1.s.3.orderindex=-1 -unit.1.6.port.1.s.3.visible=1 -unit.1.6.port.1.s.30.alias= -unit.1.6.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.30.name=TriggerPort1[30] -unit.1.6.port.1.s.30.orderindex=-1 -unit.1.6.port.1.s.30.visible=1 -unit.1.6.port.1.s.31.alias= -unit.1.6.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.31.name=TriggerPort1[31] -unit.1.6.port.1.s.31.orderindex=-1 -unit.1.6.port.1.s.31.visible=1 -unit.1.6.port.1.s.4.alias= -unit.1.6.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.4.name=TriggerPort1[4] -unit.1.6.port.1.s.4.orderindex=-1 -unit.1.6.port.1.s.4.visible=1 -unit.1.6.port.1.s.5.alias= -unit.1.6.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.5.name=TriggerPort1[5] -unit.1.6.port.1.s.5.orderindex=-1 -unit.1.6.port.1.s.5.visible=1 -unit.1.6.port.1.s.6.alias= -unit.1.6.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.6.name=TriggerPort1[6] -unit.1.6.port.1.s.6.orderindex=-1 -unit.1.6.port.1.s.6.visible=1 -unit.1.6.port.1.s.7.alias= -unit.1.6.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.7.name=TriggerPort1[7] -unit.1.6.port.1.s.7.orderindex=-1 -unit.1.6.port.1.s.7.visible=1 -unit.1.6.port.1.s.8.alias= -unit.1.6.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.8.name=TriggerPort1[8] -unit.1.6.port.1.s.8.orderindex=-1 -unit.1.6.port.1.s.8.visible=1 -unit.1.6.port.1.s.9.alias= -unit.1.6.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.9.name=TriggerPort1[9] -unit.1.6.port.1.s.9.orderindex=-1 -unit.1.6.port.1.s.9.visible=1 -unit.1.6.port.2.b.0.alias= -unit.1.6.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.b.0.name=TriggerPort2 -unit.1.6.port.2.b.0.orderindex=-1 -unit.1.6.port.2.b.0.radix=Hex -unit.1.6.port.2.b.0.signedOffset=0.0 -unit.1.6.port.2.b.0.signedPrecision=0 -unit.1.6.port.2.b.0.signedScaleFactor=1.0 -unit.1.6.port.2.b.0.unsignedOffset=0.0 -unit.1.6.port.2.b.0.unsignedPrecision=0 -unit.1.6.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.2.b.0.visible=1 -unit.1.6.port.2.buscount=1 -unit.1.6.port.2.channelcount=32 -unit.1.6.port.2.s.0.alias= -unit.1.6.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.0.name=TriggerPort2[0] -unit.1.6.port.2.s.0.orderindex=-1 -unit.1.6.port.2.s.0.visible=1 -unit.1.6.port.2.s.1.alias= -unit.1.6.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.1.name=TriggerPort2[1] -unit.1.6.port.2.s.1.orderindex=-1 -unit.1.6.port.2.s.1.visible=1 -unit.1.6.port.2.s.10.alias= -unit.1.6.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.10.name=TriggerPort2[10] -unit.1.6.port.2.s.10.orderindex=-1 -unit.1.6.port.2.s.10.visible=1 -unit.1.6.port.2.s.11.alias= -unit.1.6.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.11.name=TriggerPort2[11] -unit.1.6.port.2.s.11.orderindex=-1 -unit.1.6.port.2.s.11.visible=1 -unit.1.6.port.2.s.12.alias= -unit.1.6.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.12.name=TriggerPort2[12] -unit.1.6.port.2.s.12.orderindex=-1 -unit.1.6.port.2.s.12.visible=1 -unit.1.6.port.2.s.13.alias= -unit.1.6.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.13.name=TriggerPort2[13] -unit.1.6.port.2.s.13.orderindex=-1 -unit.1.6.port.2.s.13.visible=1 -unit.1.6.port.2.s.14.alias= -unit.1.6.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.14.name=TriggerPort2[14] -unit.1.6.port.2.s.14.orderindex=-1 -unit.1.6.port.2.s.14.visible=1 -unit.1.6.port.2.s.15.alias= -unit.1.6.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.15.name=TriggerPort2[15] -unit.1.6.port.2.s.15.orderindex=-1 -unit.1.6.port.2.s.15.visible=1 -unit.1.6.port.2.s.16.alias= -unit.1.6.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.16.name=TriggerPort2[16] -unit.1.6.port.2.s.16.orderindex=-1 -unit.1.6.port.2.s.16.visible=1 -unit.1.6.port.2.s.17.alias= -unit.1.6.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.17.name=TriggerPort2[17] -unit.1.6.port.2.s.17.orderindex=-1 -unit.1.6.port.2.s.17.visible=1 -unit.1.6.port.2.s.18.alias= -unit.1.6.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.18.name=TriggerPort2[18] -unit.1.6.port.2.s.18.orderindex=-1 -unit.1.6.port.2.s.18.visible=1 -unit.1.6.port.2.s.19.alias= -unit.1.6.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.19.name=TriggerPort2[19] -unit.1.6.port.2.s.19.orderindex=-1 -unit.1.6.port.2.s.19.visible=1 -unit.1.6.port.2.s.2.alias= -unit.1.6.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.2.name=TriggerPort2[2] -unit.1.6.port.2.s.2.orderindex=-1 -unit.1.6.port.2.s.2.visible=1 -unit.1.6.port.2.s.20.alias= -unit.1.6.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.20.name=TriggerPort2[20] -unit.1.6.port.2.s.20.orderindex=-1 -unit.1.6.port.2.s.20.visible=1 -unit.1.6.port.2.s.21.alias= -unit.1.6.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.21.name=TriggerPort2[21] -unit.1.6.port.2.s.21.orderindex=-1 -unit.1.6.port.2.s.21.visible=1 -unit.1.6.port.2.s.22.alias= -unit.1.6.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.22.name=TriggerPort2[22] -unit.1.6.port.2.s.22.orderindex=-1 -unit.1.6.port.2.s.22.visible=1 -unit.1.6.port.2.s.23.alias= -unit.1.6.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.23.name=TriggerPort2[23] -unit.1.6.port.2.s.23.orderindex=-1 -unit.1.6.port.2.s.23.visible=1 -unit.1.6.port.2.s.24.alias= -unit.1.6.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.24.name=TriggerPort2[24] -unit.1.6.port.2.s.24.orderindex=-1 -unit.1.6.port.2.s.24.visible=1 -unit.1.6.port.2.s.25.alias= -unit.1.6.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.25.name=TriggerPort2[25] -unit.1.6.port.2.s.25.orderindex=-1 -unit.1.6.port.2.s.25.visible=1 -unit.1.6.port.2.s.26.alias= -unit.1.6.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.26.name=TriggerPort2[26] -unit.1.6.port.2.s.26.orderindex=-1 -unit.1.6.port.2.s.26.visible=1 -unit.1.6.port.2.s.27.alias= -unit.1.6.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.27.name=TriggerPort2[27] -unit.1.6.port.2.s.27.orderindex=-1 -unit.1.6.port.2.s.27.visible=1 -unit.1.6.port.2.s.28.alias= -unit.1.6.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.28.name=TriggerPort2[28] -unit.1.6.port.2.s.28.orderindex=-1 -unit.1.6.port.2.s.28.visible=1 -unit.1.6.port.2.s.29.alias= -unit.1.6.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.29.name=TriggerPort2[29] -unit.1.6.port.2.s.29.orderindex=-1 -unit.1.6.port.2.s.29.visible=1 -unit.1.6.port.2.s.3.alias= -unit.1.6.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.3.name=TriggerPort2[3] -unit.1.6.port.2.s.3.orderindex=-1 -unit.1.6.port.2.s.3.visible=1 -unit.1.6.port.2.s.30.alias= -unit.1.6.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.30.name=TriggerPort2[30] -unit.1.6.port.2.s.30.orderindex=-1 -unit.1.6.port.2.s.30.visible=1 -unit.1.6.port.2.s.31.alias= -unit.1.6.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.31.name=TriggerPort2[31] -unit.1.6.port.2.s.31.orderindex=-1 -unit.1.6.port.2.s.31.visible=1 -unit.1.6.port.2.s.4.alias= -unit.1.6.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.4.name=TriggerPort2[4] -unit.1.6.port.2.s.4.orderindex=-1 -unit.1.6.port.2.s.4.visible=1 -unit.1.6.port.2.s.5.alias= -unit.1.6.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.5.name=TriggerPort2[5] -unit.1.6.port.2.s.5.orderindex=-1 -unit.1.6.port.2.s.5.visible=1 -unit.1.6.port.2.s.6.alias= -unit.1.6.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.6.name=TriggerPort2[6] -unit.1.6.port.2.s.6.orderindex=-1 -unit.1.6.port.2.s.6.visible=1 -unit.1.6.port.2.s.7.alias= -unit.1.6.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.7.name=TriggerPort2[7] -unit.1.6.port.2.s.7.orderindex=-1 -unit.1.6.port.2.s.7.visible=1 -unit.1.6.port.2.s.8.alias= -unit.1.6.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.8.name=TriggerPort2[8] -unit.1.6.port.2.s.8.orderindex=-1 -unit.1.6.port.2.s.8.visible=1 -unit.1.6.port.2.s.9.alias= -unit.1.6.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.9.name=TriggerPort2[9] -unit.1.6.port.2.s.9.orderindex=-1 -unit.1.6.port.2.s.9.visible=1 -unit.1.6.port.3.b.0.alias= -unit.1.6.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.b.0.name=TriggerPort3 -unit.1.6.port.3.b.0.orderindex=-1 -unit.1.6.port.3.b.0.radix=Hex -unit.1.6.port.3.b.0.signedOffset=0.0 -unit.1.6.port.3.b.0.signedPrecision=0 -unit.1.6.port.3.b.0.signedScaleFactor=1.0 -unit.1.6.port.3.b.0.unsignedOffset=0.0 -unit.1.6.port.3.b.0.unsignedPrecision=0 -unit.1.6.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.3.b.0.visible=1 -unit.1.6.port.3.buscount=1 -unit.1.6.port.3.channelcount=32 -unit.1.6.port.3.s.0.alias= -unit.1.6.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.0.name=TriggerPort3[0] -unit.1.6.port.3.s.0.orderindex=-1 -unit.1.6.port.3.s.0.visible=1 -unit.1.6.port.3.s.1.alias= -unit.1.6.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.1.name=TriggerPort3[1] -unit.1.6.port.3.s.1.orderindex=-1 -unit.1.6.port.3.s.1.visible=1 -unit.1.6.port.3.s.10.alias= -unit.1.6.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.10.name=TriggerPort3[10] -unit.1.6.port.3.s.10.orderindex=-1 -unit.1.6.port.3.s.10.visible=1 -unit.1.6.port.3.s.11.alias= -unit.1.6.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.11.name=TriggerPort3[11] -unit.1.6.port.3.s.11.orderindex=-1 -unit.1.6.port.3.s.11.visible=1 -unit.1.6.port.3.s.12.alias= -unit.1.6.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.12.name=TriggerPort3[12] -unit.1.6.port.3.s.12.orderindex=-1 -unit.1.6.port.3.s.12.visible=1 -unit.1.6.port.3.s.13.alias= -unit.1.6.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.13.name=TriggerPort3[13] -unit.1.6.port.3.s.13.orderindex=-1 -unit.1.6.port.3.s.13.visible=1 -unit.1.6.port.3.s.14.alias= -unit.1.6.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.14.name=TriggerPort3[14] -unit.1.6.port.3.s.14.orderindex=-1 -unit.1.6.port.3.s.14.visible=1 -unit.1.6.port.3.s.15.alias= -unit.1.6.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.15.name=TriggerPort3[15] -unit.1.6.port.3.s.15.orderindex=-1 -unit.1.6.port.3.s.15.visible=1 -unit.1.6.port.3.s.16.alias= -unit.1.6.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.16.name=TriggerPort3[16] -unit.1.6.port.3.s.16.orderindex=-1 -unit.1.6.port.3.s.16.visible=1 -unit.1.6.port.3.s.17.alias= -unit.1.6.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.17.name=TriggerPort3[17] -unit.1.6.port.3.s.17.orderindex=-1 -unit.1.6.port.3.s.17.visible=1 -unit.1.6.port.3.s.18.alias= -unit.1.6.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.18.name=TriggerPort3[18] -unit.1.6.port.3.s.18.orderindex=-1 -unit.1.6.port.3.s.18.visible=1 -unit.1.6.port.3.s.19.alias= -unit.1.6.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.19.name=TriggerPort3[19] -unit.1.6.port.3.s.19.orderindex=-1 -unit.1.6.port.3.s.19.visible=1 -unit.1.6.port.3.s.2.alias= -unit.1.6.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.2.name=TriggerPort3[2] -unit.1.6.port.3.s.2.orderindex=-1 -unit.1.6.port.3.s.2.visible=1 -unit.1.6.port.3.s.20.alias= -unit.1.6.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.20.name=TriggerPort3[20] -unit.1.6.port.3.s.20.orderindex=-1 -unit.1.6.port.3.s.20.visible=1 -unit.1.6.port.3.s.21.alias= -unit.1.6.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.21.name=TriggerPort3[21] -unit.1.6.port.3.s.21.orderindex=-1 -unit.1.6.port.3.s.21.visible=1 -unit.1.6.port.3.s.22.alias= -unit.1.6.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.22.name=TriggerPort3[22] -unit.1.6.port.3.s.22.orderindex=-1 -unit.1.6.port.3.s.22.visible=1 -unit.1.6.port.3.s.23.alias= -unit.1.6.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.23.name=TriggerPort3[23] -unit.1.6.port.3.s.23.orderindex=-1 -unit.1.6.port.3.s.23.visible=1 -unit.1.6.port.3.s.24.alias= -unit.1.6.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.24.name=TriggerPort3[24] -unit.1.6.port.3.s.24.orderindex=-1 -unit.1.6.port.3.s.24.visible=1 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-unit.1.6.port.4.s.10.name=TriggerPort4[10] -unit.1.6.port.4.s.10.orderindex=-1 -unit.1.6.port.4.s.10.visible=1 -unit.1.6.port.4.s.11.alias= -unit.1.6.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.11.name=TriggerPort4[11] -unit.1.6.port.4.s.11.orderindex=-1 -unit.1.6.port.4.s.11.visible=1 -unit.1.6.port.4.s.12.alias= -unit.1.6.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.12.name=TriggerPort4[12] -unit.1.6.port.4.s.12.orderindex=-1 -unit.1.6.port.4.s.12.visible=1 -unit.1.6.port.4.s.13.alias= -unit.1.6.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.13.name=TriggerPort4[13] -unit.1.6.port.4.s.13.orderindex=-1 -unit.1.6.port.4.s.13.visible=1 -unit.1.6.port.4.s.14.alias= -unit.1.6.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.14.name=TriggerPort4[14] -unit.1.6.port.4.s.14.orderindex=-1 -unit.1.6.port.4.s.14.visible=1 -unit.1.6.port.4.s.15.alias= -unit.1.6.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.15.name=TriggerPort4[15] -unit.1.6.port.4.s.15.orderindex=-1 -unit.1.6.port.4.s.15.visible=1 -unit.1.6.port.4.s.16.alias= -unit.1.6.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.16.name=TriggerPort4[16] -unit.1.6.port.4.s.16.orderindex=-1 -unit.1.6.port.4.s.16.visible=1 -unit.1.6.port.4.s.17.alias= -unit.1.6.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.17.name=TriggerPort4[17] -unit.1.6.port.4.s.17.orderindex=-1 -unit.1.6.port.4.s.17.visible=1 -unit.1.6.port.4.s.18.alias= -unit.1.6.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.18.name=TriggerPort4[18] -unit.1.6.port.4.s.18.orderindex=-1 -unit.1.6.port.4.s.18.visible=1 -unit.1.6.port.4.s.19.alias= -unit.1.6.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.19.name=TriggerPort4[19] -unit.1.6.port.4.s.19.orderindex=-1 -unit.1.6.port.4.s.19.visible=1 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-unit.1.6.port.4.s.9.orderindex=-1 -unit.1.6.port.4.s.9.visible=1 -unit.1.6.portcount=5 -unit.1.6.rep_trigger.clobber=1 -unit.1.6.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/C\:\\Documents and Settings\\lucas.russo\\Desktop\\position_test\\logs\\run3_08_08_2013_18_30\\dsp_monit_amp -unit.1.6.rep_trigger.filename=dsp_monit_amp -unit.1.6.rep_trigger.format=ASCII -unit.1.6.rep_trigger.loggingEnabled=0 -unit.1.6.rep_trigger.signals=Bus Plot Buses -unit.1.6.samplesPerTrigger=1 -unit.1.6.triggerCapture=1 -unit.1.6.triggerNSamplesTS=0 -unit.1.6.triggerPosition=0 -unit.1.6.triggerWindowCount=1 -unit.1.6.triggerWindowDepth=64 -unit.1.6.triggerWindowTS=0 -unit.1.6.username=monit_amp -unit.1.6.waveform.count=35 -unit.1.6.waveform.posn.0.channel=2147483646 -unit.1.6.waveform.posn.0.name=dsp_monit_amp_ch3 -unit.1.6.waveform.posn.0.radix=3 -unit.1.6.waveform.posn.0.type=bus -unit.1.6.waveform.posn.1.channel=2147483646 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-unit.1.6.waveform.posn.42.channel=2147483646 -unit.1.6.waveform.posn.42.name=dsp_y_monit -unit.1.6.waveform.posn.42.radix=3 -unit.1.6.waveform.posn.42.type=bus -unit.1.6.waveform.posn.43.channel=2147483646 -unit.1.6.waveform.posn.43.name=dsp_y_monit -unit.1.6.waveform.posn.43.radix=3 -unit.1.6.waveform.posn.43.type=bus -unit.1.6.waveform.posn.44.channel=2147483646 -unit.1.6.waveform.posn.44.name=dsp_y_monit -unit.1.6.waveform.posn.44.radix=3 -unit.1.6.waveform.posn.44.type=bus -unit.1.6.waveform.posn.45.channel=2147483646 -unit.1.6.waveform.posn.45.name=dsp_y_monit -unit.1.6.waveform.posn.45.radix=3 -unit.1.6.waveform.posn.45.type=bus -unit.1.6.waveform.posn.46.channel=2147483646 -unit.1.6.waveform.posn.46.name=dsp_y_monit -unit.1.6.waveform.posn.46.radix=3 -unit.1.6.waveform.posn.46.type=bus -unit.1.6.waveform.posn.5.channel=1 -unit.1.6.waveform.posn.5.name=DataPort[1] -unit.1.6.waveform.posn.5.type=signal -unit.1.6.waveform.posn.6.channel=2 -unit.1.6.waveform.posn.6.name=DataPort[2] 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-unit.1.7.port.1.s.10.orderindex=-1 -unit.1.7.port.1.s.10.visible=1 -unit.1.7.port.1.s.11.alias= -unit.1.7.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.11.name=TriggerPort1[11] -unit.1.7.port.1.s.11.orderindex=-1 -unit.1.7.port.1.s.11.visible=1 -unit.1.7.port.1.s.12.alias= -unit.1.7.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.12.name=TriggerPort1[12] -unit.1.7.port.1.s.12.orderindex=-1 -unit.1.7.port.1.s.12.visible=1 -unit.1.7.port.1.s.13.alias= -unit.1.7.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.13.name=TriggerPort1[13] -unit.1.7.port.1.s.13.orderindex=-1 -unit.1.7.port.1.s.13.visible=1 -unit.1.7.port.1.s.14.alias= -unit.1.7.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.14.name=TriggerPort1[14] -unit.1.7.port.1.s.14.orderindex=-1 -unit.1.7.port.1.s.14.visible=1 -unit.1.7.port.1.s.15.alias= -unit.1.7.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.15.name=TriggerPort1[15] -unit.1.7.port.1.s.15.orderindex=-1 -unit.1.7.port.1.s.15.visible=1 -unit.1.7.port.1.s.16.alias= -unit.1.7.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.16.name=TriggerPort1[16] -unit.1.7.port.1.s.16.orderindex=-1 -unit.1.7.port.1.s.16.visible=1 -unit.1.7.port.1.s.17.alias= -unit.1.7.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.17.name=TriggerPort1[17] -unit.1.7.port.1.s.17.orderindex=-1 -unit.1.7.port.1.s.17.visible=1 -unit.1.7.port.1.s.18.alias= -unit.1.7.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.18.name=TriggerPort1[18] -unit.1.7.port.1.s.18.orderindex=-1 -unit.1.7.port.1.s.18.visible=1 -unit.1.7.port.1.s.19.alias= -unit.1.7.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.19.name=TriggerPort1[19] -unit.1.7.port.1.s.19.orderindex=-1 -unit.1.7.port.1.s.19.visible=1 -unit.1.7.port.1.s.2.alias= -unit.1.7.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.2.name=TriggerPort1[2] -unit.1.7.port.1.s.2.orderindex=-1 -unit.1.7.port.1.s.2.visible=1 -unit.1.7.port.1.s.20.alias= -unit.1.7.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.20.name=TriggerPort1[20] -unit.1.7.port.1.s.20.orderindex=-1 -unit.1.7.port.1.s.20.visible=1 -unit.1.7.port.1.s.21.alias= -unit.1.7.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.21.name=TriggerPort1[21] -unit.1.7.port.1.s.21.orderindex=-1 -unit.1.7.port.1.s.21.visible=1 -unit.1.7.port.1.s.22.alias= -unit.1.7.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.22.name=TriggerPort1[22] -unit.1.7.port.1.s.22.orderindex=-1 -unit.1.7.port.1.s.22.visible=1 -unit.1.7.port.1.s.23.alias= -unit.1.7.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.23.name=TriggerPort1[23] -unit.1.7.port.1.s.23.orderindex=-1 -unit.1.7.port.1.s.23.visible=1 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-unit.1.7.port.1.s.28.visible=1 -unit.1.7.port.1.s.29.alias= -unit.1.7.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.29.name=TriggerPort1[29] -unit.1.7.port.1.s.29.orderindex=-1 -unit.1.7.port.1.s.29.visible=1 -unit.1.7.port.1.s.3.alias= -unit.1.7.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.3.name=TriggerPort1[3] -unit.1.7.port.1.s.3.orderindex=-1 -unit.1.7.port.1.s.3.visible=1 -unit.1.7.port.1.s.30.alias= -unit.1.7.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.30.name=TriggerPort1[30] -unit.1.7.port.1.s.30.orderindex=-1 -unit.1.7.port.1.s.30.visible=1 -unit.1.7.port.1.s.31.alias= -unit.1.7.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.31.name=TriggerPort1[31] -unit.1.7.port.1.s.31.orderindex=-1 -unit.1.7.port.1.s.31.visible=1 -unit.1.7.port.1.s.4.alias= -unit.1.7.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.4.name=TriggerPort1[4] -unit.1.7.port.1.s.4.orderindex=-1 -unit.1.7.port.1.s.4.visible=1 -unit.1.7.port.1.s.5.alias= -unit.1.7.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.5.name=TriggerPort1[5] -unit.1.7.port.1.s.5.orderindex=-1 -unit.1.7.port.1.s.5.visible=1 -unit.1.7.port.1.s.6.alias= -unit.1.7.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.6.name=TriggerPort1[6] -unit.1.7.port.1.s.6.orderindex=-1 -unit.1.7.port.1.s.6.visible=1 -unit.1.7.port.1.s.7.alias= -unit.1.7.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.7.name=TriggerPort1[7] -unit.1.7.port.1.s.7.orderindex=-1 -unit.1.7.port.1.s.7.visible=1 -unit.1.7.port.1.s.8.alias= -unit.1.7.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.8.name=TriggerPort1[8] -unit.1.7.port.1.s.8.orderindex=-1 -unit.1.7.port.1.s.8.visible=1 -unit.1.7.port.1.s.9.alias= -unit.1.7.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.9.name=TriggerPort1[9] -unit.1.7.port.1.s.9.orderindex=-1 -unit.1.7.port.1.s.9.visible=1 -unit.1.7.port.2.b.0.alias= -unit.1.7.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.7.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.b.0.name=TriggerPort2 -unit.1.7.port.2.b.0.orderindex=-1 -unit.1.7.port.2.b.0.radix=Hex -unit.1.7.port.2.b.0.signedOffset=0.0 -unit.1.7.port.2.b.0.signedPrecision=0 -unit.1.7.port.2.b.0.signedScaleFactor=1.0 -unit.1.7.port.2.b.0.unsignedOffset=0.0 -unit.1.7.port.2.b.0.unsignedPrecision=0 -unit.1.7.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.7.port.2.b.0.visible=1 -unit.1.7.port.2.buscount=1 -unit.1.7.port.2.channelcount=32 -unit.1.7.port.2.s.0.alias= -unit.1.7.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.0.name=TriggerPort2[0] -unit.1.7.port.2.s.0.orderindex=-1 -unit.1.7.port.2.s.0.visible=1 -unit.1.7.port.2.s.1.alias= -unit.1.7.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.1.name=TriggerPort2[1] -unit.1.7.port.2.s.1.orderindex=-1 -unit.1.7.port.2.s.1.visible=1 -unit.1.7.port.2.s.10.alias= -unit.1.7.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.10.name=TriggerPort2[10] -unit.1.7.port.2.s.10.orderindex=-1 -unit.1.7.port.2.s.10.visible=1 -unit.1.7.port.2.s.11.alias= -unit.1.7.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.11.name=TriggerPort2[11] -unit.1.7.port.2.s.11.orderindex=-1 -unit.1.7.port.2.s.11.visible=1 -unit.1.7.port.2.s.12.alias= -unit.1.7.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.12.name=TriggerPort2[12] -unit.1.7.port.2.s.12.orderindex=-1 -unit.1.7.port.2.s.12.visible=1 -unit.1.7.port.2.s.13.alias= -unit.1.7.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.13.name=TriggerPort2[13] -unit.1.7.port.2.s.13.orderindex=-1 -unit.1.7.port.2.s.13.visible=1 -unit.1.7.port.2.s.14.alias= -unit.1.7.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.14.name=TriggerPort2[14] -unit.1.7.port.2.s.14.orderindex=-1 -unit.1.7.port.2.s.14.visible=1 -unit.1.7.port.2.s.15.alias= -unit.1.7.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.15.name=TriggerPort2[15] -unit.1.7.port.2.s.15.orderindex=-1 -unit.1.7.port.2.s.15.visible=1 -unit.1.7.port.2.s.16.alias= -unit.1.7.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.16.name=TriggerPort2[16] -unit.1.7.port.2.s.16.orderindex=-1 -unit.1.7.port.2.s.16.visible=1 -unit.1.7.port.2.s.17.alias= -unit.1.7.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.17.name=TriggerPort2[17] -unit.1.7.port.2.s.17.orderindex=-1 -unit.1.7.port.2.s.17.visible=1 -unit.1.7.port.2.s.18.alias= -unit.1.7.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.18.name=TriggerPort2[18] -unit.1.7.port.2.s.18.orderindex=-1 -unit.1.7.port.2.s.18.visible=1 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-unit.1.7.port.2.s.27.orderindex=-1 -unit.1.7.port.2.s.27.visible=1 -unit.1.7.port.2.s.28.alias= -unit.1.7.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.28.name=TriggerPort2[28] -unit.1.7.port.2.s.28.orderindex=-1 -unit.1.7.port.2.s.28.visible=1 -unit.1.7.port.2.s.29.alias= -unit.1.7.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.29.name=TriggerPort2[29] -unit.1.7.port.2.s.29.orderindex=-1 -unit.1.7.port.2.s.29.visible=1 -unit.1.7.port.2.s.3.alias= -unit.1.7.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.3.name=TriggerPort2[3] -unit.1.7.port.2.s.3.orderindex=-1 -unit.1.7.port.2.s.3.visible=1 -unit.1.7.port.2.s.30.alias= -unit.1.7.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.30.name=TriggerPort2[30] -unit.1.7.port.2.s.30.orderindex=-1 -unit.1.7.port.2.s.30.visible=1 -unit.1.7.port.2.s.31.alias= -unit.1.7.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.7.port.2.s.8.name=TriggerPort2[8] -unit.1.7.port.2.s.8.orderindex=-1 -unit.1.7.port.2.s.8.visible=1 -unit.1.7.port.2.s.9.alias= -unit.1.7.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.9.name=TriggerPort2[9] -unit.1.7.port.2.s.9.orderindex=-1 -unit.1.7.port.2.s.9.visible=1 -unit.1.7.port.3.b.0.alias= -unit.1.7.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.7.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.b.0.name=TriggerPort3 -unit.1.7.port.3.b.0.orderindex=-1 -unit.1.7.port.3.b.0.radix=Hex -unit.1.7.port.3.b.0.signedOffset=0.0 -unit.1.7.port.3.b.0.signedPrecision=0 -unit.1.7.port.3.b.0.signedScaleFactor=1.0 -unit.1.7.port.3.b.0.unsignedOffset=0.0 -unit.1.7.port.3.b.0.unsignedPrecision=0 -unit.1.7.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.7.port.3.b.0.visible=1 -unit.1.7.port.3.buscount=1 -unit.1.7.port.3.channelcount=32 -unit.1.7.port.3.s.0.alias= -unit.1.7.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.0.name=TriggerPort3[0] -unit.1.7.port.3.s.0.orderindex=-1 -unit.1.7.port.3.s.0.visible=1 -unit.1.7.port.3.s.1.alias= -unit.1.7.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.1.name=TriggerPort3[1] -unit.1.7.port.3.s.1.orderindex=-1 -unit.1.7.port.3.s.1.visible=1 -unit.1.7.port.3.s.10.alias= -unit.1.7.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.10.name=TriggerPort3[10] -unit.1.7.port.3.s.10.orderindex=-1 -unit.1.7.port.3.s.10.visible=1 -unit.1.7.port.3.s.11.alias= -unit.1.7.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.11.name=TriggerPort3[11] -unit.1.7.port.3.s.11.orderindex=-1 -unit.1.7.port.3.s.11.visible=1 -unit.1.7.port.3.s.12.alias= -unit.1.7.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.12.name=TriggerPort3[12] -unit.1.7.port.3.s.12.orderindex=-1 -unit.1.7.port.3.s.12.visible=1 -unit.1.7.port.3.s.13.alias= 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-unit.1.7.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.4.s.6.name=TriggerPort4[6] -unit.1.7.port.4.s.6.orderindex=-1 -unit.1.7.port.4.s.6.visible=1 -unit.1.7.port.4.s.7.alias= -unit.1.7.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.4.s.7.name=TriggerPort4[7] -unit.1.7.port.4.s.7.orderindex=-1 -unit.1.7.port.4.s.7.visible=1 -unit.1.7.port.4.s.8.alias= -unit.1.7.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.4.s.8.name=TriggerPort4[8] -unit.1.7.port.4.s.8.orderindex=-1 -unit.1.7.port.4.s.8.visible=1 -unit.1.7.port.4.s.9.alias= -unit.1.7.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.4.s.9.name=TriggerPort4[9] -unit.1.7.port.4.s.9.orderindex=-1 -unit.1.7.port.4.s.9.visible=1 -unit.1.7.portcount=5 -unit.1.7.rep_trigger.clobber=1 -unit.1.7.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/C\:\\Documents and Settings\\lucas.russo\\Desktop\\position_test\\logs\\run3_08_08_2013_18_30\\dsp_monit_pos -unit.1.7.rep_trigger.filename=dsp_monit_pos -unit.1.7.rep_trigger.format=ASCII -unit.1.7.rep_trigger.loggingEnabled=1 -unit.1.7.rep_trigger.signals=Bus Plot Buses -unit.1.7.samplesPerTrigger=1 -unit.1.7.triggerCapture=1 -unit.1.7.triggerNSamplesTS=0 -unit.1.7.triggerPosition=0 -unit.1.7.triggerWindowCount=1 -unit.1.7.triggerWindowDepth=64 -unit.1.7.triggerWindowTS=0 -unit.1.7.username=monit_pos -unit.1.7.waveform.count=4 -unit.1.7.waveform.posn.0.channel=2147483646 -unit.1.7.waveform.posn.0.name=dsp_q_monit -unit.1.7.waveform.posn.0.radix=3 -unit.1.7.waveform.posn.0.type=bus -unit.1.7.waveform.posn.1.channel=2147483646 -unit.1.7.waveform.posn.1.name=dsp_sum_monit -unit.1.7.waveform.posn.1.radix=3 -unit.1.7.waveform.posn.1.type=bus -unit.1.7.waveform.posn.10.channel=2147483646 -unit.1.7.waveform.posn.10.name=dsp_y_monit -unit.1.7.waveform.posn.10.radix=3 -unit.1.7.waveform.posn.10.type=bus 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-unit.1.8.port.-1.s.88.name=DataPort[88] -unit.1.8.port.-1.s.88.orderindex=-1 -unit.1.8.port.-1.s.88.visible=0 -unit.1.8.port.-1.s.89.alias= -unit.1.8.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.-1.s.89.name=DataPort[89] -unit.1.8.port.-1.s.89.orderindex=-1 -unit.1.8.port.-1.s.89.visible=0 -unit.1.8.port.-1.s.9.alias= -unit.1.8.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.-1.s.9.name=DataPort[9] -unit.1.8.port.-1.s.9.orderindex=-1 -unit.1.8.port.-1.s.9.visible=0 -unit.1.8.port.-1.s.90.alias= -unit.1.8.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.-1.s.90.name=DataPort[90] -unit.1.8.port.-1.s.90.orderindex=-1 -unit.1.8.port.-1.s.90.visible=0 -unit.1.8.port.-1.s.91.alias= -unit.1.8.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.-1.s.91.name=DataPort[91] -unit.1.8.port.-1.s.91.orderindex=-1 -unit.1.8.port.-1.s.91.visible=0 -unit.1.8.port.-1.s.92.alias= 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-unit.1.8.port.2.s.6.name=TriggerPort2[6] -unit.1.8.port.2.s.6.orderindex=-1 -unit.1.8.port.2.s.6.visible=1 -unit.1.8.port.2.s.7.alias= -unit.1.8.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.7.name=TriggerPort2[7] -unit.1.8.port.2.s.7.orderindex=-1 -unit.1.8.port.2.s.7.visible=1 -unit.1.8.port.2.s.8.alias= -unit.1.8.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.8.name=TriggerPort2[8] -unit.1.8.port.2.s.8.orderindex=-1 -unit.1.8.port.2.s.8.visible=1 -unit.1.8.port.2.s.9.alias= -unit.1.8.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.9.name=TriggerPort2[9] -unit.1.8.port.2.s.9.orderindex=-1 -unit.1.8.port.2.s.9.visible=1 -unit.1.8.port.3.b.0.alias= -unit.1.8.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.8.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.b.0.name=TriggerPort3 -unit.1.8.port.3.b.0.orderindex=-1 -unit.1.8.port.3.b.0.radix=Hex -unit.1.8.port.3.b.0.signedOffset=0.0 -unit.1.8.port.3.b.0.signedPrecision=0 -unit.1.8.port.3.b.0.signedScaleFactor=1.0 -unit.1.8.port.3.b.0.unsignedOffset=0.0 -unit.1.8.port.3.b.0.unsignedPrecision=0 -unit.1.8.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.8.port.3.b.0.visible=1 -unit.1.8.port.3.buscount=1 -unit.1.8.port.3.channelcount=32 -unit.1.8.port.3.s.0.alias= -unit.1.8.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.0.name=TriggerPort3[0] -unit.1.8.port.3.s.0.orderindex=-1 -unit.1.8.port.3.s.0.visible=1 -unit.1.8.port.3.s.1.alias= -unit.1.8.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.1.name=TriggerPort3[1] -unit.1.8.port.3.s.1.orderindex=-1 -unit.1.8.port.3.s.1.visible=1 -unit.1.8.port.3.s.10.alias= -unit.1.8.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.10.name=TriggerPort3[10] -unit.1.8.port.3.s.10.orderindex=-1 -unit.1.8.port.3.s.10.visible=1 -unit.1.8.port.3.s.11.alias= -unit.1.8.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.11.name=TriggerPort3[11] -unit.1.8.port.3.s.11.orderindex=-1 -unit.1.8.port.3.s.11.visible=1 -unit.1.8.port.3.s.12.alias= -unit.1.8.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.12.name=TriggerPort3[12] -unit.1.8.port.3.s.12.orderindex=-1 -unit.1.8.port.3.s.12.visible=1 -unit.1.8.port.3.s.13.alias= -unit.1.8.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.13.name=TriggerPort3[13] -unit.1.8.port.3.s.13.orderindex=-1 -unit.1.8.port.3.s.13.visible=1 -unit.1.8.port.3.s.14.alias= -unit.1.8.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.14.name=TriggerPort3[14] -unit.1.8.port.3.s.14.orderindex=-1 -unit.1.8.port.3.s.14.visible=1 -unit.1.8.port.3.s.15.alias= -unit.1.8.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.15.name=TriggerPort3[15] -unit.1.8.port.3.s.15.orderindex=-1 -unit.1.8.port.3.s.15.visible=1 -unit.1.8.port.3.s.16.alias= -unit.1.8.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.16.name=TriggerPort3[16] -unit.1.8.port.3.s.16.orderindex=-1 -unit.1.8.port.3.s.16.visible=1 -unit.1.8.port.3.s.17.alias= -unit.1.8.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.17.name=TriggerPort3[17] -unit.1.8.port.3.s.17.orderindex=-1 -unit.1.8.port.3.s.17.visible=1 -unit.1.8.port.3.s.18.alias= -unit.1.8.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.18.name=TriggerPort3[18] -unit.1.8.port.3.s.18.orderindex=-1 -unit.1.8.port.3.s.18.visible=1 -unit.1.8.port.3.s.19.alias= -unit.1.8.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.19.name=TriggerPort3[19] -unit.1.8.port.3.s.19.orderindex=-1 -unit.1.8.port.3.s.19.visible=1 -unit.1.8.port.3.s.2.alias= -unit.1.8.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.2.name=TriggerPort3[2] -unit.1.8.port.3.s.2.orderindex=-1 -unit.1.8.port.3.s.2.visible=1 -unit.1.8.port.3.s.20.alias= -unit.1.8.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.20.name=TriggerPort3[20] -unit.1.8.port.3.s.20.orderindex=-1 -unit.1.8.port.3.s.20.visible=1 -unit.1.8.port.3.s.21.alias= -unit.1.8.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.21.name=TriggerPort3[21] -unit.1.8.port.3.s.21.orderindex=-1 -unit.1.8.port.3.s.21.visible=1 -unit.1.8.port.3.s.22.alias= -unit.1.8.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.22.name=TriggerPort3[22] -unit.1.8.port.3.s.22.orderindex=-1 -unit.1.8.port.3.s.22.visible=1 -unit.1.8.port.3.s.23.alias= -unit.1.8.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.23.name=TriggerPort3[23] -unit.1.8.port.3.s.23.orderindex=-1 -unit.1.8.port.3.s.23.visible=1 -unit.1.8.port.3.s.24.alias= -unit.1.8.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.24.name=TriggerPort3[24] -unit.1.8.port.3.s.24.orderindex=-1 -unit.1.8.port.3.s.24.visible=1 -unit.1.8.port.3.s.25.alias= -unit.1.8.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.25.name=TriggerPort3[25] -unit.1.8.port.3.s.25.orderindex=-1 -unit.1.8.port.3.s.25.visible=1 -unit.1.8.port.3.s.26.alias= -unit.1.8.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.26.name=TriggerPort3[26] -unit.1.8.port.3.s.26.orderindex=-1 -unit.1.8.port.3.s.26.visible=1 -unit.1.8.port.3.s.27.alias= -unit.1.8.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.27.name=TriggerPort3[27] -unit.1.8.port.3.s.27.orderindex=-1 -unit.1.8.port.3.s.27.visible=1 -unit.1.8.port.3.s.28.alias= -unit.1.8.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.28.name=TriggerPort3[28] -unit.1.8.port.3.s.28.orderindex=-1 -unit.1.8.port.3.s.28.visible=1 -unit.1.8.port.3.s.29.alias= -unit.1.8.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.29.name=TriggerPort3[29] -unit.1.8.port.3.s.29.orderindex=-1 -unit.1.8.port.3.s.29.visible=1 -unit.1.8.port.3.s.3.alias= -unit.1.8.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.3.name=TriggerPort3[3] -unit.1.8.port.3.s.3.orderindex=-1 -unit.1.8.port.3.s.3.visible=1 -unit.1.8.port.3.s.30.alias= -unit.1.8.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.30.name=TriggerPort3[30] -unit.1.8.port.3.s.30.orderindex=-1 -unit.1.8.port.3.s.30.visible=1 -unit.1.8.port.3.s.31.alias= -unit.1.8.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.31.name=TriggerPort3[31] -unit.1.8.port.3.s.31.orderindex=-1 -unit.1.8.port.3.s.31.visible=1 -unit.1.8.port.3.s.4.alias= -unit.1.8.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.4.name=TriggerPort3[4] -unit.1.8.port.3.s.4.orderindex=-1 -unit.1.8.port.3.s.4.visible=1 -unit.1.8.port.3.s.5.alias= -unit.1.8.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.5.name=TriggerPort3[5] -unit.1.8.port.3.s.5.orderindex=-1 -unit.1.8.port.3.s.5.visible=1 -unit.1.8.port.3.s.6.alias= -unit.1.8.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.6.name=TriggerPort3[6] -unit.1.8.port.3.s.6.orderindex=-1 -unit.1.8.port.3.s.6.visible=1 -unit.1.8.port.3.s.7.alias= -unit.1.8.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.7.name=TriggerPort3[7] -unit.1.8.port.3.s.7.orderindex=-1 -unit.1.8.port.3.s.7.visible=1 -unit.1.8.port.3.s.8.alias= -unit.1.8.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.8.name=TriggerPort3[8] -unit.1.8.port.3.s.8.orderindex=-1 -unit.1.8.port.3.s.8.visible=1 -unit.1.8.port.3.s.9.alias= -unit.1.8.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.9.name=TriggerPort3[9] -unit.1.8.port.3.s.9.orderindex=-1 -unit.1.8.port.3.s.9.visible=1 -unit.1.8.port.4.b.0.alias= -unit.1.8.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.8.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.b.0.name=TriggerPort4 -unit.1.8.port.4.b.0.orderindex=-1 -unit.1.8.port.4.b.0.radix=Hex -unit.1.8.port.4.b.0.signedOffset=0.0 -unit.1.8.port.4.b.0.signedPrecision=0 -unit.1.8.port.4.b.0.signedScaleFactor=1.0 -unit.1.8.port.4.b.0.unsignedOffset=0.0 -unit.1.8.port.4.b.0.unsignedPrecision=0 -unit.1.8.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.8.port.4.b.0.visible=1 -unit.1.8.port.4.buscount=1 -unit.1.8.port.4.channelcount=32 -unit.1.8.port.4.s.0.alias= -unit.1.8.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.0.name=TriggerPort4[0] -unit.1.8.port.4.s.0.orderindex=-1 -unit.1.8.port.4.s.0.visible=1 -unit.1.8.port.4.s.1.alias= -unit.1.8.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.1.name=TriggerPort4[1] -unit.1.8.port.4.s.1.orderindex=-1 -unit.1.8.port.4.s.1.visible=1 -unit.1.8.port.4.s.10.alias= -unit.1.8.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.10.name=TriggerPort4[10] -unit.1.8.port.4.s.10.orderindex=-1 -unit.1.8.port.4.s.10.visible=1 -unit.1.8.port.4.s.11.alias= -unit.1.8.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.11.name=TriggerPort4[11] -unit.1.8.port.4.s.11.orderindex=-1 -unit.1.8.port.4.s.11.visible=1 -unit.1.8.port.4.s.12.alias= -unit.1.8.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.12.name=TriggerPort4[12] -unit.1.8.port.4.s.12.orderindex=-1 -unit.1.8.port.4.s.12.visible=1 -unit.1.8.port.4.s.13.alias= -unit.1.8.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.13.name=TriggerPort4[13] -unit.1.8.port.4.s.13.orderindex=-1 -unit.1.8.port.4.s.13.visible=1 -unit.1.8.port.4.s.14.alias= -unit.1.8.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.4.s.14.name=TriggerPort4[14] -unit.1.8.port.4.s.14.orderindex=-1 -unit.1.8.port.4.s.14.visible=1 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-unit.1.8.waveform.posn.133.type=signal -unit.1.8.waveform.posn.134.channel=134 -unit.1.8.waveform.posn.134.name=DataPort[134] -unit.1.8.waveform.posn.134.type=signal -unit.1.8.waveform.posn.135.channel=135 -unit.1.8.waveform.posn.135.name=DataPort[135] -unit.1.8.waveform.posn.135.type=signal -unit.1.8.waveform.posn.14.channel=14 -unit.1.8.waveform.posn.14.name=DataPort[14] -unit.1.8.waveform.posn.14.type=signal -unit.1.8.waveform.posn.15.channel=15 -unit.1.8.waveform.posn.15.name=DataPort[15] -unit.1.8.waveform.posn.15.type=signal -unit.1.8.waveform.posn.16.channel=16 -unit.1.8.waveform.posn.16.name=DataPort[16] -unit.1.8.waveform.posn.16.type=signal -unit.1.8.waveform.posn.17.channel=17 -unit.1.8.waveform.posn.17.name=DataPort[17] -unit.1.8.waveform.posn.17.type=signal -unit.1.8.waveform.posn.18.channel=18 -unit.1.8.waveform.posn.18.name=DataPort[18] -unit.1.8.waveform.posn.18.type=signal -unit.1.8.waveform.posn.19.channel=19 -unit.1.8.waveform.posn.19.name=DataPort[19] -unit.1.8.waveform.posn.19.type=signal -unit.1.8.waveform.posn.2.channel=2 -unit.1.8.waveform.posn.2.name=DataPort[2] -unit.1.8.waveform.posn.2.type=signal -unit.1.8.waveform.posn.20.channel=20 -unit.1.8.waveform.posn.20.name=DataPort[20] -unit.1.8.waveform.posn.20.type=signal -unit.1.8.waveform.posn.21.channel=21 -unit.1.8.waveform.posn.21.name=DataPort[21] -unit.1.8.waveform.posn.21.type=signal -unit.1.8.waveform.posn.22.channel=22 -unit.1.8.waveform.posn.22.name=DataPort[22] -unit.1.8.waveform.posn.22.type=signal -unit.1.8.waveform.posn.23.channel=23 -unit.1.8.waveform.posn.23.name=DataPort[23] -unit.1.8.waveform.posn.23.type=signal -unit.1.8.waveform.posn.24.channel=24 -unit.1.8.waveform.posn.24.name=DataPort[24] -unit.1.8.waveform.posn.24.type=signal -unit.1.8.waveform.posn.25.channel=25 -unit.1.8.waveform.posn.25.name=DataPort[25] -unit.1.8.waveform.posn.25.type=signal -unit.1.8.waveform.posn.26.channel=26 -unit.1.8.waveform.posn.26.name=DataPort[26] -unit.1.8.waveform.posn.26.type=signal -unit.1.8.waveform.posn.27.channel=27 -unit.1.8.waveform.posn.27.name=DataPort[27] -unit.1.8.waveform.posn.27.type=signal -unit.1.8.waveform.posn.28.channel=28 -unit.1.8.waveform.posn.28.name=DataPort[28] -unit.1.8.waveform.posn.28.type=signal -unit.1.8.waveform.posn.29.channel=29 -unit.1.8.waveform.posn.29.name=DataPort[29] -unit.1.8.waveform.posn.29.type=signal -unit.1.8.waveform.posn.3.channel=3 -unit.1.8.waveform.posn.3.name=DataPort[3] -unit.1.8.waveform.posn.3.type=signal -unit.1.8.waveform.posn.30.channel=30 -unit.1.8.waveform.posn.30.name=DataPort[30] -unit.1.8.waveform.posn.30.type=signal -unit.1.8.waveform.posn.31.channel=31 -unit.1.8.waveform.posn.31.name=DataPort[31] -unit.1.8.waveform.posn.31.type=signal -unit.1.8.waveform.posn.32.channel=32 -unit.1.8.waveform.posn.32.name=DataPort[32] -unit.1.8.waveform.posn.32.type=signal -unit.1.8.waveform.posn.33.channel=33 -unit.1.8.waveform.posn.33.name=DataPort[33] -unit.1.8.waveform.posn.33.type=signal -unit.1.8.waveform.posn.34.channel=34 -unit.1.8.waveform.posn.34.name=DataPort[34] -unit.1.8.waveform.posn.34.type=signal -unit.1.8.waveform.posn.35.channel=35 -unit.1.8.waveform.posn.35.name=DataPort[35] -unit.1.8.waveform.posn.35.type=signal -unit.1.8.waveform.posn.36.channel=36 -unit.1.8.waveform.posn.36.name=DataPort[36] -unit.1.8.waveform.posn.36.type=signal -unit.1.8.waveform.posn.37.channel=37 -unit.1.8.waveform.posn.37.name=DataPort[37] -unit.1.8.waveform.posn.37.type=signal -unit.1.8.waveform.posn.38.channel=38 -unit.1.8.waveform.posn.38.name=DataPort[38] -unit.1.8.waveform.posn.38.type=signal -unit.1.8.waveform.posn.39.channel=39 -unit.1.8.waveform.posn.39.name=DataPort[39] -unit.1.8.waveform.posn.39.type=signal -unit.1.8.waveform.posn.4.channel=4 -unit.1.8.waveform.posn.4.name=DataPort[4] -unit.1.8.waveform.posn.4.type=signal -unit.1.8.waveform.posn.40.channel=40 -unit.1.8.waveform.posn.40.name=DataPort[40] -unit.1.8.waveform.posn.40.type=signal -unit.1.8.waveform.posn.41.channel=41 -unit.1.8.waveform.posn.41.name=DataPort[41] -unit.1.8.waveform.posn.41.type=signal -unit.1.8.waveform.posn.42.channel=42 -unit.1.8.waveform.posn.42.name=DataPort[42] -unit.1.8.waveform.posn.42.type=signal -unit.1.8.waveform.posn.43.channel=43 -unit.1.8.waveform.posn.43.name=DataPort[43] -unit.1.8.waveform.posn.43.type=signal -unit.1.8.waveform.posn.44.channel=44 -unit.1.8.waveform.posn.44.name=DataPort[44] -unit.1.8.waveform.posn.44.type=signal -unit.1.8.waveform.posn.45.channel=45 -unit.1.8.waveform.posn.45.name=DataPort[45] -unit.1.8.waveform.posn.45.type=signal -unit.1.8.waveform.posn.46.channel=46 -unit.1.8.waveform.posn.46.name=DataPort[46] -unit.1.8.waveform.posn.46.type=signal -unit.1.8.waveform.posn.47.channel=47 -unit.1.8.waveform.posn.47.name=DataPort[47] -unit.1.8.waveform.posn.47.type=signal -unit.1.8.waveform.posn.48.channel=48 -unit.1.8.waveform.posn.48.name=DataPort[48] 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-unit.1.8.waveform.posn.77.type=signal -unit.1.8.waveform.posn.78.channel=78 -unit.1.8.waveform.posn.78.name=DataPort[78] -unit.1.8.waveform.posn.78.type=signal -unit.1.8.waveform.posn.79.channel=79 -unit.1.8.waveform.posn.79.name=DataPort[79] -unit.1.8.waveform.posn.79.type=signal -unit.1.8.waveform.posn.8.channel=8 -unit.1.8.waveform.posn.8.name=DataPort[8] -unit.1.8.waveform.posn.8.type=signal -unit.1.8.waveform.posn.80.channel=80 -unit.1.8.waveform.posn.80.name=DataPort[80] -unit.1.8.waveform.posn.80.type=signal -unit.1.8.waveform.posn.81.channel=81 -unit.1.8.waveform.posn.81.name=DataPort[81] -unit.1.8.waveform.posn.81.type=signal -unit.1.8.waveform.posn.82.channel=82 -unit.1.8.waveform.posn.82.name=DataPort[82] -unit.1.8.waveform.posn.82.type=signal -unit.1.8.waveform.posn.83.channel=83 -unit.1.8.waveform.posn.83.name=DataPort[83] -unit.1.8.waveform.posn.83.type=signal -unit.1.8.waveform.posn.84.channel=84 -unit.1.8.waveform.posn.84.name=DataPort[84] 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-unit.1.8.waveform.posn.99.type=signal -unit.1.9.0.HEIGHT0=0.3764321 -unit.1.9.0.TriggerRow0=1 -unit.1.9.0.TriggerRow1=1 -unit.1.9.0.TriggerRow2=1 -unit.1.9.0.WIDTH0=0.8225564 -unit.1.9.0.X0=0.17744361 -unit.1.9.0.Y0=0.0 -unit.1.9.5.HEIGHT5=1.0 -unit.1.9.5.WIDTH5=1.0 -unit.1.9.5.X5=0.0 -unit.1.9.5.Y5=0.0 -unit.1.9.6.HEIGHT6=0.8130081 -unit.1.9.6.WIDTH6=0.7312253 -unit.1.9.6.X6=0.2814229 -unit.1.9.6.Y6=0.596748 -unit.1.9.MFBitsA0=1XXXXXXX -unit.1.9.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.9.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.9.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.9.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.9.MFBitsB0=00000000 -unit.1.9.MFBitsB1=00000000000000000000000000000000 -unit.1.9.MFBitsB2=00000000000000000000000000000000 -unit.1.9.MFBitsB3=00000000000000000000000000000000 -unit.1.9.MFBitsB4=00000000000000000000000000000000 -unit.1.9.MFCompareA0=0 -unit.1.9.MFCompareA1=0 -unit.1.9.MFCompareA2=0 -unit.1.9.MFCompareA3=0 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29 30 31 -unit.1.9.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.-1.b.0.name=DataPort -unit.1.9.port.-1.b.0.orderindex=-1 -unit.1.9.port.-1.b.0.radix=Signed -unit.1.9.port.-1.b.0.signedOffset=0.0 -unit.1.9.port.-1.b.0.signedPrecision=0 -unit.1.9.port.-1.b.0.signedScaleFactor=1.0 -unit.1.9.port.-1.b.0.tokencount=0 -unit.1.9.port.-1.b.0.unsignedOffset=0.0 -unit.1.9.port.-1.b.0.unsignedPrecision=0 -unit.1.9.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.9.port.-1.b.0.visible=1 -unit.1.9.port.-1.b.1.alias=dsp_tbt_pha_ch1 -unit.1.9.port.-1.b.1.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.9.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.9.port.-1.b.1.name=DataPort -unit.1.9.port.-1.b.1.orderindex=-1 -unit.1.9.port.-1.b.1.radix=Signed -unit.1.9.port.-1.b.1.signedOffset=0.0 -unit.1.9.port.-1.b.1.signedPrecision=0 -unit.1.9.port.-1.b.1.signedScaleFactor=1.0 -unit.1.9.port.-1.b.1.tokencount=0 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-unit.1.9.port.2.s.16.orderindex=-1 -unit.1.9.port.2.s.16.visible=1 -unit.1.9.port.2.s.17.alias= -unit.1.9.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.17.name=TriggerPort2[17] -unit.1.9.port.2.s.17.orderindex=-1 -unit.1.9.port.2.s.17.visible=1 -unit.1.9.port.2.s.18.alias= -unit.1.9.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.18.name=TriggerPort2[18] -unit.1.9.port.2.s.18.orderindex=-1 -unit.1.9.port.2.s.18.visible=1 -unit.1.9.port.2.s.19.alias= -unit.1.9.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.19.name=TriggerPort2[19] -unit.1.9.port.2.s.19.orderindex=-1 -unit.1.9.port.2.s.19.visible=1 -unit.1.9.port.2.s.2.alias= -unit.1.9.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.2.name=TriggerPort2[2] -unit.1.9.port.2.s.2.orderindex=-1 -unit.1.9.port.2.s.2.visible=1 -unit.1.9.port.2.s.20.alias= -unit.1.9.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.20.name=TriggerPort2[20] -unit.1.9.port.2.s.20.orderindex=-1 -unit.1.9.port.2.s.20.visible=1 -unit.1.9.port.2.s.21.alias= -unit.1.9.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.21.name=TriggerPort2[21] -unit.1.9.port.2.s.21.orderindex=-1 -unit.1.9.port.2.s.21.visible=1 -unit.1.9.port.2.s.22.alias= -unit.1.9.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.22.name=TriggerPort2[22] -unit.1.9.port.2.s.22.orderindex=-1 -unit.1.9.port.2.s.22.visible=1 -unit.1.9.port.2.s.23.alias= -unit.1.9.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.23.name=TriggerPort2[23] -unit.1.9.port.2.s.23.orderindex=-1 -unit.1.9.port.2.s.23.visible=1 -unit.1.9.port.2.s.24.alias= -unit.1.9.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.24.name=TriggerPort2[24] -unit.1.9.port.2.s.24.orderindex=-1 -unit.1.9.port.2.s.24.visible=1 -unit.1.9.port.2.s.25.alias= -unit.1.9.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.25.name=TriggerPort2[25] -unit.1.9.port.2.s.25.orderindex=-1 -unit.1.9.port.2.s.25.visible=1 -unit.1.9.port.2.s.26.alias= -unit.1.9.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.26.name=TriggerPort2[26] -unit.1.9.port.2.s.26.orderindex=-1 -unit.1.9.port.2.s.26.visible=1 -unit.1.9.port.2.s.27.alias= -unit.1.9.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.27.name=TriggerPort2[27] -unit.1.9.port.2.s.27.orderindex=-1 -unit.1.9.port.2.s.27.visible=1 -unit.1.9.port.2.s.28.alias= -unit.1.9.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.28.name=TriggerPort2[28] -unit.1.9.port.2.s.28.orderindex=-1 -unit.1.9.port.2.s.28.visible=1 -unit.1.9.port.2.s.29.alias= -unit.1.9.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.2.s.29.name=TriggerPort2[29] -unit.1.9.port.2.s.29.orderindex=-1 -unit.1.9.port.2.s.29.visible=1 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-unit.1.9.port.3.s.10.orderindex=-1 -unit.1.9.port.3.s.10.visible=1 -unit.1.9.port.3.s.11.alias= -unit.1.9.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.11.name=TriggerPort3[11] -unit.1.9.port.3.s.11.orderindex=-1 -unit.1.9.port.3.s.11.visible=1 -unit.1.9.port.3.s.12.alias= -unit.1.9.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.12.name=TriggerPort3[12] -unit.1.9.port.3.s.12.orderindex=-1 -unit.1.9.port.3.s.12.visible=1 -unit.1.9.port.3.s.13.alias= -unit.1.9.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.13.name=TriggerPort3[13] -unit.1.9.port.3.s.13.orderindex=-1 -unit.1.9.port.3.s.13.visible=1 -unit.1.9.port.3.s.14.alias= -unit.1.9.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.14.name=TriggerPort3[14] -unit.1.9.port.3.s.14.orderindex=-1 -unit.1.9.port.3.s.14.visible=1 -unit.1.9.port.3.s.15.alias= -unit.1.9.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.9.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.2.name=TriggerPort3[2] -unit.1.9.port.3.s.2.orderindex=-1 -unit.1.9.port.3.s.2.visible=1 -unit.1.9.port.3.s.20.alias= -unit.1.9.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.20.name=TriggerPort3[20] -unit.1.9.port.3.s.20.orderindex=-1 -unit.1.9.port.3.s.20.visible=1 -unit.1.9.port.3.s.21.alias= -unit.1.9.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.21.name=TriggerPort3[21] -unit.1.9.port.3.s.21.orderindex=-1 -unit.1.9.port.3.s.21.visible=1 -unit.1.9.port.3.s.22.alias= -unit.1.9.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.22.name=TriggerPort3[22] -unit.1.9.port.3.s.22.orderindex=-1 -unit.1.9.port.3.s.22.visible=1 -unit.1.9.port.3.s.23.alias= -unit.1.9.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.9.port.3.s.23.name=TriggerPort3[23] -unit.1.9.port.3.s.23.orderindex=-1 -unit.1.9.port.3.s.23.visible=1 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-unit.1.9.vio.posn.94.type=signal -unit.1.9.vio.posn.95.channel=255 -unit.1.9.vio.posn.95.name=AsyncOut[255] -unit.1.9.vio.posn.95.port=1 -unit.1.9.vio.posn.95.radix=1 -unit.1.9.vio.posn.95.type=signal -unit.1.9.vio.posn.96.channel=255 -unit.1.9.vio.posn.96.name=AsyncOut[255] -unit.1.9.vio.posn.96.port=1 -unit.1.9.vio.posn.96.radix=1 -unit.1.9.vio.posn.96.type=signal -unit.1.9.vio.posn.97.channel=255 -unit.1.9.vio.posn.97.name=AsyncOut[255] -unit.1.9.vio.posn.97.port=1 -unit.1.9.vio.posn.97.radix=1 -unit.1.9.vio.posn.97.type=signal -unit.1.9.vio.posn.98.channel=255 -unit.1.9.vio.posn.98.name=AsyncOut[255] -unit.1.9.vio.posn.98.port=1 -unit.1.9.vio.posn.98.radix=1 -unit.1.9.vio.posn.98.type=signal -unit.1.9.vio.posn.99.channel=255 -unit.1.9.vio.posn.99.name=AsyncOut[255] -unit.1.9.vio.posn.99.port=1 -unit.1.9.vio.posn.99.radix=1 -unit.1.9.vio.posn.99.type=signal -unit.1.9.vio.readperiod=0 diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope_2.cpj b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope_2.cpj deleted file mode 100644 index e10675b4..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/chipscope_2.cpj +++ /dev/null @@ -1,13480 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Tue Apr 23 13:17:37 BRT 2013 -avoidUserRegDevice1=2,3,4 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109364250093 -mdiAreaHeight=0.7114942528735633 -mdiAreaHeightLast=0.6540229885057471 -mdiCount=20 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice10=1 -mdiDevice11=1 -mdiDevice12=1 -mdiDevice13=1 -mdiDevice14=1 -mdiDevice15=1 -mdiDevice16=1 -mdiDevice17=1 -mdiDevice18=1 -mdiDevice19=1 -mdiDevice2=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiDevice6=1 -mdiDevice7=1 -mdiDevice8=1 -mdiDevice9=1 -mdiType0=5 -mdiType1=1 -mdiType10=5 -mdiType11=0 -mdiType12=1 -mdiType13=5 -mdiType14=0 -mdiType15=1 -mdiType16=5 -mdiType17=0 -mdiType18=1 -mdiType19=5 -mdiType2=5 -mdiType3=0 -mdiType4=0 -mdiType5=0 -mdiType6=1 -mdiType7=5 -mdiType8=0 -mdiType9=1 -mdiUnit0=1 -mdiUnit1=0 -mdiUnit10=3 -mdiUnit11=4 -mdiUnit12=4 -mdiUnit13=4 -mdiUnit14=5 -mdiUnit15=5 -mdiUnit16=5 -mdiUnit17=6 -mdiUnit18=6 -mdiUnit19=6 -mdiUnit2=0 -mdiUnit3=1 -mdiUnit4=0 -mdiUnit5=2 -mdiUnit6=2 -mdiUnit7=2 -mdiUnit8=3 -mdiUnit9=3 -navigatorHeight=0.16666666666666666 -navigatorHeightLast=0.16666666666666666 -navigatorWidth=0.13320825515947468 -navigatorWidthLast=0.13320825515947468 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.44805196 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=0.70772594 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5211039 -unit.1.0.1.WIDTH1=0.70772594 -unit.1.0.1.X1=0.0 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-unit.1.0.port.-1.s.88.visible=1 -unit.1.0.port.-1.s.89.alias= -unit.1.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.89.name=DataPort[89] -unit.1.0.port.-1.s.89.orderindex=-1 -unit.1.0.port.-1.s.89.visible=1 -unit.1.0.port.-1.s.9.alias= -unit.1.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.9.name=DataPort[9] -unit.1.0.port.-1.s.9.orderindex=-1 -unit.1.0.port.-1.s.9.visible=0 -unit.1.0.port.-1.s.90.alias= -unit.1.0.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.90.name=DataPort[90] -unit.1.0.port.-1.s.90.orderindex=-1 -unit.1.0.port.-1.s.90.visible=1 -unit.1.0.port.-1.s.91.alias= -unit.1.0.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.91.name=DataPort[91] -unit.1.0.port.-1.s.91.orderindex=-1 -unit.1.0.port.-1.s.91.visible=1 -unit.1.0.port.-1.s.92.alias= -unit.1.0.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.92.name=DataPort[92] -unit.1.0.port.-1.s.92.orderindex=-1 -unit.1.0.port.-1.s.92.visible=1 -unit.1.0.port.-1.s.93.alias= -unit.1.0.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.93.name=DataPort[93] -unit.1.0.port.-1.s.93.orderindex=-1 -unit.1.0.port.-1.s.93.visible=1 -unit.1.0.port.-1.s.94.alias= -unit.1.0.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.94.name=DataPort[94] -unit.1.0.port.-1.s.94.orderindex=-1 -unit.1.0.port.-1.s.94.visible=1 -unit.1.0.port.-1.s.95.alias= -unit.1.0.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.95.name=DataPort[95] -unit.1.0.port.-1.s.95.orderindex=-1 -unit.1.0.port.-1.s.95.visible=1 -unit.1.0.port.-1.s.96.alias= -unit.1.0.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.96.name=DataPort[96] -unit.1.0.port.-1.s.96.orderindex=-1 -unit.1.0.port.-1.s.96.visible=1 -unit.1.0.port.-1.s.97.alias= -unit.1.0.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.97.name=DataPort[97] -unit.1.0.port.-1.s.97.orderindex=-1 -unit.1.0.port.-1.s.97.visible=1 -unit.1.0.port.-1.s.98.alias= -unit.1.0.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.98.name=DataPort[98] -unit.1.0.port.-1.s.98.orderindex=-1 -unit.1.0.port.-1.s.98.visible=1 -unit.1.0.port.-1.s.99.alias= -unit.1.0.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.99.name=DataPort[99] -unit.1.0.port.-1.s.99.orderindex=-1 -unit.1.0.port.-1.s.99.visible=1 -unit.1.0.port.0.b.0.alias= -unit.1.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.b.0.name=TriggerPort0 -unit.1.0.port.0.b.0.orderindex=-1 -unit.1.0.port.0.b.0.radix=Hex -unit.1.0.port.0.b.0.signedOffset=0.0 -unit.1.0.port.0.b.0.signedPrecision=0 -unit.1.0.port.0.b.0.signedScaleFactor=1.0 -unit.1.0.port.0.b.0.unsignedOffset=0.0 -unit.1.0.port.0.b.0.unsignedPrecision=0 -unit.1.0.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.0.b.0.visible=1 -unit.1.0.port.0.buscount=1 -unit.1.0.port.0.channelcount=32 -unit.1.0.port.0.s.0.alias= -unit.1.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= -unit.1.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.10.name=TriggerPort0[10] -unit.1.0.port.0.s.10.orderindex=-1 -unit.1.0.port.0.s.10.visible=1 -unit.1.0.port.0.s.11.alias= -unit.1.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.11.name=TriggerPort0[11] -unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= -unit.1.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.10.name=TriggerPort3[10] -unit.1.0.port.3.s.10.orderindex=-1 -unit.1.0.port.3.s.10.visible=1 -unit.1.0.port.3.s.11.alias= -unit.1.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.11.name=TriggerPort3[11] -unit.1.0.port.3.s.11.orderindex=-1 -unit.1.0.port.3.s.11.visible=1 -unit.1.0.port.3.s.12.alias= -unit.1.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.12.name=TriggerPort3[12] -unit.1.0.port.3.s.12.orderindex=-1 -unit.1.0.port.3.s.12.visible=1 -unit.1.0.port.3.s.13.alias= -unit.1.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.13.name=TriggerPort3[13] -unit.1.0.port.3.s.13.orderindex=-1 -unit.1.0.port.3.s.13.visible=1 -unit.1.0.port.3.s.14.alias= -unit.1.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.14.name=TriggerPort3[14] -unit.1.0.port.3.s.14.orderindex=-1 -unit.1.0.port.3.s.14.visible=1 -unit.1.0.port.3.s.15.alias= -unit.1.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.15.name=TriggerPort3[15] -unit.1.0.port.3.s.15.orderindex=-1 -unit.1.0.port.3.s.15.visible=1 -unit.1.0.port.3.s.16.alias= -unit.1.0.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.16.name=TriggerPort3[16] -unit.1.0.port.3.s.16.orderindex=-1 -unit.1.0.port.3.s.16.visible=1 -unit.1.0.port.3.s.17.alias= -unit.1.0.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.17.name=TriggerPort3[17] -unit.1.0.port.3.s.17.orderindex=-1 -unit.1.0.port.3.s.17.visible=1 -unit.1.0.port.3.s.18.alias= -unit.1.0.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.18.name=TriggerPort3[18] -unit.1.0.port.3.s.18.orderindex=-1 -unit.1.0.port.3.s.18.visible=1 -unit.1.0.port.3.s.19.alias= -unit.1.0.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.19.name=TriggerPort3[19] -unit.1.0.port.3.s.19.orderindex=-1 -unit.1.0.port.3.s.19.visible=1 -unit.1.0.port.3.s.2.alias= -unit.1.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.2.name=TriggerPort3[2] -unit.1.0.port.3.s.2.orderindex=-1 -unit.1.0.port.3.s.2.visible=1 -unit.1.0.port.3.s.20.alias= -unit.1.0.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.20.name=TriggerPort3[20] -unit.1.0.port.3.s.20.orderindex=-1 -unit.1.0.port.3.s.20.visible=1 -unit.1.0.port.3.s.21.alias= -unit.1.0.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.21.name=TriggerPort3[21] -unit.1.0.port.3.s.21.orderindex=-1 -unit.1.0.port.3.s.21.visible=1 -unit.1.0.port.3.s.22.alias= -unit.1.0.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.22.name=TriggerPort3[22] -unit.1.0.port.3.s.22.orderindex=-1 -unit.1.0.port.3.s.22.visible=1 -unit.1.0.port.3.s.23.alias= -unit.1.0.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.23.name=TriggerPort3[23] -unit.1.0.port.3.s.23.orderindex=-1 -unit.1.0.port.3.s.23.visible=1 -unit.1.0.port.3.s.24.alias= -unit.1.0.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.24.name=TriggerPort3[24] -unit.1.0.port.3.s.24.orderindex=-1 -unit.1.0.port.3.s.24.visible=1 -unit.1.0.port.3.s.25.alias= -unit.1.0.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.25.name=TriggerPort3[25] -unit.1.0.port.3.s.25.orderindex=-1 -unit.1.0.port.3.s.25.visible=1 -unit.1.0.port.3.s.26.alias= -unit.1.0.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.26.name=TriggerPort3[26] -unit.1.0.port.3.s.26.orderindex=-1 -unit.1.0.port.3.s.26.visible=1 -unit.1.0.port.3.s.27.alias= -unit.1.0.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.27.name=TriggerPort3[27] -unit.1.0.port.3.s.27.orderindex=-1 -unit.1.0.port.3.s.27.visible=1 -unit.1.0.port.3.s.28.alias= -unit.1.0.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.28.name=TriggerPort3[28] -unit.1.0.port.3.s.28.orderindex=-1 -unit.1.0.port.3.s.28.visible=1 -unit.1.0.port.3.s.29.alias= -unit.1.0.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.29.name=TriggerPort3[29] -unit.1.0.port.3.s.29.orderindex=-1 -unit.1.0.port.3.s.29.visible=1 -unit.1.0.port.3.s.3.alias= -unit.1.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.3.name=TriggerPort3[3] -unit.1.0.port.3.s.3.orderindex=-1 -unit.1.0.port.3.s.3.visible=1 -unit.1.0.port.3.s.30.alias= -unit.1.0.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=MyILA0 -unit.1.0.waveform.count=4 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=adc_data_ch3 -unit.1.0.waveform.posn.0.radix=3 -unit.1.0.waveform.posn.0.type=bus -unit.1.0.waveform.posn.1.channel=2147483646 -unit.1.0.waveform.posn.1.name=adc_data_ch2 -unit.1.0.waveform.posn.1.radix=3 -unit.1.0.waveform.posn.1.type=bus -unit.1.0.waveform.posn.10.channel=2147483646 -unit.1.0.waveform.posn.10.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.10.radix=1 -unit.1.0.waveform.posn.10.type=bus -unit.1.0.waveform.posn.100.channel=127 -unit.1.0.waveform.posn.100.name=DataPort[127] -unit.1.0.waveform.posn.100.type=signal -unit.1.0.waveform.posn.101.channel=127 -unit.1.0.waveform.posn.101.name=DataPort[127] -unit.1.0.waveform.posn.101.type=signal -unit.1.0.waveform.posn.102.channel=127 -unit.1.0.waveform.posn.102.name=DataPort[127] -unit.1.0.waveform.posn.102.type=signal -unit.1.0.waveform.posn.103.channel=127 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-unit.1.0.waveform.posn.13.channel=2147483646 -unit.1.0.waveform.posn.13.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.13.radix=1 -unit.1.0.waveform.posn.13.type=bus -unit.1.0.waveform.posn.2.channel=2147483646 -unit.1.0.waveform.posn.2.name=adc_data_ch1 -unit.1.0.waveform.posn.2.radix=3 -unit.1.0.waveform.posn.2.type=bus -unit.1.0.waveform.posn.3.channel=2147483646 -unit.1.0.waveform.posn.3.name=adc_data_ch0 -unit.1.0.waveform.posn.3.radix=3 -unit.1.0.waveform.posn.3.type=bus -unit.1.0.waveform.posn.4.channel=2147483646 -unit.1.0.waveform.posn.4.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.4.radix=1 -unit.1.0.waveform.posn.4.type=bus -unit.1.0.waveform.posn.5.channel=2147483646 -unit.1.0.waveform.posn.5.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.5.radix=1 -unit.1.0.waveform.posn.5.type=bus -unit.1.0.waveform.posn.6.channel=2147483646 -unit.1.0.waveform.posn.6.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.6.radix=1 -unit.1.0.waveform.posn.6.type=bus -unit.1.0.waveform.posn.7.channel=2147483646 -unit.1.0.waveform.posn.7.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.7.radix=1 -unit.1.0.waveform.posn.7.type=bus -unit.1.0.waveform.posn.8.channel=2147483646 -unit.1.0.waveform.posn.8.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.37337664 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.6727405 -unit.1.1.0.X0=0.034985423 -unit.1.1.0.Y0=0.0 -unit.1.1.1.HEIGHT1=0.84889644 -unit.1.1.1.WIDTH1=0.90138674 -unit.1.1.1.X1=0.07395994 -unit.1.1.1.Y1=0.3344652 -unit.1.1.5.HEIGHT5=0.77922076 -unit.1.1.5.WIDTH5=0.6202624 -unit.1.1.5.X5=0.029154519 -unit.1.1.5.Y5=0.15746753 -unit.1.1.MFBitsA0=XXXXX1XX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 -unit.1.1.MFBitsB2=00000000000000000000000000000000 -unit.1.1.MFBitsB3=00000000000000000000000000000000 -unit.1.1.MFBitsB4=00000000000000000000000000000000 -unit.1.1.MFCompareA0=0 -unit.1.1.MFCompareA1=0 -unit.1.1.MFCompareA2=0 -unit.1.1.MFCompareA3=0 -unit.1.1.MFCompareA4=0 -unit.1.1.MFCompareB0=999 -unit.1.1.MFCompareB1=999 -unit.1.1.MFCompareB2=999 -unit.1.1.MFCompareB3=999 -unit.1.1.MFCompareB4=999 -unit.1.1.MFCount=5 -unit.1.1.MFDisplay0=0 -unit.1.1.MFDisplay1=0 -unit.1.1.MFDisplay2=0 -unit.1.1.MFDisplay3=0 -unit.1.1.MFDisplay4=0 -unit.1.1.MFEventType0=3 -unit.1.1.MFEventType1=3 -unit.1.1.MFEventType2=3 -unit.1.1.MFEventType3=3 -unit.1.1.MFEventType4=3 -unit.1.1.RunMode=SINGLE RUN -unit.1.1.SQCondition=M0 -unit.1.1.SQContiguous0=0 -unit.1.1.SequencerOn=0 -unit.1.1.TCActive=0 -unit.1.1.TCAdvanced0=0 -unit.1.1.TCCondition0_0=M0 -unit.1.1.TCCondition0_1= -unit.1.1.TCConditionType0=0 -unit.1.1.TCCount=1 -unit.1.1.TCEventCount0=1 -unit.1.1.TCEventType0=3 -unit.1.1.TCName0=TriggerCondition0 -unit.1.1.TCOutputEnable0=0 -unit.1.1.TCOutputHigh0=1 -unit.1.1.TCOutputMode0=0 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.coretype=ILA -unit.1.1.eventCount0=1 -unit.1.1.eventCount1=1 -unit.1.1.eventCount2=1 -unit.1.1.eventCount3=1 -unit.1.1.eventCount4=1 -unit.1.1.plotBusColor0=-16777092 -unit.1.1.plotBusColor1=-3407770 -unit.1.1.plotBusColor2=-6723841 -unit.1.1.plotBusColor3=-6711040 -unit.1.1.plotBusCount=4 -unit.1.1.plotBusName0=dsp_poly35_ch0 -unit.1.1.plotBusName1=dsp_poly35_ch2 -unit.1.1.plotBusName2=dsp_mix_ch0 -unit.1.1.plotBusName3=dsp_mix_ch2 -unit.1.1.plotBusX=dsp_poly35_ch0 -unit.1.1.plotBusY=dsp_poly35_ch0 -unit.1.1.plotDataTimeMode=1 -unit.1.1.plotDisplayMode=line -unit.1.1.plotMaxX=0.0 -unit.1.1.plotMaxY=0.0 -unit.1.1.plotMinX=0.0 -unit.1.1.plotMinY=0.0 -unit.1.1.plotSelectedBus=0 -unit.1.1.port.-1.b.0.alias=dsp_mix_ch0 -unit.1.1.port.-1.b.0.channellist=72 73 74 76 75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.1.port.-1.b.0.color=java.awt.Color[r\=153,g\=102,b\=255] -unit.1.1.port.-1.b.0.name=DataPort -unit.1.1.port.-1.b.0.orderindex=-1 -unit.1.1.port.-1.b.0.radix=Signed -unit.1.1.port.-1.b.0.signedOffset=0.0 -unit.1.1.port.-1.b.0.signedPrecision=0 -unit.1.1.port.-1.b.0.signedScaleFactor=1.0 -unit.1.1.port.-1.b.0.tokencount=0 -unit.1.1.port.-1.b.0.unsignedOffset=0.0 -unit.1.1.port.-1.b.0.unsignedPrecision=0 -unit.1.1.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.0.visible=1 -unit.1.1.port.-1.b.1.alias=dsp_mix_ch2 -unit.1.1.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 -unit.1.1.port.-1.b.1.color=java.awt.Color[r\=153,g\=153,b\=0] -unit.1.1.port.-1.b.1.name=DataPort -unit.1.1.port.-1.b.1.orderindex=-1 -unit.1.1.port.-1.b.1.radix=Signed -unit.1.1.port.-1.b.1.signedOffset=0.0 -unit.1.1.port.-1.b.1.signedPrecision=0 -unit.1.1.port.-1.b.1.signedScaleFactor=1.0 -unit.1.1.port.-1.b.1.tokencount=0 -unit.1.1.port.-1.b.1.unsignedOffset=0.0 -unit.1.1.port.-1.b.1.unsignedPrecision=0 -unit.1.1.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.1.visible=1 -unit.1.1.port.-1.b.2.alias=dsp_poly35_ch0 -unit.1.1.port.-1.b.2.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.b.2.name=DataPort -unit.1.1.port.-1.b.2.orderindex=-1 -unit.1.1.port.-1.b.2.radix=Signed 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-unit.1.1.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.106.name=DataPort[106] -unit.1.1.port.-1.s.106.orderindex=-1 -unit.1.1.port.-1.s.106.visible=0 -unit.1.1.port.-1.s.107.alias= -unit.1.1.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.107.name=DataPort[107] -unit.1.1.port.-1.s.107.orderindex=-1 -unit.1.1.port.-1.s.107.visible=0 -unit.1.1.port.-1.s.108.alias= -unit.1.1.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.108.name=DataPort[108] -unit.1.1.port.-1.s.108.orderindex=-1 -unit.1.1.port.-1.s.108.visible=0 -unit.1.1.port.-1.s.109.alias= -unit.1.1.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.109.name=DataPort[109] -unit.1.1.port.-1.s.109.orderindex=-1 -unit.1.1.port.-1.s.109.visible=0 -unit.1.1.port.-1.s.11.alias= -unit.1.1.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.11.name=DataPort[11] -unit.1.1.port.-1.s.11.orderindex=-1 -unit.1.1.port.-1.s.11.visible=0 -unit.1.1.port.-1.s.110.alias= -unit.1.1.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.110.name=DataPort[110] -unit.1.1.port.-1.s.110.orderindex=-1 -unit.1.1.port.-1.s.110.visible=0 -unit.1.1.port.-1.s.111.alias= -unit.1.1.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.111.name=DataPort[111] -unit.1.1.port.-1.s.111.orderindex=-1 -unit.1.1.port.-1.s.111.visible=0 -unit.1.1.port.-1.s.112.alias= -unit.1.1.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.112.name=DataPort[112] -unit.1.1.port.-1.s.112.orderindex=-1 -unit.1.1.port.-1.s.112.visible=0 -unit.1.1.port.-1.s.113.alias= -unit.1.1.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.113.name=DataPort[113] -unit.1.1.port.-1.s.113.orderindex=-1 -unit.1.1.port.-1.s.113.visible=0 -unit.1.1.port.-1.s.114.alias= -unit.1.1.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.114.name=DataPort[114] -unit.1.1.port.-1.s.114.orderindex=-1 -unit.1.1.port.-1.s.114.visible=0 -unit.1.1.port.-1.s.115.alias= -unit.1.1.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.115.name=DataPort[115] -unit.1.1.port.-1.s.115.orderindex=-1 -unit.1.1.port.-1.s.115.visible=0 -unit.1.1.port.-1.s.116.alias= -unit.1.1.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.116.name=DataPort[116] -unit.1.1.port.-1.s.116.orderindex=-1 -unit.1.1.port.-1.s.116.visible=0 -unit.1.1.port.-1.s.117.alias= -unit.1.1.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.117.name=DataPort[117] -unit.1.1.port.-1.s.117.orderindex=-1 -unit.1.1.port.-1.s.117.visible=0 -unit.1.1.port.-1.s.118.alias= -unit.1.1.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.118.name=DataPort[118] -unit.1.1.port.-1.s.118.orderindex=-1 -unit.1.1.port.-1.s.118.visible=0 -unit.1.1.port.-1.s.119.alias= -unit.1.1.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.119.name=DataPort[119] -unit.1.1.port.-1.s.119.orderindex=-1 -unit.1.1.port.-1.s.119.visible=0 -unit.1.1.port.-1.s.12.alias= -unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=0 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=0 -unit.1.1.port.-1.s.121.alias= -unit.1.1.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.121.name=DataPort[121] -unit.1.1.port.-1.s.121.orderindex=-1 -unit.1.1.port.-1.s.121.visible=0 -unit.1.1.port.-1.s.122.alias= -unit.1.1.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.122.name=DataPort[122] -unit.1.1.port.-1.s.122.orderindex=-1 -unit.1.1.port.-1.s.122.visible=0 -unit.1.1.port.-1.s.123.alias= -unit.1.1.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.123.name=DataPort[123] -unit.1.1.port.-1.s.123.orderindex=-1 -unit.1.1.port.-1.s.123.visible=0 -unit.1.1.port.-1.s.124.alias= -unit.1.1.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.124.name=DataPort[124] -unit.1.1.port.-1.s.124.orderindex=-1 -unit.1.1.port.-1.s.124.visible=0 -unit.1.1.port.-1.s.125.alias= -unit.1.1.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.125.name=DataPort[125] -unit.1.1.port.-1.s.125.orderindex=-1 -unit.1.1.port.-1.s.125.visible=0 -unit.1.1.port.-1.s.126.alias= -unit.1.1.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.126.name=DataPort[126] -unit.1.1.port.-1.s.126.orderindex=-1 -unit.1.1.port.-1.s.126.visible=0 -unit.1.1.port.-1.s.127.alias= -unit.1.1.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.127.name=DataPort[127] -unit.1.1.port.-1.s.127.orderindex=-1 -unit.1.1.port.-1.s.127.visible=0 -unit.1.1.port.-1.s.128.alias= -unit.1.1.port.-1.s.128.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.128.name=DataPort[128] -unit.1.1.port.-1.s.128.orderindex=-1 -unit.1.1.port.-1.s.128.visible=1 -unit.1.1.port.-1.s.129.alias= -unit.1.1.port.-1.s.129.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.129.name=DataPort[129] -unit.1.1.port.-1.s.129.orderindex=-1 -unit.1.1.port.-1.s.129.visible=1 -unit.1.1.port.-1.s.13.alias= -unit.1.1.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.13.name=DataPort[13] -unit.1.1.port.-1.s.13.orderindex=-1 -unit.1.1.port.-1.s.13.visible=0 -unit.1.1.port.-1.s.130.alias= -unit.1.1.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.130.name=DataPort[130] -unit.1.1.port.-1.s.130.orderindex=-1 -unit.1.1.port.-1.s.130.visible=1 -unit.1.1.port.-1.s.131.alias= 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-unit.1.1.port.-1.s.66.name=DataPort[66] -unit.1.1.port.-1.s.66.orderindex=-1 -unit.1.1.port.-1.s.66.visible=1 -unit.1.1.port.-1.s.67.alias= -unit.1.1.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.67.name=DataPort[67] -unit.1.1.port.-1.s.67.orderindex=-1 -unit.1.1.port.-1.s.67.visible=1 -unit.1.1.port.-1.s.68.alias= -unit.1.1.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.68.name=DataPort[68] -unit.1.1.port.-1.s.68.orderindex=-1 -unit.1.1.port.-1.s.68.visible=1 -unit.1.1.port.-1.s.69.alias= -unit.1.1.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.69.name=DataPort[69] -unit.1.1.port.-1.s.69.orderindex=-1 -unit.1.1.port.-1.s.69.visible=1 -unit.1.1.port.-1.s.7.alias= -unit.1.1.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.7.name=DataPort[7] -unit.1.1.port.-1.s.7.orderindex=-1 -unit.1.1.port.-1.s.7.visible=1 -unit.1.1.port.-1.s.70.alias= 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-unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.1.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.6.name=TriggerPort4[6] -unit.1.1.port.4.s.6.orderindex=-1 -unit.1.1.port.4.s.6.visible=1 -unit.1.1.port.4.s.7.alias= -unit.1.1.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.7.name=TriggerPort4[7] -unit.1.1.port.4.s.7.orderindex=-1 -unit.1.1.port.4.s.7.visible=1 -unit.1.1.port.4.s.8.alias= -unit.1.1.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.8.name=TriggerPort4[8] -unit.1.1.port.4.s.8.orderindex=-1 -unit.1.1.port.4.s.8.visible=1 -unit.1.1.port.4.s.9.alias= -unit.1.1.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.9.name=TriggerPort4[9] -unit.1.1.port.4.s.9.orderindex=-1 -unit.1.1.port.4.s.9.visible=1 -unit.1.1.portcount=5 -unit.1.1.rep_trigger.clobber=1 -unit.1.1.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.1.rep_trigger.filename=waveform -unit.1.1.rep_trigger.format=ASCII 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-unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=127 -unit.1.1.waveform.posn.93.name=DataPort[127] -unit.1.1.waveform.posn.93.type=signal -unit.1.1.waveform.posn.94.channel=127 -unit.1.1.waveform.posn.94.name=DataPort[127] -unit.1.1.waveform.posn.94.type=signal -unit.1.1.waveform.posn.95.channel=127 -unit.1.1.waveform.posn.95.name=DataPort[127] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=127 -unit.1.1.waveform.posn.96.name=DataPort[127] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal -unit.1.2.0.HEIGHT0=0.37337664 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 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-unit.1.2.port.-1.s.69.visible=1 -unit.1.2.port.-1.s.7.alias= -unit.1.2.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.7.name=DataPort[7] -unit.1.2.port.-1.s.7.orderindex=-1 -unit.1.2.port.-1.s.7.visible=1 -unit.1.2.port.-1.s.70.alias= -unit.1.2.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.70.name=DataPort[70] -unit.1.2.port.-1.s.70.orderindex=-1 -unit.1.2.port.-1.s.70.visible=1 -unit.1.2.port.-1.s.71.alias= -unit.1.2.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.71.name=DataPort[71] -unit.1.2.port.-1.s.71.orderindex=-1 -unit.1.2.port.-1.s.71.visible=1 -unit.1.2.port.-1.s.72.alias= -unit.1.2.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.72.name=DataPort[72] -unit.1.2.port.-1.s.72.orderindex=-1 -unit.1.2.port.-1.s.72.visible=0 -unit.1.2.port.-1.s.73.alias= -unit.1.2.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.73.name=DataPort[73] -unit.1.2.port.-1.s.73.orderindex=-1 -unit.1.2.port.-1.s.73.visible=0 -unit.1.2.port.-1.s.74.alias= -unit.1.2.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.74.name=DataPort[74] -unit.1.2.port.-1.s.74.orderindex=-1 -unit.1.2.port.-1.s.74.visible=0 -unit.1.2.port.-1.s.75.alias= -unit.1.2.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.75.name=DataPort[75] -unit.1.2.port.-1.s.75.orderindex=-1 -unit.1.2.port.-1.s.75.visible=0 -unit.1.2.port.-1.s.76.alias= -unit.1.2.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.76.name=DataPort[76] -unit.1.2.port.-1.s.76.orderindex=-1 -unit.1.2.port.-1.s.76.visible=0 -unit.1.2.port.-1.s.77.alias= -unit.1.2.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.77.name=DataPort[77] -unit.1.2.port.-1.s.77.orderindex=-1 -unit.1.2.port.-1.s.77.visible=0 -unit.1.2.port.-1.s.78.alias= -unit.1.2.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.78.name=DataPort[78] -unit.1.2.port.-1.s.78.orderindex=-1 -unit.1.2.port.-1.s.78.visible=0 -unit.1.2.port.-1.s.79.alias= -unit.1.2.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.79.name=DataPort[79] -unit.1.2.port.-1.s.79.orderindex=-1 -unit.1.2.port.-1.s.79.visible=0 -unit.1.2.port.-1.s.8.alias= -unit.1.2.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.8.name=DataPort[8] -unit.1.2.port.-1.s.8.orderindex=-1 -unit.1.2.port.-1.s.8.visible=0 -unit.1.2.port.-1.s.80.alias= -unit.1.2.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.80.name=DataPort[80] -unit.1.2.port.-1.s.80.orderindex=-1 -unit.1.2.port.-1.s.80.visible=0 -unit.1.2.port.-1.s.81.alias= -unit.1.2.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.81.name=DataPort[81] -unit.1.2.port.-1.s.81.orderindex=-1 -unit.1.2.port.-1.s.81.visible=0 -unit.1.2.port.-1.s.82.alias= -unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=0 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=0 -unit.1.2.port.-1.s.84.alias= -unit.1.2.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.84.name=DataPort[84] -unit.1.2.port.-1.s.84.orderindex=-1 -unit.1.2.port.-1.s.84.visible=0 -unit.1.2.port.-1.s.85.alias= -unit.1.2.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.85.name=DataPort[85] -unit.1.2.port.-1.s.85.orderindex=-1 -unit.1.2.port.-1.s.85.visible=0 -unit.1.2.port.-1.s.86.alias= -unit.1.2.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.86.name=DataPort[86] -unit.1.2.port.-1.s.86.orderindex=-1 -unit.1.2.port.-1.s.86.visible=0 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-unit.1.2.port.-1.s.90.visible=0 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=0 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 -unit.1.2.port.-1.s.92.visible=0 -unit.1.2.port.-1.s.93.alias= -unit.1.2.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.93.name=DataPort[93] -unit.1.2.port.-1.s.93.orderindex=-1 -unit.1.2.port.-1.s.93.visible=0 -unit.1.2.port.-1.s.94.alias= -unit.1.2.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.94.name=DataPort[94] -unit.1.2.port.-1.s.94.orderindex=-1 -unit.1.2.port.-1.s.94.visible=0 -unit.1.2.port.-1.s.95.alias= -unit.1.2.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.95.name=DataPort[95] -unit.1.2.port.-1.s.95.orderindex=-1 -unit.1.2.port.-1.s.95.visible=0 -unit.1.2.port.-1.s.96.alias= -unit.1.2.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.96.name=DataPort[96] -unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=0 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 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-unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 -unit.1.2.port.3.s.27.alias= -unit.1.2.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.27.name=TriggerPort3[27] -unit.1.2.port.3.s.27.orderindex=-1 -unit.1.2.port.3.s.27.visible=1 -unit.1.2.port.3.s.28.alias= -unit.1.2.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.28.name=TriggerPort3[28] -unit.1.2.port.3.s.28.orderindex=-1 -unit.1.2.port.3.s.28.visible=1 -unit.1.2.port.3.s.29.alias= -unit.1.2.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.29.name=TriggerPort3[29] -unit.1.2.port.3.s.29.orderindex=-1 -unit.1.2.port.3.s.29.visible=1 -unit.1.2.port.3.s.3.alias= -unit.1.2.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.3.name=TriggerPort3[3] -unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.port.4.b.0.alias= -unit.1.2.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.b.0.name=TriggerPort4 -unit.1.2.port.4.b.0.orderindex=-1 -unit.1.2.port.4.b.0.radix=Hex -unit.1.2.port.4.b.0.signedOffset=0.0 -unit.1.2.port.4.b.0.signedPrecision=0 -unit.1.2.port.4.b.0.signedScaleFactor=1.0 -unit.1.2.port.4.b.0.unsignedOffset=0.0 -unit.1.2.port.4.b.0.unsignedPrecision=0 -unit.1.2.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.4.b.0.visible=1 -unit.1.2.port.4.buscount=1 -unit.1.2.port.4.channelcount=32 -unit.1.2.port.4.s.0.alias= -unit.1.2.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.0.name=TriggerPort4[0] -unit.1.2.port.4.s.0.orderindex=-1 -unit.1.2.port.4.s.0.visible=1 -unit.1.2.port.4.s.1.alias= -unit.1.2.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.1.name=TriggerPort4[1] -unit.1.2.port.4.s.1.orderindex=-1 -unit.1.2.port.4.s.1.visible=1 -unit.1.2.port.4.s.10.alias= -unit.1.2.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.10.name=TriggerPort4[10] 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-unit.1.2.port.4.s.15.name=TriggerPort4[15] -unit.1.2.port.4.s.15.orderindex=-1 -unit.1.2.port.4.s.15.visible=1 -unit.1.2.port.4.s.16.alias= -unit.1.2.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.16.name=TriggerPort4[16] -unit.1.2.port.4.s.16.orderindex=-1 -unit.1.2.port.4.s.16.visible=1 -unit.1.2.port.4.s.17.alias= -unit.1.2.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.17.name=TriggerPort4[17] -unit.1.2.port.4.s.17.orderindex=-1 -unit.1.2.port.4.s.17.visible=1 -unit.1.2.port.4.s.18.alias= -unit.1.2.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.18.name=TriggerPort4[18] -unit.1.2.port.4.s.18.orderindex=-1 -unit.1.2.port.4.s.18.visible=1 -unit.1.2.port.4.s.19.alias= -unit.1.2.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.19.name=TriggerPort4[19] -unit.1.2.port.4.s.19.orderindex=-1 -unit.1.2.port.4.s.19.visible=1 -unit.1.2.port.4.s.2.alias= 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88 89 90 91 92 93 94 95 -unit.1.3.port.-1.b.0.color=java.awt.Color[r\=102,g\=102,b\=255] -unit.1.3.port.-1.b.0.name=DataPort -unit.1.3.port.-1.b.0.orderindex=-1 -unit.1.3.port.-1.b.0.radix=Signed -unit.1.3.port.-1.b.0.signedOffset=0.0 -unit.1.3.port.-1.b.0.signedPrecision=0 -unit.1.3.port.-1.b.0.signedScaleFactor=1.0 -unit.1.3.port.-1.b.0.tokencount=0 -unit.1.3.port.-1.b.0.unsignedOffset=0.0 -unit.1.3.port.-1.b.0.unsignedPrecision=0 -unit.1.3.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.-1.b.0.visible=1 -unit.1.3.port.-1.b.1.alias=dsp_sum_tbt -unit.1.3.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 -unit.1.3.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.3.port.-1.b.1.name=DataPort -unit.1.3.port.-1.b.1.orderindex=-1 -unit.1.3.port.-1.b.1.radix=Signed -unit.1.3.port.-1.b.1.signedOffset=0.0 -unit.1.3.port.-1.b.1.signedPrecision=0 -unit.1.3.port.-1.b.1.signedScaleFactor=1.0 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-unit.1.3.port.-1.b.3.color=java.awt.Color[r\=255,g\=51,b\=0] -unit.1.3.port.-1.b.3.name=DataPort -unit.1.3.port.-1.b.3.orderindex=-1 -unit.1.3.port.-1.b.3.radix=Signed -unit.1.3.port.-1.b.3.signedOffset=0.0 -unit.1.3.port.-1.b.3.signedPrecision=0 -unit.1.3.port.-1.b.3.signedScaleFactor=1.0 -unit.1.3.port.-1.b.3.tokencount=0 -unit.1.3.port.-1.b.3.unsignedOffset=0.0 -unit.1.3.port.-1.b.3.unsignedPrecision=0 -unit.1.3.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.3.port.-1.b.3.visible=1 -unit.1.3.port.-1.buscount=4 -unit.1.3.port.-1.channelcount=136 -unit.1.3.port.-1.s.0.alias= -unit.1.3.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.0.name=DataPort[0] -unit.1.3.port.-1.s.0.orderindex=-1 -unit.1.3.port.-1.s.0.visible=1 -unit.1.3.port.-1.s.1.alias= -unit.1.3.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.1.name=DataPort[1] -unit.1.3.port.-1.s.1.orderindex=-1 -unit.1.3.port.-1.s.1.visible=1 -unit.1.3.port.-1.s.10.alias= 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-unit.1.3.port.-1.s.77.orderindex=-1 -unit.1.3.port.-1.s.77.visible=0 -unit.1.3.port.-1.s.78.alias= -unit.1.3.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.78.name=DataPort[78] -unit.1.3.port.-1.s.78.orderindex=-1 -unit.1.3.port.-1.s.78.visible=0 -unit.1.3.port.-1.s.79.alias= -unit.1.3.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.79.name=DataPort[79] -unit.1.3.port.-1.s.79.orderindex=-1 -unit.1.3.port.-1.s.79.visible=0 -unit.1.3.port.-1.s.8.alias= -unit.1.3.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.8.name=DataPort[8] -unit.1.3.port.-1.s.8.orderindex=-1 -unit.1.3.port.-1.s.8.visible=0 -unit.1.3.port.-1.s.80.alias= -unit.1.3.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.80.name=DataPort[80] -unit.1.3.port.-1.s.80.orderindex=-1 -unit.1.3.port.-1.s.80.visible=0 -unit.1.3.port.-1.s.81.alias= -unit.1.3.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.81.name=DataPort[81] -unit.1.3.port.-1.s.81.orderindex=-1 -unit.1.3.port.-1.s.81.visible=0 -unit.1.3.port.-1.s.82.alias= -unit.1.3.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.82.name=DataPort[82] -unit.1.3.port.-1.s.82.orderindex=-1 -unit.1.3.port.-1.s.82.visible=0 -unit.1.3.port.-1.s.83.alias= -unit.1.3.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.83.name=DataPort[83] -unit.1.3.port.-1.s.83.orderindex=-1 -unit.1.3.port.-1.s.83.visible=0 -unit.1.3.port.-1.s.84.alias= -unit.1.3.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.84.name=DataPort[84] -unit.1.3.port.-1.s.84.orderindex=-1 -unit.1.3.port.-1.s.84.visible=0 -unit.1.3.port.-1.s.85.alias= -unit.1.3.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.85.name=DataPort[85] -unit.1.3.port.-1.s.85.orderindex=-1 -unit.1.3.port.-1.s.85.visible=0 -unit.1.3.port.-1.s.86.alias= -unit.1.3.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.86.name=DataPort[86] -unit.1.3.port.-1.s.86.orderindex=-1 -unit.1.3.port.-1.s.86.visible=0 -unit.1.3.port.-1.s.87.alias= -unit.1.3.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.87.name=DataPort[87] -unit.1.3.port.-1.s.87.orderindex=-1 -unit.1.3.port.-1.s.87.visible=0 -unit.1.3.port.-1.s.88.alias= -unit.1.3.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.88.name=DataPort[88] -unit.1.3.port.-1.s.88.orderindex=-1 -unit.1.3.port.-1.s.88.visible=0 -unit.1.3.port.-1.s.89.alias= -unit.1.3.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.89.name=DataPort[89] -unit.1.3.port.-1.s.89.orderindex=-1 -unit.1.3.port.-1.s.89.visible=0 -unit.1.3.port.-1.s.9.alias= -unit.1.3.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.9.name=DataPort[9] -unit.1.3.port.-1.s.9.orderindex=-1 -unit.1.3.port.-1.s.9.visible=0 -unit.1.3.port.-1.s.90.alias= -unit.1.3.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.90.name=DataPort[90] -unit.1.3.port.-1.s.90.orderindex=-1 -unit.1.3.port.-1.s.90.visible=0 -unit.1.3.port.-1.s.91.alias= -unit.1.3.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.91.name=DataPort[91] -unit.1.3.port.-1.s.91.orderindex=-1 -unit.1.3.port.-1.s.91.visible=0 -unit.1.3.port.-1.s.92.alias= -unit.1.3.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.92.name=DataPort[92] -unit.1.3.port.-1.s.92.orderindex=-1 -unit.1.3.port.-1.s.92.visible=0 -unit.1.3.port.-1.s.93.alias= -unit.1.3.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.93.name=DataPort[93] -unit.1.3.port.-1.s.93.orderindex=-1 -unit.1.3.port.-1.s.93.visible=0 -unit.1.3.port.-1.s.94.alias= -unit.1.3.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.94.name=DataPort[94] -unit.1.3.port.-1.s.94.orderindex=-1 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-unit.1.3.port.-1.s.99.orderindex=-1 -unit.1.3.port.-1.s.99.visible=1 -unit.1.3.port.0.b.0.alias= -unit.1.3.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.3.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.b.0.name=TriggerPort0 -unit.1.3.port.0.b.0.orderindex=-1 -unit.1.3.port.0.b.0.radix=Hex -unit.1.3.port.0.b.0.signedOffset=0.0 -unit.1.3.port.0.b.0.signedPrecision=0 -unit.1.3.port.0.b.0.signedScaleFactor=1.0 -unit.1.3.port.0.b.0.unsignedOffset=0.0 -unit.1.3.port.0.b.0.unsignedPrecision=0 -unit.1.3.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.0.b.0.visible=1 -unit.1.3.port.0.buscount=1 -unit.1.3.port.0.channelcount=8 -unit.1.3.port.0.s.0.alias= -unit.1.3.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.0.name=TriggerPort0[0] -unit.1.3.port.0.s.0.orderindex=-1 -unit.1.3.port.0.s.0.visible=1 -unit.1.3.port.0.s.1.alias= -unit.1.3.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.1.name=TriggerPort0[1] -unit.1.3.port.0.s.1.orderindex=-1 -unit.1.3.port.0.s.1.visible=1 -unit.1.3.port.0.s.10.alias= -unit.1.3.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.10.name=TriggerPort0[10] -unit.1.3.port.0.s.10.orderindex=-1 -unit.1.3.port.0.s.10.visible=1 -unit.1.3.port.0.s.11.alias= -unit.1.3.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.port.4.b.0.alias= -unit.1.3.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.b.0.name=TriggerPort4 -unit.1.3.port.4.b.0.orderindex=-1 -unit.1.3.port.4.b.0.radix=Hex -unit.1.3.port.4.b.0.signedOffset=0.0 -unit.1.3.port.4.b.0.signedPrecision=0 -unit.1.3.port.4.b.0.signedScaleFactor=1.0 -unit.1.3.port.4.b.0.unsignedOffset=0.0 -unit.1.3.port.4.b.0.unsignedPrecision=0 -unit.1.3.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.4.b.0.visible=1 -unit.1.3.port.4.buscount=1 -unit.1.3.port.4.channelcount=32 -unit.1.3.port.4.s.0.alias= -unit.1.3.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.0.name=TriggerPort4[0] -unit.1.3.port.4.s.0.orderindex=-1 -unit.1.3.port.4.s.0.visible=1 -unit.1.3.port.4.s.1.alias= -unit.1.3.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.1.name=TriggerPort4[1] -unit.1.3.port.4.s.1.orderindex=-1 -unit.1.3.port.4.s.1.visible=1 -unit.1.3.port.4.s.10.alias= -unit.1.3.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.10.name=TriggerPort4[10] -unit.1.3.port.4.s.10.orderindex=-1 -unit.1.3.port.4.s.10.visible=1 -unit.1.3.port.4.s.11.alias= -unit.1.3.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.11.name=TriggerPort4[11] -unit.1.3.port.4.s.11.orderindex=-1 -unit.1.3.port.4.s.11.visible=1 -unit.1.3.port.4.s.12.alias= -unit.1.3.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.12.name=TriggerPort4[12] -unit.1.3.port.4.s.12.orderindex=-1 -unit.1.3.port.4.s.12.visible=1 -unit.1.3.port.4.s.13.alias= -unit.1.3.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.13.name=TriggerPort4[13] -unit.1.3.port.4.s.13.orderindex=-1 -unit.1.3.port.4.s.13.visible=1 -unit.1.3.port.4.s.14.alias= -unit.1.3.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.14.name=TriggerPort4[14] -unit.1.3.port.4.s.14.orderindex=-1 -unit.1.3.port.4.s.14.visible=1 -unit.1.3.port.4.s.15.alias= -unit.1.3.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.15.name=TriggerPort4[15] -unit.1.3.port.4.s.15.orderindex=-1 -unit.1.3.port.4.s.15.visible=1 -unit.1.3.port.4.s.16.alias= -unit.1.3.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.16.name=TriggerPort4[16] -unit.1.3.port.4.s.16.orderindex=-1 -unit.1.3.port.4.s.16.visible=1 -unit.1.3.port.4.s.17.alias= -unit.1.3.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.17.name=TriggerPort4[17] -unit.1.3.port.4.s.17.orderindex=-1 -unit.1.3.port.4.s.17.visible=1 -unit.1.3.port.4.s.18.alias= -unit.1.3.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.18.name=TriggerPort4[18] -unit.1.3.port.4.s.18.orderindex=-1 -unit.1.3.port.4.s.18.visible=1 -unit.1.3.port.4.s.19.alias= -unit.1.3.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.19.name=TriggerPort4[19] -unit.1.3.port.4.s.19.orderindex=-1 -unit.1.3.port.4.s.19.visible=1 -unit.1.3.port.4.s.2.alias= -unit.1.3.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.2.name=TriggerPort4[2] -unit.1.3.port.4.s.2.orderindex=-1 -unit.1.3.port.4.s.2.visible=1 -unit.1.3.port.4.s.20.alias= -unit.1.3.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.20.name=TriggerPort4[20] -unit.1.3.port.4.s.20.orderindex=-1 -unit.1.3.port.4.s.20.visible=1 -unit.1.3.port.4.s.21.alias= -unit.1.3.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.21.name=TriggerPort4[21] -unit.1.3.port.4.s.21.orderindex=-1 -unit.1.3.port.4.s.21.visible=1 -unit.1.3.port.4.s.22.alias= -unit.1.3.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.22.name=TriggerPort4[22] -unit.1.3.port.4.s.22.orderindex=-1 -unit.1.3.port.4.s.22.visible=1 -unit.1.3.port.4.s.23.alias= -unit.1.3.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.23.name=TriggerPort4[23] -unit.1.3.port.4.s.23.orderindex=-1 -unit.1.3.port.4.s.23.visible=1 -unit.1.3.port.4.s.24.alias= -unit.1.3.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.24.name=TriggerPort4[24] -unit.1.3.port.4.s.24.orderindex=-1 -unit.1.3.port.4.s.24.visible=1 -unit.1.3.port.4.s.25.alias= -unit.1.3.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.25.name=TriggerPort4[25] -unit.1.3.port.4.s.25.orderindex=-1 -unit.1.3.port.4.s.25.visible=1 -unit.1.3.port.4.s.26.alias= -unit.1.3.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.26.name=TriggerPort4[26] -unit.1.3.port.4.s.26.orderindex=-1 -unit.1.3.port.4.s.26.visible=1 -unit.1.3.port.4.s.27.alias= -unit.1.3.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.27.name=TriggerPort4[27] -unit.1.3.port.4.s.27.orderindex=-1 -unit.1.3.port.4.s.27.visible=1 -unit.1.3.port.4.s.28.alias= -unit.1.3.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.28.name=TriggerPort4[28] -unit.1.3.port.4.s.28.orderindex=-1 -unit.1.3.port.4.s.28.visible=1 -unit.1.3.port.4.s.29.alias= -unit.1.3.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.29.name=TriggerPort4[29] -unit.1.3.port.4.s.29.orderindex=-1 -unit.1.3.port.4.s.29.visible=1 -unit.1.3.port.4.s.3.alias= -unit.1.3.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.3.name=TriggerPort4[3] -unit.1.3.port.4.s.3.orderindex=-1 -unit.1.3.port.4.s.3.visible=1 -unit.1.3.port.4.s.30.alias= -unit.1.3.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.30.name=TriggerPort4[30] -unit.1.3.port.4.s.30.orderindex=-1 -unit.1.3.port.4.s.30.visible=1 -unit.1.3.port.4.s.31.alias= -unit.1.3.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.31.name=TriggerPort4[31] -unit.1.3.port.4.s.31.orderindex=-1 -unit.1.3.port.4.s.31.visible=1 -unit.1.3.port.4.s.4.alias= -unit.1.3.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.4.name=TriggerPort4[4] -unit.1.3.port.4.s.4.orderindex=-1 -unit.1.3.port.4.s.4.visible=1 -unit.1.3.port.4.s.5.alias= -unit.1.3.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.5.name=TriggerPort4[5] -unit.1.3.port.4.s.5.orderindex=-1 -unit.1.3.port.4.s.5.visible=1 -unit.1.3.port.4.s.6.alias= -unit.1.3.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.6.name=TriggerPort4[6] -unit.1.3.port.4.s.6.orderindex=-1 -unit.1.3.port.4.s.6.visible=1 -unit.1.3.port.4.s.7.alias= -unit.1.3.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.7.name=TriggerPort4[7] -unit.1.3.port.4.s.7.orderindex=-1 -unit.1.3.port.4.s.7.visible=1 -unit.1.3.port.4.s.8.alias= -unit.1.3.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.8.name=TriggerPort4[8] -unit.1.3.port.4.s.8.orderindex=-1 -unit.1.3.port.4.s.8.visible=1 -unit.1.3.port.4.s.9.alias= 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-unit.1.4.port.-1.s.85.name=DataPort[85] -unit.1.4.port.-1.s.85.orderindex=-1 -unit.1.4.port.-1.s.85.visible=0 -unit.1.4.port.-1.s.86.alias= -unit.1.4.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.86.name=DataPort[86] -unit.1.4.port.-1.s.86.orderindex=-1 -unit.1.4.port.-1.s.86.visible=0 -unit.1.4.port.-1.s.87.alias= -unit.1.4.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.87.name=DataPort[87] -unit.1.4.port.-1.s.87.orderindex=-1 -unit.1.4.port.-1.s.87.visible=0 -unit.1.4.port.-1.s.88.alias= -unit.1.4.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.88.name=DataPort[88] -unit.1.4.port.-1.s.88.orderindex=-1 -unit.1.4.port.-1.s.88.visible=0 -unit.1.4.port.-1.s.89.alias= -unit.1.4.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.89.name=DataPort[89] -unit.1.4.port.-1.s.89.orderindex=-1 -unit.1.4.port.-1.s.89.visible=0 -unit.1.4.port.-1.s.9.alias= -unit.1.4.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.9.name=DataPort[9] -unit.1.4.port.-1.s.9.orderindex=-1 -unit.1.4.port.-1.s.9.visible=0 -unit.1.4.port.-1.s.90.alias= -unit.1.4.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.90.name=DataPort[90] -unit.1.4.port.-1.s.90.orderindex=-1 -unit.1.4.port.-1.s.90.visible=0 -unit.1.4.port.-1.s.91.alias= -unit.1.4.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.91.name=DataPort[91] -unit.1.4.port.-1.s.91.orderindex=-1 -unit.1.4.port.-1.s.91.visible=0 -unit.1.4.port.-1.s.92.alias= -unit.1.4.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.92.name=DataPort[92] -unit.1.4.port.-1.s.92.orderindex=-1 -unit.1.4.port.-1.s.92.visible=0 -unit.1.4.port.-1.s.93.alias= -unit.1.4.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.93.name=DataPort[93] -unit.1.4.port.-1.s.93.orderindex=-1 -unit.1.4.port.-1.s.93.visible=0 -unit.1.4.port.-1.s.94.alias= -unit.1.4.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.94.name=DataPort[94] -unit.1.4.port.-1.s.94.orderindex=-1 -unit.1.4.port.-1.s.94.visible=0 -unit.1.4.port.-1.s.95.alias= -unit.1.4.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.95.name=DataPort[95] -unit.1.4.port.-1.s.95.orderindex=-1 -unit.1.4.port.-1.s.95.visible=0 -unit.1.4.port.-1.s.96.alias= -unit.1.4.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.96.name=DataPort[96] -unit.1.4.port.-1.s.96.orderindex=-1 -unit.1.4.port.-1.s.96.visible=0 -unit.1.4.port.-1.s.97.alias= -unit.1.4.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.97.name=DataPort[97] -unit.1.4.port.-1.s.97.orderindex=-1 -unit.1.4.port.-1.s.97.visible=1 -unit.1.4.port.-1.s.98.alias= -unit.1.4.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.98.name=DataPort[98] -unit.1.4.port.-1.s.98.orderindex=-1 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-unit.1.4.port.0.s.0.visible=1 -unit.1.4.port.0.s.1.alias= -unit.1.4.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.1.name=TriggerPort0[1] -unit.1.4.port.0.s.1.orderindex=-1 -unit.1.4.port.0.s.1.visible=1 -unit.1.4.port.0.s.2.alias= -unit.1.4.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.2.name=TriggerPort0[2] -unit.1.4.port.0.s.2.orderindex=-1 -unit.1.4.port.0.s.2.visible=1 -unit.1.4.port.0.s.3.alias= -unit.1.4.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.3.name=TriggerPort0[3] -unit.1.4.port.0.s.3.orderindex=-1 -unit.1.4.port.0.s.3.visible=1 -unit.1.4.port.0.s.4.alias= -unit.1.4.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.4.name=TriggerPort0[4] -unit.1.4.port.0.s.4.orderindex=-1 -unit.1.4.port.0.s.4.visible=1 -unit.1.4.port.0.s.5.alias= -unit.1.4.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.5.name=TriggerPort0[5] -unit.1.4.port.0.s.5.orderindex=-1 -unit.1.4.port.0.s.5.visible=1 -unit.1.4.port.0.s.6.alias= -unit.1.4.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.6.name=TriggerPort0[6] -unit.1.4.port.0.s.6.orderindex=-1 -unit.1.4.port.0.s.6.visible=1 -unit.1.4.port.0.s.7.alias= -unit.1.4.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.7.name=TriggerPort0[7] -unit.1.4.port.0.s.7.orderindex=-1 -unit.1.4.port.0.s.7.visible=1 -unit.1.4.port.1.b.0.alias= -unit.1.4.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex -unit.1.4.port.1.b.0.signedOffset=0.0 -unit.1.4.port.1.b.0.signedPrecision=0 -unit.1.4.port.1.b.0.signedScaleFactor=1.0 -unit.1.4.port.1.b.0.unsignedOffset=0.0 -unit.1.4.port.1.b.0.unsignedPrecision=0 -unit.1.4.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.1.b.0.visible=1 -unit.1.4.port.1.buscount=1 -unit.1.4.port.1.channelcount=32 -unit.1.4.port.1.s.0.alias= -unit.1.4.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.0.name=TriggerPort1[0] -unit.1.4.port.1.s.0.orderindex=-1 -unit.1.4.port.1.s.0.visible=1 -unit.1.4.port.1.s.1.alias= -unit.1.4.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.1.name=TriggerPort1[1] -unit.1.4.port.1.s.1.orderindex=-1 -unit.1.4.port.1.s.1.visible=1 -unit.1.4.port.1.s.10.alias= -unit.1.4.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.10.name=TriggerPort1[10] -unit.1.4.port.1.s.10.orderindex=-1 -unit.1.4.port.1.s.10.visible=1 -unit.1.4.port.1.s.11.alias= -unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 -unit.1.4.port.1.s.16.alias= -unit.1.4.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.16.name=TriggerPort1[16] -unit.1.4.port.1.s.16.orderindex=-1 -unit.1.4.port.1.s.16.visible=1 -unit.1.4.port.1.s.17.alias= -unit.1.4.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.17.name=TriggerPort1[17] -unit.1.4.port.1.s.17.orderindex=-1 -unit.1.4.port.1.s.17.visible=1 -unit.1.4.port.1.s.18.alias= -unit.1.4.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.18.name=TriggerPort1[18] -unit.1.4.port.1.s.18.orderindex=-1 -unit.1.4.port.1.s.18.visible=1 -unit.1.4.port.1.s.19.alias= -unit.1.4.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.19.name=TriggerPort1[19] -unit.1.4.port.1.s.19.orderindex=-1 -unit.1.4.port.1.s.19.visible=1 -unit.1.4.port.1.s.2.alias= -unit.1.4.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.2.name=TriggerPort1[2] -unit.1.4.port.1.s.2.orderindex=-1 -unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.18.name=TriggerPort3[18] -unit.1.4.port.3.s.18.orderindex=-1 -unit.1.4.port.3.s.18.visible=1 -unit.1.4.port.3.s.19.alias= -unit.1.4.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.19.name=TriggerPort3[19] -unit.1.4.port.3.s.19.orderindex=-1 -unit.1.4.port.3.s.19.visible=1 -unit.1.4.port.3.s.2.alias= -unit.1.4.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.2.name=TriggerPort3[2] -unit.1.4.port.3.s.2.orderindex=-1 -unit.1.4.port.3.s.2.visible=1 -unit.1.4.port.3.s.20.alias= -unit.1.4.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.20.name=TriggerPort3[20] -unit.1.4.port.3.s.20.orderindex=-1 -unit.1.4.port.3.s.20.visible=1 -unit.1.4.port.3.s.21.alias= -unit.1.4.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.21.name=TriggerPort3[21] -unit.1.4.port.3.s.21.orderindex=-1 -unit.1.4.port.3.s.21.visible=1 -unit.1.4.port.3.s.22.alias= -unit.1.4.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.22.name=TriggerPort3[22] -unit.1.4.port.3.s.22.orderindex=-1 -unit.1.4.port.3.s.22.visible=1 -unit.1.4.port.3.s.23.alias= -unit.1.4.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.23.name=TriggerPort3[23] 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-unit.1.4.waveform.posn.23.channel=98 -unit.1.4.waveform.posn.23.name=DataPort[98] -unit.1.4.waveform.posn.23.type=signal -unit.1.4.waveform.posn.24.channel=99 -unit.1.4.waveform.posn.24.name=DataPort[99] -unit.1.4.waveform.posn.24.type=signal -unit.1.4.waveform.posn.25.channel=100 -unit.1.4.waveform.posn.25.name=DataPort[100] -unit.1.4.waveform.posn.25.type=signal -unit.1.4.waveform.posn.26.channel=101 -unit.1.4.waveform.posn.26.name=DataPort[101] -unit.1.4.waveform.posn.26.type=signal -unit.1.4.waveform.posn.27.channel=102 -unit.1.4.waveform.posn.27.name=DataPort[102] -unit.1.4.waveform.posn.27.type=signal -unit.1.4.waveform.posn.28.channel=103 -unit.1.4.waveform.posn.28.name=DataPort[103] -unit.1.4.waveform.posn.28.type=signal -unit.1.4.waveform.posn.29.channel=129 -unit.1.4.waveform.posn.29.name=DataPort[129] -unit.1.4.waveform.posn.29.type=signal -unit.1.4.waveform.posn.3.channel=3 -unit.1.4.waveform.posn.3.name=DataPort[3] -unit.1.4.waveform.posn.3.type=signal -unit.1.4.waveform.posn.30.channel=130 -unit.1.4.waveform.posn.30.name=DataPort[130] -unit.1.4.waveform.posn.30.type=signal -unit.1.4.waveform.posn.31.channel=131 -unit.1.4.waveform.posn.31.name=DataPort[131] -unit.1.4.waveform.posn.31.type=signal -unit.1.4.waveform.posn.32.channel=132 -unit.1.4.waveform.posn.32.name=DataPort[132] -unit.1.4.waveform.posn.32.type=signal -unit.1.4.waveform.posn.33.channel=133 -unit.1.4.waveform.posn.33.name=DataPort[133] -unit.1.4.waveform.posn.33.type=signal -unit.1.4.waveform.posn.34.channel=134 -unit.1.4.waveform.posn.34.name=DataPort[134] -unit.1.4.waveform.posn.34.type=signal -unit.1.4.waveform.posn.35.channel=135 -unit.1.4.waveform.posn.35.name=DataPort[135] -unit.1.4.waveform.posn.35.type=signal -unit.1.4.waveform.posn.36.channel=2147483646 -unit.1.4.waveform.posn.36.name=dsp_fofb_amp_ch0 -unit.1.4.waveform.posn.36.radix=3 -unit.1.4.waveform.posn.36.type=bus -unit.1.4.waveform.posn.37.channel=2147483646 -unit.1.4.waveform.posn.37.name=dsp_fofb_amp_ch1 -unit.1.4.waveform.posn.37.radix=3 -unit.1.4.waveform.posn.37.type=bus -unit.1.4.waveform.posn.38.channel=2147483646 -unit.1.4.waveform.posn.38.name=dsp_fofb_amp_ch2 -unit.1.4.waveform.posn.38.radix=3 -unit.1.4.waveform.posn.38.type=bus -unit.1.4.waveform.posn.39.channel=2147483646 -unit.1.4.waveform.posn.39.name=dsp_fofb_amp_ch3 -unit.1.4.waveform.posn.39.radix=3 -unit.1.4.waveform.posn.39.type=bus -unit.1.4.waveform.posn.4.channel=4 -unit.1.4.waveform.posn.4.name=DataPort[4] -unit.1.4.waveform.posn.4.type=signal -unit.1.4.waveform.posn.5.channel=5 -unit.1.4.waveform.posn.5.name=DataPort[5] -unit.1.4.waveform.posn.5.type=signal -unit.1.4.waveform.posn.6.channel=6 -unit.1.4.waveform.posn.6.name=DataPort[6] -unit.1.4.waveform.posn.6.type=signal -unit.1.4.waveform.posn.7.channel=7 -unit.1.4.waveform.posn.7.name=DataPort[7] -unit.1.4.waveform.posn.7.type=signal -unit.1.4.waveform.posn.8.channel=33 -unit.1.4.waveform.posn.8.name=DataPort[33] -unit.1.4.waveform.posn.8.type=signal -unit.1.4.waveform.posn.9.channel=34 -unit.1.4.waveform.posn.9.name=DataPort[34] -unit.1.4.waveform.posn.9.type=signal -unit.1.5.0.HEIGHT0=0.37337664 -unit.1.5.0.TriggerRow0=1 -unit.1.5.0.TriggerRow1=1 -unit.1.5.0.TriggerRow2=1 -unit.1.5.0.WIDTH0=0.6727405 -unit.1.5.0.X0=0.034985423 -unit.1.5.0.Y0=0.0 -unit.1.5.1.HEIGHT1=0.77922076 -unit.1.5.1.WIDTH1=0.6202624 -unit.1.5.1.X1=0.018950438 -unit.1.5.1.Y1=0.055194806 -unit.1.5.5.HEIGHT5=0.77922076 -unit.1.5.5.WIDTH5=0.8731778 -unit.1.5.5.X5=0.043002915 -unit.1.5.5.Y5=0.08928572 -unit.1.5.MFBitsA0=XX1XXXXX -unit.1.5.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsB0=00000000 -unit.1.5.MFBitsB1=00000000000000000000000000000000 -unit.1.5.MFBitsB2=00000000000000000000000000000000 -unit.1.5.MFBitsB3=00000000000000000000000000000000 -unit.1.5.MFBitsB4=00000000000000000000000000000000 -unit.1.5.MFCompareA0=0 -unit.1.5.MFCompareA1=0 -unit.1.5.MFCompareA2=0 -unit.1.5.MFCompareA3=0 -unit.1.5.MFCompareA4=0 -unit.1.5.MFCompareB0=999 -unit.1.5.MFCompareB1=999 -unit.1.5.MFCompareB2=999 -unit.1.5.MFCompareB3=999 -unit.1.5.MFCompareB4=999 -unit.1.5.MFCount=5 -unit.1.5.MFDisplay0=0 -unit.1.5.MFDisplay1=0 -unit.1.5.MFDisplay2=0 -unit.1.5.MFDisplay3=0 -unit.1.5.MFDisplay4=0 -unit.1.5.MFEventType0=3 -unit.1.5.MFEventType1=3 -unit.1.5.MFEventType2=3 -unit.1.5.MFEventType3=3 -unit.1.5.MFEventType4=3 -unit.1.5.RunMode=SINGLE RUN -unit.1.5.SQCondition=M0 -unit.1.5.SQContiguous0=0 -unit.1.5.SequencerOn=0 -unit.1.5.TCActive=0 -unit.1.5.TCAdvanced0=0 -unit.1.5.TCCondition0_0=M0 -unit.1.5.TCCondition0_1= -unit.1.5.TCConditionType0=0 -unit.1.5.TCCount=1 -unit.1.5.TCEventCount0=1 -unit.1.5.TCEventType0=3 -unit.1.5.TCName0=TriggerCondition0 -unit.1.5.TCOutputEnable0=0 -unit.1.5.TCOutputHigh0=1 -unit.1.5.TCOutputMode0=0 -unit.1.5.browser_tree_state=1 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.coretype=ILA -unit.1.5.eventCount0=1 -unit.1.5.eventCount1=1 -unit.1.5.eventCount2=1 -unit.1.5.eventCount3=1 -unit.1.5.eventCount4=1 -unit.1.5.plotBusColor0=-10066177 -unit.1.5.plotBusColor1=-3355648 -unit.1.5.plotBusColor2=-16777012 -unit.1.5.plotBusColor3=-52429 -unit.1.5.plotBusCount=4 -unit.1.5.plotBusName0=dsp_q_fofb -unit.1.5.plotBusName1=dsp_sum_fofb -unit.1.5.plotBusName2=dsp_x_fofb -unit.1.5.plotBusName3=dsp_y_fofb -unit.1.5.plotBusX=dsp_q_fofb -unit.1.5.plotBusY=dsp_sum_fofb -unit.1.5.plotDataTimeMode=1 -unit.1.5.plotDisplayMode=line -unit.1.5.plotMaxX=0.0 -unit.1.5.plotMaxY=0.0 -unit.1.5.plotMinX=0.0 -unit.1.5.plotMinY=0.0 -unit.1.5.plotSelectedBus=2 -unit.1.5.port.-1.b.0.alias=dsp_q_fofb -unit.1.5.port.-1.b.0.channellist=72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.5.port.-1.b.0.color=java.awt.Color[r\=102,g\=102,b\=255] -unit.1.5.port.-1.b.0.name=DataPort -unit.1.5.port.-1.b.0.orderindex=-1 -unit.1.5.port.-1.b.0.radix=Signed -unit.1.5.port.-1.b.0.signedOffset=0.0 -unit.1.5.port.-1.b.0.signedPrecision=0 -unit.1.5.port.-1.b.0.signedScaleFactor=1.0 -unit.1.5.port.-1.b.0.tokencount=0 -unit.1.5.port.-1.b.0.unsignedOffset=0.0 -unit.1.5.port.-1.b.0.unsignedPrecision=0 -unit.1.5.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.0.visible=1 -unit.1.5.port.-1.b.1.alias=dsp_sum_fofb -unit.1.5.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 -unit.1.5.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.5.port.-1.b.1.name=DataPort -unit.1.5.port.-1.b.1.orderindex=-1 -unit.1.5.port.-1.b.1.radix=Signed -unit.1.5.port.-1.b.1.signedOffset=0.0 -unit.1.5.port.-1.b.1.signedPrecision=0 -unit.1.5.port.-1.b.1.signedScaleFactor=1.0 -unit.1.5.port.-1.b.1.tokencount=0 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-unit.1.5.port.-1.b.3.name=DataPort -unit.1.5.port.-1.b.3.orderindex=-1 -unit.1.5.port.-1.b.3.radix=Signed -unit.1.5.port.-1.b.3.signedOffset=0.0 -unit.1.5.port.-1.b.3.signedPrecision=0 -unit.1.5.port.-1.b.3.signedScaleFactor=1.0 -unit.1.5.port.-1.b.3.tokencount=0 -unit.1.5.port.-1.b.3.unsignedOffset=0.0 -unit.1.5.port.-1.b.3.unsignedPrecision=0 -unit.1.5.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.3.visible=1 -unit.1.5.port.-1.buscount=4 -unit.1.5.port.-1.channelcount=136 -unit.1.5.port.-1.s.0.alias= -unit.1.5.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.0.name=DataPort[0] -unit.1.5.port.-1.s.0.orderindex=-1 -unit.1.5.port.-1.s.0.visible=1 -unit.1.5.port.-1.s.1.alias= -unit.1.5.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.1.name=DataPort[1] -unit.1.5.port.-1.s.1.orderindex=-1 -unit.1.5.port.-1.s.1.visible=1 -unit.1.5.port.-1.s.10.alias= -unit.1.5.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.5.port.0.s.6.visible=1 -unit.1.5.port.0.s.7.alias= -unit.1.5.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.7.name=TriggerPort0[7] -unit.1.5.port.0.s.7.orderindex=-1 -unit.1.5.port.0.s.7.visible=1 -unit.1.5.port.1.b.0.alias= -unit.1.5.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.b.0.name=TriggerPort1 -unit.1.5.port.1.b.0.orderindex=-1 -unit.1.5.port.1.b.0.radix=Hex -unit.1.5.port.1.b.0.signedOffset=0.0 -unit.1.5.port.1.b.0.signedPrecision=0 -unit.1.5.port.1.b.0.signedScaleFactor=1.0 -unit.1.5.port.1.b.0.unsignedOffset=0.0 -unit.1.5.port.1.b.0.unsignedPrecision=0 -unit.1.5.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.1.b.0.visible=1 -unit.1.5.port.1.buscount=1 -unit.1.5.port.1.channelcount=32 -unit.1.5.port.1.s.0.alias= -unit.1.5.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.0.name=TriggerPort1[0] -unit.1.5.port.1.s.0.orderindex=-1 -unit.1.5.port.1.s.0.visible=1 -unit.1.5.port.1.s.1.alias= -unit.1.5.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.1.name=TriggerPort1[1] -unit.1.5.port.1.s.1.orderindex=-1 -unit.1.5.port.1.s.1.visible=1 -unit.1.5.port.1.s.10.alias= -unit.1.5.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.10.name=TriggerPort1[10] -unit.1.5.port.1.s.10.orderindex=-1 -unit.1.5.port.1.s.10.visible=1 -unit.1.5.port.1.s.11.alias= -unit.1.5.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.11.name=TriggerPort1[11] -unit.1.5.port.1.s.11.orderindex=-1 -unit.1.5.port.1.s.11.visible=1 -unit.1.5.port.1.s.12.alias= -unit.1.5.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.12.name=TriggerPort1[12] -unit.1.5.port.1.s.12.orderindex=-1 -unit.1.5.port.1.s.12.visible=1 -unit.1.5.port.1.s.13.alias= -unit.1.5.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.13.name=TriggerPort1[13] -unit.1.5.port.1.s.13.orderindex=-1 -unit.1.5.port.1.s.13.visible=1 -unit.1.5.port.1.s.14.alias= -unit.1.5.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.14.name=TriggerPort1[14] -unit.1.5.port.1.s.14.orderindex=-1 -unit.1.5.port.1.s.14.visible=1 -unit.1.5.port.1.s.15.alias= -unit.1.5.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.15.name=TriggerPort1[15] -unit.1.5.port.1.s.15.orderindex=-1 -unit.1.5.port.1.s.15.visible=1 -unit.1.5.port.1.s.16.alias= -unit.1.5.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.16.name=TriggerPort1[16] -unit.1.5.port.1.s.16.orderindex=-1 -unit.1.5.port.1.s.16.visible=1 -unit.1.5.port.1.s.17.alias= -unit.1.5.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.17.name=TriggerPort1[17] -unit.1.5.port.1.s.17.orderindex=-1 -unit.1.5.port.1.s.17.visible=1 -unit.1.5.port.1.s.18.alias= -unit.1.5.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.18.name=TriggerPort1[18] -unit.1.5.port.1.s.18.orderindex=-1 -unit.1.5.port.1.s.18.visible=1 -unit.1.5.port.1.s.19.alias= -unit.1.5.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.19.name=TriggerPort1[19] -unit.1.5.port.1.s.19.orderindex=-1 -unit.1.5.port.1.s.19.visible=1 -unit.1.5.port.1.s.2.alias= -unit.1.5.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.2.name=TriggerPort1[2] -unit.1.5.port.1.s.2.orderindex=-1 -unit.1.5.port.1.s.2.visible=1 -unit.1.5.port.1.s.20.alias= -unit.1.5.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.20.name=TriggerPort1[20] -unit.1.5.port.1.s.20.orderindex=-1 -unit.1.5.port.1.s.20.visible=1 -unit.1.5.port.1.s.21.alias= -unit.1.5.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.21.name=TriggerPort1[21] -unit.1.5.port.1.s.21.orderindex=-1 -unit.1.5.port.1.s.21.visible=1 -unit.1.5.port.1.s.22.alias= -unit.1.5.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.22.name=TriggerPort1[22] -unit.1.5.port.1.s.22.orderindex=-1 -unit.1.5.port.1.s.22.visible=1 -unit.1.5.port.1.s.23.alias= -unit.1.5.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.23.name=TriggerPort1[23] -unit.1.5.port.1.s.23.orderindex=-1 -unit.1.5.port.1.s.23.visible=1 -unit.1.5.port.1.s.24.alias= -unit.1.5.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.24.name=TriggerPort1[24] -unit.1.5.port.1.s.24.orderindex=-1 -unit.1.5.port.1.s.24.visible=1 -unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 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-unit.1.5.port.3.s.2.visible=1 -unit.1.5.port.3.s.20.alias= -unit.1.5.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.20.name=TriggerPort3[20] -unit.1.5.port.3.s.20.orderindex=-1 -unit.1.5.port.3.s.20.visible=1 -unit.1.5.port.3.s.21.alias= -unit.1.5.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.21.name=TriggerPort3[21] -unit.1.5.port.3.s.21.orderindex=-1 -unit.1.5.port.3.s.21.visible=1 -unit.1.5.port.3.s.22.alias= -unit.1.5.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.22.name=TriggerPort3[22] -unit.1.5.port.3.s.22.orderindex=-1 -unit.1.5.port.3.s.22.visible=1 -unit.1.5.port.3.s.23.alias= -unit.1.5.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.23.name=TriggerPort3[23] -unit.1.5.port.3.s.23.orderindex=-1 -unit.1.5.port.3.s.23.visible=1 -unit.1.5.port.3.s.24.alias= -unit.1.5.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.24.name=TriggerPort3[24] -unit.1.5.port.3.s.24.orderindex=-1 -unit.1.5.port.3.s.24.visible=1 -unit.1.5.port.3.s.25.alias= -unit.1.5.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.25.name=TriggerPort3[25] -unit.1.5.port.3.s.25.orderindex=-1 -unit.1.5.port.3.s.25.visible=1 -unit.1.5.port.3.s.26.alias= -unit.1.5.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.26.name=TriggerPort3[26] -unit.1.5.port.3.s.26.orderindex=-1 -unit.1.5.port.3.s.26.visible=1 -unit.1.5.port.3.s.27.alias= -unit.1.5.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.27.name=TriggerPort3[27] -unit.1.5.port.3.s.27.orderindex=-1 -unit.1.5.port.3.s.27.visible=1 -unit.1.5.port.3.s.28.alias= -unit.1.5.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.28.name=TriggerPort3[28] -unit.1.5.port.3.s.28.orderindex=-1 -unit.1.5.port.3.s.28.visible=1 -unit.1.5.port.3.s.29.alias= -unit.1.5.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.29.name=TriggerPort3[29] -unit.1.5.port.3.s.29.orderindex=-1 -unit.1.5.port.3.s.29.visible=1 -unit.1.5.port.3.s.3.alias= -unit.1.5.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.3.name=TriggerPort3[3] -unit.1.5.port.3.s.3.orderindex=-1 -unit.1.5.port.3.s.3.visible=1 -unit.1.5.port.3.s.30.alias= -unit.1.5.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.30.name=TriggerPort3[30] -unit.1.5.port.3.s.30.orderindex=-1 -unit.1.5.port.3.s.30.visible=1 -unit.1.5.port.3.s.31.alias= -unit.1.5.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.31.name=TriggerPort3[31] -unit.1.5.port.3.s.31.orderindex=-1 -unit.1.5.port.3.s.31.visible=1 -unit.1.5.port.3.s.4.alias= -unit.1.5.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.4.name=TriggerPort3[4] -unit.1.5.port.3.s.4.orderindex=-1 -unit.1.5.port.3.s.4.visible=1 -unit.1.5.port.3.s.5.alias= -unit.1.5.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.5.name=TriggerPort3[5] -unit.1.5.port.3.s.5.orderindex=-1 -unit.1.5.port.3.s.5.visible=1 -unit.1.5.port.3.s.6.alias= -unit.1.5.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.6.name=TriggerPort3[6] -unit.1.5.port.3.s.6.orderindex=-1 -unit.1.5.port.3.s.6.visible=1 -unit.1.5.port.3.s.7.alias= -unit.1.5.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.7.name=TriggerPort3[7] -unit.1.5.port.3.s.7.orderindex=-1 -unit.1.5.port.3.s.7.visible=1 -unit.1.5.port.3.s.8.alias= -unit.1.5.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.8.name=TriggerPort3[8] -unit.1.5.port.3.s.8.orderindex=-1 -unit.1.5.port.3.s.8.visible=1 -unit.1.5.port.3.s.9.alias= -unit.1.5.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.9.name=TriggerPort3[9] -unit.1.5.port.3.s.9.orderindex=-1 -unit.1.5.port.3.s.9.visible=1 -unit.1.5.port.4.b.0.alias= -unit.1.5.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.b.0.name=TriggerPort4 -unit.1.5.port.4.b.0.orderindex=-1 -unit.1.5.port.4.b.0.radix=Hex -unit.1.5.port.4.b.0.signedOffset=0.0 -unit.1.5.port.4.b.0.signedPrecision=0 -unit.1.5.port.4.b.0.signedScaleFactor=1.0 -unit.1.5.port.4.b.0.unsignedOffset=0.0 -unit.1.5.port.4.b.0.unsignedPrecision=0 -unit.1.5.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.4.b.0.visible=1 -unit.1.5.port.4.buscount=1 -unit.1.5.port.4.channelcount=32 -unit.1.5.port.4.s.0.alias= -unit.1.5.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.0.name=TriggerPort4[0] -unit.1.5.port.4.s.0.orderindex=-1 -unit.1.5.port.4.s.0.visible=1 -unit.1.5.port.4.s.1.alias= -unit.1.5.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.1.name=TriggerPort4[1] -unit.1.5.port.4.s.1.orderindex=-1 -unit.1.5.port.4.s.1.visible=1 -unit.1.5.port.4.s.10.alias= -unit.1.5.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.10.name=TriggerPort4[10] -unit.1.5.port.4.s.10.orderindex=-1 -unit.1.5.port.4.s.10.visible=1 -unit.1.5.port.4.s.11.alias= -unit.1.5.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.11.name=TriggerPort4[11] -unit.1.5.port.4.s.11.orderindex=-1 -unit.1.5.port.4.s.11.visible=1 -unit.1.5.port.4.s.12.alias= -unit.1.5.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.12.name=TriggerPort4[12] -unit.1.5.port.4.s.12.orderindex=-1 -unit.1.5.port.4.s.12.visible=1 -unit.1.5.port.4.s.13.alias= -unit.1.5.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.13.name=TriggerPort4[13] -unit.1.5.port.4.s.13.orderindex=-1 -unit.1.5.port.4.s.13.visible=1 -unit.1.5.port.4.s.14.alias= -unit.1.5.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.14.name=TriggerPort4[14] -unit.1.5.port.4.s.14.orderindex=-1 -unit.1.5.port.4.s.14.visible=1 -unit.1.5.port.4.s.15.alias= -unit.1.5.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.15.name=TriggerPort4[15] -unit.1.5.port.4.s.15.orderindex=-1 -unit.1.5.port.4.s.15.visible=1 -unit.1.5.port.4.s.16.alias= -unit.1.5.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.16.name=TriggerPort4[16] -unit.1.5.port.4.s.16.orderindex=-1 -unit.1.5.port.4.s.16.visible=1 -unit.1.5.port.4.s.17.alias= -unit.1.5.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.17.name=TriggerPort4[17] -unit.1.5.port.4.s.17.orderindex=-1 -unit.1.5.port.4.s.17.visible=1 -unit.1.5.port.4.s.18.alias= -unit.1.5.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.18.name=TriggerPort4[18] -unit.1.5.port.4.s.18.orderindex=-1 -unit.1.5.port.4.s.18.visible=1 -unit.1.5.port.4.s.19.alias= -unit.1.5.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.19.name=TriggerPort4[19] -unit.1.5.port.4.s.19.orderindex=-1 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-unit.1.5.port.4.s.23.orderindex=-1 -unit.1.5.port.4.s.23.visible=1 -unit.1.5.port.4.s.24.alias= -unit.1.5.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.24.name=TriggerPort4[24] -unit.1.5.port.4.s.24.orderindex=-1 -unit.1.5.port.4.s.24.visible=1 -unit.1.5.port.4.s.25.alias= -unit.1.5.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.25.name=TriggerPort4[25] -unit.1.5.port.4.s.25.orderindex=-1 -unit.1.5.port.4.s.25.visible=1 -unit.1.5.port.4.s.26.alias= -unit.1.5.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.26.name=TriggerPort4[26] -unit.1.5.port.4.s.26.orderindex=-1 -unit.1.5.port.4.s.26.visible=1 -unit.1.5.port.4.s.27.alias= -unit.1.5.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.27.name=TriggerPort4[27] -unit.1.5.port.4.s.27.orderindex=-1 -unit.1.5.port.4.s.27.visible=1 -unit.1.5.port.4.s.28.alias= -unit.1.5.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.28.name=TriggerPort4[28] -unit.1.5.port.4.s.28.orderindex=-1 -unit.1.5.port.4.s.28.visible=1 -unit.1.5.port.4.s.29.alias= -unit.1.5.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.29.name=TriggerPort4[29] -unit.1.5.port.4.s.29.orderindex=-1 -unit.1.5.port.4.s.29.visible=1 -unit.1.5.port.4.s.3.alias= -unit.1.5.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.3.name=TriggerPort4[3] -unit.1.5.port.4.s.3.orderindex=-1 -unit.1.5.port.4.s.3.visible=1 -unit.1.5.port.4.s.30.alias= -unit.1.5.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.30.name=TriggerPort4[30] -unit.1.5.port.4.s.30.orderindex=-1 -unit.1.5.port.4.s.30.visible=1 -unit.1.5.port.4.s.31.alias= -unit.1.5.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.31.name=TriggerPort4[31] -unit.1.5.port.4.s.31.orderindex=-1 -unit.1.5.port.4.s.31.visible=1 -unit.1.5.port.4.s.4.alias= -unit.1.5.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.4.name=TriggerPort4[4] -unit.1.5.port.4.s.4.orderindex=-1 -unit.1.5.port.4.s.4.visible=1 -unit.1.5.port.4.s.5.alias= -unit.1.5.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.5.name=TriggerPort4[5] -unit.1.5.port.4.s.5.orderindex=-1 -unit.1.5.port.4.s.5.visible=1 -unit.1.5.port.4.s.6.alias= -unit.1.5.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.6.name=TriggerPort4[6] -unit.1.5.port.4.s.6.orderindex=-1 -unit.1.5.port.4.s.6.visible=1 -unit.1.5.port.4.s.7.alias= -unit.1.5.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.7.name=TriggerPort4[7] -unit.1.5.port.4.s.7.orderindex=-1 -unit.1.5.port.4.s.7.visible=1 -unit.1.5.port.4.s.8.alias= -unit.1.5.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.8.name=TriggerPort4[8] -unit.1.5.port.4.s.8.orderindex=-1 -unit.1.5.port.4.s.8.visible=1 -unit.1.5.port.4.s.9.alias= -unit.1.5.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.9.name=TriggerPort4[9] -unit.1.5.port.4.s.9.orderindex=-1 -unit.1.5.port.4.s.9.visible=1 -unit.1.5.portcount=5 -unit.1.5.rep_trigger.clobber=1 -unit.1.5.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp -unit.1.5.rep_trigger.filename=waveform -unit.1.5.rep_trigger.format=ASCII -unit.1.5.rep_trigger.loggingEnabled=0 -unit.1.5.rep_trigger.signals=All Signals/Buses -unit.1.5.samplesPerTrigger=1 -unit.1.5.triggerCapture=1 -unit.1.5.triggerNSamplesTS=0 -unit.1.5.triggerPosition=0 -unit.1.5.triggerWindowCount=1 -unit.1.5.triggerWindowDepth=4096 -unit.1.5.triggerWindowTS=0 -unit.1.5.username=MyILA5 -unit.1.5.waveform.count=42 -unit.1.5.waveform.posn.0.channel=0 -unit.1.5.waveform.posn.0.name=DataPort[0] -unit.1.5.waveform.posn.0.type=signal -unit.1.5.waveform.posn.1.channel=1 -unit.1.5.waveform.posn.1.name=DataPort[1] -unit.1.5.waveform.posn.1.type=signal -unit.1.5.waveform.posn.10.channel=34 -unit.1.5.waveform.posn.10.name=DataPort[34] -unit.1.5.waveform.posn.10.type=signal -unit.1.5.waveform.posn.11.channel=35 -unit.1.5.waveform.posn.11.name=DataPort[35] -unit.1.5.waveform.posn.11.type=signal -unit.1.5.waveform.posn.12.channel=36 -unit.1.5.waveform.posn.12.name=DataPort[36] -unit.1.5.waveform.posn.12.type=signal -unit.1.5.waveform.posn.13.channel=37 -unit.1.5.waveform.posn.13.name=DataPort[37] -unit.1.5.waveform.posn.13.type=signal -unit.1.5.waveform.posn.14.channel=38 -unit.1.5.waveform.posn.14.name=DataPort[38] -unit.1.5.waveform.posn.14.type=signal -unit.1.5.waveform.posn.15.channel=39 -unit.1.5.waveform.posn.15.name=DataPort[39] -unit.1.5.waveform.posn.15.type=signal -unit.1.5.waveform.posn.16.channel=64 -unit.1.5.waveform.posn.16.name=DataPort[64] -unit.1.5.waveform.posn.16.type=signal -unit.1.5.waveform.posn.17.channel=65 -unit.1.5.waveform.posn.17.name=DataPort[65] -unit.1.5.waveform.posn.17.type=signal -unit.1.5.waveform.posn.18.channel=66 -unit.1.5.waveform.posn.18.name=DataPort[66] -unit.1.5.waveform.posn.18.type=signal -unit.1.5.waveform.posn.19.channel=67 -unit.1.5.waveform.posn.19.name=DataPort[67] -unit.1.5.waveform.posn.19.type=signal -unit.1.5.waveform.posn.2.channel=2 -unit.1.5.waveform.posn.2.name=DataPort[2] -unit.1.5.waveform.posn.2.type=signal -unit.1.5.waveform.posn.20.channel=68 -unit.1.5.waveform.posn.20.name=DataPort[68] -unit.1.5.waveform.posn.20.type=signal -unit.1.5.waveform.posn.21.channel=69 -unit.1.5.waveform.posn.21.name=DataPort[69] -unit.1.5.waveform.posn.21.type=signal -unit.1.5.waveform.posn.22.channel=70 -unit.1.5.waveform.posn.22.name=DataPort[70] -unit.1.5.waveform.posn.22.type=signal -unit.1.5.waveform.posn.23.channel=71 -unit.1.5.waveform.posn.23.name=DataPort[71] -unit.1.5.waveform.posn.23.type=signal -unit.1.5.waveform.posn.24.channel=96 -unit.1.5.waveform.posn.24.name=DataPort[96] -unit.1.5.waveform.posn.24.type=signal -unit.1.5.waveform.posn.25.channel=97 -unit.1.5.waveform.posn.25.name=DataPort[97] -unit.1.5.waveform.posn.25.type=signal -unit.1.5.waveform.posn.26.channel=98 -unit.1.5.waveform.posn.26.name=DataPort[98] -unit.1.5.waveform.posn.26.type=signal -unit.1.5.waveform.posn.27.channel=99 -unit.1.5.waveform.posn.27.name=DataPort[99] -unit.1.5.waveform.posn.27.type=signal -unit.1.5.waveform.posn.28.channel=100 -unit.1.5.waveform.posn.28.name=DataPort[100] -unit.1.5.waveform.posn.28.type=signal -unit.1.5.waveform.posn.29.channel=101 -unit.1.5.waveform.posn.29.name=DataPort[101] -unit.1.5.waveform.posn.29.type=signal -unit.1.5.waveform.posn.3.channel=3 -unit.1.5.waveform.posn.3.name=DataPort[3] -unit.1.5.waveform.posn.3.type=signal -unit.1.5.waveform.posn.30.channel=102 -unit.1.5.waveform.posn.30.name=DataPort[102] -unit.1.5.waveform.posn.30.type=signal -unit.1.5.waveform.posn.31.channel=103 -unit.1.5.waveform.posn.31.name=DataPort[103] -unit.1.5.waveform.posn.31.type=signal -unit.1.5.waveform.posn.32.channel=130 -unit.1.5.waveform.posn.32.name=DataPort[130] -unit.1.5.waveform.posn.32.type=signal -unit.1.5.waveform.posn.33.channel=131 -unit.1.5.waveform.posn.33.name=DataPort[131] -unit.1.5.waveform.posn.33.type=signal -unit.1.5.waveform.posn.34.channel=132 -unit.1.5.waveform.posn.34.name=DataPort[132] -unit.1.5.waveform.posn.34.type=signal -unit.1.5.waveform.posn.35.channel=133 -unit.1.5.waveform.posn.35.name=DataPort[133] -unit.1.5.waveform.posn.35.type=signal -unit.1.5.waveform.posn.36.channel=134 -unit.1.5.waveform.posn.36.name=DataPort[134] -unit.1.5.waveform.posn.36.type=signal -unit.1.5.waveform.posn.37.channel=135 -unit.1.5.waveform.posn.37.name=DataPort[135] -unit.1.5.waveform.posn.37.type=signal -unit.1.5.waveform.posn.38.channel=2147483646 -unit.1.5.waveform.posn.38.name=dsp_q_fofb -unit.1.5.waveform.posn.38.radix=3 -unit.1.5.waveform.posn.38.type=bus -unit.1.5.waveform.posn.39.channel=2147483646 -unit.1.5.waveform.posn.39.name=dsp_sum_fofb -unit.1.5.waveform.posn.39.radix=3 -unit.1.5.waveform.posn.39.type=bus -unit.1.5.waveform.posn.4.channel=4 -unit.1.5.waveform.posn.4.name=DataPort[4] -unit.1.5.waveform.posn.4.type=signal -unit.1.5.waveform.posn.40.channel=2147483646 -unit.1.5.waveform.posn.40.name=dsp_x_fofb -unit.1.5.waveform.posn.40.radix=3 -unit.1.5.waveform.posn.40.type=bus -unit.1.5.waveform.posn.41.channel=2147483646 -unit.1.5.waveform.posn.41.name=dsp_y_fofb -unit.1.5.waveform.posn.41.radix=3 -unit.1.5.waveform.posn.41.type=bus -unit.1.5.waveform.posn.42.channel=2147483646 -unit.1.5.waveform.posn.42.name=dsp_y_fofb -unit.1.5.waveform.posn.42.radix=3 -unit.1.5.waveform.posn.42.type=bus -unit.1.5.waveform.posn.43.channel=2147483646 -unit.1.5.waveform.posn.43.name=dsp_y_fofb -unit.1.5.waveform.posn.43.radix=3 -unit.1.5.waveform.posn.43.type=bus -unit.1.5.waveform.posn.44.channel=2147483646 -unit.1.5.waveform.posn.44.name=dsp_y_fofb -unit.1.5.waveform.posn.44.radix=3 -unit.1.5.waveform.posn.44.type=bus -unit.1.5.waveform.posn.45.channel=2147483646 -unit.1.5.waveform.posn.45.name=dsp_y_fofb -unit.1.5.waveform.posn.45.radix=3 -unit.1.5.waveform.posn.45.type=bus -unit.1.5.waveform.posn.46.channel=2147483646 -unit.1.5.waveform.posn.46.name=dsp_y_fofb -unit.1.5.waveform.posn.46.radix=3 -unit.1.5.waveform.posn.46.type=bus -unit.1.5.waveform.posn.5.channel=5 -unit.1.5.waveform.posn.5.name=DataPort[5] -unit.1.5.waveform.posn.5.type=signal -unit.1.5.waveform.posn.6.channel=6 -unit.1.5.waveform.posn.6.name=DataPort[6] -unit.1.5.waveform.posn.6.type=signal -unit.1.5.waveform.posn.7.channel=7 -unit.1.5.waveform.posn.7.name=DataPort[7] -unit.1.5.waveform.posn.7.type=signal -unit.1.5.waveform.posn.8.channel=32 -unit.1.5.waveform.posn.8.name=DataPort[32] -unit.1.5.waveform.posn.8.type=signal -unit.1.5.waveform.posn.9.channel=33 -unit.1.5.waveform.posn.9.name=DataPort[33] -unit.1.5.waveform.posn.9.type=signal -unit.1.6.0.HEIGHT0=0.37337664 -unit.1.6.0.TriggerRow0=1 -unit.1.6.0.TriggerRow1=1 -unit.1.6.0.TriggerRow2=1 -unit.1.6.0.WIDTH0=0.6377551 -unit.1.6.0.X0=0.069970846 -unit.1.6.0.Y0=0.0 -unit.1.6.1.HEIGHT1=0.77922076 -unit.1.6.1.WIDTH1=0.58527696 -unit.1.6.1.X1=0.02478134 -unit.1.6.1.Y1=0.06818182 -unit.1.6.5.HEIGHT5=0.77922076 -unit.1.6.5.WIDTH5=0.85495627 -unit.1.6.5.X5=0.07653061 -unit.1.6.5.Y5=0.03733766 -unit.1.6.MFBitsA0=XXXXX1XX -unit.1.6.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsB0=00000000 -unit.1.6.MFBitsB1=00000000000000000000000000000000 -unit.1.6.MFBitsB2=00000000000000000000000000000000 -unit.1.6.MFBitsB3=00000000000000000000000000000000 -unit.1.6.MFBitsB4=00000000000000000000000000000000 -unit.1.6.MFCompareA0=0 -unit.1.6.MFCompareA1=0 -unit.1.6.MFCompareA2=0 -unit.1.6.MFCompareA3=0 -unit.1.6.MFCompareA4=0 -unit.1.6.MFCompareB0=999 -unit.1.6.MFCompareB1=999 -unit.1.6.MFCompareB2=999 -unit.1.6.MFCompareB3=999 -unit.1.6.MFCompareB4=999 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29 30 31 -unit.1.6.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=255] -unit.1.6.port.-1.b.2.name=DataPort -unit.1.6.port.-1.b.2.orderindex=-1 -unit.1.6.port.-1.b.2.radix=Signed -unit.1.6.port.-1.b.2.signedOffset=0.0 -unit.1.6.port.-1.b.2.signedPrecision=0 -unit.1.6.port.-1.b.2.signedScaleFactor=1.0 -unit.1.6.port.-1.b.2.tokencount=0 -unit.1.6.port.-1.b.2.unsignedOffset=0.0 -unit.1.6.port.-1.b.2.unsignedPrecision=0 -unit.1.6.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.2.visible=1 -unit.1.6.port.-1.b.3.alias=dsp_y_monit -unit.1.6.port.-1.b.3.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.6.port.-1.b.3.color=java.awt.Color[r\=255,g\=51,b\=51] -unit.1.6.port.-1.b.3.name=DataPort -unit.1.6.port.-1.b.3.orderindex=-1 -unit.1.6.port.-1.b.3.radix=Signed -unit.1.6.port.-1.b.3.signedOffset=0.0 -unit.1.6.port.-1.b.3.signedPrecision=0 -unit.1.6.port.-1.b.3.signedScaleFactor=1.0 -unit.1.6.port.-1.b.3.tokencount=0 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19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.b.0.name=TriggerPort1 -unit.1.6.port.1.b.0.orderindex=-1 -unit.1.6.port.1.b.0.radix=Hex -unit.1.6.port.1.b.0.signedOffset=0.0 -unit.1.6.port.1.b.0.signedPrecision=0 -unit.1.6.port.1.b.0.signedScaleFactor=1.0 -unit.1.6.port.1.b.0.unsignedOffset=0.0 -unit.1.6.port.1.b.0.unsignedPrecision=0 -unit.1.6.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.1.b.0.visible=1 -unit.1.6.port.1.buscount=1 -unit.1.6.port.1.channelcount=32 -unit.1.6.port.1.s.0.alias= -unit.1.6.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.0.name=TriggerPort1[0] -unit.1.6.port.1.s.0.orderindex=-1 -unit.1.6.port.1.s.0.visible=1 -unit.1.6.port.1.s.1.alias= -unit.1.6.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.1.name=TriggerPort1[1] -unit.1.6.port.1.s.1.orderindex=-1 -unit.1.6.port.1.s.1.visible=1 -unit.1.6.port.1.s.10.alias= -unit.1.6.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.10.name=TriggerPort1[10] -unit.1.6.port.1.s.10.orderindex=-1 -unit.1.6.port.1.s.10.visible=1 -unit.1.6.port.1.s.11.alias= -unit.1.6.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.11.name=TriggerPort1[11] -unit.1.6.port.1.s.11.orderindex=-1 -unit.1.6.port.1.s.11.visible=1 -unit.1.6.port.1.s.12.alias= -unit.1.6.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.12.name=TriggerPort1[12] -unit.1.6.port.1.s.12.orderindex=-1 -unit.1.6.port.1.s.12.visible=1 -unit.1.6.port.1.s.13.alias= -unit.1.6.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.13.name=TriggerPort1[13] -unit.1.6.port.1.s.13.orderindex=-1 -unit.1.6.port.1.s.13.visible=1 -unit.1.6.port.1.s.14.alias= -unit.1.6.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.14.name=TriggerPort1[14] -unit.1.6.port.1.s.14.orderindex=-1 -unit.1.6.port.1.s.14.visible=1 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-unit.1.6.port.1.s.19.visible=1 -unit.1.6.port.1.s.2.alias= -unit.1.6.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.2.name=TriggerPort1[2] -unit.1.6.port.1.s.2.orderindex=-1 -unit.1.6.port.1.s.2.visible=1 -unit.1.6.port.1.s.20.alias= -unit.1.6.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.20.name=TriggerPort1[20] -unit.1.6.port.1.s.20.orderindex=-1 -unit.1.6.port.1.s.20.visible=1 -unit.1.6.port.1.s.21.alias= -unit.1.6.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.21.name=TriggerPort1[21] -unit.1.6.port.1.s.21.orderindex=-1 -unit.1.6.port.1.s.21.visible=1 -unit.1.6.port.1.s.22.alias= -unit.1.6.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.22.name=TriggerPort1[22] -unit.1.6.port.1.s.22.orderindex=-1 -unit.1.6.port.1.s.22.visible=1 -unit.1.6.port.1.s.23.alias= -unit.1.6.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.23.name=TriggerPort1[23] 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-unit.1.6.port.1.s.28.name=TriggerPort1[28] -unit.1.6.port.1.s.28.orderindex=-1 -unit.1.6.port.1.s.28.visible=1 -unit.1.6.port.1.s.29.alias= -unit.1.6.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.29.name=TriggerPort1[29] -unit.1.6.port.1.s.29.orderindex=-1 -unit.1.6.port.1.s.29.visible=1 -unit.1.6.port.1.s.3.alias= -unit.1.6.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.3.name=TriggerPort1[3] -unit.1.6.port.1.s.3.orderindex=-1 -unit.1.6.port.1.s.3.visible=1 -unit.1.6.port.1.s.30.alias= -unit.1.6.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.30.name=TriggerPort1[30] -unit.1.6.port.1.s.30.orderindex=-1 -unit.1.6.port.1.s.30.visible=1 -unit.1.6.port.1.s.31.alias= -unit.1.6.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.31.name=TriggerPort1[31] -unit.1.6.port.1.s.31.orderindex=-1 -unit.1.6.port.1.s.31.visible=1 -unit.1.6.port.1.s.4.alias= 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-unit.1.6.port.2.s.0.visible=1 -unit.1.6.port.2.s.1.alias= -unit.1.6.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.1.name=TriggerPort2[1] -unit.1.6.port.2.s.1.orderindex=-1 -unit.1.6.port.2.s.1.visible=1 -unit.1.6.port.2.s.10.alias= -unit.1.6.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.10.name=TriggerPort2[10] -unit.1.6.port.2.s.10.orderindex=-1 -unit.1.6.port.2.s.10.visible=1 -unit.1.6.port.2.s.11.alias= -unit.1.6.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.11.name=TriggerPort2[11] -unit.1.6.port.2.s.11.orderindex=-1 -unit.1.6.port.2.s.11.visible=1 -unit.1.6.port.2.s.12.alias= -unit.1.6.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.12.name=TriggerPort2[12] -unit.1.6.port.2.s.12.orderindex=-1 -unit.1.6.port.2.s.12.visible=1 -unit.1.6.port.2.s.13.alias= -unit.1.6.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.13.name=TriggerPort2[13] -unit.1.6.port.2.s.13.orderindex=-1 -unit.1.6.port.2.s.13.visible=1 -unit.1.6.port.2.s.14.alias= -unit.1.6.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.14.name=TriggerPort2[14] -unit.1.6.port.2.s.14.orderindex=-1 -unit.1.6.port.2.s.14.visible=1 -unit.1.6.port.2.s.15.alias= -unit.1.6.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.15.name=TriggerPort2[15] -unit.1.6.port.2.s.15.orderindex=-1 -unit.1.6.port.2.s.15.visible=1 -unit.1.6.port.2.s.16.alias= -unit.1.6.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.16.name=TriggerPort2[16] -unit.1.6.port.2.s.16.orderindex=-1 -unit.1.6.port.2.s.16.visible=1 -unit.1.6.port.2.s.17.alias= -unit.1.6.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.17.name=TriggerPort2[17] -unit.1.6.port.2.s.17.orderindex=-1 -unit.1.6.port.2.s.17.visible=1 -unit.1.6.port.2.s.18.alias= -unit.1.6.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.6.port.2.s.30.visible=1 -unit.1.6.port.2.s.31.alias= -unit.1.6.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.31.name=TriggerPort2[31] -unit.1.6.port.2.s.31.orderindex=-1 -unit.1.6.port.2.s.31.visible=1 -unit.1.6.port.2.s.4.alias= -unit.1.6.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.4.name=TriggerPort2[4] -unit.1.6.port.2.s.4.orderindex=-1 -unit.1.6.port.2.s.4.visible=1 -unit.1.6.port.2.s.5.alias= -unit.1.6.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.5.name=TriggerPort2[5] -unit.1.6.port.2.s.5.orderindex=-1 -unit.1.6.port.2.s.5.visible=1 -unit.1.6.port.2.s.6.alias= -unit.1.6.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.6.name=TriggerPort2[6] -unit.1.6.port.2.s.6.orderindex=-1 -unit.1.6.port.2.s.6.visible=1 -unit.1.6.port.2.s.7.alias= -unit.1.6.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.7.name=TriggerPort2[7] -unit.1.6.port.2.s.7.orderindex=-1 -unit.1.6.port.2.s.7.visible=1 -unit.1.6.port.2.s.8.alias= -unit.1.6.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.8.name=TriggerPort2[8] -unit.1.6.port.2.s.8.orderindex=-1 -unit.1.6.port.2.s.8.visible=1 -unit.1.6.port.2.s.9.alias= -unit.1.6.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.9.name=TriggerPort2[9] -unit.1.6.port.2.s.9.orderindex=-1 -unit.1.6.port.2.s.9.visible=1 -unit.1.6.port.3.b.0.alias= -unit.1.6.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.b.0.name=TriggerPort3 -unit.1.6.port.3.b.0.orderindex=-1 -unit.1.6.port.3.b.0.radix=Hex -unit.1.6.port.3.b.0.signedOffset=0.0 -unit.1.6.port.3.b.0.signedPrecision=0 -unit.1.6.port.3.b.0.signedScaleFactor=1.0 -unit.1.6.port.3.b.0.unsignedOffset=0.0 -unit.1.6.port.3.b.0.unsignedPrecision=0 -unit.1.6.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.3.b.0.visible=1 -unit.1.6.port.3.buscount=1 -unit.1.6.port.3.channelcount=32 -unit.1.6.port.3.s.0.alias= -unit.1.6.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.0.name=TriggerPort3[0] -unit.1.6.port.3.s.0.orderindex=-1 -unit.1.6.port.3.s.0.visible=1 -unit.1.6.port.3.s.1.alias= -unit.1.6.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.1.name=TriggerPort3[1] -unit.1.6.port.3.s.1.orderindex=-1 -unit.1.6.port.3.s.1.visible=1 -unit.1.6.port.3.s.10.alias= -unit.1.6.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.10.name=TriggerPort3[10] -unit.1.6.port.3.s.10.orderindex=-1 -unit.1.6.port.3.s.10.visible=1 -unit.1.6.port.3.s.11.alias= -unit.1.6.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.11.name=TriggerPort3[11] -unit.1.6.port.3.s.11.orderindex=-1 -unit.1.6.port.3.s.11.visible=1 -unit.1.6.port.3.s.12.alias= -unit.1.6.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.12.name=TriggerPort3[12] -unit.1.6.port.3.s.12.orderindex=-1 -unit.1.6.port.3.s.12.visible=1 -unit.1.6.port.3.s.13.alias= -unit.1.6.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.13.name=TriggerPort3[13] -unit.1.6.port.3.s.13.orderindex=-1 -unit.1.6.port.3.s.13.visible=1 -unit.1.6.port.3.s.14.alias= -unit.1.6.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.14.name=TriggerPort3[14] -unit.1.6.port.3.s.14.orderindex=-1 -unit.1.6.port.3.s.14.visible=1 -unit.1.6.port.3.s.15.alias= -unit.1.6.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.15.name=TriggerPort3[15] -unit.1.6.port.3.s.15.orderindex=-1 -unit.1.6.port.3.s.15.visible=1 -unit.1.6.port.3.s.16.alias= -unit.1.6.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.16.name=TriggerPort3[16] -unit.1.6.port.3.s.16.orderindex=-1 -unit.1.6.port.3.s.16.visible=1 -unit.1.6.port.3.s.17.alias= -unit.1.6.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.17.name=TriggerPort3[17] -unit.1.6.port.3.s.17.orderindex=-1 -unit.1.6.port.3.s.17.visible=1 -unit.1.6.port.3.s.18.alias= -unit.1.6.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.18.name=TriggerPort3[18] -unit.1.6.port.3.s.18.orderindex=-1 -unit.1.6.port.3.s.18.visible=1 -unit.1.6.port.3.s.19.alias= -unit.1.6.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.19.name=TriggerPort3[19] -unit.1.6.port.3.s.19.orderindex=-1 -unit.1.6.port.3.s.19.visible=1 -unit.1.6.port.3.s.2.alias= -unit.1.6.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.2.name=TriggerPort3[2] -unit.1.6.port.3.s.2.orderindex=-1 -unit.1.6.port.3.s.2.visible=1 -unit.1.6.port.3.s.20.alias= -unit.1.6.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.20.name=TriggerPort3[20] -unit.1.6.port.3.s.20.orderindex=-1 -unit.1.6.port.3.s.20.visible=1 -unit.1.6.port.3.s.21.alias= -unit.1.6.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.21.name=TriggerPort3[21] -unit.1.6.port.3.s.21.orderindex=-1 -unit.1.6.port.3.s.21.visible=1 -unit.1.6.port.3.s.22.alias= -unit.1.6.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.22.name=TriggerPort3[22] -unit.1.6.port.3.s.22.orderindex=-1 -unit.1.6.port.3.s.22.visible=1 -unit.1.6.port.3.s.23.alias= -unit.1.6.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.23.name=TriggerPort3[23] -unit.1.6.port.3.s.23.orderindex=-1 -unit.1.6.port.3.s.23.visible=1 -unit.1.6.port.3.s.24.alias= -unit.1.6.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.24.name=TriggerPort3[24] -unit.1.6.port.3.s.24.orderindex=-1 -unit.1.6.port.3.s.24.visible=1 -unit.1.6.port.3.s.25.alias= -unit.1.6.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.25.name=TriggerPort3[25] -unit.1.6.port.3.s.25.orderindex=-1 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-unit.1.6.port.3.s.3.orderindex=-1 -unit.1.6.port.3.s.3.visible=1 -unit.1.6.port.3.s.30.alias= -unit.1.6.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.30.name=TriggerPort3[30] -unit.1.6.port.3.s.30.orderindex=-1 -unit.1.6.port.3.s.30.visible=1 -unit.1.6.port.3.s.31.alias= -unit.1.6.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.31.name=TriggerPort3[31] -unit.1.6.port.3.s.31.orderindex=-1 -unit.1.6.port.3.s.31.visible=1 -unit.1.6.port.3.s.4.alias= -unit.1.6.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.4.name=TriggerPort3[4] -unit.1.6.port.3.s.4.orderindex=-1 -unit.1.6.port.3.s.4.visible=1 -unit.1.6.port.3.s.5.alias= -unit.1.6.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.5.name=TriggerPort3[5] -unit.1.6.port.3.s.5.orderindex=-1 -unit.1.6.port.3.s.5.visible=1 -unit.1.6.port.3.s.6.alias= -unit.1.6.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.6.name=TriggerPort3[6] -unit.1.6.port.3.s.6.orderindex=-1 -unit.1.6.port.3.s.6.visible=1 -unit.1.6.port.3.s.7.alias= -unit.1.6.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.7.name=TriggerPort3[7] -unit.1.6.port.3.s.7.orderindex=-1 -unit.1.6.port.3.s.7.visible=1 -unit.1.6.port.3.s.8.alias= -unit.1.6.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.8.name=TriggerPort3[8] -unit.1.6.port.3.s.8.orderindex=-1 -unit.1.6.port.3.s.8.visible=1 -unit.1.6.port.3.s.9.alias= -unit.1.6.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.9.name=TriggerPort3[9] -unit.1.6.port.3.s.9.orderindex=-1 -unit.1.6.port.3.s.9.visible=1 -unit.1.6.port.4.b.0.alias= -unit.1.6.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.b.0.name=TriggerPort4 -unit.1.6.port.4.b.0.orderindex=-1 -unit.1.6.port.4.b.0.radix=Hex -unit.1.6.port.4.b.0.signedOffset=0.0 -unit.1.6.port.4.b.0.signedPrecision=0 -unit.1.6.port.4.b.0.signedScaleFactor=1.0 -unit.1.6.port.4.b.0.unsignedOffset=0.0 -unit.1.6.port.4.b.0.unsignedPrecision=0 -unit.1.6.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.4.b.0.visible=1 -unit.1.6.port.4.buscount=1 -unit.1.6.port.4.channelcount=32 -unit.1.6.port.4.s.0.alias= -unit.1.6.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.0.name=TriggerPort4[0] -unit.1.6.port.4.s.0.orderindex=-1 -unit.1.6.port.4.s.0.visible=1 -unit.1.6.port.4.s.1.alias= -unit.1.6.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.1.name=TriggerPort4[1] -unit.1.6.port.4.s.1.orderindex=-1 -unit.1.6.port.4.s.1.visible=1 -unit.1.6.port.4.s.10.alias= -unit.1.6.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.10.name=TriggerPort4[10] -unit.1.6.port.4.s.10.orderindex=-1 -unit.1.6.port.4.s.10.visible=1 -unit.1.6.port.4.s.11.alias= -unit.1.6.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.11.name=TriggerPort4[11] -unit.1.6.port.4.s.11.orderindex=-1 -unit.1.6.port.4.s.11.visible=1 -unit.1.6.port.4.s.12.alias= -unit.1.6.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.12.name=TriggerPort4[12] -unit.1.6.port.4.s.12.orderindex=-1 -unit.1.6.port.4.s.12.visible=1 -unit.1.6.port.4.s.13.alias= -unit.1.6.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.13.name=TriggerPort4[13] -unit.1.6.port.4.s.13.orderindex=-1 -unit.1.6.port.4.s.13.visible=1 -unit.1.6.port.4.s.14.alias= -unit.1.6.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.14.name=TriggerPort4[14] -unit.1.6.port.4.s.14.orderindex=-1 -unit.1.6.port.4.s.14.visible=1 -unit.1.6.port.4.s.15.alias= -unit.1.6.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.15.name=TriggerPort4[15] -unit.1.6.port.4.s.15.orderindex=-1 -unit.1.6.port.4.s.15.visible=1 -unit.1.6.port.4.s.16.alias= -unit.1.6.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.16.name=TriggerPort4[16] -unit.1.6.port.4.s.16.orderindex=-1 -unit.1.6.port.4.s.16.visible=1 -unit.1.6.port.4.s.17.alias= -unit.1.6.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.17.name=TriggerPort4[17] -unit.1.6.port.4.s.17.orderindex=-1 -unit.1.6.port.4.s.17.visible=1 -unit.1.6.port.4.s.18.alias= -unit.1.6.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.18.name=TriggerPort4[18] -unit.1.6.port.4.s.18.orderindex=-1 -unit.1.6.port.4.s.18.visible=1 -unit.1.6.port.4.s.19.alias= -unit.1.6.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.19.name=TriggerPort4[19] -unit.1.6.port.4.s.19.orderindex=-1 -unit.1.6.port.4.s.19.visible=1 -unit.1.6.port.4.s.2.alias= -unit.1.6.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.2.name=TriggerPort4[2] -unit.1.6.port.4.s.2.orderindex=-1 -unit.1.6.port.4.s.2.visible=1 -unit.1.6.port.4.s.20.alias= -unit.1.6.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.20.name=TriggerPort4[20] -unit.1.6.port.4.s.20.orderindex=-1 -unit.1.6.port.4.s.20.visible=1 -unit.1.6.port.4.s.21.alias= -unit.1.6.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.21.name=TriggerPort4[21] -unit.1.6.port.4.s.21.orderindex=-1 -unit.1.6.port.4.s.21.visible=1 -unit.1.6.port.4.s.22.alias= -unit.1.6.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.22.name=TriggerPort4[22] -unit.1.6.port.4.s.22.orderindex=-1 -unit.1.6.port.4.s.22.visible=1 -unit.1.6.port.4.s.23.alias= -unit.1.6.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.23.name=TriggerPort4[23] -unit.1.6.port.4.s.23.orderindex=-1 -unit.1.6.port.4.s.23.visible=1 -unit.1.6.port.4.s.24.alias= -unit.1.6.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.24.name=TriggerPort4[24] -unit.1.6.port.4.s.24.orderindex=-1 -unit.1.6.port.4.s.24.visible=1 -unit.1.6.port.4.s.25.alias= -unit.1.6.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.25.name=TriggerPort4[25] -unit.1.6.port.4.s.25.orderindex=-1 -unit.1.6.port.4.s.25.visible=1 -unit.1.6.port.4.s.26.alias= -unit.1.6.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.26.name=TriggerPort4[26] -unit.1.6.port.4.s.26.orderindex=-1 -unit.1.6.port.4.s.26.visible=1 -unit.1.6.port.4.s.27.alias= -unit.1.6.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.27.name=TriggerPort4[27] -unit.1.6.port.4.s.27.orderindex=-1 -unit.1.6.port.4.s.27.visible=1 -unit.1.6.port.4.s.28.alias= -unit.1.6.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.28.name=TriggerPort4[28] -unit.1.6.port.4.s.28.orderindex=-1 -unit.1.6.port.4.s.28.visible=1 -unit.1.6.port.4.s.29.alias= -unit.1.6.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.29.name=TriggerPort4[29] -unit.1.6.port.4.s.29.orderindex=-1 -unit.1.6.port.4.s.29.visible=1 -unit.1.6.port.4.s.3.alias= -unit.1.6.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.3.name=TriggerPort4[3] -unit.1.6.port.4.s.3.orderindex=-1 -unit.1.6.port.4.s.3.visible=1 -unit.1.6.port.4.s.30.alias= -unit.1.6.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.30.name=TriggerPort4[30] -unit.1.6.port.4.s.30.orderindex=-1 -unit.1.6.port.4.s.30.visible=1 -unit.1.6.port.4.s.31.alias= -unit.1.6.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.31.name=TriggerPort4[31] -unit.1.6.port.4.s.31.orderindex=-1 -unit.1.6.port.4.s.31.visible=1 -unit.1.6.port.4.s.4.alias= -unit.1.6.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.4.name=TriggerPort4[4] -unit.1.6.port.4.s.4.orderindex=-1 -unit.1.6.port.4.s.4.visible=1 -unit.1.6.port.4.s.5.alias= -unit.1.6.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.5.name=TriggerPort4[5] -unit.1.6.port.4.s.5.orderindex=-1 -unit.1.6.port.4.s.5.visible=1 -unit.1.6.port.4.s.6.alias= -unit.1.6.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.6.name=TriggerPort4[6] -unit.1.6.port.4.s.6.orderindex=-1 -unit.1.6.port.4.s.6.visible=1 -unit.1.6.port.4.s.7.alias= -unit.1.6.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.7.name=TriggerPort4[7] -unit.1.6.port.4.s.7.orderindex=-1 -unit.1.6.port.4.s.7.visible=1 -unit.1.6.port.4.s.8.alias= -unit.1.6.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.8.name=TriggerPort4[8] -unit.1.6.port.4.s.8.orderindex=-1 -unit.1.6.port.4.s.8.visible=1 -unit.1.6.port.4.s.9.alias= -unit.1.6.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.9.name=TriggerPort4[9] -unit.1.6.port.4.s.9.orderindex=-1 -unit.1.6.port.4.s.9.visible=1 -unit.1.6.portcount=5 -unit.1.6.rep_trigger.clobber=1 -unit.1.6.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp -unit.1.6.rep_trigger.filename=waveform -unit.1.6.rep_trigger.format=ASCII -unit.1.6.rep_trigger.loggingEnabled=0 -unit.1.6.rep_trigger.signals=All Signals/Buses -unit.1.6.samplesPerTrigger=1 -unit.1.6.triggerCapture=1 -unit.1.6.triggerNSamplesTS=0 -unit.1.6.triggerPosition=0 -unit.1.6.triggerWindowCount=1 -unit.1.6.triggerWindowDepth=4096 -unit.1.6.triggerWindowTS=0 -unit.1.6.username=MyILA6 -unit.1.6.waveform.count=42 -unit.1.6.waveform.posn.0.channel=0 -unit.1.6.waveform.posn.0.name=DataPort[0] -unit.1.6.waveform.posn.0.type=signal -unit.1.6.waveform.posn.1.channel=1 -unit.1.6.waveform.posn.1.name=DataPort[1] -unit.1.6.waveform.posn.1.type=signal -unit.1.6.waveform.posn.10.channel=34 -unit.1.6.waveform.posn.10.name=DataPort[34] -unit.1.6.waveform.posn.10.type=signal -unit.1.6.waveform.posn.11.channel=35 -unit.1.6.waveform.posn.11.name=DataPort[35] -unit.1.6.waveform.posn.11.type=signal -unit.1.6.waveform.posn.12.channel=36 -unit.1.6.waveform.posn.12.name=DataPort[36] -unit.1.6.waveform.posn.12.type=signal -unit.1.6.waveform.posn.13.channel=37 -unit.1.6.waveform.posn.13.name=DataPort[37] -unit.1.6.waveform.posn.13.type=signal -unit.1.6.waveform.posn.14.channel=38 -unit.1.6.waveform.posn.14.name=DataPort[38] -unit.1.6.waveform.posn.14.type=signal -unit.1.6.waveform.posn.15.channel=39 -unit.1.6.waveform.posn.15.name=DataPort[39] -unit.1.6.waveform.posn.15.type=signal -unit.1.6.waveform.posn.16.channel=64 -unit.1.6.waveform.posn.16.name=DataPort[64] -unit.1.6.waveform.posn.16.type=signal -unit.1.6.waveform.posn.17.channel=65 -unit.1.6.waveform.posn.17.name=DataPort[65] -unit.1.6.waveform.posn.17.type=signal -unit.1.6.waveform.posn.18.channel=66 -unit.1.6.waveform.posn.18.name=DataPort[66] -unit.1.6.waveform.posn.18.type=signal -unit.1.6.waveform.posn.19.channel=67 -unit.1.6.waveform.posn.19.name=DataPort[67] -unit.1.6.waveform.posn.19.type=signal -unit.1.6.waveform.posn.2.channel=2 -unit.1.6.waveform.posn.2.name=DataPort[2] -unit.1.6.waveform.posn.2.type=signal -unit.1.6.waveform.posn.20.channel=68 -unit.1.6.waveform.posn.20.name=DataPort[68] -unit.1.6.waveform.posn.20.type=signal -unit.1.6.waveform.posn.21.channel=69 -unit.1.6.waveform.posn.21.name=DataPort[69] -unit.1.6.waveform.posn.21.type=signal -unit.1.6.waveform.posn.22.channel=70 -unit.1.6.waveform.posn.22.name=DataPort[70] -unit.1.6.waveform.posn.22.type=signal -unit.1.6.waveform.posn.23.channel=71 -unit.1.6.waveform.posn.23.name=DataPort[71] -unit.1.6.waveform.posn.23.type=signal -unit.1.6.waveform.posn.24.channel=96 -unit.1.6.waveform.posn.24.name=DataPort[96] -unit.1.6.waveform.posn.24.type=signal -unit.1.6.waveform.posn.25.channel=97 -unit.1.6.waveform.posn.25.name=DataPort[97] -unit.1.6.waveform.posn.25.type=signal -unit.1.6.waveform.posn.26.channel=98 -unit.1.6.waveform.posn.26.name=DataPort[98] -unit.1.6.waveform.posn.26.type=signal -unit.1.6.waveform.posn.27.channel=99 -unit.1.6.waveform.posn.27.name=DataPort[99] -unit.1.6.waveform.posn.27.type=signal -unit.1.6.waveform.posn.28.channel=100 -unit.1.6.waveform.posn.28.name=DataPort[100] -unit.1.6.waveform.posn.28.type=signal -unit.1.6.waveform.posn.29.channel=101 -unit.1.6.waveform.posn.29.name=DataPort[101] -unit.1.6.waveform.posn.29.type=signal -unit.1.6.waveform.posn.3.channel=3 -unit.1.6.waveform.posn.3.name=DataPort[3] -unit.1.6.waveform.posn.3.type=signal -unit.1.6.waveform.posn.30.channel=102 -unit.1.6.waveform.posn.30.name=DataPort[102] -unit.1.6.waveform.posn.30.type=signal -unit.1.6.waveform.posn.31.channel=103 -unit.1.6.waveform.posn.31.name=DataPort[103] -unit.1.6.waveform.posn.31.type=signal -unit.1.6.waveform.posn.32.channel=130 -unit.1.6.waveform.posn.32.name=DataPort[130] -unit.1.6.waveform.posn.32.type=signal -unit.1.6.waveform.posn.33.channel=131 -unit.1.6.waveform.posn.33.name=DataPort[131] -unit.1.6.waveform.posn.33.type=signal -unit.1.6.waveform.posn.34.channel=132 -unit.1.6.waveform.posn.34.name=DataPort[132] -unit.1.6.waveform.posn.34.type=signal -unit.1.6.waveform.posn.35.channel=133 -unit.1.6.waveform.posn.35.name=DataPort[133] -unit.1.6.waveform.posn.35.type=signal -unit.1.6.waveform.posn.36.channel=134 -unit.1.6.waveform.posn.36.name=DataPort[134] -unit.1.6.waveform.posn.36.type=signal -unit.1.6.waveform.posn.37.channel=135 -unit.1.6.waveform.posn.37.name=DataPort[135] -unit.1.6.waveform.posn.37.type=signal -unit.1.6.waveform.posn.38.channel=2147483646 -unit.1.6.waveform.posn.38.name=dsp_q_monit -unit.1.6.waveform.posn.38.radix=3 -unit.1.6.waveform.posn.38.type=bus -unit.1.6.waveform.posn.39.channel=2147483646 -unit.1.6.waveform.posn.39.name=dsp_sum_monit -unit.1.6.waveform.posn.39.radix=3 -unit.1.6.waveform.posn.39.type=bus -unit.1.6.waveform.posn.4.channel=4 -unit.1.6.waveform.posn.4.name=DataPort[4] -unit.1.6.waveform.posn.4.type=signal -unit.1.6.waveform.posn.40.channel=2147483646 -unit.1.6.waveform.posn.40.name=dsp_x_monit -unit.1.6.waveform.posn.40.radix=3 -unit.1.6.waveform.posn.40.type=bus -unit.1.6.waveform.posn.41.channel=2147483646 -unit.1.6.waveform.posn.41.name=dsp_y_monit -unit.1.6.waveform.posn.41.radix=3 -unit.1.6.waveform.posn.41.type=bus -unit.1.6.waveform.posn.42.channel=2147483646 -unit.1.6.waveform.posn.42.name=dsp_y_monit -unit.1.6.waveform.posn.42.radix=3 -unit.1.6.waveform.posn.42.type=bus -unit.1.6.waveform.posn.43.channel=2147483646 -unit.1.6.waveform.posn.43.name=dsp_y_monit -unit.1.6.waveform.posn.43.radix=3 -unit.1.6.waveform.posn.43.type=bus -unit.1.6.waveform.posn.44.channel=2147483646 -unit.1.6.waveform.posn.44.name=dsp_y_monit -unit.1.6.waveform.posn.44.radix=3 -unit.1.6.waveform.posn.44.type=bus -unit.1.6.waveform.posn.45.channel=2147483646 -unit.1.6.waveform.posn.45.name=dsp_y_monit -unit.1.6.waveform.posn.45.radix=3 -unit.1.6.waveform.posn.45.type=bus -unit.1.6.waveform.posn.46.channel=2147483646 -unit.1.6.waveform.posn.46.name=dsp_y_monit -unit.1.6.waveform.posn.46.radix=3 -unit.1.6.waveform.posn.46.type=bus -unit.1.6.waveform.posn.5.channel=5 -unit.1.6.waveform.posn.5.name=DataPort[5] -unit.1.6.waveform.posn.5.type=signal -unit.1.6.waveform.posn.6.channel=6 -unit.1.6.waveform.posn.6.name=DataPort[6] -unit.1.6.waveform.posn.6.type=signal -unit.1.6.waveform.posn.7.channel=7 -unit.1.6.waveform.posn.7.name=DataPort[7] -unit.1.6.waveform.posn.7.type=signal -unit.1.6.waveform.posn.8.channel=32 -unit.1.6.waveform.posn.8.name=DataPort[32] -unit.1.6.waveform.posn.8.type=signal -unit.1.6.waveform.posn.9.channel=33 -unit.1.6.waveform.posn.9.name=DataPort[33] -unit.1.6.waveform.posn.9.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd deleted file mode 100644 index 82273c68..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic; - sys_clk_bufg_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - sys_clk_o <= s_sys_clk; - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf deleted file mode 100644 index 1cea7598..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf +++ /dev/null @@ -1,703 +0,0 @@ -####################################################################### -## Virtex6 Board ML605 ## -####################################################################### - -NET "sys_clk_n_i" LOC = H9 | IOSTANDARD = LVDS_25; # 5 on U11, 5 on U89 (DNP) -NET "sys_clk_p_i" LOC = J9 | IOSTANDARD = LVDS_25; # 4 on U11, 4 on U89 (DNP) - -NET "rs232_rxd_i" LOC = J24 | IOSTANDARD = LVCMOS25; # 25 on U34 -NET "rs232_txd_o" LOC = J25 | IOSTANDARD = LVCMOS25; # 24 on U34 - -NET "sys_rst_button_i" LOC = H10 | IOSTANDARD = "SSTL15" | TIG; - -# MMCM Status -NET "fmc_mmcm_lock_led_o" LOC = "AP24" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_C, DS16 - -# LMK clock distribution Status -NET "fmc_pll_status_led_o" LOC = "AD21" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_W, DS17 - -#NET "led_south_o" LOC = "AH28" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_S, DS18 -#NET "led_east_o" LOC = "AE21" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_E, DS19 -#NET "led_north_o" LOC = "AH27" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_N, DS20 - -#NET "board_led1_o" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 0 -#NET "board_led2_o" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 1 -#NET "board_led3_o" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 2 - -NET "clk_swap_o" LOC = V34 | IOSTANDARD = LVCMOS25; # USER_SMA_GPIO_P -NET "clk_swap2x_o" LOC = L23 | IOSTANDARD = LVCMOS25; # USER_SMA_CLK_P -NET "flag1_o" LOC = W34 | IOSTANDARD = LVCMOS25; # USER_SMA_GPIO_N -NET "flag2_o" LOC = M22 | IOSTANDARD = LVCMOS25; # USER_SMA_CLK_N - -####################################################################### -## Button/LEDs Contraints ## -####################################################################### - -#NET "buttons_i[0]" LOC = D22 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[1]" LOC = C22 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[2]" LOC = L21 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[3]" LOC = L20 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[4]" LOC = C18 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[5]" LOC = B18 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[6]" LOC = K22 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[7]" LOC = K21 | IOSTANDARD = LVCMOS25; -NET "leds_o[0]" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[1]" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[2]" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[3]" LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[4]" LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[5]" LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[6]" LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[7]" LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; - -####################################################################### -## UART Constraints ## -####################################################################### - -####################################################################### -## Clock and Reset Contraints ## -####################################################################### - -NET "sys_clk_n_i" LOC = H9 | IOSTANDARD = LVDS_25; -NET "sys_clk_p_i" LOC = J9 | IOSTANDARD = LVDS_25; -NET "sys_rst_button_i" LOC = H10 | IOSTANDARD = SSTL15 | TIG; - -NET "clk_sys" TNM_NET = "sys_clk_group"; -NET "clk_200mhz" TNM_NET = "sys_clk200_group"; - -TIMESPEC "TS_sys_clk_group" = PERIOD "sys_clk_group" 10 ns; # 100 MHz -TIMESPEC "TS_sys_clk200_group" = PERIOD "sys_clk200_group" 5 ns; # 200 MHz - -####################################################################### -## Ethernet Contraints. MII 10/100 Mode ## -####################################################################### - -NET "mrstn_o" LOC = AH13; -NET "mcoll_pad_i" LOC = AK13; ## 114 on U80 -NET "mcrs_pad_i" LOC = AL13; ## 115 on U80 -# NET "PHY_INT" LOC = AH14; ## 32 on U80 -NET "mdc_pad_o" LOC = AP14; ## 35 on U80 -NET "md_pad_b" LOC = AN14; ## 33 on U80 -# NET "PHY_RESET" LOC = AH13; ## 36 on U80 -NET "mrx_clk_pad_i" LOC = AP11; ## 7 on U80 -NET "mrxdv_pad_i" LOC = AM13; ## 4 on U80 -NET "mrxd_pad_i[0]" LOC = AN13; ## 3 on U80 -NET "mrxd_pad_i[1]" LOC = AF14; ## 128 on U80 -NET "mrxd_pad_i[2]" LOC = AE14; ## 126 on U80 -NET "mrxd_pad_i[3]" LOC = AN12; ## 125 on U80 -# NET "PHY_RXD4" LOC = AM12; ## 124 on U80 -# NET "PHY_RXD5" LOC = AD11; ## 123 on U80 -# NET "PHY_RXD6" LOC = AC12; ## 121 on U80 -# NET "PHY_RXD7" LOC = AC13; ## 120 on U80 -NET "mrxerr_pad_i" LOC = AG12; ## 9 on U80 -NET "mtx_clk_pad_i" LOC = AD12; ## 10 on U80 -NET "mtxen_pad_o" LOC = AJ10; ## 16 on U80 -# NET "PHY_TXC_GTXCLK" LOC = AH12; ## 14 on U80 -NET "mtxd_pad_o[0]" LOC = AM11; ## 18 on U80 -NET "mtxd_pad_o[1]" LOC = AL11; ## 19 on U80 -NET "mtxd_pad_o[2]" LOC = AG10; ## 20 on U80 -NET "mtxd_pad_o[3]" LOC = AG11; ## 24 on U80 -# NET "PHY_TXD4" LOC = AL10; ## 25 on U80 -# NET "PHY_TXD5" LOC = AM10; ## 26 on U80 -# NET "PHY_TXD6" LOC = AE11; ## 28 on U80 -# NET "PHY_TXD7" LOC = AF11; ## 29 on U80 -NET "mtxerr_pad_o" LOC = AH10; ## 13 on U80 - -####################################################################### -## FMC Connector HPC ## -####################################################################### - - -NET "fmc_prsnt_i" LOC = AP25 | IOSTANDARD = "LVCMOS25"; -NET "fmc_pg_m2c_i" LOC = AK29 | IOSTANDARD = "LVCMOS25"; // LA31_N - -// Trigger -NET "fmc_trig_dir_o" LOC = AK27 | IOSTANDARD = "LVCMOS25"; // LA28_P -NET "fmc_trig_term_o" LOC = AL25 | IOSTANDARD = "LVCMOS25"; // LA26_N -NET "fmc_trig_val_p_b" LOC = AG25 | IOSTANDARD = "BLVDS_25"; // LA32_P -NET "fmc_trig_val_n_b" LOC = AG26 | IOSTANDARD = "BLVDS_25"; // LA32_N - -// Si571 clock gen -NET "si571_scl_pad_b" LOC = AE32 | IOSTANDARD = "LVCMOS25"; // HA12_N -NET "si571_sda_pad_b" LOC = AE31 | IOSTANDARD = "LVCMOS25"; // HA13_P -NET "fmc_si571_oe_o" LOC = AD32 | IOSTANDARD = "LVCMOS25"; // HA12_P - -// AD9510 clock distribution PLL -NET "spi_ad9510_cs_o" LOC = AN18 | IOSTANDARD = "LVCMOS25"; // LA13_N -NET "spi_ad9510_sclk_o" LOC = AP19 | IOSTANDARD = "LVCMOS25"; // LA13_P -NET "spi_ad9510_mosi_o" LOC = AL18 | IOSTANDARD = "LVCMOS25"; // LA09_N -NET "spi_ad9510_miso_i" LOC = AN19 | IOSTANDARD = "LVCMOS25"; // LA14_P -NET "fmc_pll_function_o" LOC = AN20 | IOSTANDARD = "LVCMOS25"; // LA14_N -NET "fmc_pll_status_i" LOC = AM18 | IOSTANDARD = "LVCMOS25"; // LA09_P - -#NET "fmc_fpga_clk_p_i" LOC = K24 | IOSTANDARD = "LVDS_25"; // CLK0_M2C_P -#NET "fmc_fpga_clk_n_i" LOC = K23 | IOSTANDARD = "LVDS_25"; // CLK0_M2C_N - -// Clock reference selection (TS3USB221) -NET "fmc_clk_sel_o" LOC = AL29 | IOSTANDARD = "LVCMOS25"; // LA31_P - -// EEPROM (multiplexer PCA9548) -NET "eeprom_scl_pad_b" LOC = AK9 | IOSTANDARD ="LVCMOS25"; # SCL C30 -NET "eeprom_sda_pad_b" LOC = AE9 | IOSTANDARD ="LVCMOS25"; # SDA C31 - -// LM75 temperature monitor (can be used without multiplexer on KC705 board) -NET "lm75_scl_pad_b" LOC = AP30 | IOSTANDARD = "LVCMOS25"; // LA27_P -NET "lm75_sda_pad_b" LOC = AP31 | IOSTANDARD = "LVCMOS25"; // LA27_N -NET "fmc_lm75_temp_alarm_i" LOC = AJ27 | IOSTANDARD = "LVCMOS25"; // LA28_N - -// LTC ADC control pins -NET "fmc_adc_pga_o" LOC = AG20 | IOSTANDARD = "LVCMOS25"; // LA06_P -NET "fmc_adc_shdn_o" LOC = AL20 | IOSTANDARD = "LVCMOS25"; // LA10_N -NET "fmc_adc_dith_o" LOC = AM20 | IOSTANDARD = "LVCMOS25"; // LA10_P -NET "fmc_adc_rand_o" LOC = AG21 | IOSTANDARD = "LVCMOS25"; // LA06_N - -// LEDs -NET "fmc_led1_o" LOC = AN23 | IOSTANDARD = "LVCMOS25"; // LA16_N -NET "fmc_led2_o" LOC = AP22 | IOSTANDARD = "LVCMOS25"; // LA16_P -NET "fmc_led3_o" LOC = AM25 | IOSTANDARD = "LVCMOS25"; // LA26_P - -####################################################################### -## FMC Connector HPC # -## LTC ADC lines # -####################################################################### - -// ADC0 -NET "fmc_adc0_clk_i" LOC = AN27 | IOSTANDARD = "LVCMOS25"; // LA17_CC_P - -NET "fmc_adc0_data_i[0]" LOC = AN30 | IOSTANDARD = "LVCMOS25"; // LA24_P -NET "fmc_adc0_data_i[1]" LOC = AM30 | IOSTANDARD = "LVCMOS25"; // LA24_N -NET "fmc_adc0_data_i[2]" LOC = AN28 | IOSTANDARD = "LVCMOS25"; // LA25_P -NET "fmc_adc0_data_i[3]" LOC = AM28 | IOSTANDARD = "LVCMOS25"; // LA25_N -NET "fmc_adc0_data_i[4]" LOC = AN29 | IOSTANDARD = "LVCMOS25"; // LA21_P -NET "fmc_adc0_data_i[5]" LOC = AP29 | IOSTANDARD = "LVCMOS25"; // LA21_N -NET "fmc_adc0_data_i[6]" LOC = AP27 | IOSTANDARD = "LVCMOS25"; // LA22_P -NET "fmc_adc0_data_i[7]" LOC = AP26 | IOSTANDARD = "LVCMOS25"; // LA22_N -NET "fmc_adc0_data_i[8]" LOC = AM26 | IOSTANDARD = "LVCMOS25"; // LA23_N -NET "fmc_adc0_data_i[9]" LOC = AN24 | IOSTANDARD = "LVCMOS25"; // LA19_N -NET "fmc_adc0_data_i[10]" LOC = AJ25 | IOSTANDARD = "LVCMOS25"; // LA18_CC_N -NET "fmc_adc0_data_i[11]" LOC = AL26 | IOSTANDARD = "LVCMOS25"; // LA23_P -NET "fmc_adc0_data_i[12]" LOC = AL24 | IOSTANDARD = "LVCMOS25"; // LA20_N -NET "fmc_adc0_data_i[13]" LOC = AN25 | IOSTANDARD = "LVCMOS25"; // LA19_P -NET "fmc_adc0_data_i[14]" LOC = AH25 | IOSTANDARD = "LVCMOS25"; // LA18_CC_P -NET "fmc_adc0_data_i[15]" LOC = AK23 | IOSTANDARD = "LVCMOS25"; // LA20_P -NET "fmc_adc0_of_i" LOC = AL28 | IOSTANDARD = "LVCMOS25"; // LA29_P - -// ADC1 -NET "fmc_adc1_clk_i" LOC = V30 | IOSTANDARD = "LVCMOS25"; // HA17_CC_P - -NET "fmc_adc1_data_i[15]" LOC = AD34 | IOSTANDARD = "LVCMOS25"; // HA10_P -NET "fmc_adc1_data_i[14]" LOC = AG33 | IOSTANDARD = "LVCMOS25"; // HA11_P -NET "fmc_adc1_data_i[13]" LOC = AC34 | IOSTANDARD = "LVCMOS25"; // HA10_N -NET "fmc_adc1_data_i[12]" LOC = AG32 | IOSTANDARD = "LVCMOS25"; // HA11_N -NET "fmc_adc1_data_i[11]" LOC = AB32 | IOSTANDARD = "LVCMOS25"; // HA15_P -NET "fmc_adc1_data_i[10]" LOC = AA30 | IOSTANDARD = "LVCMOS25"; // HA14_P -NET "fmc_adc1_data_i[9]" LOC = AC32 | IOSTANDARD = "LVCMOS25"; // HA15_N -NET "fmc_adc1_data_i[8]" LOC = AA31 | IOSTANDARD = "LVCMOS25"; // HA14_N -NET "fmc_adc1_data_i[7]" LOC = T34 | IOSTANDARD = "LVCMOS25"; // HA18_N -NET "fmc_adc1_data_i[6]" LOC = T33 | IOSTANDARD = "LVCMOS25"; // HA18_P -NET "fmc_adc1_data_i[5]" LOC = U32 | IOSTANDARD = "LVCMOS25"; // HA19_N -NET "fmc_adc1_data_i[4]" LOC = U31 | IOSTANDARD = "LVCMOS25"; // HA21_P -NET "fmc_adc1_data_i[3]" LOC = U28 | IOSTANDARD = "LVCMOS25"; // HA22_P -NET "fmc_adc1_data_i[2]" LOC = U30 | IOSTANDARD = "LVCMOS25"; // HA21_N -NET "fmc_adc1_data_i[1]" LOC = U26 | IOSTANDARD = "LVCMOS25"; // HA23_P -NET "fmc_adc1_data_i[0]" LOC = V29 | IOSTANDARD = "LVCMOS25"; // HA22_N -NET "fmc_adc1_of_i" LOC = U27 | IOSTANDARD = "LVCMOS25"; // HA23_N - -// ADC2 -NET "fmc_adc2_clk_i" LOC = AF20 | IOSTANDARD = "LVCMOS25"; // LA00_CC_P - -NET "fmc_adc2_data_i[15]" LOC = AK19 | IOSTANDARD = "LVCMOS25"; // LA01_CC_P -NET "fmc_adc2_data_i[14]" LOC = AC20 | IOSTANDARD = "LVCMOS25"; // LA02_P -NET "fmc_adc2_data_i[13]" LOC = AL19 | IOSTANDARD = "LVCMOS25"; // LA01_CC_N -NET "fmc_adc2_data_i[12]" LOC = AD20 | IOSTANDARD = "LVCMOS25"; // LA02_N -NET "fmc_adc2_data_i[11]" LOC = AD19 | IOSTANDARD = "LVCMOS25"; // LA03_N -NET "fmc_adc2_data_i[10]" LOC = AC19 | IOSTANDARD = "LVCMOS25"; // LA03_P -NET "fmc_adc2_data_i[9]" LOC = AE19 | IOSTANDARD = "LVCMOS25"; // LA04_N -NET "fmc_adc2_data_i[8]" LOC = AF19 | IOSTANDARD = "LVCMOS25"; // LA04_P -NET "fmc_adc2_data_i[7]" LOC = AH22 | IOSTANDARD = "LVCMOS25"; // LA05_N -NET "fmc_adc2_data_i[6]" LOC = AG22 | IOSTANDARD = "LVCMOS25"; // LA05_P -NET "fmc_adc2_data_i[5]" LOC = AJ22 | IOSTANDARD = "LVCMOS25"; // LA08_N -NET "fmc_adc2_data_i[4]" LOC = AK22 | IOSTANDARD = "LVCMOS25"; // LA08_P -NET "fmc_adc2_data_i[3]" LOC = AJ21 | IOSTANDARD = "LVCMOS25"; // LA07_N -NET "fmc_adc2_data_i[2]" LOC = AK21 | IOSTANDARD = "LVCMOS25"; // LA07_P -NET "fmc_adc2_data_i[1]" LOC = AL21 | IOSTANDARD = "LVCMOS25"; // LA12_N -NET "fmc_adc2_data_i[0]" LOC = AM21 | IOSTANDARD = "LVCMOS25"; // LA12_P -NET "fmc_adc2_of_i" LOC = AM22 | IOSTANDARD = "LVCMOS25"; // LA11_P - -// ADC3 -NET "fmc_adc3_clk_i" LOC = AD29 | IOSTANDARD = "LVCMOS25"; // HA01_CC_P - -NET "fmc_adc3_data_i[15]" LOC = AF33 | IOSTANDARD = "LVCMOS25"; // HA00_CC_N -NET "fmc_adc3_data_i[14]" LOC = AE33 | IOSTANDARD = "LVCMOS25"; // HA00_CC_P -NET "fmc_adc3_data_i[13]" LOC = AC27 | IOSTANDARD = "LVCMOS25"; // HA05_N -NET "fmc_adc3_data_i[12]" LOC = AB27 | IOSTANDARD = "LVCMOS25"; // HA05_P -NET "fmc_adc3_data_i[11]" LOC = AC28 | IOSTANDARD = "LVCMOS25"; // HA04_N -NET "fmc_adc3_data_i[10]" LOC = AB28 | IOSTANDARD = "LVCMOS25"; // HA04_P -NET "fmc_adc3_data_i[9]" LOC = AB31 | IOSTANDARD = "LVCMOS25"; // HA09_N -NET "fmc_adc3_data_i[8]" LOC = AB30 | IOSTANDARD = "LVCMOS25"; // HA09_P -NET "fmc_adc3_data_i[7]" LOC = Y26 | IOSTANDARD = "LVCMOS25"; // HA03_N -NET "fmc_adc3_data_i[6]" LOC = AA25 | IOSTANDARD = "LVCMOS25"; // HA03_P -NET "fmc_adc3_data_i[5]" LOC = AG31 | IOSTANDARD = "LVCMOS25"; // HA08_P -NET "fmc_adc3_data_i[4]" LOC = AB25 | IOSTANDARD = "LVCMOS25"; // HA02_P -NET "fmc_adc3_data_i[3]" LOC = AA26 | IOSTANDARD = "LVCMOS25"; // HA07_P -NET "fmc_adc3_data_i[2]" LOC = AC25 | IOSTANDARD = "LVCMOS25"; // HA02_N -NET "fmc_adc3_data_i[1]" LOC = AA28 | IOSTANDARD = "LVCMOS25"; // HA06_P -NET "fmc_adc3_data_i[0]" LOC = AB26 | IOSTANDARD = "LVCMOS25"; // HA07_N -NET "fmc_adc3_of_i" LOC = AA29 | IOSTANDARD = "LVCMOS25"; // HA06_N - -####################################################################### -## Pinout and Related I/O Constraints ## -####################################################################### - -# On ML605 kit, all clock pins are assigned to MRCC pins. However, two of them -# (fmc_adc1_clk and fmc_adc3_clk) are located in the outer left/right column -# I/Os. These locations cannot connect to BUFG primitives, only inner (center) -# left/right column I/Os on the same half top/bottom can! -# -# For 7-series FPGAs there is no such impediment, apparently. - -####################################################################### -## DIFF TERM ## -####################################################################### - -NET "sys_clk_p_i" DIFF_TERM = TRUE; -NET "sys_clk_n_i" DIFF_TERM = TRUE; - -NET "fmc_trig_val_p_b" DIFF_TERM = TRUE; -NET "fmc_trig_val_n_b" DIFF_TERM = TRUE; - -#NET "fmc_fpga_clk_p_i" DIFF_TERM = TRUE; -#NET "fmc_fpga_clk_n_i" DIFF_TERM = TRUE; - -####################################################################### -## Timing constraints ## -####################################################################### - -# Overrides default_delay hdl parameter for the VARIABLE mode. -# For Virtex-6: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps -INST "*cmp_fmc_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 29; -INST "*cmp_fmc_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 31; -INST "*cmp_fmc_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 17; -INST "*cmp_fmc_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; - -# Overrides default_delay hdl parameter - INST "*cmp_fmc_adc_iface/gen_clock_chains[0].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0; - INST "*cmp_fmc_adc_iface/gen_clock_chains[1].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0; -# INST "*cmp_fmc_adc_iface/gen_clock_chains[2].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0; -# INST "*cmp_fmc_adc_iface/gen_clock_chains[3].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0; - -####################################################################### -## Clocks ## -####################################################################### - -# 200 MHz onboard input clock -NET "sys_clk_p_i" TNM_NET = "sys_clk_group"; -TIMESPEC "TS_sys_clk_group" = PERIOD "sys_clk_group" 5 ns HIGH 50%; - -# 100 MHz wihsbone clock -NET "clk_sys" TNM_NET = "clk_sys_group"; -TIMESPEC "TS_clk_sys_group" = PERIOD "clk_sys_group" 10 ns HIGH 50%; - -# 200 MHz DDR3 and IDELAY CONTROL clock -NET "clk_200mhz" TNM_NET = TNM_200mhz_sys_clk; -TIMESPEC "TS_200mhz_sys_clk" = PERIOD "TNM_200mhz_sys_clk" 5 ns HIGH 50%; - -# 200 MHz DDR3 UI Clock -NET "*/u_infrastructure/clk_pll" TNM_NET = "TNM_ddr_sys_clk"; -TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns HIGH 50%; -NET "clk_sys" TNM_NET = "TNM_clk_sys_group_ffs"; -TIMESPEC TS_clk_sys_to_ddr3_ui_clk = FROM "TNM_clk_sys_group_ffs" TO "TNM_ddr_sys_clk" 10 ns DATAPATHONLY; - -// real jitter is about 22ps peak-to-peak -NET "fmc_adc0_clk_i" TNM_NET = fmc_adc0_clk_i; -// TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -//TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc1_clk_i" TNM_NET = fmc_adc1_clk_i; -// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc2_clk_i" TNM_NET = fmc_adc2_clk_i; -// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc3_clk_i" TNM_NET = fmc_adc3_clk_i; -// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -//NET "fmc_fpga_clk_p" TNM_NET = fmc_fpga_clk_p; -//TIMESPEC TS_fmc_fpga_clk_p = PERIOD "fmc_fpga_clk_p" 130 MHz HIGH 50% INPUT_JITTER 40 ps; - -####################################################################### -## Data ## -####################################################################### - -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc0_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc1_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y2; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc2_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y0; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc3_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; // same as ADC1 - -// including 50ps jitter, for 130MHz clock -// since design uses copy of input ADC clock -// there is additional delay for clock/ data (tC) - -INST "fmc_adc0_data_i<*>" TNM = fmc_adc0_data_i; -INST "fmc_adc1_data_i<*>" TNM = fmc_adc1_data_i; -INST "fmc_adc2_data_i<*>" TNM = fmc_adc2_data_i; -INST "fmc_adc3_data_i<*>" TNM = fmc_adc3_data_i; - -TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc0_clk_i"; -TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc1_clk_i"; -TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc2_clk_i"; -TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc3_clk_i"; - -####################################################################### -## PCIe constraints ## -####################################################################### -# -CONFIG PART = xc6vlx240t-ff1156-1; - -#PCIe reset -NET "pcie_rst_n_i" IOSTANDARD = "LVCMOS25" | PULLUP | NODELAY; -NET "pcie_rst_n_i" TIG; -# Bank 16 VCCO - VADJ_FPGA - IO_25_16 -NET "pcie_rst_n_i" LOC = AE13; -#PCIe reset -#PCIe clock -NET "pcie_clk_n_i" LOC = P5; -# Bank 115 - MGTREFCLK1N_115 -NET "pcie_clk_p_i" LOC = P6; - -####################################################################### -## DDR controller ## -####################################################################### -NET "ddr3_dq_b[0]" LOC = "J11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[1]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[2]" LOC = "F13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[3]" LOC = "K11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[4]" LOC = "L11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[5]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[6]" LOC = "K12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[7]" LOC = "D11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[8]" LOC = "M13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[9]" LOC = "J14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[10]" LOC = "B13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[11]" LOC = "B12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[12]" LOC = "G10" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[13]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[14]" LOC = "C12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[15]" LOC = "A11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[16]" LOC = "G11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[17]" LOC = "F11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[18]" LOC = "D14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[19]" LOC = "C14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[20]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[21]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[23]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[24]" LOC = "C19" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[25]" LOC = "G20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[26]" LOC = "E19" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[27]" LOC = "F20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[28]" LOC = "A20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[29]" LOC = "A21" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[30]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[31]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[32]" LOC = "G21" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[33]" LOC = "B21" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[34]" LOC = "A23" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[35]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[36]" LOC = "C20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[37]" LOC = "D20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[38]" LOC = "J20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[39]" LOC = "G22" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[40]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[41]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[42]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[43]" LOC = "E26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[44]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[45]" LOC = "D25" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[46]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[47]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[48]" LOC = "C27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[49]" LOC = "B28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[50]" LOC = "D29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[51]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[52]" LOC = "G27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[53]" LOC = "A28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[54]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[55]" LOC = "G25" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[56]" LOC = "F28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[57]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[58]" LOC = "H29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[59]" LOC = "H28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[60]" LOC = "B30" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[61]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[62]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[63]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_addr_o[13]" LOC = "J15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[12]" LOC = "H15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[11]" LOC = "M15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[10]" LOC = "M16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[9]" LOC = "F15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[8]" LOC = "G15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[7]" LOC = "B15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[6]" LOC = "A15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[5]" LOC = "J17" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[4]" LOC = "D16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[3]" LOC = "E16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[2]" LOC = "B16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[1]" LOC = "A16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[0]" LOC = "L14" | IOSTANDARD = SSTL15 ; -NET "ddr3_ba_o[2]" LOC = "L15" | IOSTANDARD = SSTL15 ; -NET "ddr3_ba_o[1]" LOC = "J19" | IOSTANDARD = SSTL15 ; -NET "ddr3_ba_o[0]" LOC = "K19" | IOSTANDARD = SSTL15 ; -NET "ddr3_ras_n_o" LOC = "L19" | IOSTANDARD = SSTL15 ; -NET "ddr3_cas_n_o" LOC = "C17" | IOSTANDARD = SSTL15 ; -NET "ddr3_we_n_o" LOC = "B17" | IOSTANDARD = SSTL15 ; -NET "ddr3_reset_n_o" LOC = "E18" | IOSTANDARD = LVCMOS15 ; -NET "ddr3_cke_o[0]" LOC = "M18" | IOSTANDARD = SSTL15 ; -NET "ddr3_odt_o[0]" LOC = "F18" | IOSTANDARD = SSTL15 ; -NET "ddr3_cs_n_o[0]" LOC = "K18" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[0]" LOC = "E11" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[1]" LOC = "B11" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[2]" LOC = "E14" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[3]" LOC = "D19" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[4]" LOC = "B22" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[5]" LOC = "A26" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[6]" LOC = "A29" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[7]" LOC = "A31" | IOSTANDARD = SSTL15 ; -NET "ddr3_dqs_p_b[0]" LOC = "D12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[0]" LOC = "E12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[1]" LOC = "H12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[2]" LOC = "A13" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[2]" LOC = "A14" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[3]" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[3]" LOC = "H20" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[4]" LOC = "B23" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[4]" LOC = "C23" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[5]" LOC = "B25" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[5]" LOC = "A25" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[6]" LOC = "H27" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[6]" LOC = "G28" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[7]" LOC = "C30" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[7]" LOC = "D30" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_ck_p_o[0]" LOC = "G18" | IOSTANDARD = DIFF_SSTL15 ; -NET "ddr3_ck_n_o[0]" LOC = "H18" | IOSTANDARD = DIFF_SSTL15 ; -#NET "ddr_sys_clk_p_i" LOC = "J9" | IOSTANDARD = LVDS_25; -#NET "ddr_sys_clk_n_i" LOC = "H9" | IOSTANDARD = LVDS_25; - -####################################################################### -# Pinout and Related I/O Constraints -####################################################################### - -# -# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n -# signals are the PCI Express reference clock. Virtex-6 GT -# Transceiver architecture requires the use of a dedicated clock -# resources (FPGA input pins) associated with each GT Transceiver. -# To use these pins an IBUFDS primitive (refclk_ibuf) is -# instantiated in user's design. -# Please refer to the Virtex-6 GT Transceiver User Guide -# (UG) for guidelines regarding clock resource selection. -# - -INST "*/pcieclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6; - -# -# Transceiver instance placement. This constraint selects the -# transceivers to be used, which also dictates the pinout for the -# transmit and receive differential pairs. Please refer to the -# Virtex-6 GT Transceiver User Guide (UG) for more information. -# -# PCIe Lane 0 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX" LOC = GTXE1_X0Y15; -# PCIe Lane 1 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX" LOC = GTXE1_X0Y14; -# PCIe Lane 2 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX" LOC = GTXE1_X0Y13; -# PCIe Lane 3 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX" LOC = GTXE1_X0Y12; - -# -# PCI Express Block placement. This constraint selects the PCI Express -# Block to be used. -# -INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1; - - -# -# DDR controller component placement -# Check it after changing memory controller paramenters - -#-------------------------------- -#DCI_CASCADING -#Syntax : CONFIG DCI_CASCADE = " .."; -#-------------------------------- - -CONFIG DCI_CASCADE = "26 25";# -CONFIG DCI_CASCADE = "36 35";# - -#-------------------------------- -## The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must -## be a clock pin capable of spanning to all of the banks containing data bytes in the particular -## column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be -## used for other functions and should not be connected externally. If a different pin is chosen, -## he corresponding LOC constraint must also be changed. -#-------------------------------- -CONFIG PROHIBIT = C29,M12; - -#-------------------------------- -## The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock -## capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for -## this pin. This pin cannot be used for other functions and should not be connected externally. -## If a different pin is chosen, the corresponding LOC constraint must also be changed. -#-------------------------------- -CONFIG PROHIBIT = B20,C13,C28,D24,F21,F25,K14,L13; - -#-------------------------------- -#Place RSYNC OSERDES and IODELAYy -#-------------------------------- - -##Site: C29 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" - LOC = "OLOGIC_X1Y139"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" - LOC = "IODELAY_X1Y139"; - -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" - LOC = "BUFR_X1Y6"; - -##Site: M12 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" - LOC = "OLOGIC_X2Y139"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" - LOC = "IODELAY_X2Y139"; - -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" - LOC = "BUFR_X2Y6"; - -#-------------------------------- -# Place CPT OSERDES and IODELAY: -#-------------------------------- - -##Site: C13 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" - LOC = "OLOGIC_X2Y137"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" - LOC = "IODELAY_X2Y137"; - -##Site: L13 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" - LOC = "OLOGIC_X2Y141"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" - LOC = "IODELAY_X2Y141"; - -##Site: K14 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" - LOC = "OLOGIC_X2Y143"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" - LOC = "IODELAY_X2Y143"; - -##Site: F21 -- Bank 26 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" - LOC = "OLOGIC_X1Y179"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" - LOC = "IODELAY_X1Y179"; - -##Site: B20 -- Bank 26 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" - LOC = "OLOGIC_X1Y181"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" - LOC = "IODELAY_X1Y181"; - -##Site: F25 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" - LOC = "OLOGIC_X1Y137"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" - LOC = "IODELAY_X1Y137"; - -##Site: C28 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" - LOC = "OLOGIC_X1Y141"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" - LOC = "IODELAY_X1Y141"; - -##Site: D24 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" - LOC = "OLOGIC_X1Y143"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" - LOC = "IODELAY_X1Y143"; - -INST "*/u_infrastructure/u_mmcm_adv" LOC = "MMCM_ADV_X0Y8"; #Banks 16, 26, 36 - -####################################################################### -# Timing Constraints -####################################################################### - -NET "*/sys_clk_c" TNM_NET = "SYSCLK" ; -NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; -NET "*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG"; - -TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ; -TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1 ; -TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ; - - -PIN "*/trn_reset_n_int_i.CLR" TIG ; -PIN "*/trn_reset_n_i.CLR" TIG ; -PIN "*/pcie_clocking_i/mmcm_adv_i.RST" TIG ; - -INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7; - -#-------------------------------- -# DDR -#-------------------------------- - -# Constrain BUFR clocks used to synchronize data from IOB to fabric logic -# Note that ISE cannot infer this from other PERIOD constraints because -# of the use of OSERDES blocks in the BUFR clock generation path -NET "*/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync[?]" TNM_NET = TNM_clk_rsync; -TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5 ns; - -# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling -# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for -# that particular flop. Mark this path as being a full-cycle, rather than -# a half cycle path for timing purposes. NOTE: This constraint forces full- -# cycle timing to be applied globally for all rising->falling edge paths -# in all resynchronizaton clock domains. If the user had modified the logic -# in the resync clock domain such that other rising->falling edge paths -# exist, then constraint below should be modified to utilize pattern -# matching to specific affect only the DQ/DQS ISERDES.Q outputs -TIMEGRP "TG_clk_rsync_rise" = RISING "TNM_clk_rsync"; -TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync"; -TIMESPEC "TS_clk_rsync_rise_to_fall" = - FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" "TS_ddr_sys_clk" * 4; - -# Signal to select between controller and physical layer signals. Four divided by two clock -# cycles (4 memory clock cycles) are provided by design for the signal to settle down. -# Used only by the phy modules. -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL"; -TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_ddr_sys_clk"*8; - -####################################################################### -## Placement Constraints ## -####################################################################### - -#INST "*/cmp_wb_position_calc_core" AREA_GROUP = "GRP_position_core"; -#AREA_GROUP "GRP_position_core" RANGE = CLOCKREGION_X1Y1:CLOCKREGION_X1Y4; - -## Constrain the PCIe core elements placement, so that it won't fail -## timing analysis. -## Comment out because we use nonstandard GTP location -#INST "*/pcie_core_i" AREA_GROUP = "GRP_PCIE_CORE"; -#AREA_GROUP "GRP_PCIE_CORE" RANGE = CLOCKREGION_X0Y4; -# -## Place the DMA design not far from PCIe core, otherwise it also breaks timing -#INST "*/theTlpControl" AREA_GROUP = "GRP_tlpControl"; -#AREA_GROUP "GRP_tlpControl" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y4; diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd deleted file mode 100755 index 46440444..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd +++ /dev/null @@ -1,2391 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top DSP design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2013-09-01 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control of the DSP with --- FMC130M_4ch board -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2013-09-01 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Custom common cores -use work.ifc_common_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_generic_pkg.all; --- Ethernet MAC Modules and SDB structure -use work.ethmac_pkg.all; --- Wishbone Fabric interface -use work.wr_fabric_pkg.all; --- Etherbone slave core -use work.etherbone_pkg.all; --- FMC516 definitions -use work.fmc_adc_pkg.all; --- DSP definitions -use work.dsp_cores_pkg.all; --- BPM definitions -use work.bpm_cores_pkg.all; --- Genrams -use work.genram_pkg.all; --- Data Acquisition core -use work.acq_core_pkg.all; --- PCIe Core -use work.bpm_pcie_ml605_pkg.all; --- PCIe Core Constants -use work.bpm_pcie_ml605_const_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_dsp is -port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - rs232_txd_o : out std_logic; - rs232_rxd_i : in std_logic; - --uart_txd_o : out std_logic; - --uart_rxd_i : in std_logic; - - ----------------------------------------- - -- PHY pins - ----------------------------------------- - - -- Clock and resets to PHY (GMII). Not used in MII mode (10/100) - mgtx_clk_o : out std_logic; - mrstn_o : out std_logic; - - -- PHY TX - mtx_clk_pad_i : in std_logic; - mtxd_pad_o : out std_logic_vector(3 downto 0); - mtxen_pad_o : out std_logic; - mtxerr_pad_o : out std_logic; - - -- PHY RX - mrx_clk_pad_i : in std_logic; - mrxd_pad_i : in std_logic_vector(3 downto 0); - mrxdv_pad_i : in std_logic; - mrxerr_pad_i : in std_logic; - mcoll_pad_i : in std_logic; - mcrs_pad_i : in std_logic; - - -- MII - mdc_pad_o : out std_logic; - md_pad_b : inout std_logic; - - ----------------------------- - -- FMC130m_4ch ports - ----------------------------- - - -- ADC LTC2208 interface - fmc_adc_pga_o : out std_logic; - fmc_adc_shdn_o : out std_logic; - fmc_adc_dith_o : out std_logic; - fmc_adc_rand_o : out std_logic; - - -- ADC0 LTC2208 - fmc_adc0_clk_i : in std_logic; - fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc0_of_i : in std_logic; -- Unused - - -- ADC1 LTC2208 - fmc_adc1_clk_i : in std_logic; - fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc1_of_i : in std_logic; -- Unused - - -- ADC2 LTC2208 - fmc_adc2_clk_i : in std_logic; - fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc2_of_i : in std_logic; -- Unused - - -- ADC3 LTC2208 - fmc_adc3_clk_i : in std_logic; - fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc3_of_i : in std_logic; -- Unused - - -- FMC General Status - fmc_prsnt_i : in std_logic; - fmc_pg_m2c_i : in std_logic; - --fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board - - -- Trigger - fmc_trig_dir_o : out std_logic; - fmc_trig_term_o : out std_logic; - fmc_trig_val_p_b : inout std_logic; - fmc_trig_val_n_b : inout std_logic; - - -- Si571 clock gen - si571_scl_pad_b : inout std_logic; - si571_sda_pad_b : inout std_logic; - fmc_si571_oe_o : out std_logic; - - -- AD9510 clock distribution PLL - spi_ad9510_cs_o : out std_logic; - spi_ad9510_sclk_o : out std_logic; - spi_ad9510_mosi_o : out std_logic; - spi_ad9510_miso_i : in std_logic; - - fmc_pll_function_o : out std_logic; - fmc_pll_status_i : in std_logic; - - -- AD9510 clock copy - fmc_fpga_clk_p_i : in std_logic; - fmc_fpga_clk_n_i : in std_logic; - - -- Clock reference selection (TS3USB221) - fmc_clk_sel_o : out std_logic; - - -- EEPROM - eeprom_scl_pad_b : inout std_logic; - eeprom_sda_pad_b : inout std_logic; - - -- Temperature monitor (LM75AIMM) - lm75_scl_pad_b : inout std_logic; - lm75_sda_pad_b : inout std_logic; - - fmc_lm75_temp_alarm_i : in std_logic; - - -- FMC LEDs - fmc_led1_o : out std_logic; - fmc_led2_o : out std_logic; - fmc_led3_o : out std_logic; - - ----------------------------------------- - -- Position Calc signals - ----------------------------------------- - - -- Uncross signals - clk_swap_o : out std_logic; - clk_swap2x_o : out std_logic; - flag1_o : out std_logic; - flag2_o : out std_logic; - - ----------------------------------------- - -- General board status - ----------------------------------------- - fmc_mmcm_lock_led_o : out std_logic; - fmc_pll_status_led_o : out std_logic; - - ----------------------------------------- - -- PCIe pins - ----------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b : inout std_logic_vector(c_ddr_dq_width-1 downto 0); - ddr3_dqs_p_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0); - ddr3_dqs_n_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0); - ddr3_addr_o : out std_logic_vector(c_ddr_row_width-1 downto 0); - ddr3_ba_o : out std_logic_vector(c_ddr_bank_width-1 downto 0); - ddr3_cs_n_o : out std_logic_vector(0 downto 0); - ddr3_ras_n_o : out std_logic; - ddr3_cas_n_o : out std_logic; - ddr3_we_n_o : out std_logic; - ddr3_reset_n_o : out std_logic; - ddr3_ck_p_o : out std_logic_vector(c_ddr_ck_width-1 downto 0); - ddr3_ck_n_o : out std_logic_vector(c_ddr_ck_width-1 downto 0); - ddr3_cke_o : out std_logic_vector(c_ddr_cke_width-1 downto 0); - ddr3_dm_o : out std_logic_vector(c_ddr_dm_width-1 downto 0); - ddr3_odt_o : out std_logic_vector(c_ddr_odt_width-1 downto 0); - - -- PCIe transceivers - pci_exp_rxp_i : in std_logic_vector(c_pcie_lanes - 1 downto 0); - pci_exp_rxn_i : in std_logic_vector(c_pcie_lanes - 1 downto 0); - pci_exp_txp_o : out std_logic_vector(c_pcie_lanes - 1 downto 0); - pci_exp_txn_o : out std_logic_vector(c_pcie_lanes - 1 downto 0); - - -- PCI clock and reset signals - pcie_rst_n_i : in std_logic; - pcie_clk_p_i : in std_logic; - pcie_clk_n_i : in std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - --buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - leds_o : out std_logic_vector(7 downto 0) -); -end dbe_bpm_dsp; - -architecture rtl of dbe_bpm_dsp is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 11; - -- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC, - --Etherbone, FMC516, Peripherals - -- Number of masters - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon - constant c_masters : natural := 8; -- RS232-Syscon, PCIe - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone - - --constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB) - constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB) - --constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB) - --constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB) - constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB) - - constant c_acq_fifo_size : natural := 256; - - constant c_acq_addr_width : natural := c_ddr_addr_width; - constant c_acq_ddr_addr_res_width : natural := 32; - constant c_acq_ddr_addr_diff : natural := c_acq_ddr_addr_res_width-c_ddr_addr_width; - - constant c_acq_adc_id : natural := 0; - constant c_acq_tbt_amp_id : natural := 1; - constant c_acq_tbt_pos_id : natural := 2; - constant c_acq_fofb_amp_id : natural := 3; - constant c_acq_fofb_pos_id : natural := 4; - constant c_acq_monit_amp_id : natural := 5; - constant c_acq_monit_pos_id : natural := 6; - constant c_acq_monit_1_pos_id : natural := 7; - - - constant c_acq_pos_ddr3_width : natural := 32; - constant c_acq_num_channels : natural := 8; -- ADC + TBT AMP + TBT POS + - -- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT_1 POS - constant c_acq_channels : t_acq_chan_param_array(c_acq_num_channels-1 downto 0) := - ( c_acq_adc_id => (width => to_unsigned(64, c_acq_chan_max_w_log2)), - c_acq_tbt_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_tbt_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_fofb_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_fofb_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_monit_amp_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_monit_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_monit_1_pos_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)) - ); - - -- GPIO num pinscalc - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- TICs counter period. 100MHz clock -> msec granularity - constant c_tics_cntr_period : natural := 100000; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - -- number of the ADC reference clock used for all downstream - -- FPGA logic - constant c_adc_ref_clk : natural := 1; - - -- Number of top level clocks - constant c_num_tlvl_clks : natural := 2; -- CLK_SYS and CLK_200 MHz - constant c_clk_sys_id : natural := 0; -- CLK_SYS and CLK_200 MHz - constant c_clk_200mhz_id : natural := 1; -- CLK_SYS and CLK_200 MHz - - constant c_xwb_etherbone_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"0000000000000651", -- GSI - device_id => x"68202b22", - version => x"00000001", - date => x"20120912", - name => "GSI_ETHERBONE_CFG "))); - - constant c_xwb_ethmac_adapter_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"1000000000001215", -- LNLS - device_id => x"2ff9a28e", - version => x"00000001", - date => x"20130701", - name => "ETHMAC_ADAPTER "))); - - -- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure - -- no address overlaps will occur - --constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - -- FMC130m_4ch - constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - - -- Position CAlC. layout. Regs, SWAP - constant c_pos_calc_core_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000600"); - - -- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter - constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400"); - - -- WB SDB (Self describing bus) layout - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00100000"), -- Second port to the same memory - 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - x"00200000"), -- 64KB RAM - 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"00304000"), -- DMA control port - 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"00305000"), -- Ethernet MAC control port - 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"00306000"), -- Ethernet Adapter control port - 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"00307000"), -- Etherbone control port - 7 => f_sdb_embed_bridge(c_pos_calc_core_bridge_sdb, - x"00308000"), -- Position Calc Core control port - 8 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"00310000"), -- FMC130m_4ch control port - 9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"00320000"), -- General peripherals control port - 10 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"00330000") -- Data Acquisition control port - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well - constant c_sdb_address : t_wishbone_address := x"00300000"; - - -- FMC ADC data constants - constant c_adc_data_ch0_lsb : natural := 0; - constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb; - - constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1; - constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb; - - constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1; - constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb; - - constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1; - constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- PCIe signals - signal wb_ma_pcie_ack_in : std_logic; - signal wb_ma_pcie_dat_in : std_logic_vector(63 downto 0); - signal wb_ma_pcie_addr_out : std_logic_vector(28 downto 0); - signal wb_ma_pcie_dat_out : std_logic_vector(63 downto 0); - signal wb_ma_pcie_we_out : std_logic; - signal wb_ma_pcie_stb_out : std_logic; - signal wb_ma_pcie_sel_out : std_logic; - signal wb_ma_pcie_cyc_out : std_logic; - - signal wb_ma_pcie_rst : std_logic; - signal wb_ma_pcie_rstn : std_logic; - - signal wb_ma_sladp_pcie_ack_in : std_logic; - signal wb_ma_sladp_pcie_dat_in : std_logic_vector(31 downto 0); - signal wb_ma_sladp_pcie_addr_out : std_logic_vector(31 downto 0); - signal wb_ma_sladp_pcie_dat_out : std_logic_vector(31 downto 0); - signal wb_ma_sladp_pcie_we_out : std_logic; - signal wb_ma_sladp_pcie_stb_out : std_logic; - signal wb_ma_sladp_pcie_sel_out : std_logic_vector(3 downto 0); - signal wb_ma_sladp_pcie_cyc_out : std_logic; - - -- PCIe Debug signals - - signal dbg_app_addr : std_logic_vector(31 downto 0); - signal dbg_app_cmd : std_logic_vector(2 downto 0); - signal dbg_app_en : std_logic; - signal dbg_app_wdf_data : std_logic_vector(c_ddr_payload_width-1 downto 0); - signal dbg_app_wdf_end : std_logic; - signal dbg_app_wdf_wren : std_logic; - signal dbg_app_wdf_mask : std_logic_vector(c_ddr_payload_width/8-1 downto 0); - signal dbg_app_rd_data : std_logic_vector(c_ddr_payload_width-1 downto 0); - signal dbg_app_rd_data_end : std_logic; - signal dbg_app_rd_data_valid : std_logic; - signal dbg_app_rdy : std_logic; - signal dbg_app_wdf_rdy : std_logic; - signal dbg_ddr_ui_clk : std_logic; - signal dbg_ddr_ui_reset : std_logic; - - signal dbg_arb_req : std_logic_vector(1 downto 0); - signal dbg_arb_gnt : std_logic_vector(1 downto 0); - - -- To/From Acquisition Core - signal acq_chan_array : t_acq_chan_array(c_acq_num_channels-1 downto 0); - - signal bpm_acq_dpram_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0); - signal bpm_acq_dpram_valid : std_logic; - - signal bpm_acq_ext_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0); - signal bpm_acq_ext_valid : std_logic; - signal bpm_acq_ext_addr : std_logic_vector(c_acq_addr_width-1 downto 0); - signal bpm_acq_ext_sof : std_logic; - signal bpm_acq_ext_eof : std_logic; - signal bpm_acq_ext_dreq : std_logic; - signal bpm_acq_ext_stall : std_logic; - - signal memc_ui_clk : std_logic; - signal memc_ui_rst : std_logic; - signal memc_ui_rstn : std_logic; - signal memc_cmd_rdy : std_logic; - signal memc_cmd_en : std_logic; - signal memc_cmd_instr : std_logic_vector(2 downto 0); - signal memc_cmd_addr_resized : std_logic_vector(c_acq_ddr_addr_res_width-1 downto 0); - signal memc_cmd_addr : std_logic_vector(c_ddr_addr_width-1 downto 0); - signal memc_wr_en : std_logic; - signal memc_wr_end : std_logic; - signal memc_wr_mask : std_logic_vector(c_ddr_payload_width/8-1 downto 0); - signal memc_wr_data : std_logic_vector(c_ddr_payload_width-1 downto 0); - signal memc_wr_rdy : std_logic; - signal memc_rd_data : std_logic_vector(c_ddr_payload_width-1 downto 0); - signal memc_rd_valid : std_logic; - - signal dbg_ddr_rb_data : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0); - signal dbg_ddr_rb_addr : std_logic_vector(c_acq_addr_width-1 downto 0); - signal dbg_ddr_rb_valid : std_logic; - - -- memory arbiter interface - signal memarb_acc_req : std_logic; - signal memarb_acc_gnt : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - signal clk_200mhz_rst : std_logic; - signal clk_200mhz_rstn : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - -- "c_num_tlvl_clks" clocks - signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0); - signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0); - - signal rs232_rstn : std_logic; - signal fs_rstn : std_logic; - signal fs_rst2xn : std_logic; - - -- 200 Mhz clocck for iodelay_ctrl - signal clk_200mhz : std_logic; - - -- ADC clock - signal fs_clk : std_logic; - signal fs_clk2x : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - signal sys_clk_gen_bufg : std_logic; - - -- Ethernet MAC signals - signal ethmac_int : std_logic; - signal ethmac_md_in : std_logic; - signal ethmac_md_out : std_logic; - signal ethmac_md_oe : std_logic; - - signal mtxd_pad_int : std_logic_vector(3 downto 0); - signal mtxen_pad_int : std_logic; - signal mtxerr_pad_int : std_logic; - signal mdc_pad_int : std_logic; - - -- Ethrnet MAC adapter signals - signal irq_rx_done : std_logic; - signal irq_tx_done : std_logic; - - -- Etherbone signals - signal wb_ebone_out : t_wishbone_master_out; - signal wb_ebone_in : t_wishbone_master_in; - - signal eb_src_i : t_wrf_source_in; - signal eb_src_o : t_wrf_source_out; - signal eb_snk_i : t_wrf_sink_in; - signal eb_snk_o : t_wrf_sink_out; - - -- DMA signals - signal dma_int : std_logic; - - -- FMC130m_4ch Signals - signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0); - signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0); - - signal fmc_mmcm_lock_int : std_logic; - signal fmc_pll_status_int : std_logic; - - signal fmc_led1_int : std_logic; - signal fmc_led2_int : std_logic; - signal fmc_led3_int : std_logic; - - signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0); - signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal adc_data_ch0 : std_logic_vector(c_num_adc_bits-1 downto 0); - signal adc_data_ch1 : std_logic_vector(c_num_adc_bits-1 downto 0); - signal adc_data_ch2 : std_logic_vector(c_num_adc_bits-1 downto 0); - signal adc_data_ch3 : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal fmc_debug : std_logic; - signal reset_adc_counter : unsigned(6 downto 0) := (others => '0'); - signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_rst2x_n : std_logic_vector(c_num_adc_channels-1 downto 0); - - -- fmc130m_4ch Debug - signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0); - - -- Uncross signals - signal flag1_int : std_logic; - signal flag2_int : std_logic; - - -- DSP signals - signal dsp_kx : std_logic_vector(24 downto 0); - signal dsp_ky : std_logic_vector(24 downto 0); - signal dsp_ksum : std_logic_vector(24 downto 0); - - signal dsp_kx_in : std_logic_vector(24 downto 0); - signal dsp_ky_in : std_logic_vector(24 downto 0); - signal dsp_ksum_in : std_logic_vector(24 downto 0); - - signal dsp_del_sig_div_thres_sel : std_logic_vector(1 downto 0); - signal dsp_kx_sel : std_logic_vector(1 downto 0); - signal dsp_ky_sel : std_logic_vector(1 downto 0); - signal dsp_ksum_sel : std_logic_vector(1 downto 0); - - signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0); - signal dsp_del_sig_div_thres_in : std_logic_vector(25 downto 0); - - signal dsp_dds_config_valid_ch0 : std_logic; - signal dsp_dds_config_valid_ch1 : std_logic; - signal dsp_dds_config_valid_ch2 : std_logic; - signal dsp_dds_config_valid_ch3 : std_logic; - signal dsp_dds_pinc_ch0 : std_logic_vector(29 downto 0); - signal dsp_dds_pinc_ch1 : std_logic_vector(29 downto 0); - signal dsp_dds_pinc_ch2 : std_logic_vector(29 downto 0); - signal dsp_dds_pinc_ch3 : std_logic_vector(29 downto 0); - signal dsp_dds_poff_ch0 : std_logic_vector(29 downto 0); - signal dsp_dds_poff_ch1 : std_logic_vector(29 downto 0); - signal dsp_dds_poff_ch2 : std_logic_vector(29 downto 0); - signal dsp_dds_poff_ch3 : std_logic_vector(29 downto 0); - - signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_bpf_valid : std_logic; - - signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_mix_valid : std_logic; - - signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_poly35_valid : std_logic; - - signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_cic_fofb_valid : std_logic; - - signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_valid : std_logic; - - signal dsp_tbt_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_pha_valid : std_logic; - - signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_valid : std_logic; - - signal dsp_fofb_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_pha_valid : std_logic; - - signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_valid : std_logic; - - signal dsp_pos_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_tbt_valid : std_logic; - - signal dsp_pos_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_fofb_valid : std_logic; - - signal dsp_pos_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_monit_valid : std_logic; - - signal dsp_pos_x_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_y_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_q_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_sum_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_pos_monit_1_valid : std_logic; - - signal dsp_clk_ce_1 : std_logic; - signal dsp_clk_ce_2 : std_logic; - signal dsp_clk_ce_35 : std_logic; - signal dsp_clk_ce_70 : std_logic; - signal dsp_clk_ce_1390000 : std_logic; - signal dsp_clk_ce_1112 : std_logic; - signal dsp_clk_ce_2224 : std_logic; - signal dsp_clk_ce_11120000 : std_logic; - signal dsp_clk_ce_111200000 : std_logic; - signal dsp_clk_ce_22240000 : std_logic; - signal dsp_clk_ce_222400000 : std_logic; - signal dsp_clk_ce_5000 : std_logic; - signal dsp_clk_ce_556 : std_logic; - signal dsp_clk_ce_2780000 : std_logic; - signal dsp_clk_ce_5560000 : std_logic; - - signal dbg_cur_address : std_logic_vector(31 downto 0); - signal dbg_adc_ch0_cond : std_logic_vector(15 downto 0); - signal dbg_adc_ch1_cond : std_logic_vector(15 downto 0); - signal dbg_adc_ch2_cond : std_logic_vector(15 downto 0); - signal dbg_adc_ch3_cond : std_logic_vector(15 downto 0); - - -- DDS test - signal dds_data : std_logic_vector(2*c_num_adc_bits-1 downto 0); -- cosine + sine - signal dds_sine : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dds_cosine : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal synth_adc0 : std_logic_vector(c_num_adc_bits-1 downto 0); - signal synth_adc1 : std_logic_vector(c_num_adc_bits-1 downto 0); - signal synth_adc2 : std_logic_vector(c_num_adc_bits-1 downto 0); - signal synth_adc3 : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal synth_adc0_full : std_logic_vector(25 downto 0); - signal synth_adc1_full : std_logic_vector(25 downto 0); - signal synth_adc2_full : std_logic_vector(25 downto 0); - signal synth_adc3_full : std_logic_vector(25 downto 0); - - signal dds_sine_gain_ch0 : std_logic_vector(9 downto 0); - signal dds_sine_gain_ch1 : std_logic_vector(9 downto 0); - signal dds_sine_gain_ch2 : std_logic_vector(9 downto 0); - signal dds_sine_gain_ch3 : std_logic_vector(9 downto 0); - signal adc_synth_data_en : std_logic; - - signal clk_rffe_swap : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - signal buttons_dummy : std_logic_vector(7 downto 0) := (others => '0'); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - ---- Chipscope control signals - --signal CONTROL0 : std_logic_vector(35 downto 0); - --signal CONTROL1 : std_logic_vector(35 downto 0); - --signal CONTROL2 : std_logic_vector(35 downto 0); - --signal CONTROL3 : std_logic_vector(35 downto 0); - --signal CONTROL4 : std_logic_vector(35 downto 0); - --signal CONTROL5 : std_logic_vector(35 downto 0); - --signal CONTROL6 : std_logic_vector(35 downto 0); - --signal CONTROL7 : std_logic_vector(35 downto 0); - --signal CONTROL8 : std_logic_vector(35 downto 0); - --signal CONTROL9 : std_logic_vector(35 downto 0); - --signal CONTROL10 : std_logic_vector(35 downto 0); - --signal CONTROL11 : std_logic_vector(35 downto 0); - --signal CONTROL12 : std_logic_vector(35 downto 0); - - ---- Chipscope ILA 0 signals - --signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 1 signals - --signal TRIG_ILA1_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA1_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 2 signals - --signal TRIG_ILA2_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA2_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA2_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA2_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA2_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 3 signals - --signal TRIG_ILA3_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA3_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA3_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA3_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA3_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 4 signals - --signal TRIG_ILA4_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA4_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA4_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA4_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA4_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 5 signals - --signal TRIG_ILA5_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA5_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA5_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA5_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA5_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 6 signals - --signal TRIG_ILA6_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA6_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA6_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA6_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA6_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 7 signals - --signal TRIG_ILA7_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA7_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA7_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA7_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA7_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 8 signals - --signal TRIG_ILA8_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA8_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA8_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA8_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA8_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 9 signals - --signal TRIG_ILA9_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA9_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA9_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA9_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA9_4 : std_logic_vector(31 downto 0); - - ---- Chipscope ILA 10 signals - --signal TRIG_ILA10_0 : std_logic_vector(7 downto 0); - --signal TRIG_ILA10_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA10_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA10_3 : std_logic_vector(31 downto 0); - --signal TRIG_ILA10_4 : std_logic_vector(31 downto 0); - - ---- Chipscope VIO signals - --signal vio_out : std_logic_vector(255 downto 0); - --signal vio_out_dsp_config : std_logic_vector(255 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic; - sys_clk_bufg_o : out std_logic - ); - end component; - - -- Xilinx PLL - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - component multiplier_16x10_DSP - port ( - clk : in std_logic; - a : in std_logic_vector(15 downto 0); - b : in std_logic_vector(9 downto 0); - p : out std_logic_vector(25 downto 0) - ); - end component; - - component dds_adc_input - port ( - aclk : in std_logic; - m_axis_data_tvalid : out std_logic; - m_axis_data_tdata : out std_logic_vector(31 downto 0) - ); - end component; - - component chipscope_icon_13_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0); - CONTROL2 : inout std_logic_vector(35 downto 0); - CONTROL3 : inout std_logic_vector(35 downto 0); - CONTROL4 : inout std_logic_vector(35 downto 0); - CONTROL5 : inout std_logic_vector(35 downto 0); - CONTROL6 : inout std_logic_vector(35 downto 0); - CONTROL7 : inout std_logic_vector(35 downto 0); - CONTROL8 : inout std_logic_vector(35 downto 0); - CONTROL9 : inout std_logic_vector(35 downto 0); - CONTROL10 : inout std_logic_vector(35 downto 0); - CONTROL11 : inout std_logic_vector(35 downto 0); - CONTROL12 : inout std_logic_vector(35 downto 0) - ); - end component; - - component chipscope_ila - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(31 downto 0); - trig1 : in std_logic_vector(31 downto 0); - trig2 : in std_logic_vector(31 downto 0); - trig3 : in std_logic_vector(31 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila_1024_5_port - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(31 downto 0); - trig1 : in std_logic_vector(31 downto 0); - trig2 : in std_logic_vector(31 downto 0); - trig3 : in std_logic_vector(31 downto 0); - trig4 : in std_logic_vector(31 downto 0)); - end component; - - component chipscope_ila_8192_5_port - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(31 downto 0); - trig1 : in std_logic_vector(31 downto 0); - trig2 : in std_logic_vector(31 downto 0); - trig3 : in std_logic_vector(31 downto 0); - trig4 : in std_logic_vector(31 downto 0)); - end component; - - component chipscope_ila_1024 - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(7 downto 0); - trig1 : in std_logic_vector(31 downto 0); - trig2 : in std_logic_vector(31 downto 0); - trig3 : in std_logic_vector(31 downto 0); - trig4 : in std_logic_vector(31 downto 0)); - end component; - - component chipscope_ila_4096 - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(7 downto 0); - trig1 : in std_logic_vector(31 downto 0); - trig2 : in std_logic_vector(31 downto 0); - trig3 : in std_logic_vector(31 downto 0); - trig4 : in std_logic_vector(31 downto 0)); - end component; - - component chipscope_ila_65536 - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(7 downto 0); - trig1 : in std_logic_vector(31 downto 0); - trig2 : in std_logic_vector(31 downto 0); - trig3 : in std_logic_vector(31 downto 0); - trig4 : in std_logic_vector(31 downto 0)); - end component; - - component chipscope_ila_131072 - port ( - control : inout std_logic_vector(35 downto 0); - clk : in std_logic; - trig0 : in std_logic_vector(7 downto 0); - trig1 : in std_logic_vector(15 downto 0); - trig2 : in std_logic_vector(15 downto 0); - trig3 : in std_logic_vector(15 downto 0); - trig4 : in std_logic_vector(15 downto 0)); - end component; - - component chipscope_vio_256 is - port ( - control : inout std_logic_vector(35 downto 0); - async_out : out std_logic_vector(255 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; - -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen, - sys_clk_bufg_o => sys_clk_gen_bufg - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - clk_i => sys_clk_gen_bufg, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200 - ) - port map( - --free_clk_i => sys_clk_gen, - free_clk_i => sys_clk_gen_bufg, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(c_clk_sys_id) <= clk_sys; - reset_clks(c_clk_200mhz_id) <= clk_200mhz; - --clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n; - clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and - rs232_rstn;-- and wb_ma_pcie_rstn; - clk_sys_rst <= not clk_sys_rstn; - mrstn_o <= clk_sys_rstn; - clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id); - clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id)); - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => true, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - lm32_rstn <= clk_sys_rstn; - - --cmp_lm32 : xwb_lm32 - --generic map( - -- g_profile => "medium_icache_debug" - --) -- Including JTAG and I-cache (no divide) - --port map( - -- clk_sys_i => clk_sys, - -- rst_n_i => lm32_rstn, - -- irq_i => lm32_interrupt, - -- dwb_o => cbar_slave_i(0), -- Data bus - -- dwb_i => cbar_slave_o(0), - -- iwb_o => cbar_slave_i(1), -- Instruction bus - -- iwb_i => cbar_slave_o(1) - --); - - -- Interrupt '0' is Ethmac. - -- Interrupt '1' is DMA completion. - -- Interrupt '2' is Button(0). - -- Interrupt '3' is Ethernet Adapter RX completion. - -- Interrupt '4' is Ethernet Adapter TX completion. - -- Interrupts 31 downto 5 are disabled - - --lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done, - -- 4 => irq_tx_done, others => '0'); - - ---------------------------------- - -- PCIe Core -- - ---------------------------------- - - cmp_xwb_bpm_pcie_ml605 : xwb_bpm_pcie_ml605 - generic map ( - g_ma_interface_mode => PIPELINED, - g_ma_address_granularity => BYTE, - g_sim_bypass_init_cal => "OFF" - ) - port map ( - -- DDR3 memory pins - ddr3_dq_b => ddr3_dq_b, - ddr3_dqs_p_b => ddr3_dqs_p_b, - ddr3_dqs_n_b => ddr3_dqs_n_b, - ddr3_addr_o => ddr3_addr_o, - ddr3_ba_o => ddr3_ba_o, - ddr3_cs_n_o => ddr3_cs_n_o, - ddr3_ras_n_o => ddr3_ras_n_o, - ddr3_cas_n_o => ddr3_cas_n_o, - ddr3_we_n_o => ddr3_we_n_o, - ddr3_reset_n_o => ddr3_reset_n_o, - ddr3_ck_p_o => ddr3_ck_p_o, - ddr3_ck_n_o => ddr3_ck_n_o, - ddr3_cke_o => ddr3_cke_o, - ddr3_dm_o => ddr3_dm_o, - ddr3_odt_o => ddr3_odt_o, - - -- PCIe transceivers - pci_exp_rxp_i => pci_exp_rxp_i, - pci_exp_rxn_i => pci_exp_rxn_i, - pci_exp_txp_o => pci_exp_txp_o, - pci_exp_txn_o => pci_exp_txn_o, - - -- Necessity signals - ddr_clk_p_i => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL) - ddr_clk_n_i => '0', --200 MHz DDR core clock (connect through BUFG or PLL) - pcie_clk_p_i => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin) - pcie_clk_n_i => pcie_clk_n_i, --100 MHz PCIe Clock - pcie_rst_n_i => pcie_rst_n_i, -- PCIe core reset - - -- DDR memory controller interface -- - ddr_core_rst_i => clk_sys_rst, - memc_ui_clk_o => memc_ui_clk, - memc_ui_rst_o => memc_ui_rst, - memc_cmd_rdy_o => memc_cmd_rdy, - memc_cmd_en_i => memc_cmd_en, - memc_cmd_instr_i => memc_cmd_instr, - memc_cmd_addr_i => memc_cmd_addr_resized, - memc_wr_en_i => memc_wr_en, - memc_wr_end_i => memc_wr_end, - memc_wr_mask_i => memc_wr_mask, - memc_wr_data_i => memc_wr_data, - memc_wr_rdy_o => memc_wr_rdy, - memc_rd_data_o => memc_rd_data, - memc_rd_valid_o => memc_rd_valid, - ---- memory arbiter interface - memarb_acc_req_i => memarb_acc_req, - memarb_acc_gnt_o => memarb_acc_gnt, - - -- Wishbone interface -- - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - wb_ma_i => cbar_slave_o(0), - wb_ma_o => cbar_slave_i(0), - -- Additional exported signals for instantiation - wb_ma_pcie_rst_o => wb_ma_pcie_rst, - - -- Debug signals - dbg_app_addr_o => dbg_app_addr, - dbg_app_cmd_o => dbg_app_cmd, - dbg_app_en_o => dbg_app_en, - dbg_app_wdf_data_o => dbg_app_wdf_data, - dbg_app_wdf_end_o => dbg_app_wdf_end, - dbg_app_wdf_wren_o => dbg_app_wdf_wren, - dbg_app_wdf_mask_o => dbg_app_wdf_mask, - dbg_app_rd_data_o => dbg_app_rd_data, - dbg_app_rd_data_end_o => dbg_app_rd_data_end, - dbg_app_rd_data_valid_o => dbg_app_rd_data_valid, - dbg_app_rdy_o => dbg_app_rdy, - dbg_app_wdf_rdy_o => dbg_app_wdf_rdy, - dbg_ddr_ui_clk_o => dbg_ddr_ui_clk, - dbg_ddr_ui_reset_o => dbg_ddr_ui_reset, - - dbg_arb_req_o => dbg_arb_req, - dbg_arb_gnt_o => dbg_arb_gnt - ); - - wb_ma_pcie_rstn <= not wb_ma_pcie_rst; - - ---------------------------------- - -- RS232 Core -- - ---------------------------------- - cmp_xwb_rs232_syscon : xwb_rs232_syscon - generic map ( - g_ma_interface_mode => PIPELINED, - g_ma_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rstn_i => '1', -- No need for resetting the controller - - -- External ports - rs232_rxd_i => rs232_rxd_i, - rs232_txd_o => rs232_txd_o, - - -- Reset to FPGA logic - rstn_o => rs232_rstn, - - -- WISHBONE master - wb_master_i => cbar_slave_o(1), - wb_master_o => cbar_slave_i(1) - ); - - -- A DMA controller is master 2+3, slave 3, and interrupt 1 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(3), - slave_o => cbar_master_i(3), - r_master_i => cbar_slave_o(2), - r_master_o => cbar_slave_i(2), - w_master_i => cbar_slave_o(3), - w_master_o => cbar_slave_i(3), - interrupt_o => dma_int - ); - - -- Slave 0+1 is the RAM. Load a input file containing the embedded software - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - --g_init_file => "../../../embedded-sw/dbe.ram", - --"../../top/ml_605/dbe_bpm_simple/sw/main.ram", - --g_must_have_init_file => true, - g_must_have_init_file => false, - g_slave1_interface_mode => PIPELINED, - g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE, - g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - ); - - -- Slave 2 is the RAM Buffer for Ethernet MAC. - cmp_ethmac_buf_ram : xwb_dpram - generic map( - g_size => c_dpram_ethbuf_size, - g_init_file => "", - g_must_have_init_file => false, - g_slave1_interface_mode => CLASSIC, - --g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE - --g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(2), - slave1_o => cbar_master_i(2), - -- Second port connected to the crossbar - slave2_i => cc_dummy_slave_in, -- CYC always low - slave2_o => open - ); - - -- The Ethernet MAC is master 4, slave 4 - cmp_xwb_ethmac : xwb_ethmac - generic map ( - --g_ma_interface_mode => PIPELINED, - g_ma_interface_mode => CLASSIC, -- NOT used for now - --g_ma_address_granularity => WORD, - g_ma_address_granularity => BYTE, -- NOT used for now - g_sl_interface_mode => PIPELINED, - --g_sl_interface_mode => CLASSIC, - --g_sl_address_granularity => WORD - g_sl_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - - -- WISHBONE slave - wb_slave_in => cbar_master_o(4), - wb_slave_out => cbar_master_i(4), - - -- WISHBONE master - wb_master_in => cbar_slave_o(4), - wb_master_out => cbar_slave_i(4), - - -- PHY TX - mtx_clk_pad_i => mtx_clk_pad_i, - --mtxd_pad_o => mtxd_pad_o, - mtxd_pad_o => mtxd_pad_int, - --mtxen_pad_o => mtxen_pad_o, - mtxen_pad_o => mtxen_pad_int, - --mtxerr_pad_o => mtxerr_pad_o, - mtxerr_pad_o => mtxerr_pad_int, - - -- PHY RX - mrx_clk_pad_i => mrx_clk_pad_i, - mrxd_pad_i => mrxd_pad_i, - mrxdv_pad_i => mrxdv_pad_i, - mrxerr_pad_i => mrxerr_pad_i, - mcoll_pad_i => mcoll_pad_i, - mcrs_pad_i => mcrs_pad_i, - - -- MII - --mdc_pad_o => mdc_pad_o, - mdc_pad_o => mdc_pad_int, - md_pad_i => ethmac_md_in, - md_pad_o => ethmac_md_out, - md_padoe_o => ethmac_md_oe, - - -- Interrupt - int_o => ethmac_int - ); - - ---- Tri-state buffer for MII config - md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z'; - ethmac_md_in <= md_pad_b; - - mtxd_pad_o <= mtxd_pad_int; - mtxen_pad_o <= mtxen_pad_int; - mtxerr_pad_o <= mtxerr_pad_int; - mdc_pad_o <= mdc_pad_int; - - --The Ethernet MAC Adapter is master 5+6, slave 5 - cmp_xwb_ethmac_adapter : xwb_ethmac_adapter - port map( - clk_i => clk_sys, - rstn_i => clk_sys_rstn, - - wb_slave_o => cbar_master_i(5), - wb_slave_i => cbar_master_o(5), - - tx_ram_o => cbar_slave_i(5), - tx_ram_i => cbar_slave_o(5), - - rx_ram_o => cbar_slave_i(6), - rx_ram_i => cbar_slave_o(6), - - rx_eb_o => eb_snk_i, - rx_eb_i => eb_snk_o, - - tx_eb_o => eb_src_i, - tx_eb_i => eb_src_o, - - irq_tx_done_o => irq_tx_done, - irq_rx_done_o => irq_rx_done - ); - - -- The Etherbone is slave 6 - cmp_eb_slave_core : eb_slave_core - generic map( - g_sdb_address => x"00000000" & c_sdb_address - ) - port map - ( - clk_i => clk_sys, - nRst_i => clk_sys_rstn, - - -- EB streaming sink - snk_i => eb_snk_i, - snk_o => eb_snk_o, - - -- EB streaming source - src_i => eb_src_i, - src_o => eb_src_o, - - -- WB slave - Cfg IF - cfg_slave_o => cbar_master_i(6), - cfg_slave_i => cbar_master_o(6), - - -- WB master - Bus IF - master_o => wb_ebone_out, - master_i => wb_ebone_in - ); - - cbar_slave_i(7) <= wb_ebone_out; - wb_ebone_in <= cbar_slave_o(7); - - -- The FMC130M_4CH is slave 8 - cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch - generic map( - g_fpga_device => "VIRTEX6", - g_delay_type => "VAR_LOADABLE", - g_interface_mode => PIPELINED, - --g_address_granularity => WORD, - g_address_granularity => BYTE, - --g_adc_clk_period_values => default_adc_clk_period_values, - g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88), - --g_use_clk_chains => default_clk_use_chain, - -- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair) - -- using clock0 from fmc130m_4ch. - -- BUFIO can drive half-bank only, not the full IO bank - g_use_clk_chains => "1111", - g_with_bufio_clk_chains => "0000", - g_with_bufr_clk_chains => "1111", - g_use_data_chains => "1111", - --g_map_clk_data_chains => (-1,-1,-1,-1), - -- Clock 1 is the adc reference clock - g_ref_clk => c_adc_ref_clk, - g_packet_size => 32, - g_sim => 0 - ) - port map( - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - sys_clk_200Mhz_i => clk_200mhz, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(8), - wb_slv_o => cbar_master_i(8), - - ----------------------------- - -- External ports - ----------------------------- - - -- ADC LTC2208 interface - fmc_adc_pga_o => fmc_adc_pga_o, - fmc_adc_shdn_o => fmc_adc_shdn_o, - fmc_adc_dith_o => fmc_adc_dith_o, - fmc_adc_rand_o => fmc_adc_rand_o, - - -- ADC0 LTC2208 - fmc_adc0_clk_i => fmc_adc0_clk_i, - fmc_adc0_data_i => fmc_adc0_data_i, - fmc_adc0_of_i => fmc_adc0_of_i, - - -- ADC1 LTC2208 - fmc_adc1_clk_i => fmc_adc1_clk_i, - fmc_adc1_data_i => fmc_adc1_data_i, - fmc_adc1_of_i => fmc_adc1_of_i, - - -- ADC2 LTC2208 - fmc_adc2_clk_i => fmc_adc2_clk_i, - fmc_adc2_data_i => fmc_adc2_data_i, - fmc_adc2_of_i => fmc_adc2_of_i, - - -- ADC3 LTC2208 - fmc_adc3_clk_i => fmc_adc3_clk_i, - fmc_adc3_data_i => fmc_adc3_data_i, - fmc_adc3_of_i => fmc_adc3_of_i, - - -- FMC General Status - fmc_prsnt_i => fmc_prsnt_i, - fmc_pg_m2c_i => fmc_pg_m2c_i, - - -- Trigger - fmc_trig_dir_o => fmc_trig_dir_o, - fmc_trig_term_o => fmc_trig_term_o, - fmc_trig_val_p_b => fmc_trig_val_p_b, - fmc_trig_val_n_b => fmc_trig_val_n_b, - - -- Si571 clock gen - si571_scl_pad_b => si571_scl_pad_b, - si571_sda_pad_b => si571_sda_pad_b, - fmc_si571_oe_o => fmc_si571_oe_o, - - -- AD9510 clock distribution PLL - spi_ad9510_cs_o => spi_ad9510_cs_o, - spi_ad9510_sclk_o => spi_ad9510_sclk_o, - spi_ad9510_mosi_o => spi_ad9510_mosi_o, - spi_ad9510_miso_i => spi_ad9510_miso_i, - - fmc_pll_function_o => fmc_pll_function_o, - fmc_pll_status_i => fmc_pll_status_i, - - -- AD9510 clock copy - fmc_fpga_clk_p_i => fmc_fpga_clk_p_i, - fmc_fpga_clk_n_i => fmc_fpga_clk_n_i, - - -- Clock reference selection (TS3USB221) - fmc_clk_sel_o => fmc_clk_sel_o, - - -- EEPROM - eeprom_scl_pad_b => eeprom_scl_pad_b, - eeprom_sda_pad_b => eeprom_sda_pad_b, - - -- Temperature monitor - -- LM75AIMM - lm75_scl_pad_b => lm75_scl_pad_b, - lm75_sda_pad_b => lm75_sda_pad_b, - - fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i, - - -- FMC LEDs - fmc_led1_o => fmc_led1_int, - fmc_led2_o => fmc_led2_int, - fmc_led3_o => fmc_led3_int, - - ----------------------------- - -- Optional external reference clock ports - ----------------------------- - fmc_ext_ref_clk_i => '0', -- Unused - fmc_ext_ref_clk2x_i => '0', -- Unused - fmc_ext_ref_mmcm_locked_i => '0', -- Unused - - ----------------------------- - -- ADC output signals. Continuous flow - ----------------------------- - adc_clk_o => fmc_130m_4ch_clk, - adc_clk2x_o => fmc_130m_4ch_clk2x, - adc_rst_n_o => fmc_130m_4ch_rst_n, - adc_rst2x_n_o => fmc_130m_4ch_rst2x_n, - adc_data_o => fmc_130m_4ch_data, - adc_data_valid_o => fmc_130m_4ch_data_valid, - - ----------------------------- - -- General ADC output signals and status - ----------------------------- - -- Trigger to other FPGA logic - trig_hw_o => open, - trig_hw_i => '0', - - -- General board status - fmc_mmcm_lock_o => fmc_mmcm_lock_int, - fmc_pll_status_o => fmc_pll_status_int, - - ----------------------------- - -- Wishbone Streaming Interface Source - ----------------------------- - wbs_source_i => wbs_fmc130m_4ch_in_array, - wbs_source_o => wbs_fmc130m_4ch_out_array, - - adc_dly_debug_o => adc_dly_debug_int, - - fifo_debug_valid_o => fmc130m_4ch_debug_valid_int, - fifo_debug_full_o => fmc130m_4ch_debug_full_int, - fifo_debug_empty_o => fmc130m_4ch_debug_empty_int - ); - - gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate - wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in; - end generate; - - fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int; - fmc_pll_status_led_o <= fmc_pll_status_int; - - fmc_led1_o <= fmc_led1_int; - fmc_led2_o <= fmc_led2_int; - fmc_led3_o <= fmc_led3_int; - - adc_data_ch0 <= fmc_130m_4ch_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb); - adc_data_ch1 <= fmc_130m_4ch_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb); - adc_data_ch2 <= fmc_130m_4ch_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb); - adc_data_ch3 <= fmc_130m_4ch_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb); - - fs_clk <= fmc_130m_4ch_clk(c_adc_ref_clk); - fs_rstn <= fmc_130m_4ch_rst_n(c_adc_ref_clk); - fs_clk2x <= fmc_130m_4ch_clk2x(c_adc_ref_clk); - fs_rst2xn <= fmc_130m_4ch_rst2x_n(c_adc_ref_clk); - - --led_south_o <= fmc_led1_int; - --led_east_o <= fmc_led2_int; - --led_north_o <= fmc_led3_int; - - ---------------------------------------------------------------------- - -- DSP Chain Core -- - ---------------------------------------------------------------------- - - -- Testing with internal DDS - cmp_dds_adc_input : dds_adc_input - port map ( - aclk => fs_clk, - m_axis_data_tvalid => open, - m_axis_data_tdata => dds_data - ); - - dds_sine <= dds_data(31 downto 16); - dds_cosine <= dds_data(15 downto 0); - - cmp_multiplier_16x10_DSP_ch0 : multiplier_16x10_DSP - port map ( - clk => fs_clk, - a => dds_sine, - b => dds_sine_gain_ch0, - p => synth_adc0_full - ); - - synth_adc0 <= synth_adc0_full(25 downto 10); - - cmp_multiplier_16x10_DSP_ch1 : multiplier_16x10_DSP - port map( - clk => fs_clk, - a => dds_sine, - b => dds_sine_gain_ch1, - p => synth_adc1_full - ); - - synth_adc1 <= synth_adc1_full(25 downto 10); - - cmp_multiplier_16x10_DSP_ch2 : multiplier_16x10_DSP - port map( - clk => fs_clk, - a => dds_sine, - b => dds_sine_gain_ch2, - p => synth_adc2_full - ); - - synth_adc2 <= synth_adc2_full(25 downto 10); - - cmp_multiplier_16x10_DSP_ch3 : multiplier_16x10_DSP - port map ( - clk => fs_clk, - a => dds_sine, - b => dds_sine_gain_ch3, - p => synth_adc3_full - ); - - synth_adc3 <= synth_adc3_full(25 downto 10); - - -- MUX between sinthetic data and real ADC data - - adc_ch0_data <= synth_adc0 when adc_synth_data_en = '1' else adc_data_ch0; - adc_ch1_data <= synth_adc1 when adc_synth_data_en = '1' else adc_data_ch1; - adc_ch2_data <= synth_adc2 when adc_synth_data_en = '1' else adc_data_ch2; - adc_ch3_data <= synth_adc3 when adc_synth_data_en = '1' else adc_data_ch3; - - -- Position calc core is slave 7 - cmp_xwb_position_calc_core : xwb_position_calc_core - generic map ( - g_interface_mode => PIPELINED, - g_address_granularity => BYTE, - g_with_switching => 0 - ) - port map ( - rst_n_i => clk_sys_rstn, - clk_i => clk_sys, -- Wishbone clock - fs_rst_n_i => fs_rstn, - fs_rst2x_n_i => fs_rst2xn, - fs_clk_i => fs_clk, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz) - fs_clk2x_i => fs_clk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz) - - ----------------------------- - -- Wishbone signals - ----------------------------- - wb_slv_i => cbar_master_o(7), - wb_slv_o => cbar_master_i(7), - - ----------------------------- - -- Raw ADC signals - ----------------------------- - --adc_ch0_i => adc_ch0_data_uncross, - --adc_ch1_i => adc_ch1_data_uncross, - --adc_ch2_i => adc_ch2_data_uncross, - --adc_ch3_i => adc_ch3_data_uncross, - adc_ch0_i => adc_ch0_data, - adc_ch1_i => adc_ch1_data, - adc_ch2_i => adc_ch2_data, - adc_ch3_i => adc_ch3_data, - - ------------------------------- - ---- DSP config parameter signals - ------------------------------- - --kx_i => dsp_kx, - --ky_i => dsp_ky, - --ksum_i => dsp_ksum, - -- - --del_sig_div_fofb_thres_i => dsp_del_sig_div_thres, - --del_sig_div_tbt_thres_i => dsp_del_sig_div_thres, - --del_sig_div_monit_thres_i => dsp_del_sig_div_thres, - -- - --dds_config_valid_ch0_i => dsp_dds_config_valid_ch0, - --dds_config_valid_ch1_i => dsp_dds_config_valid_ch1, - --dds_config_valid_ch2_i => dsp_dds_config_valid_ch2, - --dds_config_valid_ch3_i => dsp_dds_config_valid_ch3, - --dds_pinc_ch0_i => dsp_dds_pinc_ch0, - --dds_pinc_ch1_i => dsp_dds_pinc_ch1, - --dds_pinc_ch2_i => dsp_dds_pinc_ch2, - --dds_pinc_ch3_i => dsp_dds_pinc_ch3, - --dds_poff_ch0_i => dsp_dds_poff_ch0, - --dds_poff_ch1_i => dsp_dds_poff_ch1, - --dds_poff_ch2_i => dsp_dds_poff_ch2, - --dds_poff_ch3_i => dsp_dds_poff_ch3, - - ----------------------------- - -- Position calculation at various rates - ----------------------------- - adc_ch0_dbg_data_o => dsp_adc_ch0_data, - adc_ch1_dbg_data_o => dsp_adc_ch1_data, - adc_ch2_dbg_data_o => dsp_adc_ch2_data, - adc_ch3_dbg_data_o => dsp_adc_ch3_data, - - bpf_ch0_o => dsp_bpf_ch0, - --bpf_ch1_o => out std_logic_vector(23 downto 0); - bpf_ch2_o => dsp_bpf_ch2, - --bpf_ch3_o => out std_logic_vector(23 downto 0); - bpf_valid_o => dsp_bpf_valid, - - mix_ch0_i_o => dsp_mix_ch0, - --mix_ch0_q_o => out std_logic_vector(23 downto 0); - --mix_ch1_i_o => out std_logic_vector(23 downto 0); - --mix_ch1_q_o => out std_logic_vector(23 downto 0); - mix_ch2_i_o => dsp_mix_ch2, - --mix_ch2_q_o => out std_logic_vector(23 downto 0); - --mix_ch3_i_o => out std_logic_vector(23 downto 0); - --mix_ch3_q_o => out std_logic_vector(23 downto 0); - mix_valid_o => dsp_mix_valid, - - tbt_decim_ch0_i_o => dsp_poly35_ch0, - --tbt_decim_ch0_i_o => open, - --poly35_ch0_q_o => out std_logic_vector(23 downto 0); - --poly35_ch1_i_o => out std_logic_vector(23 downto 0); - --poly35_ch1_q_o => out std_logic_vector(23 downto 0); - tbt_decim_ch2_i_o => dsp_poly35_ch2, - --tbt_decim_ch2_i_o => open, - --poly35_ch2_q_o => out std_logic_vector(23 downto 0); - --poly35_ch3_i_o => out std_logic_vector(23 downto 0); - --poly35_ch3_q_o => out std_logic_vector(23 downto 0); - tbt_decim_valid_o => dsp_poly35_valid, - - --tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect, - --tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect, - - tbt_amp_ch0_o => dsp_tbt_amp_ch0, - tbt_amp_ch1_o => dsp_tbt_amp_ch1, - tbt_amp_ch2_o => dsp_tbt_amp_ch2, - tbt_amp_ch3_o => dsp_tbt_amp_ch3, - tbt_amp_valid_o => dsp_tbt_amp_valid, - - tbt_pha_ch0_o => dsp_tbt_pha_ch0, - tbt_pha_ch1_o => dsp_tbt_pha_ch1, - tbt_pha_ch2_o => dsp_tbt_pha_ch2, - tbt_pha_ch3_o => dsp_tbt_pha_ch3, - tbt_pha_valid_o => dsp_tbt_pha_valid, - - fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0); - --cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0); - fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0); - --cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0); - fofb_decim_valid_o => dsp_cic_fofb_valid, - - fofb_amp_ch0_o => dsp_fofb_amp_ch0, - fofb_amp_ch1_o => dsp_fofb_amp_ch1, - fofb_amp_ch2_o => dsp_fofb_amp_ch2, - fofb_amp_ch3_o => dsp_fofb_amp_ch3, - fofb_amp_valid_o => dsp_fofb_amp_valid, - - fofb_pha_ch0_o => dsp_fofb_pha_ch0, - fofb_pha_ch1_o => dsp_fofb_pha_ch1, - fofb_pha_ch2_o => dsp_fofb_pha_ch2, - fofb_pha_ch3_o => dsp_fofb_pha_ch3, - fofb_pha_valid_o => dsp_fofb_pha_valid, - - monit_amp_ch0_o => dsp_monit_amp_ch0, - monit_amp_ch1_o => dsp_monit_amp_ch1, - monit_amp_ch2_o => dsp_monit_amp_ch2, - monit_amp_ch3_o => dsp_monit_amp_ch3, - monit_amp_valid_o => dsp_monit_amp_valid, - - pos_x_tbt_o => dsp_pos_x_tbt, - pos_y_tbt_o => dsp_pos_y_tbt, - pos_q_tbt_o => dsp_pos_q_tbt, - pos_sum_tbt_o => dsp_pos_sum_tbt, - pos_tbt_valid_o => dsp_pos_tbt_valid, - - pos_x_fofb_o => dsp_pos_x_fofb, - pos_y_fofb_o => dsp_pos_y_fofb, - pos_q_fofb_o => dsp_pos_q_fofb, - pos_sum_fofb_o => dsp_pos_sum_fofb, - pos_fofb_valid_o => dsp_pos_fofb_valid, - - pos_x_monit_o => dsp_pos_x_monit, - pos_y_monit_o => dsp_pos_y_monit, - pos_q_monit_o => dsp_pos_q_monit, - pos_sum_monit_o => dsp_pos_sum_monit, - pos_monit_valid_o => dsp_pos_monit_valid, - - pos_x_monit_1_o => dsp_pos_x_monit_1, - pos_y_monit_1_o => dsp_pos_y_monit_1, - pos_q_monit_1_o => dsp_pos_q_monit_1, - pos_sum_monit_1_o => dsp_pos_sum_monit_1, - pos_monit_1_valid_o => dsp_pos_monit_1_valid, - - ----------------------------- - -- Output to RFFE board - ----------------------------- - clk_swap_o => clk_rffe_swap, - flag1_o => flag1_int, - flag2_o => flag2_int, - ctrl1_o => open, - ctrl2_o => open, - - ----------------------------- - -- Clock drivers for various rates - ----------------------------- - clk_ce_1_o => dsp_clk_ce_1, - clk_ce_1112_o => dsp_clk_ce_1112, - clk_ce_11120000_o => dsp_clk_ce_11120000, - clk_ce_1390000_o => dsp_clk_ce_1390000, - clk_ce_2_o => dsp_clk_ce_2, - clk_ce_2224_o => dsp_clk_ce_2224, - clk_ce_22240000_o => dsp_clk_ce_22240000, - clk_ce_2780000_o => dsp_clk_ce_2780000, - clk_ce_35_o => dsp_clk_ce_35, - clk_ce_5000_o => dsp_clk_ce_5000, - clk_ce_556_o => dsp_clk_ce_556, - clk_ce_5560000_o => dsp_clk_ce_5560000, - clk_ce_70_o => dsp_clk_ce_70, - - dbg_cur_address_o => dbg_cur_address, - dbg_adc_ch0_cond_o => dbg_adc_ch0_cond, - dbg_adc_ch1_cond_o => dbg_adc_ch1_cond, - dbg_adc_ch2_cond_o => dbg_adc_ch2_cond, - dbg_adc_ch3_cond_o => dbg_adc_ch3_cond - ); - - flag1_o <= flag1_int; - flag2_o <= flag2_int; - -- There is no clk_swap2x_o, so we just output the same as clk_swap_o - clk_swap_o <= clk_rffe_swap; - clk_swap2x_o <= clk_rffe_swap; - - -- The board peripherals components is slave 9 - cmp_xwb_dbe_periph : xwb_dbe_periph - generic map( - -- NOT used! - --g_interface_mode : t_wishbone_interface_mode := CLASSIC; - -- NOT used! - --g_address_granularity : t_wishbone_address_granularity := WORD; - g_cntr_period => c_tics_cntr_period, - g_num_leds => c_leds_num_pins, - g_num_buttons => c_buttons_num_pins - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- UART - --uart_rxd_i => uart_rxd_i, - --uart_txd_o => uart_txd_o, - uart_rxd_i => '1', - uart_txd_o => open, - - -- LEDs - led_out_o => gpio_leds_int, - led_in_i => gpio_leds_int, - led_oen_o => open, - - -- Buttons - button_out_o => open, - --button_in_i => buttons_i, - button_in_i => buttons_dummy, - button_oen_o => open, - - -- Wishbone - slave_i => cbar_master_o(9), - slave_o => cbar_master_i(9) - ); - - leds_o <= gpio_leds_int; - - -------------------- - -- ADC data - -------------------- - acq_chan_array(c_acq_adc_id).val_low <= dsp_adc_ch3_data & - dsp_adc_ch2_data & - dsp_adc_ch1_data & - dsp_adc_ch0_data; - acq_chan_array(c_acq_adc_id).val_high <= (others => '0'); - acq_chan_array(c_acq_adc_id).dvalid <= '1'; - acq_chan_array(c_acq_adc_id).trig <= '0'; - - -------------------- - -- TBT AMP data - -------------------- - acq_chan_array(c_acq_tbt_amp_id).val_low <= std_logic_vector(resize(signed(dsp_tbt_amp_ch1), 32)) & - std_logic_vector(resize(signed(dsp_tbt_amp_ch0), 32)); - - acq_chan_array(c_acq_tbt_amp_id).val_high <= std_logic_vector(resize(signed(dsp_tbt_amp_ch3), 32)) & - std_logic_vector(resize(signed(dsp_tbt_amp_ch2), 32)); - - acq_chan_array(c_acq_tbt_amp_id).dvalid <= dsp_tbt_amp_valid; - acq_chan_array(c_acq_tbt_amp_id).trig <= '0'; - - -------------------- - -- TBT POS data - -------------------- - acq_chan_array(c_acq_tbt_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_tbt), 32)) & - std_logic_vector(resize(signed(dsp_pos_x_tbt), 32)); - - acq_chan_array(c_acq_tbt_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_tbt), 32)) & - std_logic_vector(resize(signed(dsp_pos_q_tbt), 32)); - - acq_chan_array(c_acq_tbt_pos_id).dvalid <= dsp_pos_tbt_valid; - acq_chan_array(c_acq_tbt_pos_id).trig <= '0'; - - -------------------- - -- FOFB AMP data - -------------------- - acq_chan_array(c_acq_fofb_amp_id).val_low <= std_logic_vector(resize(signed(dsp_fofb_amp_ch1), 32)) & - std_logic_vector(resize(signed(dsp_fofb_amp_ch0), 32)); - - acq_chan_array(c_acq_fofb_amp_id).val_high <= std_logic_vector(resize(signed(dsp_fofb_amp_ch3), 32)) & - std_logic_vector(resize(signed(dsp_fofb_amp_ch2), 32)); - - acq_chan_array(c_acq_fofb_amp_id).dvalid <= dsp_fofb_amp_valid; - acq_chan_array(c_acq_fofb_amp_id).trig <= '0'; - - -------------------- - -- FOFB POS data - -------------------- - acq_chan_array(c_acq_fofb_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_fofb), 32)) & - std_logic_vector(resize(signed(dsp_pos_x_fofb), 32)); - - acq_chan_array(c_acq_fofb_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_fofb), 32)) & - std_logic_vector(resize(signed(dsp_pos_q_fofb), 32)); - - acq_chan_array(c_acq_fofb_pos_id).dvalid <= dsp_pos_fofb_valid; - acq_chan_array(c_acq_fofb_pos_id).trig <= '0'; - - -------------------- - -- MONIT AMP data - -------------------- - acq_chan_array(c_acq_monit_amp_id).val_low <= std_logic_vector(resize(signed(dsp_monit_amp_ch1), 32)) & - std_logic_vector(resize(signed(dsp_monit_amp_ch0), 32)); - - acq_chan_array(c_acq_monit_amp_id).val_high <= std_logic_vector(resize(signed(dsp_monit_amp_ch3), 32)) & - std_logic_vector(resize(signed(dsp_monit_amp_ch2), 32)); - - acq_chan_array(c_acq_monit_amp_id).dvalid <= dsp_monit_amp_valid; - acq_chan_array(c_acq_monit_amp_id).trig <= '0'; - - -------------------- - -- MONIT POS data - -------------------- - acq_chan_array(c_acq_monit_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_monit), 32)) & - std_logic_vector(resize(signed(dsp_pos_x_monit), 32)); - - acq_chan_array(c_acq_monit_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_monit), 32)) & - std_logic_vector(resize(signed(dsp_pos_q_monit), 32)); - - acq_chan_array(c_acq_monit_pos_id).dvalid <= dsp_pos_monit_valid; - acq_chan_array(c_acq_monit_pos_id).trig <= '0'; - - -------------------- - -- MONIT1 POS data - -------------------- - acq_chan_array(c_acq_monit_1_pos_id).val_low <= std_logic_vector(resize(signed(dsp_pos_y_monit_1), 32)) & - std_logic_vector(resize(signed(dsp_pos_x_monit_1), 32)); - - acq_chan_array(c_acq_monit_1_pos_id).val_high <= std_logic_vector(resize(signed(dsp_pos_sum_monit_1), 32)) & - std_logic_vector(resize(signed(dsp_pos_q_monit_1), 32)); - - acq_chan_array(c_acq_monit_1_pos_id).dvalid <= dsp_pos_monit_1_valid; - acq_chan_array(c_acq_monit_1_pos_id).trig <= '0'; - - -- The xwb_acq_core is slave 9 - cmp_xwb_acq_core : xwb_acq_core - generic map - ( - g_interface_mode => PIPELINED, - g_address_granularity => BYTE, - g_acq_addr_width => c_acq_addr_width, - g_acq_num_channels => c_acq_num_channels, - g_acq_channels => c_acq_channels, - g_ddr_payload_width => c_ddr_payload_width, - g_ddr_dq_width => c_ddr_dq_width, - g_ddr_addr_width => c_ddr_addr_width, - --g_multishot_ram_size => 2048, - g_fifo_fc_size => c_acq_fifo_size -- avoid fifo overflow - --g_sim_readback => false - ) - port map - ( - fs_clk_i => fmc_130m_4ch_clk(c_adc_ref_clk), - fs_ce_i => '1', - fs_rst_n_i => fmc_130m_4ch_rst_n(c_adc_ref_clk), - - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - - -- From DDR3 Controller - ext_clk_i => memc_ui_clk, - ext_rst_n_i => memc_ui_rstn, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(10), - wb_slv_o => cbar_master_i(10), - - ----------------------------- - -- External Interface - ----------------------------- - acq_chan_array_i => acq_chan_array, - - ----------------------------- - -- DRRAM Interface - ----------------------------- - dpram_dout_o => bpm_acq_dpram_dout , -- to chipscope - dpram_valid_o => bpm_acq_dpram_valid, -- to chipscope - - ----------------------------- - -- External Interface (w/ FLow Control) - ----------------------------- - ext_dout_o => bpm_acq_ext_dout, -- to chipscope - ext_valid_o => bpm_acq_ext_valid, -- to chipscope - ext_addr_o => bpm_acq_ext_addr, -- to chipscope - ext_sof_o => bpm_acq_ext_sof, -- to chipscope - ext_eof_o => bpm_acq_ext_eof, -- to chipscope - ext_dreq_o => bpm_acq_ext_dreq, -- to chipscope - ext_stall_o => bpm_acq_ext_stall, -- to chipscope - - ----------------------------- - -- DDR3 SDRAM Interface - ----------------------------- - ui_app_addr_o => memc_cmd_addr, - ui_app_cmd_o => memc_cmd_instr, - ui_app_en_o => memc_cmd_en, - ui_app_rdy_i => memc_cmd_rdy, - - ui_app_wdf_data_o => memc_wr_data, - ui_app_wdf_end_o => memc_wr_end, - ui_app_wdf_mask_o => memc_wr_mask, - ui_app_wdf_wren_o => memc_wr_en, - ui_app_wdf_rdy_i => memc_wr_rdy, - - ui_app_rd_data_i => memc_rd_data, -- not used! - ui_app_rd_data_end_i => '0', -- not used! - ui_app_rd_data_valid_i => memc_rd_valid, -- not used! - - -- DDR3 arbitrer for multiple accesses - ui_app_req_o => memarb_acc_req, - ui_app_gnt_i => memarb_acc_gnt, - - ----------------------------- - -- Debug Interface - ----------------------------- - dbg_ddr_rb_data_o => dbg_ddr_rb_data, - dbg_ddr_rb_addr_o => dbg_ddr_rb_addr, - dbg_ddr_rb_valid_o => dbg_ddr_rb_valid - ); - - memc_ui_rstn <= not(memc_ui_rst); - - memc_cmd_addr_resized <= f_gen_std_logic_vector(c_acq_ddr_addr_diff, '0') & - memc_cmd_addr; - - ---- Chipscope Analysis - --cmp_chipscope_icon_13 : chipscope_icon_13_port - --port map ( - -- CONTROL0 => CONTROL0, - -- CONTROL1 => CONTROL1, - -- CONTROL2 => CONTROL2, - -- CONTROL3 => CONTROL3, - -- CONTROL4 => CONTROL4, - -- CONTROL5 => CONTROL5, - -- CONTROL6 => CONTROL6, - -- CONTROL7 => CONTROL7, - -- CONTROL8 => CONTROL8, - -- CONTROL9 => CONTROL9, - -- CONTROL10 => CONTROL10, - -- CONTROL11 => CONTROL11, - -- CONTROL12 => CONTROL12 - --); - - ----cmp_chipscope_ila_0_adc : chipscope_ila - --cmp_chipscope_ila_adc : chipscope_ila_8192_5_port - --port map ( - -- CONTROL => CONTROL0, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA0_0, - -- TRIG1 => TRIG_ILA0_1, - -- TRIG2 => TRIG_ILA0_2, - -- TRIG3 => TRIG_ILA0_3, - -- TRIG4 => TRIG_ILA0_4 - --); - - ---- ADC Data - --TRIG_ILA0_0 <= dsp_adc_ch1_data & dsp_adc_ch0_data; - --TRIG_ILA0_1 <= dsp_adc_ch3_data & dsp_adc_ch2_data; - - --TRIG_ILA0_2 <= dbg_adc_ch1_cond & dbg_adc_ch0_cond; - --TRIG_ILA0_3 <= dbg_adc_ch3_cond & dbg_adc_ch2_cond; - --TRIG_ILA0_4(dbg_cur_address'left downto 0) - -- <= dbg_cur_address; - - ---- Mix and BPF data - --cmp_chipscope_ila_1024_bpf_mix : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL1, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA1_0, - -- TRIG1 => TRIG_ILA1_1, - -- TRIG2 => TRIG_ILA1_2, - -- TRIG3 => TRIG_ILA1_3, - -- TRIG4 => TRIG_ILA1_4 - --); - - --TRIG_ILA1_0(0) <= dsp_bpf_valid; - --TRIG_ILA1_0(1) <= '0'; - --TRIG_ILA1_0(2) <= '0'; - --TRIG_ILA1_0(3) <= '0'; - --TRIG_ILA1_0(4) <= '0'; - --TRIG_ILA1_0(5) <= '0'; - --TRIG_ILA1_0(6) <= '0'; - - --TRIG_ILA1_1(dsp_bpf_ch0'left downto 0) <= dsp_bpf_ch0; - --TRIG_ILA1_2(dsp_bpf_ch2'left downto 0) <= dsp_bpf_ch2; - --TRIG_ILA1_3(dsp_mix_ch0'left downto 0) <= dsp_mix_ch0; - --TRIG_ILA1_4(dsp_mix_ch2'left downto 0) <= dsp_mix_ch2; - - ----TBT amplitudes data - --cmp_chipscope_ila_1024_tbt_amp : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL2, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA2_0, - -- TRIG1 => TRIG_ILA2_1, - -- TRIG2 => TRIG_ILA2_2, - -- TRIG3 => TRIG_ILA2_3, - -- TRIG4 => TRIG_ILA2_4 - --); - - --TRIG_ILA2_0(0) <= dsp_tbt_amp_valid; - --TRIG_ILA2_0(1) <= '0'; - --TRIG_ILA2_0(2) <= '0'; - --TRIG_ILA2_0(3) <= '0'; - --TRIG_ILA2_0(4) <= '0'; - --TRIG_ILA2_0(5) <= '0'; - --TRIG_ILA2_0(6) <= '0'; - - --TRIG_ILA2_1(dsp_tbt_amp_ch0'left downto 0) <= dsp_tbt_amp_ch0; - --TRIG_ILA2_2(dsp_tbt_amp_ch1'left downto 0) <= dsp_tbt_amp_ch1; - --TRIG_ILA2_3(dsp_tbt_amp_ch2'left downto 0) <= dsp_tbt_amp_ch2; - --TRIG_ILA2_4(dsp_tbt_amp_ch3'left downto 0) <= dsp_tbt_amp_ch3; - - ---- TBT position data - --cmp_chipscope_ila_1024_tbt_pos : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL3, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA3_0, - -- TRIG1 => TRIG_ILA3_1, - -- TRIG2 => TRIG_ILA3_2, - -- TRIG3 => TRIG_ILA3_3, - -- TRIG4 => TRIG_ILA3_4 - --); - - --TRIG_ILA3_0(0) <= dsp_pos_tbt_valid; - --TRIG_ILA3_0(1) <= '0'; - --TRIG_ILA3_0(2) <= '0'; - --TRIG_ILA3_0(3) <= '0'; - --TRIG_ILA3_0(4) <= '0'; - --TRIG_ILA3_0(5) <= '0'; - --TRIG_ILA3_0(6) <= '0'; - - --TRIG_ILA3_1(dsp_pos_x_tbt'left downto 0) <= dsp_pos_x_tbt; - --TRIG_ILA3_2(dsp_pos_y_tbt'left downto 0) <= dsp_pos_y_tbt; - --TRIG_ILA3_3(dsp_pos_q_tbt'left downto 0) <= dsp_pos_q_tbt; - --TRIG_ILA3_4(dsp_pos_sum_tbt'left downto 0) <= dsp_pos_sum_tbt; - - ---- FOFB amplitudes data - - --cmp_chipscope_ila_1024_fofb_amp : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL4, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA4_0, - -- TRIG1 => TRIG_ILA4_1, - -- TRIG2 => TRIG_ILA4_2, - -- TRIG3 => TRIG_ILA4_3, - -- TRIG4 => TRIG_ILA4_4 - --); - - --TRIG_ILA4_0(0) <= dsp_fofb_amp_valid; - --TRIG_ILA4_0(1) <= '0'; - --TRIG_ILA4_0(2) <= '0'; - --TRIG_ILA4_0(3) <= '0'; - --TRIG_ILA4_0(4) <= '0'; - --TRIG_ILA4_0(5) <= '0'; - --TRIG_ILA4_0(6) <= '0'; - - --TRIG_ILA4_1(dsp_fofb_amp_ch0'left downto 0) <= dsp_fofb_amp_ch0; - --TRIG_ILA4_2(dsp_fofb_amp_ch1'left downto 0) <= dsp_fofb_amp_ch1; - --TRIG_ILA4_3(dsp_fofb_amp_ch2'left downto 0) <= dsp_fofb_amp_ch2; - --TRIG_ILA4_4(dsp_fofb_amp_ch3'left downto 0) <= dsp_fofb_amp_ch3; - - ---- FOFB position data - --cmp_chipscope_ila_1024_fofb_pos : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL5, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA5_0, - -- TRIG1 => TRIG_ILA5_1, - -- TRIG2 => TRIG_ILA5_2, - -- TRIG3 => TRIG_ILA5_3, - -- TRIG4 => TRIG_ILA5_4 - --); - - --TRIG_ILA5_0(0) <= dsp_pos_fofb_valid; - --TRIG_ILA5_0(1) <= '0'; - --TRIG_ILA5_0(2) <= '0'; - --TRIG_ILA5_0(3) <= '0'; - --TRIG_ILA5_0(4) <= '0'; - --TRIG_ILA5_0(5) <= '0'; - --TRIG_ILA5_0(6) <= '0'; - - --TRIG_ILA5_1(dsp_pos_x_fofb'left downto 0) <= dsp_pos_x_fofb; - --TRIG_ILA5_2(dsp_pos_y_fofb'left downto 0) <= dsp_pos_y_fofb; - --TRIG_ILA5_3(dsp_pos_q_fofb'left downto 0) <= dsp_pos_q_fofb; - --TRIG_ILA5_4(dsp_pos_sum_fofb'left downto 0) <= dsp_pos_sum_fofb; - - ---- Monitoring position amplitude - --cmp_chipscope_ila_1024_monit_amp : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL6, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA6_0, - -- TRIG1 => TRIG_ILA6_1, - -- TRIG2 => TRIG_ILA6_2, - -- TRIG3 => TRIG_ILA6_3, - -- TRIG4 => TRIG_ILA6_4 - --); - - --TRIG_ILA6_0(0) <= dsp_monit_amp_valid; - --TRIG_ILA6_0(1) <= '0'; - --TRIG_ILA6_0(2) <= '0'; - --TRIG_ILA6_0(3) <= '0'; - --TRIG_ILA6_0(4) <= '0'; - --TRIG_ILA6_0(5) <= '0'; - --TRIG_ILA6_0(6) <= '0'; - - --TRIG_ILA6_1(dsp_monit_amp_ch0'left downto 0) <= dsp_monit_amp_ch0; - --TRIG_ILA6_2(dsp_monit_amp_ch1'left downto 0) <= dsp_monit_amp_ch1; - --TRIG_ILA6_3(dsp_monit_amp_ch2'left downto 0) <= dsp_monit_amp_ch2; - --TRIG_ILA6_4(dsp_monit_amp_ch3'left downto 0) <= dsp_monit_amp_ch3; - - ---- Monitoring position data - - ---- cmp_chipscope_ila_4096_monit_pos : chipscope_ila_4096 - --cmp_chipscope_ila_1024_monit_pos : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL7, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA7_0, - -- TRIG1 => TRIG_ILA7_1, - -- TRIG2 => TRIG_ILA7_2, - -- TRIG3 => TRIG_ILA7_3, - -- TRIG4 => TRIG_ILA7_4 - --); - - --TRIG_ILA7_0(0) <= dsp_pos_monit_valid; - --TRIG_ILA7_0(1) <= '0'; - --TRIG_ILA7_0(2) <= '0'; - --TRIG_ILA7_0(3) <= '0'; - --TRIG_ILA7_0(4) <= '0'; - --TRIG_ILA7_0(5) <= '0'; - --TRIG_ILA7_0(6) <= '0'; - - --TRIG_ILA7_1(dsp_pos_x_monit'left downto 0) <= dsp_pos_x_monit; - --TRIG_ILA7_2(dsp_pos_y_monit'left downto 0) <= dsp_pos_y_monit; - --TRIG_ILA7_3(dsp_pos_q_monit'left downto 0) <= dsp_pos_q_monit; - --TRIG_ILA7_4(dsp_pos_sum_monit'left downto 0) <= dsp_pos_sum_monit; - - ---- Monitoring 1 position data - --cmp_chipscope_ila_1024_monit_pos_1 : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL8, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA8_0, - -- TRIG1 => TRIG_ILA8_1, - -- TRIG2 => TRIG_ILA8_2, - -- TRIG3 => TRIG_ILA8_3, - -- TRIG4 => TRIG_ILA8_4 - --); - - --TRIG_ILA8_0(0) <= dsp_pos_monit_1_valid; - --TRIG_ILA8_0(1) <= '0'; - --TRIG_ILA8_0(2) <= '0'; - --TRIG_ILA8_0(3) <= '0'; - --TRIG_ILA8_0(4) <= '0'; - --TRIG_ILA8_0(5) <= '0'; - --TRIG_ILA8_0(6) <= '0'; - - --TRIG_ILA8_1(dsp_pos_x_monit_1'left downto 0) <= dsp_pos_x_monit_1; - --TRIG_ILA8_2(dsp_pos_y_monit_1'left downto 0) <= dsp_pos_y_monit_1; - --TRIG_ILA8_3(dsp_pos_q_monit_1'left downto 0) <= dsp_pos_q_monit_1; - --TRIG_ILA8_4(dsp_pos_sum_monit_1'left downto 0) <= dsp_pos_sum_monit_1; - - ---- TBT Phase data - --cmp_chipscope_ila_1024_tbt_pha : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL9, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA9_0, - -- TRIG1 => TRIG_ILA9_1, - -- TRIG2 => TRIG_ILA9_2, - -- TRIG3 => TRIG_ILA9_3, - -- TRIG4 => TRIG_ILA9_4 - --); - - --TRIG_ILA9_0(0) <= dsp_tbt_pha_valid; - --TRIG_ILA9_0(1) <= '0'; - --TRIG_ILA9_0(2) <= '0'; - --TRIG_ILA9_0(3) <= '0'; - --TRIG_ILA9_0(4) <= '0'; - --TRIG_ILA9_0(5) <= '0'; - --TRIG_ILA9_0(6) <= '0'; - - --TRIG_ILA9_1(dsp_tbt_pha_ch0'left downto 0) <= dsp_tbt_pha_ch0; - --TRIG_ILA9_2(dsp_tbt_pha_ch1'left downto 0) <= dsp_tbt_pha_ch1; - --TRIG_ILA9_3(dsp_tbt_pha_ch2'left downto 0) <= dsp_tbt_pha_ch2; - --TRIG_ILA9_4(dsp_tbt_pha_ch3'left downto 0) <= dsp_tbt_pha_ch3; - - ---- FOFB Phase data - --cmp_chipscope_ila_1024_fofb_pha : chipscope_ila_1024 - --port map ( - -- CONTROL => CONTROL10, - -- CLK => fs_clk, - -- TRIG0 => TRIG_ILA10_0, - -- TRIG1 => TRIG_ILA10_1, - -- TRIG2 => TRIG_ILA10_2, - -- TRIG3 => TRIG_ILA10_3, - -- TRIG4 => TRIG_ILA10_4 - --); - - --TRIG_ILA10_0(0) <= dsp_fofb_pha_valid; - --TRIG_ILA10_0(1) <= '0'; - --TRIG_ILA10_0(2) <= '0'; - --TRIG_ILA10_0(3) <= '0'; - --TRIG_ILA10_0(4) <= '0'; - --TRIG_ILA10_0(5) <= '0'; - --TRIG_ILA10_0(6) <= '0'; - - --TRIG_ILA10_1(dsp_fofb_pha_ch0'left downto 0) <= dsp_fofb_pha_ch0; - --TRIG_ILA10_2(dsp_fofb_pha_ch1'left downto 0) <= dsp_fofb_pha_ch1; - --TRIG_ILA10_3(dsp_fofb_pha_ch2'left downto 0) <= dsp_fofb_pha_ch2; - --TRIG_ILA10_4(dsp_fofb_pha_ch3'left downto 0) <= dsp_fofb_pha_ch3; - - ---- Controllable gain for test data - --cmp_chipscope_vio_256 : chipscope_vio_256 - --port map ( - -- CONTROL => CONTROL11, - -- ASYNC_OUT => vio_out - --); - - --dds_sine_gain_ch0 <= vio_out(10-1 downto 0); - --dds_sine_gain_ch1 <= vio_out(20-1 downto 10); - --dds_sine_gain_ch2 <= vio_out(30-1 downto 20); - --dds_sine_gain_ch3 <= vio_out(40-1 downto 30); - --adc_synth_data_en <= vio_out(40); - - ---- Controllable DDS frequency and phase - --cmp_chipscope_vio_256_dsp_config : chipscope_vio_256 - --port map ( - -- CONTROL => CONTROL12, - -- ASYNC_OUT => vio_out_dsp_config - --); - -end ; - diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xcf b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xcf deleted file mode 100644 index 622cfd43..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xcf +++ /dev/null @@ -1,28 +0,0 @@ - -NET "*/sys_clk_c" TNM_NET = "SYSCLK" ; -NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; - -TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 %; -TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25; - -MODEL ui_rd_data max_fanout = 20; - -BEGIN MODEL ui_wr_data -NET app_wdf_rdy_r max_fanout=20; -END; - -BEGIN MODEL ui_cmd -NET app_rdy_r max_fanout=20; -END; - -BEGIN MODEL phy_rdclk_gen -NET rst_oserdes max_fanout=10; -END; - -BEGIN MODEL phy_data_io -NET rst_r max_fanout=1; -END; - -BEGIN MODEL phy_control_io -NET rst_r max_fanout=1; -END; diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dsp_chipscope.cpj b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dsp_chipscope.cpj deleted file mode 100644 index 5900b186..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dsp_chipscope.cpj +++ /dev/null @@ -1,30265 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Mon Dec 16 09:35:12 BRST 2013 -avoidUserRegDevice1=2,3,4 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T 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39 40 41 42 43 44 45 46 47 -unit.1.0.port.-1.b.2.color=java.awt.Color[r\=153,g\=153,b\=255] -unit.1.0.port.-1.b.2.name=DataPort -unit.1.0.port.-1.b.2.orderindex=-1 -unit.1.0.port.-1.b.2.radix=Signed -unit.1.0.port.-1.b.2.signedOffset=0.0 -unit.1.0.port.-1.b.2.signedPrecision=0 -unit.1.0.port.-1.b.2.signedScaleFactor=1.0 -unit.1.0.port.-1.b.2.tokencount=0 -unit.1.0.port.-1.b.2.unsignedOffset=0.0 -unit.1.0.port.-1.b.2.unsignedPrecision=0 -unit.1.0.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.2.visible=1 -unit.1.0.port.-1.b.3.alias=adc_data_ch3 -unit.1.0.port.-1.b.3.channellist=48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.0.port.-1.b.3.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.0.port.-1.b.3.name=DataPort -unit.1.0.port.-1.b.3.orderindex=-1 -unit.1.0.port.-1.b.3.radix=Signed -unit.1.0.port.-1.b.3.signedOffset=0.0 -unit.1.0.port.-1.b.3.signedPrecision=0 -unit.1.0.port.-1.b.3.signedScaleFactor=1.0 -unit.1.0.port.-1.b.3.tokencount=0 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-unit.1.0.port.-1.s.70.orderindex=-1 -unit.1.0.port.-1.s.70.visible=1 -unit.1.0.port.-1.s.71.alias= -unit.1.0.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.71.name=DataPort[71] -unit.1.0.port.-1.s.71.orderindex=-1 -unit.1.0.port.-1.s.71.visible=1 -unit.1.0.port.-1.s.72.alias= -unit.1.0.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.72.name=DataPort[72] -unit.1.0.port.-1.s.72.orderindex=-1 -unit.1.0.port.-1.s.72.visible=1 -unit.1.0.port.-1.s.73.alias= -unit.1.0.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.73.name=DataPort[73] -unit.1.0.port.-1.s.73.orderindex=-1 -unit.1.0.port.-1.s.73.visible=1 -unit.1.0.port.-1.s.74.alias= -unit.1.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.74.name=DataPort[74] -unit.1.0.port.-1.s.74.orderindex=-1 -unit.1.0.port.-1.s.74.visible=1 -unit.1.0.port.-1.s.75.alias= -unit.1.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.75.name=DataPort[75] -unit.1.0.port.-1.s.75.orderindex=-1 -unit.1.0.port.-1.s.75.visible=1 -unit.1.0.port.-1.s.76.alias= -unit.1.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.76.name=DataPort[76] -unit.1.0.port.-1.s.76.orderindex=-1 -unit.1.0.port.-1.s.76.visible=1 -unit.1.0.port.-1.s.77.alias= -unit.1.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.77.name=DataPort[77] -unit.1.0.port.-1.s.77.orderindex=-1 -unit.1.0.port.-1.s.77.visible=1 -unit.1.0.port.-1.s.78.alias= -unit.1.0.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.78.name=DataPort[78] -unit.1.0.port.-1.s.78.orderindex=-1 -unit.1.0.port.-1.s.78.visible=1 -unit.1.0.port.-1.s.79.alias= -unit.1.0.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.79.name=DataPort[79] -unit.1.0.port.-1.s.79.orderindex=-1 -unit.1.0.port.-1.s.79.visible=1 -unit.1.0.port.-1.s.8.alias= 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-unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 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-unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 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-unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/D\:\\home\\lerwys\\Repos\\bpm-sw\\hdl\\top\\ml_605\\dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=adc_data -unit.1.0.waveform.count=4 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=adc_data_ch3 -unit.1.0.waveform.posn.0.radix=3 -unit.1.0.waveform.posn.0.type=bus -unit.1.0.waveform.posn.1.channel=2147483646 -unit.1.0.waveform.posn.1.name=adc_data_ch2 -unit.1.0.waveform.posn.1.radix=3 -unit.1.0.waveform.posn.1.type=bus -unit.1.0.waveform.posn.10.channel=2147483646 -unit.1.0.waveform.posn.10.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.10.radix=1 -unit.1.0.waveform.posn.10.type=bus -unit.1.0.waveform.posn.100.channel=127 -unit.1.0.waveform.posn.100.name=DataPort[127] -unit.1.0.waveform.posn.100.type=signal -unit.1.0.waveform.posn.101.channel=127 -unit.1.0.waveform.posn.101.name=DataPort[127] -unit.1.0.waveform.posn.101.type=signal -unit.1.0.waveform.posn.102.channel=127 -unit.1.0.waveform.posn.102.name=DataPort[127] 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-unit.1.0.waveform.posn.116.type=signal -unit.1.0.waveform.posn.117.channel=127 -unit.1.0.waveform.posn.117.name=DataPort[127] -unit.1.0.waveform.posn.117.type=signal -unit.1.0.waveform.posn.118.channel=127 -unit.1.0.waveform.posn.118.name=DataPort[127] -unit.1.0.waveform.posn.118.type=signal -unit.1.0.waveform.posn.119.channel=127 -unit.1.0.waveform.posn.119.name=DataPort[127] -unit.1.0.waveform.posn.119.type=signal -unit.1.0.waveform.posn.12.channel=2147483646 -unit.1.0.waveform.posn.12.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.12.radix=1 -unit.1.0.waveform.posn.12.type=bus -unit.1.0.waveform.posn.120.channel=127 -unit.1.0.waveform.posn.120.name=DataPort[127] -unit.1.0.waveform.posn.120.type=signal -unit.1.0.waveform.posn.121.channel=127 -unit.1.0.waveform.posn.121.name=DataPort[127] -unit.1.0.waveform.posn.121.type=signal -unit.1.0.waveform.posn.122.channel=127 -unit.1.0.waveform.posn.122.name=DataPort[127] -unit.1.0.waveform.posn.122.type=signal -unit.1.0.waveform.posn.123.channel=127 -unit.1.0.waveform.posn.123.name=DataP -unit.1.0.waveform.posn.13.channel=2147483646 -unit.1.0.waveform.posn.13.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.13.radix=1 -unit.1.0.waveform.posn.13.type=bus -unit.1.0.waveform.posn.2.channel=2147483646 -unit.1.0.waveform.posn.2.name=adc_data_ch1 -unit.1.0.waveform.posn.2.radix=3 -unit.1.0.waveform.posn.2.type=bus -unit.1.0.waveform.posn.3.channel=2147483646 -unit.1.0.waveform.posn.3.name=adc_data_ch0 -unit.1.0.waveform.posn.3.radix=3 -unit.1.0.waveform.posn.3.type=bus -unit.1.0.waveform.posn.4.channel=2147483646 -unit.1.0.waveform.posn.4.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.4.radix=1 -unit.1.0.waveform.posn.4.type=bus -unit.1.0.waveform.posn.5.channel=2147483646 -unit.1.0.waveform.posn.5.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.5.radix=1 -unit.1.0.waveform.posn.5.type=bus -unit.1.0.waveform.posn.6.channel=2147483646 -unit.1.0.waveform.posn.6.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.6.radix=1 -unit.1.0.waveform.posn.6.type=bus -unit.1.0.waveform.posn.7.channel=2147483646 -unit.1.0.waveform.posn.7.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.7.radix=1 -unit.1.0.waveform.posn.7.type=bus -unit.1.0.waveform.posn.8.channel=2147483646 -unit.1.0.waveform.posn.8.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.4027778 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.67616194 -unit.1.1.0.X0=0.036731634 -unit.1.1.0.Y0=0.0 -unit.1.1.1.HEIGHT1=0.77160496 -unit.1.1.1.WIDTH1=0.5442279 -unit.1.1.1.X1=0.25112444 -unit.1.1.1.Y1=0.5925926 -unit.1.1.5.HEIGHT5=0.9058642 -unit.1.1.5.WIDTH5=0.99550223 -unit.1.1.5.X5=0.0 -unit.1.1.5.Y5=0.0 -unit.1.1.MFBitsA0=1XXXXXXX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 -unit.1.1.MFBitsB2=00000000000000000000000000000000 -unit.1.1.MFBitsB3=00000000000000000000000000000000 -unit.1.1.MFBitsB4=00000000000000000000000000000000 -unit.1.1.MFCompareA0=0 -unit.1.1.MFCompareA1=0 -unit.1.1.MFCompareA2=0 -unit.1.1.MFCompareA3=0 -unit.1.1.MFCompareA4=0 -unit.1.1.MFCompareB0=999 -unit.1.1.MFCompareB1=999 -unit.1.1.MFCompareB2=999 -unit.1.1.MFCompareB3=999 -unit.1.1.MFCompareB4=999 -unit.1.1.MFCount=5 -unit.1.1.MFDisplay0=0 -unit.1.1.MFDisplay1=0 -unit.1.1.MFDisplay2=0 -unit.1.1.MFDisplay3=0 -unit.1.1.MFDisplay4=0 -unit.1.1.MFEventType0=3 -unit.1.1.MFEventType1=3 -unit.1.1.MFEventType2=3 -unit.1.1.MFEventType3=3 -unit.1.1.MFEventType4=3 -unit.1.1.RunMode=SINGLE RUN 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-unit.1.1.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.119.name=DataPort[119] -unit.1.1.port.-1.s.119.orderindex=-1 -unit.1.1.port.-1.s.119.visible=0 -unit.1.1.port.-1.s.12.alias= -unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=0 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=0 -unit.1.1.port.-1.s.121.alias= -unit.1.1.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.121.name=DataPort[121] -unit.1.1.port.-1.s.121.orderindex=-1 -unit.1.1.port.-1.s.121.visible=0 -unit.1.1.port.-1.s.122.alias= -unit.1.1.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.122.name=DataPort[122] -unit.1.1.port.-1.s.122.orderindex=-1 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-unit.1.1.port.-1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.27.name=DataPort[27] -unit.1.1.port.-1.s.27.orderindex=-1 -unit.1.1.port.-1.s.27.visible=0 -unit.1.1.port.-1.s.28.alias= -unit.1.1.port.-1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.28.name=DataPort[28] -unit.1.1.port.-1.s.28.orderindex=-1 -unit.1.1.port.-1.s.28.visible=0 -unit.1.1.port.-1.s.29.alias= -unit.1.1.port.-1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.29.name=DataPort[29] -unit.1.1.port.-1.s.29.orderindex=-1 -unit.1.1.port.-1.s.29.visible=0 -unit.1.1.port.-1.s.3.alias= -unit.1.1.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.3.name=DataPort[3] -unit.1.1.port.-1.s.3.orderindex=-1 -unit.1.1.port.-1.s.3.visible=1 -unit.1.1.port.-1.s.30.alias= -unit.1.1.port.-1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.30.name=DataPort[30] -unit.1.1.port.-1.s.30.orderindex=-1 -unit.1.1.port.-1.s.30.visible=0 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-unit.1.1.port.-1.s.88.name=DataPort[88] -unit.1.1.port.-1.s.88.orderindex=-1 -unit.1.1.port.-1.s.88.visible=0 -unit.1.1.port.-1.s.89.alias= -unit.1.1.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.89.name=DataPort[89] -unit.1.1.port.-1.s.89.orderindex=-1 -unit.1.1.port.-1.s.89.visible=0 -unit.1.1.port.-1.s.9.alias= -unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=0 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=0 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=0 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=0 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=0 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=0 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=8 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.port.4.b.0.alias= -unit.1.1.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.b.0.name=TriggerPort4 -unit.1.1.port.4.b.0.orderindex=-1 -unit.1.1.port.4.b.0.radix=Hex -unit.1.1.port.4.b.0.signedOffset=0.0 -unit.1.1.port.4.b.0.signedPrecision=0 -unit.1.1.port.4.b.0.signedScaleFactor=1.0 -unit.1.1.port.4.b.0.unsignedOffset=0.0 -unit.1.1.port.4.b.0.unsignedPrecision=0 -unit.1.1.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.4.b.0.visible=1 -unit.1.1.port.4.buscount=1 -unit.1.1.port.4.channelcount=32 -unit.1.1.port.4.s.0.alias= -unit.1.1.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.0.name=TriggerPort4[0] -unit.1.1.port.4.s.0.orderindex=-1 -unit.1.1.port.4.s.0.visible=1 -unit.1.1.port.4.s.1.alias= -unit.1.1.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.1.name=TriggerPort4[1] -unit.1.1.port.4.s.1.orderindex=-1 -unit.1.1.port.4.s.1.visible=1 -unit.1.1.port.4.s.10.alias= -unit.1.1.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.10.name=TriggerPort4[10] -unit.1.1.port.4.s.10.orderindex=-1 -unit.1.1.port.4.s.10.visible=1 -unit.1.1.port.4.s.11.alias= -unit.1.1.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.11.name=TriggerPort4[11] -unit.1.1.port.4.s.11.orderindex=-1 -unit.1.1.port.4.s.11.visible=1 -unit.1.1.port.4.s.12.alias= -unit.1.1.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.12.name=TriggerPort4[12] -unit.1.1.port.4.s.12.orderindex=-1 -unit.1.1.port.4.s.12.visible=1 -unit.1.1.port.4.s.13.alias= -unit.1.1.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.13.name=TriggerPort4[13] -unit.1.1.port.4.s.13.orderindex=-1 -unit.1.1.port.4.s.13.visible=1 -unit.1.1.port.4.s.14.alias= -unit.1.1.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.14.name=TriggerPort4[14] -unit.1.1.port.4.s.14.orderindex=-1 -unit.1.1.port.4.s.14.visible=1 -unit.1.1.port.4.s.15.alias= -unit.1.1.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.15.name=TriggerPort4[15] -unit.1.1.port.4.s.15.orderindex=-1 -unit.1.1.port.4.s.15.visible=1 -unit.1.1.port.4.s.16.alias= -unit.1.1.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.16.name=TriggerPort4[16] -unit.1.1.port.4.s.16.orderindex=-1 -unit.1.1.port.4.s.16.visible=1 -unit.1.1.port.4.s.17.alias= -unit.1.1.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.17.name=TriggerPort4[17] -unit.1.1.port.4.s.17.orderindex=-1 -unit.1.1.port.4.s.17.visible=1 -unit.1.1.port.4.s.18.alias= -unit.1.1.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.18.name=TriggerPort4[18] -unit.1.1.port.4.s.18.orderindex=-1 -unit.1.1.port.4.s.18.visible=1 -unit.1.1.port.4.s.19.alias= -unit.1.1.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.19.name=TriggerPort4[19] -unit.1.1.port.4.s.19.orderindex=-1 -unit.1.1.port.4.s.19.visible=1 -unit.1.1.port.4.s.2.alias= -unit.1.1.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.2.name=TriggerPort4[2] -unit.1.1.port.4.s.2.orderindex=-1 -unit.1.1.port.4.s.2.visible=1 -unit.1.1.port.4.s.20.alias= -unit.1.1.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.20.name=TriggerPort4[20] -unit.1.1.port.4.s.20.orderindex=-1 -unit.1.1.port.4.s.20.visible=1 -unit.1.1.port.4.s.21.alias= -unit.1.1.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.21.name=TriggerPort4[21] -unit.1.1.port.4.s.21.orderindex=-1 -unit.1.1.port.4.s.21.visible=1 -unit.1.1.port.4.s.22.alias= -unit.1.1.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.22.name=TriggerPort4[22] -unit.1.1.port.4.s.22.orderindex=-1 -unit.1.1.port.4.s.22.visible=1 -unit.1.1.port.4.s.23.alias= -unit.1.1.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.23.name=TriggerPort4[23] -unit.1.1.port.4.s.23.orderindex=-1 -unit.1.1.port.4.s.23.visible=1 -unit.1.1.port.4.s.24.alias= -unit.1.1.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.24.name=TriggerPort4[24] -unit.1.1.port.4.s.24.orderindex=-1 -unit.1.1.port.4.s.24.visible=1 -unit.1.1.port.4.s.25.alias= -unit.1.1.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.25.name=TriggerPort4[25] -unit.1.1.port.4.s.25.orderindex=-1 -unit.1.1.port.4.s.25.visible=1 -unit.1.1.port.4.s.26.alias= -unit.1.1.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.26.name=TriggerPort4[26] -unit.1.1.port.4.s.26.orderindex=-1 -unit.1.1.port.4.s.26.visible=1 -unit.1.1.port.4.s.27.alias= -unit.1.1.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.27.name=TriggerPort4[27] -unit.1.1.port.4.s.27.orderindex=-1 -unit.1.1.port.4.s.27.visible=1 -unit.1.1.port.4.s.28.alias= -unit.1.1.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.28.name=TriggerPort4[28] -unit.1.1.port.4.s.28.orderindex=-1 -unit.1.1.port.4.s.28.visible=1 -unit.1.1.port.4.s.29.alias= -unit.1.1.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.29.name=TriggerPort4[29] -unit.1.1.port.4.s.29.orderindex=-1 -unit.1.1.port.4.s.29.visible=1 -unit.1.1.port.4.s.3.alias= -unit.1.1.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.3.name=TriggerPort4[3] -unit.1.1.port.4.s.3.orderindex=-1 -unit.1.1.port.4.s.3.visible=1 -unit.1.1.port.4.s.30.alias= -unit.1.1.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.30.name=TriggerPort4[30] -unit.1.1.port.4.s.30.orderindex=-1 -unit.1.1.port.4.s.30.visible=1 -unit.1.1.port.4.s.31.alias= -unit.1.1.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.31.name=TriggerPort4[31] -unit.1.1.port.4.s.31.orderindex=-1 -unit.1.1.port.4.s.31.visible=1 -unit.1.1.port.4.s.4.alias= -unit.1.1.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.4.name=TriggerPort4[4] -unit.1.1.port.4.s.4.orderindex=-1 -unit.1.1.port.4.s.4.visible=1 -unit.1.1.port.4.s.5.alias= -unit.1.1.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.5.name=TriggerPort4[5] -unit.1.1.port.4.s.5.orderindex=-1 -unit.1.1.port.4.s.5.visible=1 -unit.1.1.port.4.s.6.alias= -unit.1.1.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.6.name=TriggerPort4[6] -unit.1.1.port.4.s.6.orderindex=-1 -unit.1.1.port.4.s.6.visible=1 -unit.1.1.port.4.s.7.alias= -unit.1.1.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.7.name=TriggerPort4[7] -unit.1.1.port.4.s.7.orderindex=-1 -unit.1.1.port.4.s.7.visible=1 -unit.1.1.port.4.s.8.alias= -unit.1.1.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.8.name=TriggerPort4[8] -unit.1.1.port.4.s.8.orderindex=-1 -unit.1.1.port.4.s.8.visible=1 -unit.1.1.port.4.s.9.alias= -unit.1.1.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.9.name=TriggerPort4[9] -unit.1.1.port.4.s.9.orderindex=-1 -unit.1.1.port.4.s.9.visible=1 -unit.1.1.portcount=5 -unit.1.1.rep_trigger.clobber=1 -unit.1.1.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/D\:\\home\\lerwys\\Repos\\bpm-sw\\hdl\\top\\ml_605\\dbe_bpm_fmc516 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-unit.1.10.port.0.buscount=1 -unit.1.10.port.0.channelcount=8 -unit.1.10.port.0.s.0.alias= -unit.1.10.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.0.name=TriggerPort0[0] -unit.1.10.port.0.s.0.orderindex=-1 -unit.1.10.port.0.s.0.visible=1 -unit.1.10.port.0.s.1.alias= -unit.1.10.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.1.name=TriggerPort0[1] -unit.1.10.port.0.s.1.orderindex=-1 -unit.1.10.port.0.s.1.visible=1 -unit.1.10.port.0.s.2.alias= -unit.1.10.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.2.name=TriggerPort0[2] -unit.1.10.port.0.s.2.orderindex=-1 -unit.1.10.port.0.s.2.visible=1 -unit.1.10.port.0.s.3.alias= -unit.1.10.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.3.name=TriggerPort0[3] -unit.1.10.port.0.s.3.orderindex=-1 -unit.1.10.port.0.s.3.visible=1 -unit.1.10.port.0.s.4.alias= -unit.1.10.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.4.name=TriggerPort0[4] -unit.1.10.port.0.s.4.orderindex=-1 -unit.1.10.port.0.s.4.visible=1 -unit.1.10.port.0.s.5.alias= -unit.1.10.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.5.name=TriggerPort0[5] -unit.1.10.port.0.s.5.orderindex=-1 -unit.1.10.port.0.s.5.visible=1 -unit.1.10.port.0.s.6.alias= -unit.1.10.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.6.name=TriggerPort0[6] -unit.1.10.port.0.s.6.orderindex=-1 -unit.1.10.port.0.s.6.visible=1 -unit.1.10.port.0.s.7.alias= -unit.1.10.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.0.s.7.name=TriggerPort0[7] -unit.1.10.port.0.s.7.orderindex=-1 -unit.1.10.port.0.s.7.visible=1 -unit.1.10.port.1.b.0.alias= -unit.1.10.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.b.0.name=TriggerPort1 -unit.1.10.port.1.b.0.orderindex=-1 -unit.1.10.port.1.b.0.radix=Hex -unit.1.10.port.1.b.0.signedOffset=0.0 -unit.1.10.port.1.b.0.signedPrecision=0 -unit.1.10.port.1.b.0.signedScaleFactor=1.0 -unit.1.10.port.1.b.0.unsignedOffset=0.0 -unit.1.10.port.1.b.0.unsignedPrecision=0 -unit.1.10.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.1.b.0.visible=1 -unit.1.10.port.1.buscount=1 -unit.1.10.port.1.channelcount=32 -unit.1.10.port.1.s.0.alias= -unit.1.10.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.0.name=TriggerPort1[0] -unit.1.10.port.1.s.0.orderindex=-1 -unit.1.10.port.1.s.0.visible=1 -unit.1.10.port.1.s.1.alias= -unit.1.10.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.1.name=TriggerPort1[1] -unit.1.10.port.1.s.1.orderindex=-1 -unit.1.10.port.1.s.1.visible=1 -unit.1.10.port.1.s.10.alias= -unit.1.10.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.10.name=TriggerPort1[10] -unit.1.10.port.1.s.10.orderindex=-1 -unit.1.10.port.1.s.10.visible=1 -unit.1.10.port.1.s.11.alias= -unit.1.10.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.11.name=TriggerPort1[11] -unit.1.10.port.1.s.11.orderindex=-1 -unit.1.10.port.1.s.11.visible=1 -unit.1.10.port.1.s.12.alias= -unit.1.10.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.12.name=TriggerPort1[12] -unit.1.10.port.1.s.12.orderindex=-1 -unit.1.10.port.1.s.12.visible=1 -unit.1.10.port.1.s.13.alias= -unit.1.10.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.13.name=TriggerPort1[13] -unit.1.10.port.1.s.13.orderindex=-1 -unit.1.10.port.1.s.13.visible=1 -unit.1.10.port.1.s.14.alias= -unit.1.10.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.14.name=TriggerPort1[14] -unit.1.10.port.1.s.14.orderindex=-1 -unit.1.10.port.1.s.14.visible=1 -unit.1.10.port.1.s.15.alias= -unit.1.10.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.15.name=TriggerPort1[15] -unit.1.10.port.1.s.15.orderindex=-1 -unit.1.10.port.1.s.15.visible=1 -unit.1.10.port.1.s.16.alias= -unit.1.10.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.16.name=TriggerPort1[16] -unit.1.10.port.1.s.16.orderindex=-1 -unit.1.10.port.1.s.16.visible=1 -unit.1.10.port.1.s.17.alias= -unit.1.10.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.17.name=TriggerPort1[17] -unit.1.10.port.1.s.17.orderindex=-1 -unit.1.10.port.1.s.17.visible=1 -unit.1.10.port.1.s.18.alias= -unit.1.10.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.18.name=TriggerPort1[18] -unit.1.10.port.1.s.18.orderindex=-1 -unit.1.10.port.1.s.18.visible=1 -unit.1.10.port.1.s.19.alias= -unit.1.10.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.19.name=TriggerPort1[19] -unit.1.10.port.1.s.19.orderindex=-1 -unit.1.10.port.1.s.19.visible=1 -unit.1.10.port.1.s.2.alias= -unit.1.10.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.2.name=TriggerPort1[2] -unit.1.10.port.1.s.2.orderindex=-1 -unit.1.10.port.1.s.2.visible=1 -unit.1.10.port.1.s.20.alias= -unit.1.10.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.20.name=TriggerPort1[20] -unit.1.10.port.1.s.20.orderindex=-1 -unit.1.10.port.1.s.20.visible=1 -unit.1.10.port.1.s.21.alias= -unit.1.10.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.21.name=TriggerPort1[21] -unit.1.10.port.1.s.21.orderindex=-1 -unit.1.10.port.1.s.21.visible=1 -unit.1.10.port.1.s.22.alias= -unit.1.10.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.22.name=TriggerPort1[22] -unit.1.10.port.1.s.22.orderindex=-1 -unit.1.10.port.1.s.22.visible=1 -unit.1.10.port.1.s.23.alias= -unit.1.10.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.23.name=TriggerPort1[23] -unit.1.10.port.1.s.23.orderindex=-1 -unit.1.10.port.1.s.23.visible=1 -unit.1.10.port.1.s.24.alias= -unit.1.10.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.24.name=TriggerPort1[24] -unit.1.10.port.1.s.24.orderindex=-1 -unit.1.10.port.1.s.24.visible=1 -unit.1.10.port.1.s.25.alias= -unit.1.10.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.25.name=TriggerPort1[25] -unit.1.10.port.1.s.25.orderindex=-1 -unit.1.10.port.1.s.25.visible=1 -unit.1.10.port.1.s.26.alias= -unit.1.10.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.26.name=TriggerPort1[26] -unit.1.10.port.1.s.26.orderindex=-1 -unit.1.10.port.1.s.26.visible=1 -unit.1.10.port.1.s.27.alias= -unit.1.10.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.27.name=TriggerPort1[27] -unit.1.10.port.1.s.27.orderindex=-1 -unit.1.10.port.1.s.27.visible=1 -unit.1.10.port.1.s.28.alias= -unit.1.10.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.28.name=TriggerPort1[28] -unit.1.10.port.1.s.28.orderindex=-1 -unit.1.10.port.1.s.28.visible=1 -unit.1.10.port.1.s.29.alias= -unit.1.10.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.29.name=TriggerPort1[29] -unit.1.10.port.1.s.29.orderindex=-1 -unit.1.10.port.1.s.29.visible=1 -unit.1.10.port.1.s.3.alias= -unit.1.10.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.3.name=TriggerPort1[3] -unit.1.10.port.1.s.3.orderindex=-1 -unit.1.10.port.1.s.3.visible=1 -unit.1.10.port.1.s.30.alias= -unit.1.10.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.30.name=TriggerPort1[30] -unit.1.10.port.1.s.30.orderindex=-1 -unit.1.10.port.1.s.30.visible=1 -unit.1.10.port.1.s.31.alias= -unit.1.10.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.31.name=TriggerPort1[31] -unit.1.10.port.1.s.31.orderindex=-1 -unit.1.10.port.1.s.31.visible=1 -unit.1.10.port.1.s.4.alias= -unit.1.10.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.4.name=TriggerPort1[4] -unit.1.10.port.1.s.4.orderindex=-1 -unit.1.10.port.1.s.4.visible=1 -unit.1.10.port.1.s.5.alias= -unit.1.10.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.5.name=TriggerPort1[5] -unit.1.10.port.1.s.5.orderindex=-1 -unit.1.10.port.1.s.5.visible=1 -unit.1.10.port.1.s.6.alias= -unit.1.10.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.6.name=TriggerPort1[6] -unit.1.10.port.1.s.6.orderindex=-1 -unit.1.10.port.1.s.6.visible=1 -unit.1.10.port.1.s.7.alias= -unit.1.10.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.7.name=TriggerPort1[7] -unit.1.10.port.1.s.7.orderindex=-1 -unit.1.10.port.1.s.7.visible=1 -unit.1.10.port.1.s.8.alias= -unit.1.10.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.8.name=TriggerPort1[8] -unit.1.10.port.1.s.8.orderindex=-1 -unit.1.10.port.1.s.8.visible=1 -unit.1.10.port.1.s.9.alias= -unit.1.10.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.1.s.9.name=TriggerPort1[9] -unit.1.10.port.1.s.9.orderindex=-1 -unit.1.10.port.1.s.9.visible=1 -unit.1.10.port.2.b.0.alias= -unit.1.10.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.b.0.name=TriggerPort2 -unit.1.10.port.2.b.0.orderindex=-1 -unit.1.10.port.2.b.0.radix=Hex -unit.1.10.port.2.b.0.signedOffset=0.0 -unit.1.10.port.2.b.0.signedPrecision=0 -unit.1.10.port.2.b.0.signedScaleFactor=1.0 -unit.1.10.port.2.b.0.unsignedOffset=0.0 -unit.1.10.port.2.b.0.unsignedPrecision=0 -unit.1.10.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.2.b.0.visible=1 -unit.1.10.port.2.buscount=1 -unit.1.10.port.2.channelcount=32 -unit.1.10.port.2.s.0.alias= -unit.1.10.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.0.name=TriggerPort2[0] -unit.1.10.port.2.s.0.orderindex=-1 -unit.1.10.port.2.s.0.visible=1 -unit.1.10.port.2.s.1.alias= -unit.1.10.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.1.name=TriggerPort2[1] -unit.1.10.port.2.s.1.orderindex=-1 -unit.1.10.port.2.s.1.visible=1 -unit.1.10.port.2.s.10.alias= -unit.1.10.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.10.name=TriggerPort2[10] -unit.1.10.port.2.s.10.orderindex=-1 -unit.1.10.port.2.s.10.visible=1 -unit.1.10.port.2.s.11.alias= -unit.1.10.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.11.name=TriggerPort2[11] -unit.1.10.port.2.s.11.orderindex=-1 -unit.1.10.port.2.s.11.visible=1 -unit.1.10.port.2.s.12.alias= -unit.1.10.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.12.name=TriggerPort2[12] -unit.1.10.port.2.s.12.orderindex=-1 -unit.1.10.port.2.s.12.visible=1 -unit.1.10.port.2.s.13.alias= -unit.1.10.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.13.name=TriggerPort2[13] -unit.1.10.port.2.s.13.orderindex=-1 -unit.1.10.port.2.s.13.visible=1 -unit.1.10.port.2.s.14.alias= -unit.1.10.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.14.name=TriggerPort2[14] -unit.1.10.port.2.s.14.orderindex=-1 -unit.1.10.port.2.s.14.visible=1 -unit.1.10.port.2.s.15.alias= -unit.1.10.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.15.name=TriggerPort2[15] -unit.1.10.port.2.s.15.orderindex=-1 -unit.1.10.port.2.s.15.visible=1 -unit.1.10.port.2.s.16.alias= -unit.1.10.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.16.name=TriggerPort2[16] -unit.1.10.port.2.s.16.orderindex=-1 -unit.1.10.port.2.s.16.visible=1 -unit.1.10.port.2.s.17.alias= -unit.1.10.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.17.name=TriggerPort2[17] -unit.1.10.port.2.s.17.orderindex=-1 -unit.1.10.port.2.s.17.visible=1 -unit.1.10.port.2.s.18.alias= -unit.1.10.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.18.name=TriggerPort2[18] -unit.1.10.port.2.s.18.orderindex=-1 -unit.1.10.port.2.s.18.visible=1 -unit.1.10.port.2.s.19.alias= -unit.1.10.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.19.name=TriggerPort2[19] -unit.1.10.port.2.s.19.orderindex=-1 -unit.1.10.port.2.s.19.visible=1 -unit.1.10.port.2.s.2.alias= -unit.1.10.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.2.name=TriggerPort2[2] -unit.1.10.port.2.s.2.orderindex=-1 -unit.1.10.port.2.s.2.visible=1 -unit.1.10.port.2.s.20.alias= -unit.1.10.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.20.name=TriggerPort2[20] -unit.1.10.port.2.s.20.orderindex=-1 -unit.1.10.port.2.s.20.visible=1 -unit.1.10.port.2.s.21.alias= -unit.1.10.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.21.name=TriggerPort2[21] -unit.1.10.port.2.s.21.orderindex=-1 -unit.1.10.port.2.s.21.visible=1 -unit.1.10.port.2.s.22.alias= -unit.1.10.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.22.name=TriggerPort2[22] -unit.1.10.port.2.s.22.orderindex=-1 -unit.1.10.port.2.s.22.visible=1 -unit.1.10.port.2.s.23.alias= -unit.1.10.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.23.name=TriggerPort2[23] -unit.1.10.port.2.s.23.orderindex=-1 -unit.1.10.port.2.s.23.visible=1 -unit.1.10.port.2.s.24.alias= -unit.1.10.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.24.name=TriggerPort2[24] -unit.1.10.port.2.s.24.orderindex=-1 -unit.1.10.port.2.s.24.visible=1 -unit.1.10.port.2.s.25.alias= -unit.1.10.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.25.name=TriggerPort2[25] -unit.1.10.port.2.s.25.orderindex=-1 -unit.1.10.port.2.s.25.visible=1 -unit.1.10.port.2.s.26.alias= -unit.1.10.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.26.name=TriggerPort2[26] -unit.1.10.port.2.s.26.orderindex=-1 -unit.1.10.port.2.s.26.visible=1 -unit.1.10.port.2.s.27.alias= -unit.1.10.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.27.name=TriggerPort2[27] -unit.1.10.port.2.s.27.orderindex=-1 -unit.1.10.port.2.s.27.visible=1 -unit.1.10.port.2.s.28.alias= -unit.1.10.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.28.name=TriggerPort2[28] -unit.1.10.port.2.s.28.orderindex=-1 -unit.1.10.port.2.s.28.visible=1 -unit.1.10.port.2.s.29.alias= -unit.1.10.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.29.name=TriggerPort2[29] -unit.1.10.port.2.s.29.orderindex=-1 -unit.1.10.port.2.s.29.visible=1 -unit.1.10.port.2.s.3.alias= -unit.1.10.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.3.name=TriggerPort2[3] -unit.1.10.port.2.s.3.orderindex=-1 -unit.1.10.port.2.s.3.visible=1 -unit.1.10.port.2.s.30.alias= -unit.1.10.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.30.name=TriggerPort2[30] -unit.1.10.port.2.s.30.orderindex=-1 -unit.1.10.port.2.s.30.visible=1 -unit.1.10.port.2.s.31.alias= -unit.1.10.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.31.name=TriggerPort2[31] -unit.1.10.port.2.s.31.orderindex=-1 -unit.1.10.port.2.s.31.visible=1 -unit.1.10.port.2.s.4.alias= -unit.1.10.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.4.name=TriggerPort2[4] -unit.1.10.port.2.s.4.orderindex=-1 -unit.1.10.port.2.s.4.visible=1 -unit.1.10.port.2.s.5.alias= -unit.1.10.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.5.name=TriggerPort2[5] -unit.1.10.port.2.s.5.orderindex=-1 -unit.1.10.port.2.s.5.visible=1 -unit.1.10.port.2.s.6.alias= -unit.1.10.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.6.name=TriggerPort2[6] -unit.1.10.port.2.s.6.orderindex=-1 -unit.1.10.port.2.s.6.visible=1 -unit.1.10.port.2.s.7.alias= -unit.1.10.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.7.name=TriggerPort2[7] -unit.1.10.port.2.s.7.orderindex=-1 -unit.1.10.port.2.s.7.visible=1 -unit.1.10.port.2.s.8.alias= -unit.1.10.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.8.name=TriggerPort2[8] -unit.1.10.port.2.s.8.orderindex=-1 -unit.1.10.port.2.s.8.visible=1 -unit.1.10.port.2.s.9.alias= -unit.1.10.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.2.s.9.name=TriggerPort2[9] -unit.1.10.port.2.s.9.orderindex=-1 -unit.1.10.port.2.s.9.visible=1 -unit.1.10.port.3.b.0.alias= -unit.1.10.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.b.0.name=TriggerPort3 -unit.1.10.port.3.b.0.orderindex=-1 -unit.1.10.port.3.b.0.radix=Hex -unit.1.10.port.3.b.0.signedOffset=0.0 -unit.1.10.port.3.b.0.signedPrecision=0 -unit.1.10.port.3.b.0.signedScaleFactor=1.0 -unit.1.10.port.3.b.0.unsignedOffset=0.0 -unit.1.10.port.3.b.0.unsignedPrecision=0 -unit.1.10.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.3.b.0.visible=1 -unit.1.10.port.3.buscount=1 -unit.1.10.port.3.channelcount=32 -unit.1.10.port.3.s.0.alias= -unit.1.10.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.0.name=TriggerPort3[0] -unit.1.10.port.3.s.0.orderindex=-1 -unit.1.10.port.3.s.0.visible=1 -unit.1.10.port.3.s.1.alias= -unit.1.10.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.1.name=TriggerPort3[1] -unit.1.10.port.3.s.1.orderindex=-1 -unit.1.10.port.3.s.1.visible=1 -unit.1.10.port.3.s.10.alias= -unit.1.10.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.10.name=TriggerPort3[10] -unit.1.10.port.3.s.10.orderindex=-1 -unit.1.10.port.3.s.10.visible=1 -unit.1.10.port.3.s.11.alias= -unit.1.10.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.11.name=TriggerPort3[11] -unit.1.10.port.3.s.11.orderindex=-1 -unit.1.10.port.3.s.11.visible=1 -unit.1.10.port.3.s.12.alias= -unit.1.10.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.12.name=TriggerPort3[12] -unit.1.10.port.3.s.12.orderindex=-1 -unit.1.10.port.3.s.12.visible=1 -unit.1.10.port.3.s.13.alias= -unit.1.10.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.13.name=TriggerPort3[13] -unit.1.10.port.3.s.13.orderindex=-1 -unit.1.10.port.3.s.13.visible=1 -unit.1.10.port.3.s.14.alias= -unit.1.10.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.14.name=TriggerPort3[14] -unit.1.10.port.3.s.14.orderindex=-1 -unit.1.10.port.3.s.14.visible=1 -unit.1.10.port.3.s.15.alias= -unit.1.10.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.15.name=TriggerPort3[15] -unit.1.10.port.3.s.15.orderindex=-1 -unit.1.10.port.3.s.15.visible=1 -unit.1.10.port.3.s.16.alias= -unit.1.10.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.16.name=TriggerPort3[16] -unit.1.10.port.3.s.16.orderindex=-1 -unit.1.10.port.3.s.16.visible=1 -unit.1.10.port.3.s.17.alias= -unit.1.10.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.17.name=TriggerPort3[17] -unit.1.10.port.3.s.17.orderindex=-1 -unit.1.10.port.3.s.17.visible=1 -unit.1.10.port.3.s.18.alias= -unit.1.10.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.18.name=TriggerPort3[18] -unit.1.10.port.3.s.18.orderindex=-1 -unit.1.10.port.3.s.18.visible=1 -unit.1.10.port.3.s.19.alias= -unit.1.10.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.19.name=TriggerPort3[19] -unit.1.10.port.3.s.19.orderindex=-1 -unit.1.10.port.3.s.19.visible=1 -unit.1.10.port.3.s.2.alias= -unit.1.10.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.2.name=TriggerPort3[2] -unit.1.10.port.3.s.2.orderindex=-1 -unit.1.10.port.3.s.2.visible=1 -unit.1.10.port.3.s.20.alias= -unit.1.10.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.20.name=TriggerPort3[20] -unit.1.10.port.3.s.20.orderindex=-1 -unit.1.10.port.3.s.20.visible=1 -unit.1.10.port.3.s.21.alias= -unit.1.10.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.21.name=TriggerPort3[21] -unit.1.10.port.3.s.21.orderindex=-1 -unit.1.10.port.3.s.21.visible=1 -unit.1.10.port.3.s.22.alias= -unit.1.10.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.22.name=TriggerPort3[22] -unit.1.10.port.3.s.22.orderindex=-1 -unit.1.10.port.3.s.22.visible=1 -unit.1.10.port.3.s.23.alias= -unit.1.10.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.23.name=TriggerPort3[23] -unit.1.10.port.3.s.23.orderindex=-1 -unit.1.10.port.3.s.23.visible=1 -unit.1.10.port.3.s.24.alias= -unit.1.10.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.24.name=TriggerPort3[24] -unit.1.10.port.3.s.24.orderindex=-1 -unit.1.10.port.3.s.24.visible=1 -unit.1.10.port.3.s.25.alias= -unit.1.10.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.25.name=TriggerPort3[25] -unit.1.10.port.3.s.25.orderindex=-1 -unit.1.10.port.3.s.25.visible=1 -unit.1.10.port.3.s.26.alias= -unit.1.10.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.26.name=TriggerPort3[26] -unit.1.10.port.3.s.26.orderindex=-1 -unit.1.10.port.3.s.26.visible=1 -unit.1.10.port.3.s.27.alias= -unit.1.10.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.27.name=TriggerPort3[27] -unit.1.10.port.3.s.27.orderindex=-1 -unit.1.10.port.3.s.27.visible=1 -unit.1.10.port.3.s.28.alias= -unit.1.10.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.28.name=TriggerPort3[28] -unit.1.10.port.3.s.28.orderindex=-1 -unit.1.10.port.3.s.28.visible=1 -unit.1.10.port.3.s.29.alias= -unit.1.10.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.29.name=TriggerPort3[29] -unit.1.10.port.3.s.29.orderindex=-1 -unit.1.10.port.3.s.29.visible=1 -unit.1.10.port.3.s.3.alias= -unit.1.10.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.3.name=TriggerPort3[3] -unit.1.10.port.3.s.3.orderindex=-1 -unit.1.10.port.3.s.3.visible=1 -unit.1.10.port.3.s.30.alias= -unit.1.10.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.30.name=TriggerPort3[30] -unit.1.10.port.3.s.30.orderindex=-1 -unit.1.10.port.3.s.30.visible=1 -unit.1.10.port.3.s.31.alias= -unit.1.10.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.31.name=TriggerPort3[31] -unit.1.10.port.3.s.31.orderindex=-1 -unit.1.10.port.3.s.31.visible=1 -unit.1.10.port.3.s.4.alias= -unit.1.10.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.4.name=TriggerPort3[4] -unit.1.10.port.3.s.4.orderindex=-1 -unit.1.10.port.3.s.4.visible=1 -unit.1.10.port.3.s.5.alias= -unit.1.10.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.5.name=TriggerPort3[5] -unit.1.10.port.3.s.5.orderindex=-1 -unit.1.10.port.3.s.5.visible=1 -unit.1.10.port.3.s.6.alias= -unit.1.10.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.6.name=TriggerPort3[6] -unit.1.10.port.3.s.6.orderindex=-1 -unit.1.10.port.3.s.6.visible=1 -unit.1.10.port.3.s.7.alias= -unit.1.10.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.7.name=TriggerPort3[7] -unit.1.10.port.3.s.7.orderindex=-1 -unit.1.10.port.3.s.7.visible=1 -unit.1.10.port.3.s.8.alias= -unit.1.10.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.8.name=TriggerPort3[8] -unit.1.10.port.3.s.8.orderindex=-1 -unit.1.10.port.3.s.8.visible=1 -unit.1.10.port.3.s.9.alias= -unit.1.10.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.3.s.9.name=TriggerPort3[9] -unit.1.10.port.3.s.9.orderindex=-1 -unit.1.10.port.3.s.9.visible=1 -unit.1.10.port.4.b.0.alias= -unit.1.10.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.10.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.b.0.name=TriggerPort4 -unit.1.10.port.4.b.0.orderindex=-1 -unit.1.10.port.4.b.0.radix=Hex -unit.1.10.port.4.b.0.signedOffset=0.0 -unit.1.10.port.4.b.0.signedPrecision=0 -unit.1.10.port.4.b.0.signedScaleFactor=1.0 -unit.1.10.port.4.b.0.unsignedOffset=0.0 -unit.1.10.port.4.b.0.unsignedPrecision=0 -unit.1.10.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.10.port.4.b.0.visible=1 -unit.1.10.port.4.buscount=1 -unit.1.10.port.4.channelcount=32 -unit.1.10.port.4.s.0.alias= -unit.1.10.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.0.name=TriggerPort4[0] -unit.1.10.port.4.s.0.orderindex=-1 -unit.1.10.port.4.s.0.visible=1 -unit.1.10.port.4.s.1.alias= -unit.1.10.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.1.name=TriggerPort4[1] -unit.1.10.port.4.s.1.orderindex=-1 -unit.1.10.port.4.s.1.visible=1 -unit.1.10.port.4.s.10.alias= -unit.1.10.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.10.name=TriggerPort4[10] -unit.1.10.port.4.s.10.orderindex=-1 -unit.1.10.port.4.s.10.visible=1 -unit.1.10.port.4.s.11.alias= -unit.1.10.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.11.name=TriggerPort4[11] -unit.1.10.port.4.s.11.orderindex=-1 -unit.1.10.port.4.s.11.visible=1 -unit.1.10.port.4.s.12.alias= -unit.1.10.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.12.name=TriggerPort4[12] -unit.1.10.port.4.s.12.orderindex=-1 -unit.1.10.port.4.s.12.visible=1 -unit.1.10.port.4.s.13.alias= -unit.1.10.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.13.name=TriggerPort4[13] -unit.1.10.port.4.s.13.orderindex=-1 -unit.1.10.port.4.s.13.visible=1 -unit.1.10.port.4.s.14.alias= -unit.1.10.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.14.name=TriggerPort4[14] -unit.1.10.port.4.s.14.orderindex=-1 -unit.1.10.port.4.s.14.visible=1 -unit.1.10.port.4.s.15.alias= -unit.1.10.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.15.name=TriggerPort4[15] -unit.1.10.port.4.s.15.orderindex=-1 -unit.1.10.port.4.s.15.visible=1 -unit.1.10.port.4.s.16.alias= -unit.1.10.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.16.name=TriggerPort4[16] -unit.1.10.port.4.s.16.orderindex=-1 -unit.1.10.port.4.s.16.visible=1 -unit.1.10.port.4.s.17.alias= -unit.1.10.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.17.name=TriggerPort4[17] -unit.1.10.port.4.s.17.orderindex=-1 -unit.1.10.port.4.s.17.visible=1 -unit.1.10.port.4.s.18.alias= -unit.1.10.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.18.name=TriggerPort4[18] -unit.1.10.port.4.s.18.orderindex=-1 -unit.1.10.port.4.s.18.visible=1 -unit.1.10.port.4.s.19.alias= -unit.1.10.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.10.port.4.s.19.name=TriggerPort4[19] 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-unit.1.11.vio.posn.252.name=AsyncOut[255] -unit.1.11.vio.posn.252.port=1 -unit.1.11.vio.posn.252.type=signal -unit.1.11.vio.posn.253.channel=255 -unit.1.11.vio.posn.253.name=AsyncOut[255] -unit.1.11.vio.posn.253.port=1 -unit.1.11.vio.posn.253.type=signal -unit.1.11.vio.posn.254.channel=255 -unit.1.11.vio.posn.254.name=AsyncOut[255] -unit.1.11.vio.posn.254.port=1 -unit.1.11.vio.posn.254.type=signal -unit.1.11.vio.posn.255.channel=255 -unit.1.11.vio.posn.255.name=AsyncOut[255] -unit.1.11.vio.posn.255.port=1 -unit.1.11.vio.posn.255.type=signal -unit.1.11.vio.posn.26.channel=2147483646 -unit.1.11.vio.posn.26.name=un_cross_gain_db -unit.1.11.vio.posn.26.port=1 -unit.1.11.vio.posn.26.radix=1 -unit.1.11.vio.posn.26.type=bus -unit.1.11.vio.posn.27.channel=2147483646 -unit.1.11.vio.posn.27.name=un_cross_gain_db -unit.1.11.vio.posn.27.port=1 -unit.1.11.vio.posn.27.radix=1 -unit.1.11.vio.posn.27.type=bus -unit.1.11.vio.posn.28.channel=2147483646 -unit.1.11.vio.posn.28.name=un_cross_gain_db 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-unit.1.11.vio.posn.33.channel=2147483646 -unit.1.11.vio.posn.33.name=un_cross_gain_db -unit.1.11.vio.posn.33.port=1 -unit.1.11.vio.posn.33.radix=1 -unit.1.11.vio.posn.33.type=bus -unit.1.11.vio.posn.34.channel=2147483646 -unit.1.11.vio.posn.34.name=un_cross_gain_db -unit.1.11.vio.posn.34.port=1 -unit.1.11.vio.posn.34.radix=1 -unit.1.11.vio.posn.34.type=bus -unit.1.11.vio.posn.35.channel=2147483646 -unit.1.11.vio.posn.35.name=un_cross_gain_db -unit.1.11.vio.posn.35.port=1 -unit.1.11.vio.posn.35.radix=1 -unit.1.11.vio.posn.35.type=bus -unit.1.11.vio.posn.36.channel=2147483646 -unit.1.11.vio.posn.36.name=un_cross_gain_db -unit.1.11.vio.posn.36.port=1 -unit.1.11.vio.posn.36.radix=1 -unit.1.11.vio.posn.36.type=bus -unit.1.11.vio.posn.37.channel=2147483646 -unit.1.11.vio.posn.37.name=un_cross_gain_db -unit.1.11.vio.posn.37.port=1 -unit.1.11.vio.posn.37.radix=1 -unit.1.11.vio.posn.37.type=bus -unit.1.11.vio.posn.38.channel=2147483646 -unit.1.11.vio.posn.38.name=un_cross_gain_db -unit.1.11.vio.posn.38.port=1 -unit.1.11.vio.posn.38.radix=1 -unit.1.11.vio.posn.38.type=bus -unit.1.11.vio.posn.39.channel=2147483646 -unit.1.11.vio.posn.39.name=un_cross_gain_db -unit.1.11.vio.posn.39.port=1 -unit.1.11.vio.posn.39.radix=1 -unit.1.11.vio.posn.39.type=bus -unit.1.11.vio.posn.4.channel=2147483646 -unit.1.11.vio.posn.4.name=dds_sine_gain_ch1 -unit.1.11.vio.posn.4.port=1 -unit.1.11.vio.posn.4.radix=1 -unit.1.11.vio.posn.4.type=bus -unit.1.11.vio.posn.40.channel=2147483646 -unit.1.11.vio.posn.40.name=un_cross_gain_db -unit.1.11.vio.posn.40.port=1 -unit.1.11.vio.posn.40.radix=1 -unit.1.11.vio.posn.40.type=bus -unit.1.11.vio.posn.41.channel=2147483646 -unit.1.11.vio.posn.41.name=un_cross_gain_db -unit.1.11.vio.posn.41.port=1 -unit.1.11.vio.posn.41.radix=1 -unit.1.11.vio.posn.41.type=bus -unit.1.11.vio.posn.42.channel=2147483646 -unit.1.11.vio.posn.42.name=un_cross_gain_db -unit.1.11.vio.posn.42.port=1 -unit.1.11.vio.posn.42.radix=1 -unit.1.11.vio.posn.42.type=bus -unit.1.11.vio.posn.43.channel=2147483646 -unit.1.11.vio.posn.43.name=un_cross_gain_db -unit.1.11.vio.posn.43.port=1 -unit.1.11.vio.posn.43.radix=1 -unit.1.11.vio.posn.43.type=bus -unit.1.11.vio.posn.44.channel=2147483646 -unit.1.11.vio.posn.44.name=un_cross_gain_db -unit.1.11.vio.posn.44.port=1 -unit.1.11.vio.posn.44.radix=1 -unit.1.11.vio.posn.44.type=bus -unit.1.11.vio.posn.45.channel=255 -unit.1.11.vio.posn.45.name=AsyncOut[255] -unit.1.11.vio.posn.45.port=1 -unit.1.11.vio.posn.45.type=signal -unit.1.11.vio.posn.46.channel=255 -unit.1.11.vio.posn.46.name=AsyncOut[255] -unit.1.11.vio.posn.46.port=1 -unit.1.11.vio.posn.46.type=signal -unit.1.11.vio.posn.47.channel=255 -unit.1.11.vio.posn.47.name=AsyncOut[255] -unit.1.11.vio.posn.47.port=1 -unit.1.11.vio.posn.47.radix=1 -unit.1.11.vio.posn.47.type=signal -unit.1.11.vio.posn.48.channel=255 -unit.1.11.vio.posn.48.name=AsyncOut[255] -unit.1.11.vio.posn.48.port=1 -unit.1.11.vio.posn.48.radix=1 -unit.1.11.vio.posn.48.type=signal -unit.1.11.vio.posn.49.channel=255 -unit.1.11.vio.posn.49.name=AsyncOut[255] -unit.1.11.vio.posn.49.port=1 -unit.1.11.vio.posn.49.type=signal -unit.1.11.vio.posn.5.channel=2147483646 -unit.1.11.vio.posn.5.name=dds_sine_gain_ch0 -unit.1.11.vio.posn.5.port=1 -unit.1.11.vio.posn.5.radix=1 -unit.1.11.vio.posn.5.type=bus -unit.1.11.vio.posn.50.channel=255 -unit.1.11.vio.posn.50.name=AsyncOut[255] -unit.1.11.vio.posn.50.port=1 -unit.1.11.vio.posn.50.type=signal -unit.1.11.vio.posn.51.channel=255 -unit.1.11.vio.posn.51.name=AsyncOut[255] -unit.1.11.vio.posn.51.port=1 -unit.1.11.vio.posn.51.type=signal -unit.1.11.vio.posn.52.channel=255 -unit.1.11.vio.posn.52.name=AsyncOut[255] -unit.1.11.vio.posn.52.port=1 -unit.1.11.vio.posn.52.type=signal -unit.1.11.vio.posn.53.channel=255 -unit.1.11.vio.posn.53.name=AsyncOut[255] -unit.1.11.vio.posn.53.port=1 -unit.1.11.vio.posn.53.type=signal -unit.1.11.vio.posn.54.channel=255 -unit.1.11.vio.posn.54.name=AsyncOut[255] -unit.1.11.vio.posn.54.port=1 -unit.1.11.vio.posn.54.type=signal -unit.1.11.vio.posn.55.channel=255 -unit.1.11.vio.posn.55.name=AsyncOut[255] -unit.1.11.vio.posn.55.port=1 -unit.1.11.vio.posn.55.type=signal -unit.1.11.vio.posn.56.channel=255 -unit.1.11.vio.posn.56.name=AsyncOut[255] -unit.1.11.vio.posn.56.port=1 -unit.1.11.vio.posn.56.type=signal -unit.1.11.vio.posn.57.channel=255 -unit.1.11.vio.posn.57.name=AsyncOut[255] -unit.1.11.vio.posn.57.port=1 -unit.1.11.vio.posn.57.type=signal -unit.1.11.vio.posn.58.channel=255 -unit.1.11.vio.posn.58.name=AsyncOut[255] -unit.1.11.vio.posn.58.port=1 -unit.1.11.vio.posn.58.type=signal -unit.1.11.vio.posn.59.channel=255 -unit.1.11.vio.posn.59.name=AsyncOut[255] -unit.1.11.vio.posn.59.port=1 -unit.1.11.vio.posn.59.type=signal -unit.1.11.vio.posn.6.channel=2147483646 -unit.1.11.vio.posn.6.name=adc_synth_data_en -unit.1.11.vio.posn.6.port=1 -unit.1.11.vio.posn.6.radix=1 -unit.1.11.vio.posn.6.type=bus -unit.1.11.vio.posn.60.channel=255 -unit.1.11.vio.posn.60.name=AsyncOut[255] -unit.1.11.vio.posn.60.port=1 -unit.1.11.vio.posn.60.radix=1 -unit.1.11.vio.posn.60.type=signal -unit.1.11.vio.posn.61.channel=255 -unit.1.11.vio.posn.61.name=AsyncOut[255] -unit.1.11.vio.posn.61.port=1 -unit.1.11.vio.posn.61.radix=1 -unit.1.11.vio.posn.61.type=signal -unit.1.11.vio.posn.62.channel=255 -unit.1.11.vio.posn.62.name=AsyncOut[255] -unit.1.11.vio.posn.62.port=1 -unit.1.11.vio.posn.62.type=signal -unit.1.11.vio.posn.63.channel=255 -unit.1.11.vio.posn.63.name=AsyncOut[255] -unit.1.11.vio.posn.63.port=1 -unit.1.11.vio.posn.63.type=signal -unit.1.11.vio.posn.64.channel=255 -unit.1.11.vio.posn.64.name=AsyncOut[255] -unit.1.11.vio.posn.64.port=1 -unit.1.11.vio.posn.64.type=signal -unit.1.11.vio.posn.65.channel=255 -unit.1.11.vio.posn.65.name=AsyncOut[255] -unit.1.11.vio.posn.65.port=1 -unit.1.11.vio.posn.65.type=signal -unit.1.11.vio.posn.66.channel=255 -unit.1.11.vio.posn.66.name=AsyncOut[255] -unit.1.11.vio.posn.66.port=1 -unit.1.11.vio.posn.66.type=signal -unit.1.11.vio.posn.67.channel=255 -unit.1.11.vio.posn.67.name=AsyncOut[255] -unit.1.11.vio.posn.67.port=1 -unit.1.11.vio.posn.67.type=signal -unit.1.11.vio.posn.68.channel=255 -unit.1.11.vio.posn.68.name=AsyncOut[255] -unit.1.11.vio.posn.68.port=1 -unit.1.11.vio.posn.68.type=signal -unit.1.11.vio.posn.69.channel=255 -unit.1.11.vio.posn.69.name=AsyncOut[255] -unit.1.11.vio.posn.69.port=1 -unit.1.11.vio.posn.69.type=signal -unit.1.11.vio.posn.7.channel=2147483646 -unit.1.11.vio.posn.7.name=un_cross_gain_aa -unit.1.11.vio.posn.7.port=1 -unit.1.11.vio.posn.7.radix=4 -unit.1.11.vio.posn.7.type=bus -unit.1.11.vio.posn.70.channel=255 -unit.1.11.vio.posn.70.name=AsyncOut[255] -unit.1.11.vio.posn.70.port=1 -unit.1.11.vio.posn.70.type=signal -unit.1.11.vio.posn.71.channel=255 -unit.1.11.vio.posn.71.name=AsyncOut[255] -unit.1.11.vio.posn.71.port=1 -unit.1.11.vio.posn.71.type=signal -unit.1.11.vio.posn.72.channel=255 -unit.1.11.vio.posn.72.name=AsyncOut[255] -unit.1.11.vio.posn.72.port=1 -unit.1.11.vio.posn.72.type=signal -unit.1.11.vio.posn.73.channel=255 -unit.1.11.vio.posn.73.name=AsyncOut[255] -unit.1.11.vio.posn.73.port=1 -unit.1.11.vio.posn.73.type=signal -unit.1.11.vio.posn.74.channel=255 -unit.1.11.vio.posn.74.name=AsyncOut[255] -unit.1.11.vio.posn.74.port=1 -unit.1.11.vio.posn.74.type=signal -unit.1.11.vio.posn.75.channel=255 -unit.1.11.vio.posn.75.name=AsyncOut[255] -unit.1.11.vio.posn.75.port=1 -unit.1.11.vio.posn.75.radix=1 -unit.1.11.vio.posn.75.type=signal -unit.1.11.vio.posn.76.channel=255 -unit.1.11.vio.posn.76.name=AsyncOut[255] -unit.1.11.vio.posn.76.port=1 -unit.1.11.vio.posn.76.radix=1 -unit.1.11.vio.posn.76.type=signal -unit.1.11.vio.posn.77.channel=255 -unit.1.11.vio.posn.77.name=AsyncOut[255] -unit.1.11.vio.posn.77.port=1 -unit.1.11.vio.posn.77.type=signal -unit.1.11.vio.posn.78.channel=255 -unit.1.11.vio.posn.78.name=AsyncOut[255] -unit.1.11.vio.posn.78.port=1 -unit.1.11.vio.posn.78.type=signal -unit.1.11.vio.posn.79.channel=255 -unit.1.11.vio.posn.79.name=AsyncOut[255] -unit.1.11.vio.posn.79.port=1 -unit.1.11.vio.posn.79.type=signal -unit.1.11.vio.posn.8.channel=2147483646 -unit.1.11.vio.posn.8.name=un_cross_gain_bb -unit.1.11.vio.posn.8.port=1 -unit.1.11.vio.posn.8.radix=4 -unit.1.11.vio.posn.8.type=bus -unit.1.11.vio.posn.80.channel=255 -unit.1.11.vio.posn.80.name=AsyncOut[255] -unit.1.11.vio.posn.80.port=1 -unit.1.11.vio.posn.80.type=signal -unit.1.11.vio.posn.81.channel=255 -unit.1.11.vio.posn.81.name=AsyncOut[255] -unit.1.11.vio.posn.81.port=1 -unit.1.11.vio.posn.81.type=signal -unit.1.11.vio.posn.82.channel=255 -unit.1.11.vio.posn.82.name=AsyncOut[255] -unit.1.11.vio.posn.82.port=1 -unit.1.11.vio.posn.82.type=signal -unit.1.11.vio.posn.83.channel=255 -unit.1.11.vio.posn.83.name=AsyncOut[255] -unit.1.11.vio.posn.83.port=1 -unit.1.11.vio.posn.83.type=signal -unit.1.11.vio.posn.84.channel=255 -unit.1.11.vio.posn.84.name=AsyncOut[255] -unit.1.11.vio.posn.84.port=1 -unit.1.11.vio.posn.84.type=signal -unit.1.11.vio.posn.85.channel=255 -unit.1.11.vio.posn.85.name=AsyncOut[255] -unit.1.11.vio.posn.85.port=1 -unit.1.11.vio.posn.85.type=signal -unit.1.11.vio.posn.86.channel=255 -unit.1.11.vio.posn.86.name=AsyncOut[255] -unit.1.11.vio.posn.86.port=1 -unit.1.11.vio.posn.86.type=signal -unit.1.11.vio.posn.87.channel=255 -unit.1.11.vio.posn.87.name=AsyncOut[255] -unit.1.11.vio.posn.87.port=1 -unit.1.11.vio.posn.87.radix=1 -unit.1.11.vio.posn.87.type=signal -unit.1.11.vio.posn.88.channel=255 -unit.1.11.vio.posn.88.name=AsyncOut[255] -unit.1.11.vio.posn.88.port=1 -unit.1.11.vio.posn.88.radix=1 -unit.1.11.vio.posn.88.type=signal -unit.1.11.vio.posn.89.channel=255 -unit.1.11.vio.posn.89.name=AsyncOut[255] -unit.1.11.vio.posn.89.port=1 -unit.1.11.vio.posn.89.type=signal -unit.1.11.vio.posn.9.channel=2147483646 -unit.1.11.vio.posn.9.name=un_cross_gain_cc -unit.1.11.vio.posn.9.port=1 -unit.1.11.vio.posn.9.radix=4 -unit.1.11.vio.posn.9.type=bus -unit.1.11.vio.posn.90.channel=255 -unit.1.11.vio.posn.90.name=AsyncOut[255] -unit.1.11.vio.posn.90.port=1 -unit.1.11.vio.posn.90.type=signal -unit.1.11.vio.posn.91.channel=255 -unit.1.11.vio.posn.91.name=AsyncOut[255] -unit.1.11.vio.posn.91.port=1 -unit.1.11.vio.posn.91.type=signal -unit.1.11.vio.posn.92.channel=255 -unit.1.11.vio.posn.92.name=AsyncOut[255] -unit.1.11.vio.posn.92.port=1 -unit.1.11.vio.posn.92.type=signal -unit.1.11.vio.posn.93.channel=255 -unit.1.11.vio.posn.93.name=AsyncOut[255] -unit.1.11.vio.posn.93.port=1 -unit.1.11.vio.posn.93.type=signal -unit.1.11.vio.posn.94.channel=255 -unit.1.11.vio.posn.94.name=AsyncOut[255] -unit.1.11.vio.posn.94.port=1 -unit.1.11.vio.posn.94.type=signal -unit.1.11.vio.posn.95.channel=255 -unit.1.11.vio.posn.95.name=AsyncOut[255] -unit.1.11.vio.posn.95.port=1 -unit.1.11.vio.posn.95.type=signal -unit.1.11.vio.posn.96.channel=255 -unit.1.11.vio.posn.96.name=AsyncOut[255] -unit.1.11.vio.posn.96.port=1 -unit.1.11.vio.posn.96.type=signal -unit.1.11.vio.posn.97.channel=255 -unit.1.11.vio.posn.97.name=AsyncOut[255] -unit.1.11.vio.posn.97.port=1 -unit.1.11.vio.posn.97.type=signal -unit.1.11.vio.posn.98.channel=255 -unit.1.11.vio.posn.98.name=AsyncOut[255] -unit.1.11.vio.posn.98.port=1 -unit.1.11.vio.posn.98.type=signal -unit.1.11.vio.posn.99.channel=255 -unit.1.11.vio.posn.99.name=AsyncOut[255] -unit.1.11.vio.posn.99.port=1 -unit.1.11.vio.posn.99.radix=1 -unit.1.11.vio.posn.99.type=signal -unit.1.11.vio.readperiod=0 -unit.1.12.6.HEIGHT6=0.77469134 -unit.1.12.6.WIDTH6=0.63793105 -unit.1.12.6.X6=0.028485756 -unit.1.12.6.Y6=0.043209877 -unit.1.12.browser_tree_state=1 -unit.1.12.browser_tree_state=0 -unit.1.12.browser_tree_state=0 -unit.1.12.coretype=VIO -unit.1.12.port.-1.buscount=0 -unit.1.12.port.-1.channelcount=0 -unit.1.12.port.0.buscount=0 -unit.1.12.port.0.channelcount=0 -unit.1.12.port.1.b.0.alias=dsp_dds_config_valid_ch0 -unit.1.12.port.1.b.0.channellist=240 -unit.1.12.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.0.display=0 -unit.1.12.port.1.b.0.name=AsyncOut -unit.1.12.port.1.b.0.orderindex=-1 -unit.1.12.port.1.b.0.radix=Hex -unit.1.12.port.1.b.0.signedOffset=0.0 -unit.1.12.port.1.b.0.signedPrecision=0 -unit.1.12.port.1.b.0.signedScaleFactor=1.0 -unit.1.12.port.1.b.0.tokencount=0 -unit.1.12.port.1.b.0.unsignedOffset=0.0 -unit.1.12.port.1.b.0.unsignedPrecision=0 -unit.1.12.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.0.value=0 -unit.1.12.port.1.b.0.visible=1 -unit.1.12.port.1.b.1.alias=dsp_dds_config_valid_ch1 -unit.1.12.port.1.b.1.channellist=241 -unit.1.12.port.1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.1.display=0 -unit.1.12.port.1.b.1.name=AsyncOut -unit.1.12.port.1.b.1.orderindex=-1 -unit.1.12.port.1.b.1.radix=Hex -unit.1.12.port.1.b.1.signedOffset=0.0 -unit.1.12.port.1.b.1.signedPrecision=0 -unit.1.12.port.1.b.1.signedScaleFactor=1.0 -unit.1.12.port.1.b.1.tokencount=0 -unit.1.12.port.1.b.1.unsignedOffset=0.0 -unit.1.12.port.1.b.1.unsignedPrecision=0 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221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 -unit.1.12.port.1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.11.display=0 -unit.1.12.port.1.b.11.name=AsyncOut -unit.1.12.port.1.b.11.orderindex=-1 -unit.1.12.port.1.b.11.radix=Hex -unit.1.12.port.1.b.11.signedOffset=0.0 -unit.1.12.port.1.b.11.signedPrecision=0 -unit.1.12.port.1.b.11.signedScaleFactor=1.0 -unit.1.12.port.1.b.11.tokencount=0 -unit.1.12.port.1.b.11.unsignedOffset=0.0 -unit.1.12.port.1.b.11.unsignedPrecision=0 -unit.1.12.port.1.b.11.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.11.value=00000000 -unit.1.12.port.1.b.11.visible=1 -unit.1.12.port.1.b.2.alias=dsp_dds_config_valid_ch2 -unit.1.12.port.1.b.2.channellist=242 -unit.1.12.port.1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.2.display=0 -unit.1.12.port.1.b.2.name=AsyncOut -unit.1.12.port.1.b.2.orderindex=-1 -unit.1.12.port.1.b.2.radix=Hex -unit.1.12.port.1.b.2.signedOffset=0.0 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124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 -unit.1.12.port.1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.8.display=0 -unit.1.12.port.1.b.8.name=AsyncOut -unit.1.12.port.1.b.8.orderindex=-1 -unit.1.12.port.1.b.8.radix=Hex -unit.1.12.port.1.b.8.signedOffset=0.0 -unit.1.12.port.1.b.8.signedPrecision=0 -unit.1.12.port.1.b.8.signedScaleFactor=1.0 -unit.1.12.port.1.b.8.tokencount=0 -unit.1.12.port.1.b.8.unsignedOffset=0.0 -unit.1.12.port.1.b.8.unsignedPrecision=0 -unit.1.12.port.1.b.8.unsignedScaleFactor=1.0 -unit.1.12.port.1.b.8.value=00000000 -unit.1.12.port.1.b.8.visible=1 -unit.1.12.port.1.b.9.alias=dsp_dds_poff_ch1 -unit.1.12.port.1.b.9.channellist=150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 -unit.1.12.port.1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.12.port.1.b.9.display=0 -unit.1.12.port.1.b.9.name=AsyncOut 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-unit.1.12.vio.posn.11.port=1 -unit.1.12.vio.posn.11.radix=1 -unit.1.12.vio.posn.11.type=bus -unit.1.12.vio.posn.12.channel=2147483646 -unit.1.12.vio.posn.12.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.12.port=1 -unit.1.12.vio.posn.12.radix=1 -unit.1.12.vio.posn.12.type=bus -unit.1.12.vio.posn.13.channel=2147483646 -unit.1.12.vio.posn.13.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.13.port=1 -unit.1.12.vio.posn.13.radix=1 -unit.1.12.vio.posn.13.type=bus -unit.1.12.vio.posn.14.channel=2147483646 -unit.1.12.vio.posn.14.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.14.port=1 -unit.1.12.vio.posn.14.radix=1 -unit.1.12.vio.posn.14.type=bus -unit.1.12.vio.posn.15.channel=2147483646 -unit.1.12.vio.posn.15.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.15.port=1 -unit.1.12.vio.posn.15.radix=1 -unit.1.12.vio.posn.15.type=bus -unit.1.12.vio.posn.16.channel=2147483646 -unit.1.12.vio.posn.16.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.16.port=1 -unit.1.12.vio.posn.16.radix=1 -unit.1.12.vio.posn.16.type=bus -unit.1.12.vio.posn.17.channel=2147483646 -unit.1.12.vio.posn.17.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.17.port=1 -unit.1.12.vio.posn.17.radix=1 -unit.1.12.vio.posn.17.type=bus -unit.1.12.vio.posn.18.channel=2147483646 -unit.1.12.vio.posn.18.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.18.port=1 -unit.1.12.vio.posn.18.radix=1 -unit.1.12.vio.posn.18.type=bus -unit.1.12.vio.posn.19.channel=2147483646 -unit.1.12.vio.posn.19.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.19.port=1 -unit.1.12.vio.posn.19.radix=1 -unit.1.12.vio.posn.19.type=bus -unit.1.12.vio.posn.2.channel=2147483646 -unit.1.12.vio.posn.2.name=dsp_dds_pinc_ch2 -unit.1.12.vio.posn.2.port=1 -unit.1.12.vio.posn.2.radix=4 -unit.1.12.vio.posn.2.type=bus -unit.1.12.vio.posn.20.channel=2147483646 -unit.1.12.vio.posn.20.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.20.port=1 -unit.1.12.vio.posn.20.radix=1 -unit.1.12.vio.posn.20.type=bus -unit.1.12.vio.posn.21.channel=2147483646 -unit.1.12.vio.posn.21.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.21.port=1 -unit.1.12.vio.posn.21.radix=1 -unit.1.12.vio.posn.21.type=bus -unit.1.12.vio.posn.22.channel=2147483646 -unit.1.12.vio.posn.22.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.22.port=1 -unit.1.12.vio.posn.22.radix=1 -unit.1.12.vio.posn.22.type=bus -unit.1.12.vio.posn.23.channel=2147483646 -unit.1.12.vio.posn.23.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.23.port=1 -unit.1.12.vio.posn.23.radix=1 -unit.1.12.vio.posn.23.type=bus -unit.1.12.vio.posn.24.channel=2147483646 -unit.1.12.vio.posn.24.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.24.port=1 -unit.1.12.vio.posn.24.radix=1 -unit.1.12.vio.posn.24.type=bus -unit.1.12.vio.posn.25.channel=2147483646 -unit.1.12.vio.posn.25.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.25.port=1 -unit.1.12.vio.posn.25.radix=1 -unit.1.12.vio.posn.25.type=bus -unit.1.12.vio.posn.26.channel=2147483646 -unit.1.12.vio.posn.26.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.26.port=1 -unit.1.12.vio.posn.26.radix=1 -unit.1.12.vio.posn.26.type=bus -unit.1.12.vio.posn.27.channel=2147483646 -unit.1.12.vio.posn.27.name=dsp_dds_config_valid_ch3 -unit.1.12.vio.posn.27.port=1 -unit.1.12.vio.posn.27.radix=1 -unit.1.12.vio.posn.27.type=bus -unit.1.12.vio.posn.3.channel=2147483646 -unit.1.12.vio.posn.3.name=dsp_dds_pinc_ch3 -unit.1.12.vio.posn.3.port=1 -unit.1.12.vio.posn.3.radix=4 -unit.1.12.vio.posn.3.type=bus -unit.1.12.vio.posn.4.channel=2147483646 -unit.1.12.vio.posn.4.name=dsp_dds_poff_ch0 -unit.1.12.vio.posn.4.port=1 -unit.1.12.vio.posn.4.radix=1 -unit.1.12.vio.posn.4.type=bus -unit.1.12.vio.posn.5.channel=2147483646 -unit.1.12.vio.posn.5.name=dsp_dds_poff_ch1 -unit.1.12.vio.posn.5.port=1 -unit.1.12.vio.posn.5.radix=1 -unit.1.12.vio.posn.5.type=bus -unit.1.12.vio.posn.6.channel=2147483646 -unit.1.12.vio.posn.6.name=dsp_dds_poff_ch2 -unit.1.12.vio.posn.6.port=1 -unit.1.12.vio.posn.6.radix=1 -unit.1.12.vio.posn.6.type=bus -unit.1.12.vio.posn.7.channel=2147483646 -unit.1.12.vio.posn.7.name=dsp_dds_poff_ch3 -unit.1.12.vio.posn.7.port=1 -unit.1.12.vio.posn.7.radix=1 -unit.1.12.vio.posn.7.type=bus -unit.1.12.vio.posn.8.channel=2147483646 -unit.1.12.vio.posn.8.name=dsp_dds_config_valid_ch0 -unit.1.12.vio.posn.8.port=1 -unit.1.12.vio.posn.8.radix=1 -unit.1.12.vio.posn.8.type=bus -unit.1.12.vio.posn.9.channel=2147483646 -unit.1.12.vio.posn.9.name=dsp_dds_config_valid_ch1 -unit.1.12.vio.posn.9.port=1 -unit.1.12.vio.posn.9.radix=1 -unit.1.12.vio.posn.9.type=bus -unit.1.12.vio.readperiod=0 -unit.1.2.0.HEIGHT0=0.4027778 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 -unit.1.2.0.TriggerRow2=1 -unit.1.2.0.WIDTH0=0.66041976 -unit.1.2.0.X0=0.052473765 -unit.1.2.0.Y0=0.0 -unit.1.2.1.HEIGHT1=0.70987654 -unit.1.2.1.WIDTH1=0.6071964 -unit.1.2.1.X1=0.004497751 -unit.1.2.1.Y1=0.11574074 -unit.1.2.5.HEIGHT5=0.9058642 -unit.1.2.5.WIDTH5=0.99550223 -unit.1.2.5.X5=0.0 -unit.1.2.5.Y5=0.0 -unit.1.2.MFBitsA0=1XXXXXXX -unit.1.2.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsB0=00000000 -unit.1.2.MFBitsB1=00000000000000000000000000000000 -unit.1.2.MFBitsB2=00000000000000000000000000000000 -unit.1.2.MFBitsB3=00000000000000000000000000000000 -unit.1.2.MFBitsB4=00000000000000000000000000000000 -unit.1.2.MFCompareA0=0 -unit.1.2.MFCompareA1=0 -unit.1.2.MFCompareA2=0 -unit.1.2.MFCompareA3=0 -unit.1.2.MFCompareA4=0 -unit.1.2.MFCompareB0=999 -unit.1.2.MFCompareB1=999 -unit.1.2.MFCompareB2=999 -unit.1.2.MFCompareB3=999 -unit.1.2.MFCompareB4=999 -unit.1.2.MFCount=5 -unit.1.2.MFDisplay0=0 -unit.1.2.MFDisplay1=0 -unit.1.2.MFDisplay2=0 -unit.1.2.MFDisplay3=0 -unit.1.2.MFDisplay4=0 -unit.1.2.MFEventType0=3 -unit.1.2.MFEventType1=3 -unit.1.2.MFEventType2=3 -unit.1.2.MFEventType3=3 -unit.1.2.MFEventType4=3 -unit.1.2.RunMode=SINGLE RUN -unit.1.2.SQCondition=M0 -unit.1.2.SQContiguous0=0 -unit.1.2.SequencerOn=0 -unit.1.2.TCActive=0 -unit.1.2.TCAdvanced0=0 -unit.1.2.TCCondition0_0=M0 -unit.1.2.TCCondition0_1= -unit.1.2.TCConditionType0=0 -unit.1.2.TCCount=1 -unit.1.2.TCEventCount0=1 -unit.1.2.TCEventType0=3 -unit.1.2.TCName0=TriggerCondition0 -unit.1.2.TCOutputEnable0=0 -unit.1.2.TCOutputHigh0=1 -unit.1.2.TCOutputMode0=0 -unit.1.2.browser_tree_state=1 -unit.1.2.browser_tree_state=0 -unit.1.2.browser_tree_state=0 -unit.1.2.browser_tree_state=0 -unit.1.2.browser_tree_state=0 -unit.1.2.coretype=ILA -unit.1.2.eventCount0=1 -unit.1.2.eventCount1=1 -unit.1.2.eventCount2=1 -unit.1.2.eventCount3=1 -unit.1.2.eventCount4=1 -unit.1.2.plotBusColor0=-16737844 -unit.1.2.plotBusColor1=-6711040 -unit.1.2.plotBusColor2=-65536 -unit.1.2.plotBusColor3=-16777012 -unit.1.2.plotBusCount=4 -unit.1.2.plotBusName0=dsp_tbt_amp_ch0 -unit.1.2.plotBusName1=dsp_tbt_amp_ch1 -unit.1.2.plotBusName2=dsp_tbt_amp_ch2 -unit.1.2.plotBusName3=dsp_tbt_amp_ch3 -unit.1.2.plotBusX=dsp_tbt_amp_ch0 -unit.1.2.plotBusY=dsp_tbt_amp_ch0 -unit.1.2.plotDataTimeMode=1 -unit.1.2.plotDisplayMode=line -unit.1.2.plotMaxX=0.0 -unit.1.2.plotMaxY=0.0 -unit.1.2.plotMinX=0.0 -unit.1.2.plotMinY=0.0 -unit.1.2.plotSelectedBus=f -unit.1.2.port.-1.b.0.alias=dsp_tbt_amp_ch0 -unit.1.2.port.-1.b.0.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.-1.b.0.color=java.awt.Color[r\=0,g\=153,b\=204] -unit.1.2.port.-1.b.0.name=DataPort -unit.1.2.port.-1.b.0.orderindex=-1 -unit.1.2.port.-1.b.0.radix=Signed -unit.1.2.port.-1.b.0.signedOffset=0.0 -unit.1.2.port.-1.b.0.signedPrecision=0 -unit.1.2.port.-1.b.0.signedScaleFactor=1.0 -unit.1.2.port.-1.b.0.tokencount=0 -unit.1.2.port.-1.b.0.unsignedOffset=0.0 -unit.1.2.port.-1.b.0.unsignedPrecision=0 -unit.1.2.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.-1.b.0.visible=1 -unit.1.2.port.-1.b.1.alias=dsp_tbt_amp_ch1 -unit.1.2.port.-1.b.1.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.2.port.-1.b.1.color=java.awt.Color[r\=153,g\=153,b\=0] -unit.1.2.port.-1.b.1.name=DataPort -unit.1.2.port.-1.b.1.orderindex=-1 -unit.1.2.port.-1.b.1.radix=Signed -unit.1.2.port.-1.b.1.signedOffset=0.0 -unit.1.2.port.-1.b.1.signedPrecision=0 -unit.1.2.port.-1.b.1.signedScaleFactor=1.0 -unit.1.2.port.-1.b.1.tokencount=0 -unit.1.2.port.-1.b.1.unsignedOffset=0.0 -unit.1.2.port.-1.b.1.unsignedPrecision=0 -unit.1.2.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.2.port.-1.b.1.visible=1 -unit.1.2.port.-1.b.2.alias=dsp_tbt_amp_ch2 -unit.1.2.port.-1.b.2.channellist=72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.2.port.-1.b.2.color=java.awt.Color[r\=255,g\=0,b\=0] -unit.1.2.port.-1.b.2.name=DataPort -unit.1.2.port.-1.b.2.orderindex=-1 -unit.1.2.port.-1.b.2.radix=Signed -unit.1.2.port.-1.b.2.signedOffset=0.0 -unit.1.2.port.-1.b.2.signedPrecision=0 -unit.1.2.port.-1.b.2.signedScaleFactor=1.0 -unit.1.2.port.-1.b.2.tokencount=0 -unit.1.2.port.-1.b.2.unsignedOffset=0.0 -unit.1.2.port.-1.b.2.unsignedPrecision=0 -unit.1.2.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.2.port.-1.b.2.visible=1 -unit.1.2.port.-1.b.3.alias=dsp_tbt_amp_ch3 -unit.1.2.port.-1.b.3.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 -unit.1.2.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=204] -unit.1.2.port.-1.b.3.name=DataPort -unit.1.2.port.-1.b.3.orderindex=-1 -unit.1.2.port.-1.b.3.radix=Signed -unit.1.2.port.-1.b.3.signedOffset=0.0 -unit.1.2.port.-1.b.3.signedPrecision=0 -unit.1.2.port.-1.b.3.signedScaleFactor=1.0 -unit.1.2.port.-1.b.3.tokencount=0 -unit.1.2.port.-1.b.3.unsignedOffset=0.0 -unit.1.2.port.-1.b.3.unsignedPrecision=0 -unit.1.2.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.2.port.-1.b.3.visible=1 -unit.1.2.port.-1.buscount=4 -unit.1.2.port.-1.channelcount=136 -unit.1.2.port.-1.s.0.alias= -unit.1.2.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.0.name=DataPort[0] -unit.1.2.port.-1.s.0.orderindex=-1 -unit.1.2.port.-1.s.0.visible=1 -unit.1.2.port.-1.s.1.alias= -unit.1.2.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.1.name=DataPort[1] -unit.1.2.port.-1.s.1.orderindex=-1 -unit.1.2.port.-1.s.1.visible=1 -unit.1.2.port.-1.s.10.alias= -unit.1.2.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.10.name=DataPort[10] -unit.1.2.port.-1.s.10.orderindex=-1 -unit.1.2.port.-1.s.10.visible=0 -unit.1.2.port.-1.s.100.alias= -unit.1.2.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.100.name=DataPort[100] -unit.1.2.port.-1.s.100.orderindex=-1 -unit.1.2.port.-1.s.100.visible=1 -unit.1.2.port.-1.s.101.alias= -unit.1.2.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.101.name=DataPort[101] -unit.1.2.port.-1.s.101.orderindex=-1 -unit.1.2.port.-1.s.101.visible=1 -unit.1.2.port.-1.s.102.alias= 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-unit.1.2.port.-1.s.89.alias= -unit.1.2.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.89.name=DataPort[89] -unit.1.2.port.-1.s.89.orderindex=-1 -unit.1.2.port.-1.s.89.visible=0 -unit.1.2.port.-1.s.9.alias= -unit.1.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.9.name=DataPort[9] -unit.1.2.port.-1.s.9.orderindex=-1 -unit.1.2.port.-1.s.9.visible=0 -unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=0 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=0 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 -unit.1.2.port.-1.s.92.visible=0 -unit.1.2.port.-1.s.93.alias= -unit.1.2.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.93.name=DataPort[93] -unit.1.2.port.-1.s.93.orderindex=-1 -unit.1.2.port.-1.s.93.visible=0 -unit.1.2.port.-1.s.94.alias= -unit.1.2.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.94.name=DataPort[94] -unit.1.2.port.-1.s.94.orderindex=-1 -unit.1.2.port.-1.s.94.visible=0 -unit.1.2.port.-1.s.95.alias= -unit.1.2.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.95.name=DataPort[95] -unit.1.2.port.-1.s.95.orderindex=-1 -unit.1.2.port.-1.s.95.visible=0 -unit.1.2.port.-1.s.96.alias= -unit.1.2.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.96.name=DataPort[96] -unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=1 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex -unit.1.2.port.0.b.0.signedOffset=0.0 -unit.1.2.port.0.b.0.signedPrecision=0 -unit.1.2.port.0.b.0.signedScaleFactor=1.0 -unit.1.2.port.0.b.0.unsignedOffset=0.0 -unit.1.2.port.0.b.0.unsignedPrecision=0 -unit.1.2.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.0.b.0.visible=1 -unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=8 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 -unit.1.2.port.3.s.27.alias= -unit.1.2.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.27.name=TriggerPort3[27] -unit.1.2.port.3.s.27.orderindex=-1 -unit.1.2.port.3.s.27.visible=1 -unit.1.2.port.3.s.28.alias= -unit.1.2.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.28.name=TriggerPort3[28] -unit.1.2.port.3.s.28.orderindex=-1 -unit.1.2.port.3.s.28.visible=1 -unit.1.2.port.3.s.29.alias= -unit.1.2.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.29.name=TriggerPort3[29] -unit.1.2.port.3.s.29.orderindex=-1 -unit.1.2.port.3.s.29.visible=1 -unit.1.2.port.3.s.3.alias= -unit.1.2.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.3.name=TriggerPort3[3] -unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.port.4.b.0.alias= -unit.1.2.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.b.0.name=TriggerPort4 -unit.1.2.port.4.b.0.orderindex=-1 -unit.1.2.port.4.b.0.radix=Hex -unit.1.2.port.4.b.0.signedOffset=0.0 -unit.1.2.port.4.b.0.signedPrecision=0 -unit.1.2.port.4.b.0.signedScaleFactor=1.0 -unit.1.2.port.4.b.0.unsignedOffset=0.0 -unit.1.2.port.4.b.0.unsignedPrecision=0 -unit.1.2.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.4.b.0.visible=1 -unit.1.2.port.4.buscount=1 -unit.1.2.port.4.channelcount=32 -unit.1.2.port.4.s.0.alias= -unit.1.2.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.0.name=TriggerPort4[0] -unit.1.2.port.4.s.0.orderindex=-1 -unit.1.2.port.4.s.0.visible=1 -unit.1.2.port.4.s.1.alias= -unit.1.2.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.1.name=TriggerPort4[1] -unit.1.2.port.4.s.1.orderindex=-1 -unit.1.2.port.4.s.1.visible=1 -unit.1.2.port.4.s.10.alias= -unit.1.2.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.10.name=TriggerPort4[10] -unit.1.2.port.4.s.10.orderindex=-1 -unit.1.2.port.4.s.10.visible=1 -unit.1.2.port.4.s.11.alias= -unit.1.2.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.11.name=TriggerPort4[11] -unit.1.2.port.4.s.11.orderindex=-1 -unit.1.2.port.4.s.11.visible=1 -unit.1.2.port.4.s.12.alias= -unit.1.2.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.12.name=TriggerPort4[12] -unit.1.2.port.4.s.12.orderindex=-1 -unit.1.2.port.4.s.12.visible=1 -unit.1.2.port.4.s.13.alias= -unit.1.2.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.13.name=TriggerPort4[13] -unit.1.2.port.4.s.13.orderindex=-1 -unit.1.2.port.4.s.13.visible=1 -unit.1.2.port.4.s.14.alias= -unit.1.2.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.14.name=TriggerPort4[14] -unit.1.2.port.4.s.14.orderindex=-1 -unit.1.2.port.4.s.14.visible=1 -unit.1.2.port.4.s.15.alias= -unit.1.2.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.15.name=TriggerPort4[15] -unit.1.2.port.4.s.15.orderindex=-1 -unit.1.2.port.4.s.15.visible=1 -unit.1.2.port.4.s.16.alias= -unit.1.2.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.16.name=TriggerPort4[16] -unit.1.2.port.4.s.16.orderindex=-1 -unit.1.2.port.4.s.16.visible=1 -unit.1.2.port.4.s.17.alias= -unit.1.2.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.17.name=TriggerPort4[17] -unit.1.2.port.4.s.17.orderindex=-1 -unit.1.2.port.4.s.17.visible=1 -unit.1.2.port.4.s.18.alias= -unit.1.2.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.18.name=TriggerPort4[18] -unit.1.2.port.4.s.18.orderindex=-1 -unit.1.2.port.4.s.18.visible=1 -unit.1.2.port.4.s.19.alias= -unit.1.2.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.19.name=TriggerPort4[19] -unit.1.2.port.4.s.19.orderindex=-1 -unit.1.2.port.4.s.19.visible=1 -unit.1.2.port.4.s.2.alias= -unit.1.2.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.2.name=TriggerPort4[2] -unit.1.2.port.4.s.2.orderindex=-1 -unit.1.2.port.4.s.2.visible=1 -unit.1.2.port.4.s.20.alias= -unit.1.2.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.20.name=TriggerPort4[20] -unit.1.2.port.4.s.20.orderindex=-1 -unit.1.2.port.4.s.20.visible=1 -unit.1.2.port.4.s.21.alias= -unit.1.2.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.21.name=TriggerPort4[21] -unit.1.2.port.4.s.21.orderindex=-1 -unit.1.2.port.4.s.21.visible=1 -unit.1.2.port.4.s.22.alias= -unit.1.2.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.22.name=TriggerPort4[22] -unit.1.2.port.4.s.22.orderindex=-1 -unit.1.2.port.4.s.22.visible=1 -unit.1.2.port.4.s.23.alias= -unit.1.2.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.23.name=TriggerPort4[23] -unit.1.2.port.4.s.23.orderindex=-1 -unit.1.2.port.4.s.23.visible=1 -unit.1.2.port.4.s.24.alias= -unit.1.2.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.24.name=TriggerPort4[24] -unit.1.2.port.4.s.24.orderindex=-1 -unit.1.2.port.4.s.24.visible=1 -unit.1.2.port.4.s.25.alias= -unit.1.2.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.25.name=TriggerPort4[25] -unit.1.2.port.4.s.25.orderindex=-1 -unit.1.2.port.4.s.25.visible=1 -unit.1.2.port.4.s.26.alias= -unit.1.2.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.26.name=TriggerPort4[26] -unit.1.2.port.4.s.26.orderindex=-1 -unit.1.2.port.4.s.26.visible=1 -unit.1.2.port.4.s.27.alias= -unit.1.2.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.27.name=TriggerPort4[27] -unit.1.2.port.4.s.27.orderindex=-1 -unit.1.2.port.4.s.27.visible=1 -unit.1.2.port.4.s.28.alias= -unit.1.2.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.28.name=TriggerPort4[28] -unit.1.2.port.4.s.28.orderindex=-1 -unit.1.2.port.4.s.28.visible=1 -unit.1.2.port.4.s.29.alias= -unit.1.2.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.29.name=TriggerPort4[29] -unit.1.2.port.4.s.29.orderindex=-1 -unit.1.2.port.4.s.29.visible=1 -unit.1.2.port.4.s.3.alias= -unit.1.2.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.3.name=TriggerPort4[3] -unit.1.2.port.4.s.3.orderindex=-1 -unit.1.2.port.4.s.3.visible=1 -unit.1.2.port.4.s.30.alias= -unit.1.2.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.30.name=TriggerPort4[30] -unit.1.2.port.4.s.30.orderindex=-1 -unit.1.2.port.4.s.30.visible=1 -unit.1.2.port.4.s.31.alias= -unit.1.2.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.31.name=TriggerPort4[31] -unit.1.2.port.4.s.31.orderindex=-1 -unit.1.2.port.4.s.31.visible=1 -unit.1.2.port.4.s.4.alias= -unit.1.2.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.4.name=TriggerPort4[4] -unit.1.2.port.4.s.4.orderindex=-1 -unit.1.2.port.4.s.4.visible=1 -unit.1.2.port.4.s.5.alias= -unit.1.2.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.5.name=TriggerPort4[5] -unit.1.2.port.4.s.5.orderindex=-1 -unit.1.2.port.4.s.5.visible=1 -unit.1.2.port.4.s.6.alias= -unit.1.2.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.6.name=TriggerPort4[6] -unit.1.2.port.4.s.6.orderindex=-1 -unit.1.2.port.4.s.6.visible=1 -unit.1.2.port.4.s.7.alias= -unit.1.2.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.3.port.0.b.0.signedPrecision=0 -unit.1.3.port.0.b.0.signedScaleFactor=1.0 -unit.1.3.port.0.b.0.unsignedOffset=0.0 -unit.1.3.port.0.b.0.unsignedPrecision=0 -unit.1.3.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.0.b.0.visible=1 -unit.1.3.port.0.buscount=1 -unit.1.3.port.0.channelcount=8 -unit.1.3.port.0.s.0.alias= -unit.1.3.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.0.name=TriggerPort0[0] -unit.1.3.port.0.s.0.orderindex=-1 -unit.1.3.port.0.s.0.visible=1 -unit.1.3.port.0.s.1.alias= -unit.1.3.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.1.name=TriggerPort0[1] -unit.1.3.port.0.s.1.orderindex=-1 -unit.1.3.port.0.s.1.visible=1 -unit.1.3.port.0.s.10.alias= -unit.1.3.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.10.name=TriggerPort0[10] -unit.1.3.port.0.s.10.orderindex=-1 -unit.1.3.port.0.s.10.visible=1 -unit.1.3.port.0.s.11.alias= -unit.1.3.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] 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-unit.1.4.port.0.s.5.orderindex=-1 -unit.1.4.port.0.s.5.visible=1 -unit.1.4.port.0.s.6.alias= -unit.1.4.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.6.name=TriggerPort0[6] -unit.1.4.port.0.s.6.orderindex=-1 -unit.1.4.port.0.s.6.visible=1 -unit.1.4.port.0.s.7.alias= -unit.1.4.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.7.name=TriggerPort0[7] -unit.1.4.port.0.s.7.orderindex=-1 -unit.1.4.port.0.s.7.visible=1 -unit.1.4.port.1.b.0.alias= -unit.1.4.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex -unit.1.4.port.1.b.0.signedOffset=0.0 -unit.1.4.port.1.b.0.signedPrecision=0 -unit.1.4.port.1.b.0.signedScaleFactor=1.0 -unit.1.4.port.1.b.0.unsignedOffset=0.0 -unit.1.4.port.1.b.0.unsignedPrecision=0 -unit.1.4.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.1.b.0.visible=1 -unit.1.4.port.1.buscount=1 -unit.1.4.port.1.channelcount=32 -unit.1.4.port.1.s.0.alias= -unit.1.4.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.0.name=TriggerPort1[0] -unit.1.4.port.1.s.0.orderindex=-1 -unit.1.4.port.1.s.0.visible=1 -unit.1.4.port.1.s.1.alias= -unit.1.4.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.1.name=TriggerPort1[1] -unit.1.4.port.1.s.1.orderindex=-1 -unit.1.4.port.1.s.1.visible=1 -unit.1.4.port.1.s.10.alias= -unit.1.4.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.10.name=TriggerPort1[10] -unit.1.4.port.1.s.10.orderindex=-1 -unit.1.4.port.1.s.10.visible=1 -unit.1.4.port.1.s.11.alias= -unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 -unit.1.4.port.1.s.16.alias= -unit.1.4.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.16.name=TriggerPort1[16] -unit.1.4.port.1.s.16.orderindex=-1 -unit.1.4.port.1.s.16.visible=1 -unit.1.4.port.1.s.17.alias= -unit.1.4.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.17.name=TriggerPort1[17] -unit.1.4.port.1.s.17.orderindex=-1 -unit.1.4.port.1.s.17.visible=1 -unit.1.4.port.1.s.18.alias= -unit.1.4.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.18.name=TriggerPort1[18] -unit.1.4.port.1.s.18.orderindex=-1 -unit.1.4.port.1.s.18.visible=1 -unit.1.4.port.1.s.19.alias= -unit.1.4.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.19.name=TriggerPort1[19] -unit.1.4.port.1.s.19.orderindex=-1 -unit.1.4.port.1.s.19.visible=1 -unit.1.4.port.1.s.2.alias= -unit.1.4.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.2.name=TriggerPort1[2] -unit.1.4.port.1.s.2.orderindex=-1 -unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.18.name=TriggerPort3[18] -unit.1.4.port.3.s.18.orderindex=-1 -unit.1.4.port.3.s.18.visible=1 -unit.1.4.port.3.s.19.alias= -unit.1.4.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.19.name=TriggerPort3[19] -unit.1.4.port.3.s.19.orderindex=-1 -unit.1.4.port.3.s.19.visible=1 -unit.1.4.port.3.s.2.alias= -unit.1.4.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.2.name=TriggerPort3[2] -unit.1.4.port.3.s.2.orderindex=-1 -unit.1.4.port.3.s.2.visible=1 -unit.1.4.port.3.s.20.alias= -unit.1.4.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.20.name=TriggerPort3[20] -unit.1.4.port.3.s.20.orderindex=-1 -unit.1.4.port.3.s.20.visible=1 -unit.1.4.port.3.s.21.alias= -unit.1.4.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.21.name=TriggerPort3[21] -unit.1.4.port.3.s.21.orderindex=-1 -unit.1.4.port.3.s.21.visible=1 -unit.1.4.port.3.s.22.alias= -unit.1.4.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.22.name=TriggerPort3[22] -unit.1.4.port.3.s.22.orderindex=-1 -unit.1.4.port.3.s.22.visible=1 -unit.1.4.port.3.s.23.alias= -unit.1.4.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.23.name=TriggerPort3[23] -unit.1.4.port.3.s.23.orderindex=-1 -unit.1.4.port.3.s.23.visible=1 -unit.1.4.port.3.s.24.alias= -unit.1.4.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.24.name=TriggerPort3[24] -unit.1.4.port.3.s.24.orderindex=-1 -unit.1.4.port.3.s.24.visible=1 -unit.1.4.port.3.s.25.alias= -unit.1.4.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.25.name=TriggerPort3[25] -unit.1.4.port.3.s.25.orderindex=-1 -unit.1.4.port.3.s.25.visible=1 -unit.1.4.port.3.s.26.alias= -unit.1.4.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.26.name=TriggerPort3[26] -unit.1.4.port.3.s.26.orderindex=-1 -unit.1.4.port.3.s.26.visible=1 -unit.1.4.port.3.s.27.alias= -unit.1.4.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.27.name=TriggerPort3[27] -unit.1.4.port.3.s.27.orderindex=-1 -unit.1.4.port.3.s.27.visible=1 -unit.1.4.port.3.s.28.alias= -unit.1.4.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.28.name=TriggerPort3[28] -unit.1.4.port.3.s.28.orderindex=-1 -unit.1.4.port.3.s.28.visible=1 -unit.1.4.port.3.s.29.alias= -unit.1.4.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.29.name=TriggerPort3[29] -unit.1.4.port.3.s.29.orderindex=-1 -unit.1.4.port.3.s.29.visible=1 -unit.1.4.port.3.s.3.alias= -unit.1.4.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.3.name=TriggerPort3[3] -unit.1.4.port.3.s.3.orderindex=-1 -unit.1.4.port.3.s.3.visible=1 -unit.1.4.port.3.s.30.alias= -unit.1.4.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.30.name=TriggerPort3[30] -unit.1.4.port.3.s.30.orderindex=-1 -unit.1.4.port.3.s.30.visible=1 -unit.1.4.port.3.s.31.alias= -unit.1.4.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.31.name=TriggerPort3[31] -unit.1.4.port.3.s.31.orderindex=-1 -unit.1.4.port.3.s.31.visible=1 -unit.1.4.port.3.s.4.alias= -unit.1.4.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.4.name=TriggerPort3[4] -unit.1.4.port.3.s.4.orderindex=-1 -unit.1.4.port.3.s.4.visible=1 -unit.1.4.port.3.s.5.alias= -unit.1.4.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.5.name=TriggerPort3[5] -unit.1.4.port.3.s.5.orderindex=-1 -unit.1.4.port.3.s.5.visible=1 -unit.1.4.port.3.s.6.alias= -unit.1.4.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.6.name=TriggerPort3[6] -unit.1.4.port.3.s.6.orderindex=-1 -unit.1.4.port.3.s.6.visible=1 -unit.1.4.port.3.s.7.alias= -unit.1.4.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.7.name=TriggerPort3[7] -unit.1.4.port.3.s.7.orderindex=-1 -unit.1.4.port.3.s.7.visible=1 -unit.1.4.port.3.s.8.alias= -unit.1.4.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.8.name=TriggerPort3[8] -unit.1.4.port.3.s.8.orderindex=-1 -unit.1.4.port.3.s.8.visible=1 -unit.1.4.port.3.s.9.alias= -unit.1.4.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.9.name=TriggerPort3[9] -unit.1.4.port.3.s.9.orderindex=-1 -unit.1.4.port.3.s.9.visible=1 -unit.1.4.port.4.b.0.alias= -unit.1.4.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.b.0.name=TriggerPort4 -unit.1.4.port.4.b.0.orderindex=-1 -unit.1.4.port.4.b.0.radix=Hex -unit.1.4.port.4.b.0.signedOffset=0.0 -unit.1.4.port.4.b.0.signedPrecision=0 -unit.1.4.port.4.b.0.signedScaleFactor=1.0 -unit.1.4.port.4.b.0.unsignedOffset=0.0 -unit.1.4.port.4.b.0.unsignedPrecision=0 -unit.1.4.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.4.b.0.visible=1 -unit.1.4.port.4.buscount=1 -unit.1.4.port.4.channelcount=32 -unit.1.4.port.4.s.0.alias= -unit.1.4.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.0.name=TriggerPort4[0] -unit.1.4.port.4.s.0.orderindex=-1 -unit.1.4.port.4.s.0.visible=1 -unit.1.4.port.4.s.1.alias= -unit.1.4.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.1.name=TriggerPort4[1] -unit.1.4.port.4.s.1.orderindex=-1 -unit.1.4.port.4.s.1.visible=1 -unit.1.4.port.4.s.10.alias= -unit.1.4.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.10.name=TriggerPort4[10] -unit.1.4.port.4.s.10.orderindex=-1 -unit.1.4.port.4.s.10.visible=1 -unit.1.4.port.4.s.11.alias= -unit.1.4.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.11.name=TriggerPort4[11] -unit.1.4.port.4.s.11.orderindex=-1 -unit.1.4.port.4.s.11.visible=1 -unit.1.4.port.4.s.12.alias= -unit.1.4.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.12.name=TriggerPort4[12] -unit.1.4.port.4.s.12.orderindex=-1 -unit.1.4.port.4.s.12.visible=1 -unit.1.4.port.4.s.13.alias= -unit.1.4.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.13.name=TriggerPort4[13] -unit.1.4.port.4.s.13.orderindex=-1 -unit.1.4.port.4.s.13.visible=1 -unit.1.4.port.4.s.14.alias= -unit.1.4.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.14.name=TriggerPort4[14] -unit.1.4.port.4.s.14.orderindex=-1 -unit.1.4.port.4.s.14.visible=1 -unit.1.4.port.4.s.15.alias= -unit.1.4.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.15.name=TriggerPort4[15] -unit.1.4.port.4.s.15.orderindex=-1 -unit.1.4.port.4.s.15.visible=1 -unit.1.4.port.4.s.16.alias= -unit.1.4.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.16.name=TriggerPort4[16] -unit.1.4.port.4.s.16.orderindex=-1 -unit.1.4.port.4.s.16.visible=1 -unit.1.4.port.4.s.17.alias= -unit.1.4.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.17.name=TriggerPort4[17] -unit.1.4.port.4.s.17.orderindex=-1 -unit.1.4.port.4.s.17.visible=1 -unit.1.4.port.4.s.18.alias= -unit.1.4.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.18.name=TriggerPort4[18] -unit.1.4.port.4.s.18.orderindex=-1 -unit.1.4.port.4.s.18.visible=1 -unit.1.4.port.4.s.19.alias= -unit.1.4.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.19.name=TriggerPort4[19] -unit.1.4.port.4.s.19.orderindex=-1 -unit.1.4.port.4.s.19.visible=1 -unit.1.4.port.4.s.2.alias= -unit.1.4.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.2.name=TriggerPort4[2] -unit.1.4.port.4.s.2.orderindex=-1 -unit.1.4.port.4.s.2.visible=1 -unit.1.4.port.4.s.20.alias= -unit.1.4.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.20.name=TriggerPort4[20] -unit.1.4.port.4.s.20.orderindex=-1 -unit.1.4.port.4.s.20.visible=1 -unit.1.4.port.4.s.21.alias= -unit.1.4.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.21.name=TriggerPort4[21] -unit.1.4.port.4.s.21.orderindex=-1 -unit.1.4.port.4.s.21.visible=1 -unit.1.4.port.4.s.22.alias= -unit.1.4.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.22.name=TriggerPort4[22] -unit.1.4.port.4.s.22.orderindex=-1 -unit.1.4.port.4.s.22.visible=1 -unit.1.4.port.4.s.23.alias= -unit.1.4.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.23.name=TriggerPort4[23] -unit.1.4.port.4.s.23.orderindex=-1 -unit.1.4.port.4.s.23.visible=1 -unit.1.4.port.4.s.24.alias= -unit.1.4.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.24.name=TriggerPort4[24] -unit.1.4.port.4.s.24.orderindex=-1 -unit.1.4.port.4.s.24.visible=1 -unit.1.4.port.4.s.25.alias= -unit.1.4.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.25.name=TriggerPort4[25] -unit.1.4.port.4.s.25.orderindex=-1 -unit.1.4.port.4.s.25.visible=1 -unit.1.4.port.4.s.26.alias= -unit.1.4.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.26.name=TriggerPort4[26] -unit.1.4.port.4.s.26.orderindex=-1 -unit.1.4.port.4.s.26.visible=1 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-unit.1.4.port.4.s.30.visible=1 -unit.1.4.port.4.s.31.alias= -unit.1.4.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.31.name=TriggerPort4[31] -unit.1.4.port.4.s.31.orderindex=-1 -unit.1.4.port.4.s.31.visible=1 -unit.1.4.port.4.s.4.alias= -unit.1.4.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.4.name=TriggerPort4[4] -unit.1.4.port.4.s.4.orderindex=-1 -unit.1.4.port.4.s.4.visible=1 -unit.1.4.port.4.s.5.alias= -unit.1.4.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.5.name=TriggerPort4[5] -unit.1.4.port.4.s.5.orderindex=-1 -unit.1.4.port.4.s.5.visible=1 -unit.1.4.port.4.s.6.alias= -unit.1.4.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.6.name=TriggerPort4[6] -unit.1.4.port.4.s.6.orderindex=-1 -unit.1.4.port.4.s.6.visible=1 -unit.1.4.port.4.s.7.alias= -unit.1.4.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.7.name=TriggerPort4[7] -unit.1.4.port.4.s.7.orderindex=-1 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-unit.1.4.triggerWindowTS=0 -unit.1.4.username=fofb_amp -unit.1.4.waveform.count=3 -unit.1.4.waveform.posn.0.channel=2147483646 -unit.1.4.waveform.posn.0.name=dsp_fofb_amp_ch2 -unit.1.4.waveform.posn.0.radix=1 -unit.1.4.waveform.posn.0.type=bus -unit.1.4.waveform.posn.1.channel=2147483646 -unit.1.4.waveform.posn.1.name=dsp_fofb_amp_ch1 -unit.1.4.waveform.posn.1.radix=3 -unit.1.4.waveform.posn.1.type=bus -unit.1.4.waveform.posn.10.channel=103 -unit.1.4.waveform.posn.10.name=DataPort[103] -unit.1.4.waveform.posn.10.type=signal -unit.1.4.waveform.posn.11.channel=103 -unit.1.4.waveform.posn.11.name=DataPort[103] -unit.1.4.waveform.posn.11.type=signal -unit.1.4.waveform.posn.12.channel=103 -unit.1.4.waveform.posn.12.name=DataPort[103] -unit.1.4.waveform.posn.12.type=signal -unit.1.4.waveform.posn.13.channel=103 -unit.1.4.waveform.posn.13.name=DataPort[103] -unit.1.4.waveform.posn.13.type=signal -unit.1.4.waveform.posn.14.channel=103 -unit.1.4.waveform.posn.14.name=DataPort[103] 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-unit.1.5.port.1.s.16.alias= -unit.1.5.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.16.name=TriggerPort1[16] -unit.1.5.port.1.s.16.orderindex=-1 -unit.1.5.port.1.s.16.visible=1 -unit.1.5.port.1.s.17.alias= -unit.1.5.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.17.name=TriggerPort1[17] -unit.1.5.port.1.s.17.orderindex=-1 -unit.1.5.port.1.s.17.visible=1 -unit.1.5.port.1.s.18.alias= -unit.1.5.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.18.name=TriggerPort1[18] -unit.1.5.port.1.s.18.orderindex=-1 -unit.1.5.port.1.s.18.visible=1 -unit.1.5.port.1.s.19.alias= -unit.1.5.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.19.name=TriggerPort1[19] -unit.1.5.port.1.s.19.orderindex=-1 -unit.1.5.port.1.s.19.visible=1 -unit.1.5.port.1.s.2.alias= -unit.1.5.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.2.name=TriggerPort1[2] -unit.1.5.port.1.s.2.orderindex=-1 -unit.1.5.port.1.s.2.visible=1 -unit.1.5.port.1.s.20.alias= -unit.1.5.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.20.name=TriggerPort1[20] -unit.1.5.port.1.s.20.orderindex=-1 -unit.1.5.port.1.s.20.visible=1 -unit.1.5.port.1.s.21.alias= -unit.1.5.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.21.name=TriggerPort1[21] -unit.1.5.port.1.s.21.orderindex=-1 -unit.1.5.port.1.s.21.visible=1 -unit.1.5.port.1.s.22.alias= -unit.1.5.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.22.name=TriggerPort1[22] -unit.1.5.port.1.s.22.orderindex=-1 -unit.1.5.port.1.s.22.visible=1 -unit.1.5.port.1.s.23.alias= -unit.1.5.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.23.name=TriggerPort1[23] -unit.1.5.port.1.s.23.orderindex=-1 -unit.1.5.port.1.s.23.visible=1 -unit.1.5.port.1.s.24.alias= -unit.1.5.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.24.name=TriggerPort1[24] -unit.1.5.port.1.s.24.orderindex=-1 -unit.1.5.port.1.s.24.visible=1 -unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 -unit.1.5.port.3.s.16.alias= -unit.1.5.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.16.name=TriggerPort3[16] -unit.1.5.port.3.s.16.orderindex=-1 -unit.1.5.port.3.s.16.visible=1 -unit.1.5.port.3.s.17.alias= -unit.1.5.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.17.name=TriggerPort3[17] -unit.1.5.port.3.s.17.orderindex=-1 -unit.1.5.port.3.s.17.visible=1 -unit.1.5.port.3.s.18.alias= -unit.1.5.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.18.name=TriggerPort3[18] -unit.1.5.port.3.s.18.orderindex=-1 -unit.1.5.port.3.s.18.visible=1 -unit.1.5.port.3.s.19.alias= -unit.1.5.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.19.name=TriggerPort3[19] -unit.1.5.port.3.s.19.orderindex=-1 -unit.1.5.port.3.s.19.visible=1 -unit.1.5.port.3.s.2.alias= -unit.1.5.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.2.name=TriggerPort3[2] -unit.1.5.port.3.s.2.orderindex=-1 -unit.1.5.port.3.s.2.visible=1 -unit.1.5.port.3.s.20.alias= -unit.1.5.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.20.name=TriggerPort3[20] -unit.1.5.port.3.s.20.orderindex=-1 -unit.1.5.port.3.s.20.visible=1 -unit.1.5.port.3.s.21.alias= -unit.1.5.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.21.name=TriggerPort3[21] -unit.1.5.port.3.s.21.orderindex=-1 -unit.1.5.port.3.s.21.visible=1 -unit.1.5.port.3.s.22.alias= -unit.1.5.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.22.name=TriggerPort3[22] -unit.1.5.port.3.s.22.orderindex=-1 -unit.1.5.port.3.s.22.visible=1 -unit.1.5.port.3.s.23.alias= -unit.1.5.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.23.name=TriggerPort3[23] -unit.1.5.port.3.s.23.orderindex=-1 -unit.1.5.port.3.s.23.visible=1 -unit.1.5.port.3.s.24.alias= -unit.1.5.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.24.name=TriggerPort3[24] -unit.1.5.port.3.s.24.orderindex=-1 -unit.1.5.port.3.s.24.visible=1 -unit.1.5.port.3.s.25.alias= -unit.1.5.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.25.name=TriggerPort3[25] -unit.1.5.port.3.s.25.orderindex=-1 -unit.1.5.port.3.s.25.visible=1 -unit.1.5.port.3.s.26.alias= -unit.1.5.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.26.name=TriggerPort3[26] -unit.1.5.port.3.s.26.orderindex=-1 -unit.1.5.port.3.s.26.visible=1 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-unit.1.5.port.4.b.0.visible=1 -unit.1.5.port.4.buscount=1 -unit.1.5.port.4.channelcount=32 -unit.1.5.port.4.s.0.alias= -unit.1.5.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.0.name=TriggerPort4[0] -unit.1.5.port.4.s.0.orderindex=-1 -unit.1.5.port.4.s.0.visible=1 -unit.1.5.port.4.s.1.alias= -unit.1.5.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.1.name=TriggerPort4[1] -unit.1.5.port.4.s.1.orderindex=-1 -unit.1.5.port.4.s.1.visible=1 -unit.1.5.port.4.s.10.alias= -unit.1.5.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.10.name=TriggerPort4[10] -unit.1.5.port.4.s.10.orderindex=-1 -unit.1.5.port.4.s.10.visible=1 -unit.1.5.port.4.s.11.alias= -unit.1.5.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.11.name=TriggerPort4[11] -unit.1.5.port.4.s.11.orderindex=-1 -unit.1.5.port.4.s.11.visible=1 -unit.1.5.port.4.s.12.alias= -unit.1.5.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.12.name=TriggerPort4[12] -unit.1.5.port.4.s.12.orderindex=-1 -unit.1.5.port.4.s.12.visible=1 -unit.1.5.port.4.s.13.alias= -unit.1.5.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.13.name=TriggerPort4[13] -unit.1.5.port.4.s.13.orderindex=-1 -unit.1.5.port.4.s.13.visible=1 -unit.1.5.port.4.s.14.alias= -unit.1.5.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.14.name=TriggerPort4[14] -unit.1.5.port.4.s.14.orderindex=-1 -unit.1.5.port.4.s.14.visible=1 -unit.1.5.port.4.s.15.alias= -unit.1.5.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.15.name=TriggerPort4[15] -unit.1.5.port.4.s.15.orderindex=-1 -unit.1.5.port.4.s.15.visible=1 -unit.1.5.port.4.s.16.alias= -unit.1.5.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.16.name=TriggerPort4[16] -unit.1.5.port.4.s.16.orderindex=-1 -unit.1.5.port.4.s.16.visible=1 -unit.1.5.port.4.s.17.alias= -unit.1.5.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.17.name=TriggerPort4[17] -unit.1.5.port.4.s.17.orderindex=-1 -unit.1.5.port.4.s.17.visible=1 -unit.1.5.port.4.s.18.alias= -unit.1.5.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.18.name=TriggerPort4[18] -unit.1.5.port.4.s.18.orderindex=-1 -unit.1.5.port.4.s.18.visible=1 -unit.1.5.port.4.s.19.alias= -unit.1.5.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.19.name=TriggerPort4[19] -unit.1.5.port.4.s.19.orderindex=-1 -unit.1.5.port.4.s.19.visible=1 -unit.1.5.port.4.s.2.alias= -unit.1.5.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.2.name=TriggerPort4[2] -unit.1.5.port.4.s.2.orderindex=-1 -unit.1.5.port.4.s.2.visible=1 -unit.1.5.port.4.s.20.alias= -unit.1.5.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.20.name=TriggerPort4[20] -unit.1.5.port.4.s.20.orderindex=-1 -unit.1.5.port.4.s.20.visible=1 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-unit.1.6.port.-1.s.87.visible=0 -unit.1.6.port.-1.s.88.alias= -unit.1.6.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.88.name=DataPort[88] -unit.1.6.port.-1.s.88.orderindex=-1 -unit.1.6.port.-1.s.88.visible=0 -unit.1.6.port.-1.s.89.alias= -unit.1.6.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.89.name=DataPort[89] -unit.1.6.port.-1.s.89.orderindex=-1 -unit.1.6.port.-1.s.89.visible=0 -unit.1.6.port.-1.s.9.alias= -unit.1.6.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.9.name=DataPort[9] -unit.1.6.port.-1.s.9.orderindex=-1 -unit.1.6.port.-1.s.9.visible=0 -unit.1.6.port.-1.s.90.alias= -unit.1.6.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.90.name=DataPort[90] -unit.1.6.port.-1.s.90.orderindex=-1 -unit.1.6.port.-1.s.90.visible=0 -unit.1.6.port.-1.s.91.alias= -unit.1.6.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.91.name=DataPort[91] -unit.1.6.port.-1.s.91.orderindex=-1 -unit.1.6.port.-1.s.91.visible=0 -unit.1.6.port.-1.s.92.alias= -unit.1.6.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.92.name=DataPort[92] -unit.1.6.port.-1.s.92.orderindex=-1 -unit.1.6.port.-1.s.92.visible=0 -unit.1.6.port.-1.s.93.alias= -unit.1.6.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.93.name=DataPort[93] -unit.1.6.port.-1.s.93.orderindex=-1 -unit.1.6.port.-1.s.93.visible=0 -unit.1.6.port.-1.s.94.alias= -unit.1.6.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.94.name=DataPort[94] -unit.1.6.port.-1.s.94.orderindex=-1 -unit.1.6.port.-1.s.94.visible=0 -unit.1.6.port.-1.s.95.alias= -unit.1.6.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.95.name=DataPort[95] -unit.1.6.port.-1.s.95.orderindex=-1 -unit.1.6.port.-1.s.95.visible=0 -unit.1.6.port.-1.s.96.alias= -unit.1.6.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.96.name=DataPort[96] -unit.1.6.port.-1.s.96.orderindex=-1 -unit.1.6.port.-1.s.96.visible=1 -unit.1.6.port.-1.s.97.alias= -unit.1.6.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.97.name=DataPort[97] -unit.1.6.port.-1.s.97.orderindex=-1 -unit.1.6.port.-1.s.97.visible=1 -unit.1.6.port.-1.s.98.alias= -unit.1.6.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.98.name=DataPort[98] -unit.1.6.port.-1.s.98.orderindex=-1 -unit.1.6.port.-1.s.98.visible=1 -unit.1.6.port.-1.s.99.alias= -unit.1.6.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.-1.s.99.name=DataPort[99] -unit.1.6.port.-1.s.99.orderindex=-1 -unit.1.6.port.-1.s.99.visible=1 -unit.1.6.port.0.b.0.alias= -unit.1.6.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.6.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.b.0.name=TriggerPort0 -unit.1.6.port.0.b.0.orderindex=-1 -unit.1.6.port.0.b.0.radix=Hex -unit.1.6.port.0.b.0.signedOffset=0.0 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-unit.1.6.port.0.s.3.name=TriggerPort0[3] -unit.1.6.port.0.s.3.orderindex=-1 -unit.1.6.port.0.s.3.visible=1 -unit.1.6.port.0.s.4.alias= -unit.1.6.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.4.name=TriggerPort0[4] -unit.1.6.port.0.s.4.orderindex=-1 -unit.1.6.port.0.s.4.visible=1 -unit.1.6.port.0.s.5.alias= -unit.1.6.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.5.name=TriggerPort0[5] -unit.1.6.port.0.s.5.orderindex=-1 -unit.1.6.port.0.s.5.visible=1 -unit.1.6.port.0.s.6.alias= -unit.1.6.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.6.name=TriggerPort0[6] -unit.1.6.port.0.s.6.orderindex=-1 -unit.1.6.port.0.s.6.visible=1 -unit.1.6.port.0.s.7.alias= -unit.1.6.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.7.name=TriggerPort0[7] -unit.1.6.port.0.s.7.orderindex=-1 -unit.1.6.port.0.s.7.visible=1 -unit.1.6.port.1.b.0.alias= -unit.1.6.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.b.0.name=TriggerPort1 -unit.1.6.port.1.b.0.orderindex=-1 -unit.1.6.port.1.b.0.radix=Hex -unit.1.6.port.1.b.0.signedOffset=0.0 -unit.1.6.port.1.b.0.signedPrecision=0 -unit.1.6.port.1.b.0.signedScaleFactor=1.0 -unit.1.6.port.1.b.0.unsignedOffset=0.0 -unit.1.6.port.1.b.0.unsignedPrecision=0 -unit.1.6.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.1.b.0.visible=1 -unit.1.6.port.1.buscount=1 -unit.1.6.port.1.channelcount=32 -unit.1.6.port.1.s.0.alias= -unit.1.6.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.0.name=TriggerPort1[0] -unit.1.6.port.1.s.0.orderindex=-1 -unit.1.6.port.1.s.0.visible=1 -unit.1.6.port.1.s.1.alias= -unit.1.6.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.1.name=TriggerPort1[1] -unit.1.6.port.1.s.1.orderindex=-1 -unit.1.6.port.1.s.1.visible=1 -unit.1.6.port.1.s.10.alias= -unit.1.6.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.10.name=TriggerPort1[10] -unit.1.6.port.1.s.10.orderindex=-1 -unit.1.6.port.1.s.10.visible=1 -unit.1.6.port.1.s.11.alias= -unit.1.6.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.11.name=TriggerPort1[11] -unit.1.6.port.1.s.11.orderindex=-1 -unit.1.6.port.1.s.11.visible=1 -unit.1.6.port.1.s.12.alias= -unit.1.6.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.12.name=TriggerPort1[12] -unit.1.6.port.1.s.12.orderindex=-1 -unit.1.6.port.1.s.12.visible=1 -unit.1.6.port.1.s.13.alias= -unit.1.6.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.13.name=TriggerPort1[13] -unit.1.6.port.1.s.13.orderindex=-1 -unit.1.6.port.1.s.13.visible=1 -unit.1.6.port.1.s.14.alias= -unit.1.6.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.14.name=TriggerPort1[14] -unit.1.6.port.1.s.14.orderindex=-1 -unit.1.6.port.1.s.14.visible=1 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-unit.1.6.port.1.s.28.name=TriggerPort1[28] -unit.1.6.port.1.s.28.orderindex=-1 -unit.1.6.port.1.s.28.visible=1 -unit.1.6.port.1.s.29.alias= -unit.1.6.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.29.name=TriggerPort1[29] -unit.1.6.port.1.s.29.orderindex=-1 -unit.1.6.port.1.s.29.visible=1 -unit.1.6.port.1.s.3.alias= -unit.1.6.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.3.name=TriggerPort1[3] -unit.1.6.port.1.s.3.orderindex=-1 -unit.1.6.port.1.s.3.visible=1 -unit.1.6.port.1.s.30.alias= -unit.1.6.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.30.name=TriggerPort1[30] -unit.1.6.port.1.s.30.orderindex=-1 -unit.1.6.port.1.s.30.visible=1 -unit.1.6.port.1.s.31.alias= -unit.1.6.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.31.name=TriggerPort1[31] -unit.1.6.port.1.s.31.orderindex=-1 -unit.1.6.port.1.s.31.visible=1 -unit.1.6.port.1.s.4.alias= -unit.1.6.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.4.name=TriggerPort1[4] -unit.1.6.port.1.s.4.orderindex=-1 -unit.1.6.port.1.s.4.visible=1 -unit.1.6.port.1.s.5.alias= -unit.1.6.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.5.name=TriggerPort1[5] -unit.1.6.port.1.s.5.orderindex=-1 -unit.1.6.port.1.s.5.visible=1 -unit.1.6.port.1.s.6.alias= -unit.1.6.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.6.name=TriggerPort1[6] -unit.1.6.port.1.s.6.orderindex=-1 -unit.1.6.port.1.s.6.visible=1 -unit.1.6.port.1.s.7.alias= -unit.1.6.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.7.name=TriggerPort1[7] -unit.1.6.port.1.s.7.orderindex=-1 -unit.1.6.port.1.s.7.visible=1 -unit.1.6.port.1.s.8.alias= -unit.1.6.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.8.name=TriggerPort1[8] -unit.1.6.port.1.s.8.orderindex=-1 -unit.1.6.port.1.s.8.visible=1 -unit.1.6.port.1.s.9.alias= -unit.1.6.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.9.name=TriggerPort1[9] -unit.1.6.port.1.s.9.orderindex=-1 -unit.1.6.port.1.s.9.visible=1 -unit.1.6.port.2.b.0.alias= -unit.1.6.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.b.0.name=TriggerPort2 -unit.1.6.port.2.b.0.orderindex=-1 -unit.1.6.port.2.b.0.radix=Hex -unit.1.6.port.2.b.0.signedOffset=0.0 -unit.1.6.port.2.b.0.signedPrecision=0 -unit.1.6.port.2.b.0.signedScaleFactor=1.0 -unit.1.6.port.2.b.0.unsignedOffset=0.0 -unit.1.6.port.2.b.0.unsignedPrecision=0 -unit.1.6.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.2.b.0.visible=1 -unit.1.6.port.2.buscount=1 -unit.1.6.port.2.channelcount=32 -unit.1.6.port.2.s.0.alias= -unit.1.6.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.0.name=TriggerPort2[0] -unit.1.6.port.2.s.0.orderindex=-1 -unit.1.6.port.2.s.0.visible=1 -unit.1.6.port.2.s.1.alias= -unit.1.6.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.1.name=TriggerPort2[1] -unit.1.6.port.2.s.1.orderindex=-1 -unit.1.6.port.2.s.1.visible=1 -unit.1.6.port.2.s.10.alias= -unit.1.6.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.10.name=TriggerPort2[10] -unit.1.6.port.2.s.10.orderindex=-1 -unit.1.6.port.2.s.10.visible=1 -unit.1.6.port.2.s.11.alias= -unit.1.6.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.11.name=TriggerPort2[11] -unit.1.6.port.2.s.11.orderindex=-1 -unit.1.6.port.2.s.11.visible=1 -unit.1.6.port.2.s.12.alias= -unit.1.6.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.12.name=TriggerPort2[12] -unit.1.6.port.2.s.12.orderindex=-1 -unit.1.6.port.2.s.12.visible=1 -unit.1.6.port.2.s.13.alias= -unit.1.6.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.13.name=TriggerPort2[13] -unit.1.6.port.2.s.13.orderindex=-1 -unit.1.6.port.2.s.13.visible=1 -unit.1.6.port.2.s.14.alias= -unit.1.6.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.14.name=TriggerPort2[14] -unit.1.6.port.2.s.14.orderindex=-1 -unit.1.6.port.2.s.14.visible=1 -unit.1.6.port.2.s.15.alias= -unit.1.6.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.15.name=TriggerPort2[15] -unit.1.6.port.2.s.15.orderindex=-1 -unit.1.6.port.2.s.15.visible=1 -unit.1.6.port.2.s.16.alias= -unit.1.6.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.16.name=TriggerPort2[16] -unit.1.6.port.2.s.16.orderindex=-1 -unit.1.6.port.2.s.16.visible=1 -unit.1.6.port.2.s.17.alias= -unit.1.6.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.17.name=TriggerPort2[17] -unit.1.6.port.2.s.17.orderindex=-1 -unit.1.6.port.2.s.17.visible=1 -unit.1.6.port.2.s.18.alias= -unit.1.6.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.18.name=TriggerPort2[18] -unit.1.6.port.2.s.18.orderindex=-1 -unit.1.6.port.2.s.18.visible=1 -unit.1.6.port.2.s.19.alias= -unit.1.6.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.19.name=TriggerPort2[19] -unit.1.6.port.2.s.19.orderindex=-1 -unit.1.6.port.2.s.19.visible=1 -unit.1.6.port.2.s.2.alias= -unit.1.6.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.2.name=TriggerPort2[2] -unit.1.6.port.2.s.2.orderindex=-1 -unit.1.6.port.2.s.2.visible=1 -unit.1.6.port.2.s.20.alias= -unit.1.6.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.20.name=TriggerPort2[20] -unit.1.6.port.2.s.20.orderindex=-1 -unit.1.6.port.2.s.20.visible=1 -unit.1.6.port.2.s.21.alias= -unit.1.6.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.21.name=TriggerPort2[21] -unit.1.6.port.2.s.21.orderindex=-1 -unit.1.6.port.2.s.21.visible=1 -unit.1.6.port.2.s.22.alias= -unit.1.6.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.22.name=TriggerPort2[22] -unit.1.6.port.2.s.22.orderindex=-1 -unit.1.6.port.2.s.22.visible=1 -unit.1.6.port.2.s.23.alias= -unit.1.6.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.23.name=TriggerPort2[23] -unit.1.6.port.2.s.23.orderindex=-1 -unit.1.6.port.2.s.23.visible=1 -unit.1.6.port.2.s.24.alias= -unit.1.6.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.24.name=TriggerPort2[24] -unit.1.6.port.2.s.24.orderindex=-1 -unit.1.6.port.2.s.24.visible=1 -unit.1.6.port.2.s.25.alias= -unit.1.6.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.25.name=TriggerPort2[25] -unit.1.6.port.2.s.25.orderindex=-1 -unit.1.6.port.2.s.25.visible=1 -unit.1.6.port.2.s.26.alias= -unit.1.6.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.26.name=TriggerPort2[26] -unit.1.6.port.2.s.26.orderindex=-1 -unit.1.6.port.2.s.26.visible=1 -unit.1.6.port.2.s.27.alias= -unit.1.6.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.27.name=TriggerPort2[27] -unit.1.6.port.2.s.27.orderindex=-1 -unit.1.6.port.2.s.27.visible=1 -unit.1.6.port.2.s.28.alias= -unit.1.6.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.28.name=TriggerPort2[28] -unit.1.6.port.2.s.28.orderindex=-1 -unit.1.6.port.2.s.28.visible=1 -unit.1.6.port.2.s.29.alias= -unit.1.6.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.29.name=TriggerPort2[29] -unit.1.6.port.2.s.29.orderindex=-1 -unit.1.6.port.2.s.29.visible=1 -unit.1.6.port.2.s.3.alias= -unit.1.6.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.3.name=TriggerPort2[3] -unit.1.6.port.2.s.3.orderindex=-1 -unit.1.6.port.2.s.3.visible=1 -unit.1.6.port.2.s.30.alias= -unit.1.6.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.30.name=TriggerPort2[30] -unit.1.6.port.2.s.30.orderindex=-1 -unit.1.6.port.2.s.30.visible=1 -unit.1.6.port.2.s.31.alias= -unit.1.6.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.31.name=TriggerPort2[31] -unit.1.6.port.2.s.31.orderindex=-1 -unit.1.6.port.2.s.31.visible=1 -unit.1.6.port.2.s.4.alias= -unit.1.6.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.4.name=TriggerPort2[4] -unit.1.6.port.2.s.4.orderindex=-1 -unit.1.6.port.2.s.4.visible=1 -unit.1.6.port.2.s.5.alias= -unit.1.6.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.5.name=TriggerPort2[5] -unit.1.6.port.2.s.5.orderindex=-1 -unit.1.6.port.2.s.5.visible=1 -unit.1.6.port.2.s.6.alias= -unit.1.6.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.6.name=TriggerPort2[6] -unit.1.6.port.2.s.6.orderindex=-1 -unit.1.6.port.2.s.6.visible=1 -unit.1.6.port.2.s.7.alias= -unit.1.6.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.7.name=TriggerPort2[7] -unit.1.6.port.2.s.7.orderindex=-1 -unit.1.6.port.2.s.7.visible=1 -unit.1.6.port.2.s.8.alias= -unit.1.6.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.8.name=TriggerPort2[8] -unit.1.6.port.2.s.8.orderindex=-1 -unit.1.6.port.2.s.8.visible=1 -unit.1.6.port.2.s.9.alias= -unit.1.6.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.9.name=TriggerPort2[9] -unit.1.6.port.2.s.9.orderindex=-1 -unit.1.6.port.2.s.9.visible=1 -unit.1.6.port.3.b.0.alias= -unit.1.6.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.b.0.name=TriggerPort3 -unit.1.6.port.3.b.0.orderindex=-1 -unit.1.6.port.3.b.0.radix=Hex -unit.1.6.port.3.b.0.signedOffset=0.0 -unit.1.6.port.3.b.0.signedPrecision=0 -unit.1.6.port.3.b.0.signedScaleFactor=1.0 -unit.1.6.port.3.b.0.unsignedOffset=0.0 -unit.1.6.port.3.b.0.unsignedPrecision=0 -unit.1.6.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.3.b.0.visible=1 -unit.1.6.port.3.buscount=1 -unit.1.6.port.3.channelcount=32 -unit.1.6.port.3.s.0.alias= -unit.1.6.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.0.name=TriggerPort3[0] -unit.1.6.port.3.s.0.orderindex=-1 -unit.1.6.port.3.s.0.visible=1 -unit.1.6.port.3.s.1.alias= -unit.1.6.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.1.name=TriggerPort3[1] -unit.1.6.port.3.s.1.orderindex=-1 -unit.1.6.port.3.s.1.visible=1 -unit.1.6.port.3.s.10.alias= -unit.1.6.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.10.name=TriggerPort3[10] -unit.1.6.port.3.s.10.orderindex=-1 -unit.1.6.port.3.s.10.visible=1 -unit.1.6.port.3.s.11.alias= -unit.1.6.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.11.name=TriggerPort3[11] -unit.1.6.port.3.s.11.orderindex=-1 -unit.1.6.port.3.s.11.visible=1 -unit.1.6.port.3.s.12.alias= -unit.1.6.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.12.name=TriggerPort3[12] -unit.1.6.port.3.s.12.orderindex=-1 -unit.1.6.port.3.s.12.visible=1 -unit.1.6.port.3.s.13.alias= -unit.1.6.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.13.name=TriggerPort3[13] -unit.1.6.port.3.s.13.orderindex=-1 -unit.1.6.port.3.s.13.visible=1 -unit.1.6.port.3.s.14.alias= -unit.1.6.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.14.name=TriggerPort3[14] -unit.1.6.port.3.s.14.orderindex=-1 -unit.1.6.port.3.s.14.visible=1 -unit.1.6.port.3.s.15.alias= -unit.1.6.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.15.name=TriggerPort3[15] -unit.1.6.port.3.s.15.orderindex=-1 -unit.1.6.port.3.s.15.visible=1 -unit.1.6.port.3.s.16.alias= -unit.1.6.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.16.name=TriggerPort3[16] -unit.1.6.port.3.s.16.orderindex=-1 -unit.1.6.port.3.s.16.visible=1 -unit.1.6.port.3.s.17.alias= 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-unit.1.6.waveform.posn.10.name=DataPort[6] -unit.1.6.waveform.posn.10.type=signal -unit.1.6.waveform.posn.11.channel=7 -unit.1.6.waveform.posn.11.name=DataPort[7] -unit.1.6.waveform.posn.11.type=signal -unit.1.6.waveform.posn.12.channel=34 -unit.1.6.waveform.posn.12.name=DataPort[34] -unit.1.6.waveform.posn.12.type=signal -unit.1.6.waveform.posn.13.channel=35 -unit.1.6.waveform.posn.13.name=DataPort[35] -unit.1.6.waveform.posn.13.type=signal -unit.1.6.waveform.posn.14.channel=36 -unit.1.6.waveform.posn.14.name=DataPort[36] -unit.1.6.waveform.posn.14.type=signal -unit.1.6.waveform.posn.15.channel=37 -unit.1.6.waveform.posn.15.name=DataPort[37] -unit.1.6.waveform.posn.15.type=signal -unit.1.6.waveform.posn.16.channel=38 -unit.1.6.waveform.posn.16.name=DataPort[38] -unit.1.6.waveform.posn.16.type=signal -unit.1.6.waveform.posn.17.channel=39 -unit.1.6.waveform.posn.17.name=DataPort[39] -unit.1.6.waveform.posn.17.type=signal -unit.1.6.waveform.posn.18.channel=67 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-unit.1.6.waveform.posn.25.channel=100 -unit.1.6.waveform.posn.25.name=DataPort[100] -unit.1.6.waveform.posn.25.type=signal -unit.1.6.waveform.posn.26.channel=101 -unit.1.6.waveform.posn.26.name=DataPort[101] -unit.1.6.waveform.posn.26.type=signal -unit.1.6.waveform.posn.27.channel=102 -unit.1.6.waveform.posn.27.name=DataPort[102] -unit.1.6.waveform.posn.27.type=signal -unit.1.6.waveform.posn.28.channel=103 -unit.1.6.waveform.posn.28.name=DataPort[103] -unit.1.6.waveform.posn.28.type=signal -unit.1.6.waveform.posn.29.channel=130 -unit.1.6.waveform.posn.29.name=DataPort[130] -unit.1.6.waveform.posn.29.type=signal -unit.1.6.waveform.posn.3.channel=2147483646 -unit.1.6.waveform.posn.3.name=dsp_monit_amp_ch0 -unit.1.6.waveform.posn.3.radix=3 -unit.1.6.waveform.posn.3.type=bus -unit.1.6.waveform.posn.30.channel=131 -unit.1.6.waveform.posn.30.name=DataPort[131] -unit.1.6.waveform.posn.30.type=signal -unit.1.6.waveform.posn.31.channel=132 -unit.1.6.waveform.posn.31.name=DataPort[132] -unit.1.6.waveform.posn.31.radix=3 -unit.1.6.waveform.posn.31.type=signal -unit.1.6.waveform.posn.32.channel=133 -unit.1.6.waveform.posn.32.name=DataPort[133] -unit.1.6.waveform.posn.32.radix=3 -unit.1.6.waveform.posn.32.type=signal -unit.1.6.waveform.posn.33.channel=134 -unit.1.6.waveform.posn.33.name=DataPort[134] -unit.1.6.waveform.posn.33.radix=3 -unit.1.6.waveform.posn.33.type=signal -unit.1.6.waveform.posn.34.channel=135 -unit.1.6.waveform.posn.34.name=DataPort[135] -unit.1.6.waveform.posn.34.radix=3 -unit.1.6.waveform.posn.34.type=signal -unit.1.6.waveform.posn.35.channel=2147483646 -unit.1.6.waveform.posn.35.name=dsp_y_monit -unit.1.6.waveform.posn.35.radix=3 -unit.1.6.waveform.posn.35.type=bus -unit.1.6.waveform.posn.36.channel=2147483646 -unit.1.6.waveform.posn.36.name=dsp_y_monit -unit.1.6.waveform.posn.36.radix=3 -unit.1.6.waveform.posn.36.type=bus -unit.1.6.waveform.posn.37.channel=2147483646 -unit.1.6.waveform.posn.37.name=dsp_y_monit -unit.1.6.waveform.posn.37.radix=3 -unit.1.6.waveform.posn.37.type=bus -unit.1.6.waveform.posn.38.channel=2147483646 -unit.1.6.waveform.posn.38.name=dsp_y_monit -unit.1.6.waveform.posn.38.radix=3 -unit.1.6.waveform.posn.38.type=bus -unit.1.6.waveform.posn.39.channel=2147483646 -unit.1.6.waveform.posn.39.name=dsp_y_monit -unit.1.6.waveform.posn.39.radix=3 -unit.1.6.waveform.posn.39.type=bus -unit.1.6.waveform.posn.4.channel=0 -unit.1.6.waveform.posn.4.name=DataPort[0] -unit.1.6.waveform.posn.4.type=signal -unit.1.6.waveform.posn.40.channel=2147483646 -unit.1.6.waveform.posn.40.name=dsp_y_monit -unit.1.6.waveform.posn.40.radix=3 -unit.1.6.waveform.posn.40.type=bus -unit.1.6.waveform.posn.41.channel=2147483646 -unit.1.6.waveform.posn.41.name=dsp_y_monit -unit.1.6.waveform.posn.41.radix=3 -unit.1.6.waveform.posn.41.type=bus -unit.1.6.waveform.posn.42.channel=2147483646 -unit.1.6.waveform.posn.42.name=dsp_y_monit -unit.1.6.waveform.posn.42.radix=3 -unit.1.6.waveform.posn.42.type=bus -unit.1.6.waveform.posn.43.channel=2147483646 -unit.1.6.waveform.posn.43.name=dsp_y_monit -unit.1.6.waveform.posn.43.radix=3 -unit.1.6.waveform.posn.43.type=bus -unit.1.6.waveform.posn.44.channel=2147483646 -unit.1.6.waveform.posn.44.name=dsp_y_monit -unit.1.6.waveform.posn.44.radix=3 -unit.1.6.waveform.posn.44.type=bus -unit.1.6.waveform.posn.45.channel=2147483646 -unit.1.6.waveform.posn.45.name=dsp_y_monit -unit.1.6.waveform.posn.45.radix=3 -unit.1.6.waveform.posn.45.type=bus -unit.1.6.waveform.posn.46.channel=2147483646 -unit.1.6.waveform.posn.46.name=dsp_y_monit -unit.1.6.waveform.posn.46.radix=3 -unit.1.6.waveform.posn.46.type=bus -unit.1.6.waveform.posn.5.channel=1 -unit.1.6.waveform.posn.5.name=DataPort[1] -unit.1.6.waveform.posn.5.type=signal -unit.1.6.waveform.posn.6.channel=2 -unit.1.6.waveform.posn.6.name=DataPort[2] -unit.1.6.waveform.posn.6.type=signal -unit.1.6.waveform.posn.7.channel=3 -unit.1.6.waveform.posn.7.name=DataPort[3] -unit.1.6.waveform.posn.7.type=signal -unit.1.6.waveform.posn.8.channel=4 -unit.1.6.waveform.posn.8.name=DataPort[4] -unit.1.6.waveform.posn.8.type=signal -unit.1.6.waveform.posn.9.channel=5 -unit.1.6.waveform.posn.9.name=DataPort[5] -unit.1.6.waveform.posn.9.type=signal -unit.1.7.0.HEIGHT0=0.4027778 -unit.1.7.0.TriggerRow0=1 -unit.1.7.0.TriggerRow1=1 -unit.1.7.0.TriggerRow2=1 -unit.1.7.0.WIDTH0=0.68065965 -unit.1.7.0.X0=0.13193403 -unit.1.7.0.Y0=0.0 -unit.1.7.1.HEIGHT1=0.8134206 -unit.1.7.1.WIDTH1=0.5513308 -unit.1.7.1.X1=0.082889736 -unit.1.7.1.Y1=0.0883797 -unit.1.7.2.HEIGHT2=0.8130081 -unit.1.7.2.WIDTH2=0.627094 -unit.1.7.2.X2=0.5243991 -unit.1.7.2.Y2=0.9756098 -unit.1.7.5.HEIGHT5=0.9517134 -unit.1.7.5.WIDTH5=0.99774945 -unit.1.7.5.X5=0.0 -unit.1.7.5.Y5=0.0 -unit.1.7.MFBitsA0=1XXXXXXX -unit.1.7.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.7.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.7.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.7.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.7.MFBitsB0=00000000 -unit.1.7.MFBitsB1=00000000000000000000000000000000 -unit.1.7.MFBitsB2=00000000000000000000000000000000 -unit.1.7.MFBitsB3=00000000000000000000000000000000 -unit.1.7.MFBitsB4=00000000000000000000000000000000 -unit.1.7.MFCompareA0=0 -unit.1.7.MFCompareA1=0 -unit.1.7.MFCompareA2=0 -unit.1.7.MFCompareA3=0 -unit.1.7.MFCompareA4=0 -unit.1.7.MFCompareB0=999 -unit.1.7.MFCompareB1=999 -unit.1.7.MFCompareB2=999 -unit.1.7.MFCompareB3=999 -unit.1.7.MFCompareB4=999 -unit.1.7.MFCount=5 -unit.1.7.MFDisplay0=0 -unit.1.7.MFDisplay1=0 -unit.1.7.MFDisplay2=0 -unit.1.7.MFDisplay3=0 -unit.1.7.MFDisplay4=0 -unit.1.7.MFEventType0=3 -unit.1.7.MFEventType1=3 -unit.1.7.MFEventType2=3 -unit.1.7.MFEventType3=3 -unit.1.7.MFEventType4=3 -unit.1.7.RunMode=SINGLE RUN -unit.1.7.SQCondition=M0 -unit.1.7.SQContiguous0=0 -unit.1.7.SequencerOn=0 -unit.1.7.TCActive=0 -unit.1.7.TCAdvanced0=0 -unit.1.7.TCCondition0_0=M0 -unit.1.7.TCCondition0_1= -unit.1.7.TCConditionType0=0 -unit.1.7.TCCount=1 -unit.1.7.TCEventCount0=1 -unit.1.7.TCEventType0=3 -unit.1.7.TCName0=TriggerCondition0 -unit.1.7.TCOutputEnable0=0 -unit.1.7.TCOutputHigh0=1 -unit.1.7.TCOutputMode0=0 -unit.1.7.browser_tree_state=1 -unit.1.7.browser_tree_state=0 -unit.1.7.browser_tree_state=0 -unit.1.7.browser_tree_state=0 -unit.1.7.browser_tree_state=0 -unit.1.7.coretype=ILA -unit.1.7.eventCount0=1 -unit.1.7.eventCount1=1 -unit.1.7.eventCount2=1 -unit.1.7.eventCount3=1 -unit.1.7.eventCount4=1 -unit.1.7.export.format=2 -unit.1.7.export.signals=Bus Plot Buses -unit.1.7.export.unitName=DEV\:1 MyDevice1 (XC6VLX240T) UNIT\:7 MyILA7 (ILA) -unit.1.7.listing.count=0 -unit.1.7.plotBusColor0=-16777092 -unit.1.7.plotBusColor1=-3355648 -unit.1.7.plotBusColor2=-16750849 -unit.1.7.plotBusColor3=-52480 -unit.1.7.plotBusCount=4 -unit.1.7.plotBusName0=dsp_q_monit -unit.1.7.plotBusName1=dsp_sum_monit -unit.1.7.plotBusName2=dsp_x_monit -unit.1.7.plotBusName3=dsp_y_monit -unit.1.7.plotBusX=dsp_q_monit -unit.1.7.plotBusY=dsp_sum_monit -unit.1.7.plotDataTimeMode=1 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-unit.1.7.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.7.port.-1.b.1.name=DataPort -unit.1.7.port.-1.b.1.orderindex=-1 -unit.1.7.port.-1.b.1.radix=Signed -unit.1.7.port.-1.b.1.signedOffset=0.0 -unit.1.7.port.-1.b.1.signedPrecision=0 -unit.1.7.port.-1.b.1.signedScaleFactor=1.0 -unit.1.7.port.-1.b.1.tokencount=0 -unit.1.7.port.-1.b.1.unsignedOffset=0.0 -unit.1.7.port.-1.b.1.unsignedPrecision=0 -unit.1.7.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.7.port.-1.b.1.visible=1 -unit.1.7.port.-1.b.2.alias=dsp_x_monit -unit.1.7.port.-1.b.2.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 -unit.1.7.port.-1.b.2.color=java.awt.Color[r\=0,g\=102,b\=255] -unit.1.7.port.-1.b.2.name=DataPort -unit.1.7.port.-1.b.2.orderindex=-1 -unit.1.7.port.-1.b.2.radix=Signed -unit.1.7.port.-1.b.2.signedOffset=0.0 -unit.1.7.port.-1.b.2.signedPrecision=0 -unit.1.7.port.-1.b.2.signedScaleFactor=1.0 -unit.1.7.port.-1.b.2.tokencount=0 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-unit.1.7.port.0.s.0.alias= -unit.1.7.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.0.name=TriggerPort0[0] -unit.1.7.port.0.s.0.orderindex=-1 -unit.1.7.port.0.s.0.visible=1 -unit.1.7.port.0.s.1.alias= -unit.1.7.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.1.name=TriggerPort0[1] -unit.1.7.port.0.s.1.orderindex=-1 -unit.1.7.port.0.s.1.visible=1 -unit.1.7.port.0.s.2.alias= -unit.1.7.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.2.name=TriggerPort0[2] -unit.1.7.port.0.s.2.orderindex=-1 -unit.1.7.port.0.s.2.visible=1 -unit.1.7.port.0.s.3.alias= -unit.1.7.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.3.name=TriggerPort0[3] -unit.1.7.port.0.s.3.orderindex=-1 -unit.1.7.port.0.s.3.visible=1 -unit.1.7.port.0.s.4.alias= -unit.1.7.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.4.name=TriggerPort0[4] -unit.1.7.port.0.s.4.orderindex=-1 -unit.1.7.port.0.s.4.visible=1 -unit.1.7.port.0.s.5.alias= -unit.1.7.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.5.name=TriggerPort0[5] -unit.1.7.port.0.s.5.orderindex=-1 -unit.1.7.port.0.s.5.visible=1 -unit.1.7.port.0.s.6.alias= -unit.1.7.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.6.name=TriggerPort0[6] -unit.1.7.port.0.s.6.orderindex=-1 -unit.1.7.port.0.s.6.visible=1 -unit.1.7.port.0.s.7.alias= -unit.1.7.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.0.s.7.name=TriggerPort0[7] -unit.1.7.port.0.s.7.orderindex=-1 -unit.1.7.port.0.s.7.visible=1 -unit.1.7.port.1.b.0.alias= -unit.1.7.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.7.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.b.0.name=TriggerPort1 -unit.1.7.port.1.b.0.orderindex=-1 -unit.1.7.port.1.b.0.radix=Hex -unit.1.7.port.1.b.0.signedOffset=0.0 -unit.1.7.port.1.b.0.signedPrecision=0 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-unit.1.7.port.1.s.11.orderindex=-1 -unit.1.7.port.1.s.11.visible=1 -unit.1.7.port.1.s.12.alias= -unit.1.7.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.12.name=TriggerPort1[12] -unit.1.7.port.1.s.12.orderindex=-1 -unit.1.7.port.1.s.12.visible=1 -unit.1.7.port.1.s.13.alias= -unit.1.7.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.13.name=TriggerPort1[13] -unit.1.7.port.1.s.13.orderindex=-1 -unit.1.7.port.1.s.13.visible=1 -unit.1.7.port.1.s.14.alias= -unit.1.7.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.14.name=TriggerPort1[14] -unit.1.7.port.1.s.14.orderindex=-1 -unit.1.7.port.1.s.14.visible=1 -unit.1.7.port.1.s.15.alias= -unit.1.7.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.15.name=TriggerPort1[15] -unit.1.7.port.1.s.15.orderindex=-1 -unit.1.7.port.1.s.15.visible=1 -unit.1.7.port.1.s.16.alias= -unit.1.7.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.16.name=TriggerPort1[16] -unit.1.7.port.1.s.16.orderindex=-1 -unit.1.7.port.1.s.16.visible=1 -unit.1.7.port.1.s.17.alias= -unit.1.7.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.17.name=TriggerPort1[17] -unit.1.7.port.1.s.17.orderindex=-1 -unit.1.7.port.1.s.17.visible=1 -unit.1.7.port.1.s.18.alias= -unit.1.7.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.18.name=TriggerPort1[18] -unit.1.7.port.1.s.18.orderindex=-1 -unit.1.7.port.1.s.18.visible=1 -unit.1.7.port.1.s.19.alias= -unit.1.7.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.19.name=TriggerPort1[19] -unit.1.7.port.1.s.19.orderindex=-1 -unit.1.7.port.1.s.19.visible=1 -unit.1.7.port.1.s.2.alias= -unit.1.7.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.2.name=TriggerPort1[2] -unit.1.7.port.1.s.2.orderindex=-1 -unit.1.7.port.1.s.2.visible=1 -unit.1.7.port.1.s.20.alias= -unit.1.7.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.20.name=TriggerPort1[20] -unit.1.7.port.1.s.20.orderindex=-1 -unit.1.7.port.1.s.20.visible=1 -unit.1.7.port.1.s.21.alias= -unit.1.7.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.21.name=TriggerPort1[21] -unit.1.7.port.1.s.21.orderindex=-1 -unit.1.7.port.1.s.21.visible=1 -unit.1.7.port.1.s.22.alias= -unit.1.7.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.22.name=TriggerPort1[22] -unit.1.7.port.1.s.22.orderindex=-1 -unit.1.7.port.1.s.22.visible=1 -unit.1.7.port.1.s.23.alias= -unit.1.7.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.23.name=TriggerPort1[23] -unit.1.7.port.1.s.23.orderindex=-1 -unit.1.7.port.1.s.23.visible=1 -unit.1.7.port.1.s.24.alias= -unit.1.7.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.24.name=TriggerPort1[24] -unit.1.7.port.1.s.24.orderindex=-1 -unit.1.7.port.1.s.24.visible=1 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-unit.1.7.port.1.s.29.visible=1 -unit.1.7.port.1.s.3.alias= -unit.1.7.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.3.name=TriggerPort1[3] -unit.1.7.port.1.s.3.orderindex=-1 -unit.1.7.port.1.s.3.visible=1 -unit.1.7.port.1.s.30.alias= -unit.1.7.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.30.name=TriggerPort1[30] -unit.1.7.port.1.s.30.orderindex=-1 -unit.1.7.port.1.s.30.visible=1 -unit.1.7.port.1.s.31.alias= -unit.1.7.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.31.name=TriggerPort1[31] -unit.1.7.port.1.s.31.orderindex=-1 -unit.1.7.port.1.s.31.visible=1 -unit.1.7.port.1.s.4.alias= -unit.1.7.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.4.name=TriggerPort1[4] -unit.1.7.port.1.s.4.orderindex=-1 -unit.1.7.port.1.s.4.visible=1 -unit.1.7.port.1.s.5.alias= -unit.1.7.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.5.name=TriggerPort1[5] -unit.1.7.port.1.s.5.orderindex=-1 -unit.1.7.port.1.s.5.visible=1 -unit.1.7.port.1.s.6.alias= -unit.1.7.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.6.name=TriggerPort1[6] -unit.1.7.port.1.s.6.orderindex=-1 -unit.1.7.port.1.s.6.visible=1 -unit.1.7.port.1.s.7.alias= -unit.1.7.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.7.name=TriggerPort1[7] -unit.1.7.port.1.s.7.orderindex=-1 -unit.1.7.port.1.s.7.visible=1 -unit.1.7.port.1.s.8.alias= -unit.1.7.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.8.name=TriggerPort1[8] -unit.1.7.port.1.s.8.orderindex=-1 -unit.1.7.port.1.s.8.visible=1 -unit.1.7.port.1.s.9.alias= -unit.1.7.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.1.s.9.name=TriggerPort1[9] -unit.1.7.port.1.s.9.orderindex=-1 -unit.1.7.port.1.s.9.visible=1 -unit.1.7.port.2.b.0.alias= -unit.1.7.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.7.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.b.0.name=TriggerPort2 -unit.1.7.port.2.b.0.orderindex=-1 -unit.1.7.port.2.b.0.radix=Hex -unit.1.7.port.2.b.0.signedOffset=0.0 -unit.1.7.port.2.b.0.signedPrecision=0 -unit.1.7.port.2.b.0.signedScaleFactor=1.0 -unit.1.7.port.2.b.0.unsignedOffset=0.0 -unit.1.7.port.2.b.0.unsignedPrecision=0 -unit.1.7.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.7.port.2.b.0.visible=1 -unit.1.7.port.2.buscount=1 -unit.1.7.port.2.channelcount=32 -unit.1.7.port.2.s.0.alias= -unit.1.7.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.0.name=TriggerPort2[0] -unit.1.7.port.2.s.0.orderindex=-1 -unit.1.7.port.2.s.0.visible=1 -unit.1.7.port.2.s.1.alias= -unit.1.7.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.1.name=TriggerPort2[1] -unit.1.7.port.2.s.1.orderindex=-1 -unit.1.7.port.2.s.1.visible=1 -unit.1.7.port.2.s.10.alias= -unit.1.7.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.10.name=TriggerPort2[10] -unit.1.7.port.2.s.10.orderindex=-1 -unit.1.7.port.2.s.10.visible=1 -unit.1.7.port.2.s.11.alias= -unit.1.7.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.11.name=TriggerPort2[11] -unit.1.7.port.2.s.11.orderindex=-1 -unit.1.7.port.2.s.11.visible=1 -unit.1.7.port.2.s.12.alias= -unit.1.7.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.12.name=TriggerPort2[12] -unit.1.7.port.2.s.12.orderindex=-1 -unit.1.7.port.2.s.12.visible=1 -unit.1.7.port.2.s.13.alias= -unit.1.7.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.13.name=TriggerPort2[13] -unit.1.7.port.2.s.13.orderindex=-1 -unit.1.7.port.2.s.13.visible=1 -unit.1.7.port.2.s.14.alias= -unit.1.7.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.14.name=TriggerPort2[14] -unit.1.7.port.2.s.14.orderindex=-1 -unit.1.7.port.2.s.14.visible=1 -unit.1.7.port.2.s.15.alias= -unit.1.7.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.15.name=TriggerPort2[15] -unit.1.7.port.2.s.15.orderindex=-1 -unit.1.7.port.2.s.15.visible=1 -unit.1.7.port.2.s.16.alias= -unit.1.7.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.16.name=TriggerPort2[16] -unit.1.7.port.2.s.16.orderindex=-1 -unit.1.7.port.2.s.16.visible=1 -unit.1.7.port.2.s.17.alias= -unit.1.7.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.17.name=TriggerPort2[17] -unit.1.7.port.2.s.17.orderindex=-1 -unit.1.7.port.2.s.17.visible=1 -unit.1.7.port.2.s.18.alias= -unit.1.7.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.18.name=TriggerPort2[18] -unit.1.7.port.2.s.18.orderindex=-1 -unit.1.7.port.2.s.18.visible=1 -unit.1.7.port.2.s.19.alias= -unit.1.7.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.19.name=TriggerPort2[19] -unit.1.7.port.2.s.19.orderindex=-1 -unit.1.7.port.2.s.19.visible=1 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-unit.1.7.port.2.s.28.orderindex=-1 -unit.1.7.port.2.s.28.visible=1 -unit.1.7.port.2.s.29.alias= -unit.1.7.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.29.name=TriggerPort2[29] -unit.1.7.port.2.s.29.orderindex=-1 -unit.1.7.port.2.s.29.visible=1 -unit.1.7.port.2.s.3.alias= -unit.1.7.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.3.name=TriggerPort2[3] -unit.1.7.port.2.s.3.orderindex=-1 -unit.1.7.port.2.s.3.visible=1 -unit.1.7.port.2.s.30.alias= -unit.1.7.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.30.name=TriggerPort2[30] -unit.1.7.port.2.s.30.orderindex=-1 -unit.1.7.port.2.s.30.visible=1 -unit.1.7.port.2.s.31.alias= -unit.1.7.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.31.name=TriggerPort2[31] -unit.1.7.port.2.s.31.orderindex=-1 -unit.1.7.port.2.s.31.visible=1 -unit.1.7.port.2.s.4.alias= -unit.1.7.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.4.name=TriggerPort2[4] -unit.1.7.port.2.s.4.orderindex=-1 -unit.1.7.port.2.s.4.visible=1 -unit.1.7.port.2.s.5.alias= -unit.1.7.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.5.name=TriggerPort2[5] -unit.1.7.port.2.s.5.orderindex=-1 -unit.1.7.port.2.s.5.visible=1 -unit.1.7.port.2.s.6.alias= -unit.1.7.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.6.name=TriggerPort2[6] -unit.1.7.port.2.s.6.orderindex=-1 -unit.1.7.port.2.s.6.visible=1 -unit.1.7.port.2.s.7.alias= -unit.1.7.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.7.name=TriggerPort2[7] -unit.1.7.port.2.s.7.orderindex=-1 -unit.1.7.port.2.s.7.visible=1 -unit.1.7.port.2.s.8.alias= -unit.1.7.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.8.name=TriggerPort2[8] -unit.1.7.port.2.s.8.orderindex=-1 -unit.1.7.port.2.s.8.visible=1 -unit.1.7.port.2.s.9.alias= -unit.1.7.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.2.s.9.name=TriggerPort2[9] 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-unit.1.7.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.14.name=TriggerPort3[14] -unit.1.7.port.3.s.14.orderindex=-1 -unit.1.7.port.3.s.14.visible=1 -unit.1.7.port.3.s.15.alias= -unit.1.7.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.15.name=TriggerPort3[15] -unit.1.7.port.3.s.15.orderindex=-1 -unit.1.7.port.3.s.15.visible=1 -unit.1.7.port.3.s.16.alias= -unit.1.7.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.16.name=TriggerPort3[16] -unit.1.7.port.3.s.16.orderindex=-1 -unit.1.7.port.3.s.16.visible=1 -unit.1.7.port.3.s.17.alias= -unit.1.7.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.17.name=TriggerPort3[17] -unit.1.7.port.3.s.17.orderindex=-1 -unit.1.7.port.3.s.17.visible=1 -unit.1.7.port.3.s.18.alias= -unit.1.7.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.7.port.3.s.18.name=TriggerPort3[18] -unit.1.7.port.3.s.18.orderindex=-1 -unit.1.7.port.3.s.18.visible=1 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-unit.1.7.waveform.posn.9.name=dsp_y_monit -unit.1.7.waveform.posn.9.radix=3 -unit.1.7.waveform.posn.9.type=bus -unit.1.8.0.HEIGHT0=0.62305295 -unit.1.8.0.TriggerRow0=1 -unit.1.8.0.TriggerRow1=1 -unit.1.8.0.TriggerRow2=1 -unit.1.8.0.WIDTH0=0.8604651 -unit.1.8.0.X0=0.13953489 -unit.1.8.0.Y0=0.0 -unit.1.8.1.HEIGHT1=1.0 -unit.1.8.1.WIDTH1=1.0 -unit.1.8.1.X1=0.0 -unit.1.8.1.Y1=0.0 -unit.1.8.2.HEIGHT2=0.8183306 -unit.1.8.2.WIDTH2=0.5669173 -unit.1.8.2.X2=0.007518797 -unit.1.8.2.Y2=0.016366612 -unit.1.8.5.HEIGHT5=1.0 -unit.1.8.5.WIDTH5=1.0 -unit.1.8.5.X5=0.0 -unit.1.8.5.Y5=0.0 -unit.1.8.6.HEIGHT6=0.8130081 -unit.1.8.6.WIDTH6=0.69701385 -unit.1.8.6.X6=0.1427531 -unit.1.8.6.Y6=0.10081301 -unit.1.8.MFBitsA0=1XXXXXXX -unit.1.8.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.8.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.8.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.8.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.8.MFBitsB0=00000000 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-unit.1.8.TCEventType0=3 -unit.1.8.TCName0=TriggerCondition0 -unit.1.8.TCOutputEnable0=0 -unit.1.8.TCOutputHigh0=1 -unit.1.8.TCOutputMode0=0 -unit.1.8.browser_tree_state=1 -unit.1.8.browser_tree_state=1 -unit.1.8.browser_tree_state=0 -unit.1.8.browser_tree_state=0 -unit.1.8.browser_tree_state=1 -unit.1.8.coretype=ILA -unit.1.8.eventCount0=1 -unit.1.8.eventCount1=1 -unit.1.8.eventCount2=1 -unit.1.8.eventCount3=1 -unit.1.8.eventCount4=1 -unit.1.8.listing.count=0 -unit.1.8.plotBusColor0=-10066177 -unit.1.8.plotBusColor1=-3355648 -unit.1.8.plotBusColor2=-16777012 -unit.1.8.plotBusColor3=-65536 -unit.1.8.plotBusCount=4 -unit.1.8.plotBusName0=dsp_q_monit_1 -unit.1.8.plotBusName1=dsp_sum_monit_1 -unit.1.8.plotBusName2=dsp_x_monit_1 -unit.1.8.plotBusName3=dsp_y_monit_1 -unit.1.8.plotBusX=dsp_q_monit_1 -unit.1.8.plotBusY=dsp_sum_monit_1 -unit.1.8.plotDataTimeMode=1 -unit.1.8.plotDisplayMode=line -unit.1.8.plotMaxX=0.0 -unit.1.8.plotMaxY=0.0 -unit.1.8.plotMinX=0.0 -unit.1.8.plotMinY=0.0 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-unit.1.8.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.14.name=TriggerPort2[14] -unit.1.8.port.2.s.14.orderindex=-1 -unit.1.8.port.2.s.14.visible=1 -unit.1.8.port.2.s.15.alias= -unit.1.8.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.15.name=TriggerPort2[15] -unit.1.8.port.2.s.15.orderindex=-1 -unit.1.8.port.2.s.15.visible=1 -unit.1.8.port.2.s.16.alias= -unit.1.8.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.16.name=TriggerPort2[16] -unit.1.8.port.2.s.16.orderindex=-1 -unit.1.8.port.2.s.16.visible=1 -unit.1.8.port.2.s.17.alias= -unit.1.8.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.17.name=TriggerPort2[17] -unit.1.8.port.2.s.17.orderindex=-1 -unit.1.8.port.2.s.17.visible=1 -unit.1.8.port.2.s.18.alias= -unit.1.8.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.18.name=TriggerPort2[18] -unit.1.8.port.2.s.18.orderindex=-1 -unit.1.8.port.2.s.18.visible=1 -unit.1.8.port.2.s.19.alias= -unit.1.8.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.19.name=TriggerPort2[19] -unit.1.8.port.2.s.19.orderindex=-1 -unit.1.8.port.2.s.19.visible=1 -unit.1.8.port.2.s.2.alias= -unit.1.8.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.2.name=TriggerPort2[2] -unit.1.8.port.2.s.2.orderindex=-1 -unit.1.8.port.2.s.2.visible=1 -unit.1.8.port.2.s.20.alias= -unit.1.8.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.20.name=TriggerPort2[20] -unit.1.8.port.2.s.20.orderindex=-1 -unit.1.8.port.2.s.20.visible=1 -unit.1.8.port.2.s.21.alias= -unit.1.8.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.21.name=TriggerPort2[21] -unit.1.8.port.2.s.21.orderindex=-1 -unit.1.8.port.2.s.21.visible=1 -unit.1.8.port.2.s.22.alias= -unit.1.8.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.22.name=TriggerPort2[22] -unit.1.8.port.2.s.22.orderindex=-1 -unit.1.8.port.2.s.22.visible=1 -unit.1.8.port.2.s.23.alias= -unit.1.8.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.23.name=TriggerPort2[23] -unit.1.8.port.2.s.23.orderindex=-1 -unit.1.8.port.2.s.23.visible=1 -unit.1.8.port.2.s.24.alias= -unit.1.8.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.24.name=TriggerPort2[24] -unit.1.8.port.2.s.24.orderindex=-1 -unit.1.8.port.2.s.24.visible=1 -unit.1.8.port.2.s.25.alias= -unit.1.8.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.25.name=TriggerPort2[25] -unit.1.8.port.2.s.25.orderindex=-1 -unit.1.8.port.2.s.25.visible=1 -unit.1.8.port.2.s.26.alias= -unit.1.8.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.26.name=TriggerPort2[26] -unit.1.8.port.2.s.26.orderindex=-1 -unit.1.8.port.2.s.26.visible=1 -unit.1.8.port.2.s.27.alias= -unit.1.8.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.27.name=TriggerPort2[27] -unit.1.8.port.2.s.27.orderindex=-1 -unit.1.8.port.2.s.27.visible=1 -unit.1.8.port.2.s.28.alias= -unit.1.8.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.28.name=TriggerPort2[28] -unit.1.8.port.2.s.28.orderindex=-1 -unit.1.8.port.2.s.28.visible=1 -unit.1.8.port.2.s.29.alias= -unit.1.8.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.29.name=TriggerPort2[29] -unit.1.8.port.2.s.29.orderindex=-1 -unit.1.8.port.2.s.29.visible=1 -unit.1.8.port.2.s.3.alias= -unit.1.8.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.3.name=TriggerPort2[3] -unit.1.8.port.2.s.3.orderindex=-1 -unit.1.8.port.2.s.3.visible=1 -unit.1.8.port.2.s.30.alias= -unit.1.8.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.30.name=TriggerPort2[30] -unit.1.8.port.2.s.30.orderindex=-1 -unit.1.8.port.2.s.30.visible=1 -unit.1.8.port.2.s.31.alias= -unit.1.8.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.31.name=TriggerPort2[31] -unit.1.8.port.2.s.31.orderindex=-1 -unit.1.8.port.2.s.31.visible=1 -unit.1.8.port.2.s.4.alias= -unit.1.8.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.4.name=TriggerPort2[4] -unit.1.8.port.2.s.4.orderindex=-1 -unit.1.8.port.2.s.4.visible=1 -unit.1.8.port.2.s.5.alias= -unit.1.8.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.5.name=TriggerPort2[5] -unit.1.8.port.2.s.5.orderindex=-1 -unit.1.8.port.2.s.5.visible=1 -unit.1.8.port.2.s.6.alias= -unit.1.8.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.6.name=TriggerPort2[6] -unit.1.8.port.2.s.6.orderindex=-1 -unit.1.8.port.2.s.6.visible=1 -unit.1.8.port.2.s.7.alias= -unit.1.8.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.7.name=TriggerPort2[7] -unit.1.8.port.2.s.7.orderindex=-1 -unit.1.8.port.2.s.7.visible=1 -unit.1.8.port.2.s.8.alias= -unit.1.8.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.8.name=TriggerPort2[8] -unit.1.8.port.2.s.8.orderindex=-1 -unit.1.8.port.2.s.8.visible=1 -unit.1.8.port.2.s.9.alias= -unit.1.8.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.2.s.9.name=TriggerPort2[9] -unit.1.8.port.2.s.9.orderindex=-1 -unit.1.8.port.2.s.9.visible=1 -unit.1.8.port.3.b.0.alias= -unit.1.8.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.8.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.b.0.name=TriggerPort3 -unit.1.8.port.3.b.0.orderindex=-1 -unit.1.8.port.3.b.0.radix=Hex -unit.1.8.port.3.b.0.signedOffset=0.0 -unit.1.8.port.3.b.0.signedPrecision=0 -unit.1.8.port.3.b.0.signedScaleFactor=1.0 -unit.1.8.port.3.b.0.unsignedOffset=0.0 -unit.1.8.port.3.b.0.unsignedPrecision=0 -unit.1.8.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.8.port.3.b.0.visible=1 -unit.1.8.port.3.buscount=1 -unit.1.8.port.3.channelcount=32 -unit.1.8.port.3.s.0.alias= -unit.1.8.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.0.name=TriggerPort3[0] -unit.1.8.port.3.s.0.orderindex=-1 -unit.1.8.port.3.s.0.visible=1 -unit.1.8.port.3.s.1.alias= -unit.1.8.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.1.name=TriggerPort3[1] -unit.1.8.port.3.s.1.orderindex=-1 -unit.1.8.port.3.s.1.visible=1 -unit.1.8.port.3.s.10.alias= -unit.1.8.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.10.name=TriggerPort3[10] -unit.1.8.port.3.s.10.orderindex=-1 -unit.1.8.port.3.s.10.visible=1 -unit.1.8.port.3.s.11.alias= -unit.1.8.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.11.name=TriggerPort3[11] -unit.1.8.port.3.s.11.orderindex=-1 -unit.1.8.port.3.s.11.visible=1 -unit.1.8.port.3.s.12.alias= -unit.1.8.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.12.name=TriggerPort3[12] -unit.1.8.port.3.s.12.orderindex=-1 -unit.1.8.port.3.s.12.visible=1 -unit.1.8.port.3.s.13.alias= -unit.1.8.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.13.name=TriggerPort3[13] -unit.1.8.port.3.s.13.orderindex=-1 -unit.1.8.port.3.s.13.visible=1 -unit.1.8.port.3.s.14.alias= -unit.1.8.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.14.name=TriggerPort3[14] -unit.1.8.port.3.s.14.orderindex=-1 -unit.1.8.port.3.s.14.visible=1 -unit.1.8.port.3.s.15.alias= -unit.1.8.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.15.name=TriggerPort3[15] -unit.1.8.port.3.s.15.orderindex=-1 -unit.1.8.port.3.s.15.visible=1 -unit.1.8.port.3.s.16.alias= -unit.1.8.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.16.name=TriggerPort3[16] -unit.1.8.port.3.s.16.orderindex=-1 -unit.1.8.port.3.s.16.visible=1 -unit.1.8.port.3.s.17.alias= -unit.1.8.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.8.port.3.s.17.name=TriggerPort3[17] -unit.1.8.port.3.s.17.orderindex=-1 -unit.1.8.port.3.s.17.visible=1 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-unit.1.9.vio.posn.7.name=un_cross_gain_aa -unit.1.9.vio.posn.7.port=1 -unit.1.9.vio.posn.7.radix=1 -unit.1.9.vio.posn.7.type=bus -unit.1.9.vio.posn.70.channel=255 -unit.1.9.vio.posn.70.name=AsyncOut[255] -unit.1.9.vio.posn.70.port=1 -unit.1.9.vio.posn.70.radix=1 -unit.1.9.vio.posn.70.type=signal -unit.1.9.vio.posn.71.channel=255 -unit.1.9.vio.posn.71.name=AsyncOut[255] -unit.1.9.vio.posn.71.port=1 -unit.1.9.vio.posn.71.radix=1 -unit.1.9.vio.posn.71.type=signal -unit.1.9.vio.posn.72.channel=255 -unit.1.9.vio.posn.72.name=AsyncOut[255] -unit.1.9.vio.posn.72.port=1 -unit.1.9.vio.posn.72.radix=1 -unit.1.9.vio.posn.72.type=signal -unit.1.9.vio.posn.73.channel=255 -unit.1.9.vio.posn.73.name=AsyncOut[255] -unit.1.9.vio.posn.73.port=1 -unit.1.9.vio.posn.73.radix=1 -unit.1.9.vio.posn.73.type=signal -unit.1.9.vio.posn.74.channel=255 -unit.1.9.vio.posn.74.name=AsyncOut[255] -unit.1.9.vio.posn.74.port=1 -unit.1.9.vio.posn.74.radix=1 -unit.1.9.vio.posn.74.type=signal -unit.1.9.vio.posn.75.channel=255 -unit.1.9.vio.posn.75.name=AsyncOut[255] -unit.1.9.vio.posn.75.port=1 -unit.1.9.vio.posn.75.radix=1 -unit.1.9.vio.posn.75.type=signal -unit.1.9.vio.posn.76.channel=255 -unit.1.9.vio.posn.76.name=AsyncOut[255] -unit.1.9.vio.posn.76.port=1 -unit.1.9.vio.posn.76.radix=1 -unit.1.9.vio.posn.76.type=signal -unit.1.9.vio.posn.77.channel=255 -unit.1.9.vio.posn.77.name=AsyncOut[255] -unit.1.9.vio.posn.77.port=1 -unit.1.9.vio.posn.77.radix=1 -unit.1.9.vio.posn.77.type=signal -unit.1.9.vio.posn.78.channel=255 -unit.1.9.vio.posn.78.name=AsyncOut[255] -unit.1.9.vio.posn.78.port=1 -unit.1.9.vio.posn.78.radix=1 -unit.1.9.vio.posn.78.type=signal -unit.1.9.vio.posn.79.channel=255 -unit.1.9.vio.posn.79.name=AsyncOut[255] -unit.1.9.vio.posn.79.port=1 -unit.1.9.vio.posn.79.radix=1 -unit.1.9.vio.posn.79.type=signal -unit.1.9.vio.posn.8.channel=2147483646 -unit.1.9.vio.posn.8.name=dds_sine_gain_ch0 -unit.1.9.vio.posn.8.port=1 -unit.1.9.vio.posn.8.radix=3 -unit.1.9.vio.posn.8.type=bus -unit.1.9.vio.posn.80.channel=255 -unit.1.9.vio.posn.80.name=AsyncOut[255] -unit.1.9.vio.posn.80.port=1 -unit.1.9.vio.posn.80.radix=1 -unit.1.9.vio.posn.80.type=signal -unit.1.9.vio.posn.81.channel=255 -unit.1.9.vio.posn.81.name=AsyncOut[255] -unit.1.9.vio.posn.81.port=1 -unit.1.9.vio.posn.81.radix=1 -unit.1.9.vio.posn.81.type=signal -unit.1.9.vio.posn.82.channel=255 -unit.1.9.vio.posn.82.name=AsyncOut[255] -unit.1.9.vio.posn.82.port=1 -unit.1.9.vio.posn.82.radix=1 -unit.1.9.vio.posn.82.type=signal -unit.1.9.vio.posn.83.channel=255 -unit.1.9.vio.posn.83.name=AsyncOut[255] -unit.1.9.vio.posn.83.port=1 -unit.1.9.vio.posn.83.radix=1 -unit.1.9.vio.posn.83.type=signal -unit.1.9.vio.posn.84.channel=255 -unit.1.9.vio.posn.84.name=AsyncOut[255] -unit.1.9.vio.posn.84.port=1 -unit.1.9.vio.posn.84.radix=1 -unit.1.9.vio.posn.84.type=signal -unit.1.9.vio.posn.85.channel=255 -unit.1.9.vio.posn.85.name=AsyncOut[255] -unit.1.9.vio.posn.85.port=1 -unit.1.9.vio.posn.85.radix=1 -unit.1.9.vio.posn.85.type=signal -unit.1.9.vio.posn.86.channel=255 -unit.1.9.vio.posn.86.name=AsyncOut[255] -unit.1.9.vio.posn.86.port=1 -unit.1.9.vio.posn.86.radix=1 -unit.1.9.vio.posn.86.type=signal -unit.1.9.vio.posn.87.channel=255 -unit.1.9.vio.posn.87.name=AsyncOut[255] -unit.1.9.vio.posn.87.port=1 -unit.1.9.vio.posn.87.radix=1 -unit.1.9.vio.posn.87.type=signal -unit.1.9.vio.posn.88.channel=255 -unit.1.9.vio.posn.88.name=AsyncOut[255] -unit.1.9.vio.posn.88.port=1 -unit.1.9.vio.posn.88.radix=1 -unit.1.9.vio.posn.88.type=signal -unit.1.9.vio.posn.89.channel=255 -unit.1.9.vio.posn.89.name=AsyncOut[255] -unit.1.9.vio.posn.89.port=1 -unit.1.9.vio.posn.89.radix=1 -unit.1.9.vio.posn.89.type=signal -unit.1.9.vio.posn.9.channel=2147483646 -unit.1.9.vio.posn.9.name=dds_sine_gain_ch1 -unit.1.9.vio.posn.9.port=1 -unit.1.9.vio.posn.9.radix=3 -unit.1.9.vio.posn.9.type=bus -unit.1.9.vio.posn.90.channel=255 -unit.1.9.vio.posn.90.name=AsyncOut[255] -unit.1.9.vio.posn.90.port=1 -unit.1.9.vio.posn.90.radix=1 -unit.1.9.vio.posn.90.type=signal -unit.1.9.vio.posn.91.channel=255 -unit.1.9.vio.posn.91.name=AsyncOut[255] -unit.1.9.vio.posn.91.port=1 -unit.1.9.vio.posn.91.radix=1 -unit.1.9.vio.posn.91.type=signal -unit.1.9.vio.posn.92.channel=255 -unit.1.9.vio.posn.92.name=AsyncOut[255] -unit.1.9.vio.posn.92.port=1 -unit.1.9.vio.posn.92.radix=1 -unit.1.9.vio.posn.92.type=signal -unit.1.9.vio.posn.93.channel=255 -unit.1.9.vio.posn.93.name=AsyncOut[255] -unit.1.9.vio.posn.93.port=1 -unit.1.9.vio.posn.93.radix=1 -unit.1.9.vio.posn.93.type=signal -unit.1.9.vio.posn.94.channel=255 -unit.1.9.vio.posn.94.name=AsyncOut[255] -unit.1.9.vio.posn.94.port=1 -unit.1.9.vio.posn.94.radix=1 -unit.1.9.vio.posn.94.type=signal -unit.1.9.vio.posn.95.channel=255 -unit.1.9.vio.posn.95.name=AsyncOut[255] -unit.1.9.vio.posn.95.port=1 -unit.1.9.vio.posn.95.radix=1 -unit.1.9.vio.posn.95.type=signal -unit.1.9.vio.posn.96.channel=255 -unit.1.9.vio.posn.96.name=AsyncOut[255] -unit.1.9.vio.posn.96.port=1 -unit.1.9.vio.posn.96.radix=1 -unit.1.9.vio.posn.96.type=signal -unit.1.9.vio.posn.97.channel=255 -unit.1.9.vio.posn.97.name=AsyncOut[255] -unit.1.9.vio.posn.97.port=1 -unit.1.9.vio.posn.97.radix=1 -unit.1.9.vio.posn.97.type=signal -unit.1.9.vio.posn.98.channel=255 -unit.1.9.vio.posn.98.name=AsyncOut[255] -unit.1.9.vio.posn.98.port=1 -unit.1.9.vio.posn.98.radix=1 -unit.1.9.vio.posn.98.type=signal -unit.1.9.vio.posn.99.channel=255 -unit.1.9.vio.posn.99.name=AsyncOut[255] -unit.1.9.vio.posn.99.port=1 -unit.1.9.vio.posn.99.radix=1 -unit.1.9.vio.posn.99.type=signal -unit.1.9.vio.readperiod=0 diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_core.ucf b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_core.ucf deleted file mode 100755 index 3846d128..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_core.ucf +++ /dev/null @@ -1,348 +0,0 @@ - - -# Global period constraint -NET "*position_calc_core/*/clk" TNM_NET = "clk_cc71cef7"; -TIMESPEC "TS_clk_cc71cef7" = PERIOD "clk_cc71cef7" 4.44116091946435 ns HIGH 50 %; - -# ce_10000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_10000_sg_x2*" TNM_NET = "ce_10000_cc71cef7_group"; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; - -# ce_1120_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_1120_sg_x32*" TNM_NET = "ce_1120_cc71cef7_group"; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; - -# ce_1400000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_1400000_sg_x3*" TNM_NET = "ce_1400000_cc71cef7_group"; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; - -# ce_224000000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_224000000_sg_x7*" TNM_NET = "ce_224000000_cc71cef7_group"; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 994.8200459600143 ms; - -# ce_22400000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_22400000_sg_x28*" TNM_NET = "ce_22400000_cc71cef7_group"; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 99.48200459600145 ms; - -# ce_2240_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2240_sg_x28*" TNM_NET = "ce_2240_cc71cef7_group"; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; - -# ce_2500_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2500_sg_x3*" TNM_NET = "ce_2500_cc71cef7_group"; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; - -# ce_2800000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2800000_sg_x4*" TNM_NET = "ce_2800000_cc71cef7_group"; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 12.43525057450018 ms; - -# ce_2_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2_sg_x38*" TNM_NET = "ce_2_cc71cef7_group"; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; - -# ce_35_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_35_sg_x22*" TNM_NET = "ce_35_cc71cef7_group"; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; - -# ce_44800000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_44800000_sg_x2*" TNM_NET = "ce_44800000_cc71cef7_group"; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 198.9640091920029 ms; - -# ce_4480_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_4480_sg_x9*" TNM_NET = "ce_4480_cc71cef7_group"; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; - -# ce_5000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_5000_sg_x9*" TNM_NET = "ce_5000_cc71cef7_group"; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; - -# ce_56000000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_56000000_sg_x5*" TNM_NET = "ce_56000000_cc71cef7_group"; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 248.70501149000359 ms; - -# ce_5600000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_5600000_sg_x12*" TNM_NET = "ce_5600000_cc71cef7_group"; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 24.87050114900036 ms; - -# ce_560_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_560_sg_x3*" TNM_NET = "ce_560_cc71cef7_group"; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; - -# ce_70_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_70_sg_x27*" TNM_NET = "ce_70_cc71cef7_group"; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; - -# Group-to-group constraints -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_560_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_10000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_10000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_10000_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_2240_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_2500_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_4480_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_5000_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_1120_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_1120_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_1400000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_1400000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 99.48200459600145 ms; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 198.9640091920029 ms; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 248.70501149000359 ms; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_224000000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_224000000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 99.48200459600145 ms; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 99.48200459600145 ms; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 49.74100229800072 ms; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_22400000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_22400000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_10000_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_2500_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_4480_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_5000_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_2240_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2240_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_10000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_1120_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2240_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_4480_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_5000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_560_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_2800000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2800000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_10000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_1120_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2240_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2500_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_35_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_4480_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_5000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_560_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_70_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_10000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_1120_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2240_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2500_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_4480_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_560_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_70_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 198.9640091920029 ms; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 99.48200459600145 ms; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 49.74100229800072 ms; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_44800000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_44800000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_10000_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_2500_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_5000_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_4480_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_4480_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_560_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 248.70501149000359 ms; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 49.74100229800072 ms; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 49.74100229800072 ms; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_56000000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_56000000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.411609194643496 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_1120_cc71cef7_group" 4.974100229800072 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 6.21762528725009 ms; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_2240_cc71cef7_group" 9.948200459600145 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 12.43525057450018 ms; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_4480_cc71cef7_group" 19.89640091920029 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 24.87050114900036 ms; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_560_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_5600000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_5600000_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_10000_cc71cef7_group" 355.292873557148 ns; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_1120_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_2240_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_2500_cc71cef7_group" 88.823218389287 ns; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_4480_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_5000_cc71cef7_group" 177.646436778574 ns; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 2.487050114900036 us; -TIMESPEC "TS_ce_560_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_560_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_10000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_10000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_1120_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_1120_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_1400000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_1400000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_224000000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_224000000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_22400000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_22400000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2240_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2240_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2500_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2800000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2800000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_44800000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_44800000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_4480_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_4480_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_5000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_56000000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_56000000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_5600000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_5600000_cc71cef7_group" 310.8812643625045 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_560_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_560_cc71cef7_group" 310.8812643625045 ns; - diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd deleted file mode 100644 index 036e6b5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/Manifest.py b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/Manifest.py deleted file mode 100644 index 4b61dc2e..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/Manifest.py +++ /dev/null @@ -1,3 +0,0 @@ -files = [ "dbe_bpm_dsp.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_bpm_dsp.ucf", "position_calc_core.ucf" ]; - -modules = { "local" : ["../../.." ] }; diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/adc_data.txt b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/adc_data.txt deleted file mode 100644 index fb37e1d1..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/adc_data.txt +++ /dev/null @@ -1,4097 +0,0 @@ -Sample in Buffer Sample in Window adc_data_ch0 adc_data_ch1 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-unit.1.0.port.-1.s.69.orderindex=-1 -unit.1.0.port.-1.s.69.visible=1 -unit.1.0.port.-1.s.7.alias= -unit.1.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.7.name=DataPort[7] -unit.1.0.port.-1.s.7.orderindex=-1 -unit.1.0.port.-1.s.7.visible=0 -unit.1.0.port.-1.s.70.alias= -unit.1.0.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.70.name=DataPort[70] -unit.1.0.port.-1.s.70.orderindex=-1 -unit.1.0.port.-1.s.70.visible=1 -unit.1.0.port.-1.s.71.alias= -unit.1.0.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.71.name=DataPort[71] -unit.1.0.port.-1.s.71.orderindex=-1 -unit.1.0.port.-1.s.71.visible=1 -unit.1.0.port.-1.s.72.alias= -unit.1.0.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.72.name=DataPort[72] -unit.1.0.port.-1.s.72.orderindex=-1 -unit.1.0.port.-1.s.72.visible=1 -unit.1.0.port.-1.s.73.alias= -unit.1.0.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.73.name=DataPort[73] -unit.1.0.port.-1.s.73.orderindex=-1 -unit.1.0.port.-1.s.73.visible=1 -unit.1.0.port.-1.s.74.alias= -unit.1.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.74.name=DataPort[74] -unit.1.0.port.-1.s.74.orderindex=-1 -unit.1.0.port.-1.s.74.visible=1 -unit.1.0.port.-1.s.75.alias= -unit.1.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.75.name=DataPort[75] -unit.1.0.port.-1.s.75.orderindex=-1 -unit.1.0.port.-1.s.75.visible=1 -unit.1.0.port.-1.s.76.alias= -unit.1.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.76.name=DataPort[76] -unit.1.0.port.-1.s.76.orderindex=-1 -unit.1.0.port.-1.s.76.visible=1 -unit.1.0.port.-1.s.77.alias= -unit.1.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.77.name=DataPort[77] -unit.1.0.port.-1.s.77.orderindex=-1 -unit.1.0.port.-1.s.77.visible=1 -unit.1.0.port.-1.s.78.alias= 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8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.b.0.name=TriggerPort0 -unit.1.0.port.0.b.0.orderindex=-1 -unit.1.0.port.0.b.0.radix=Hex -unit.1.0.port.0.b.0.signedOffset=0.0 -unit.1.0.port.0.b.0.signedPrecision=0 -unit.1.0.port.0.b.0.signedScaleFactor=1.0 -unit.1.0.port.0.b.0.unsignedOffset=0.0 -unit.1.0.port.0.b.0.unsignedPrecision=0 -unit.1.0.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.0.b.0.visible=1 -unit.1.0.port.0.buscount=1 -unit.1.0.port.0.channelcount=32 -unit.1.0.port.0.s.0.alias= -unit.1.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= -unit.1.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.10.name=TriggerPort0[10] -unit.1.0.port.0.s.10.orderindex=-1 -unit.1.0.port.0.s.10.visible=1 -unit.1.0.port.0.s.11.alias= -unit.1.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.11.name=TriggerPort0[11] -unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= -unit.1.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.10.name=TriggerPort3[10] -unit.1.0.port.3.s.10.orderindex=-1 -unit.1.0.port.3.s.10.visible=1 -unit.1.0.port.3.s.11.alias= -unit.1.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.11.name=TriggerPort3[11] -unit.1.0.port.3.s.11.orderindex=-1 -unit.1.0.port.3.s.11.visible=1 -unit.1.0.port.3.s.12.alias= -unit.1.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.12.name=TriggerPort3[12] -unit.1.0.port.3.s.12.orderindex=-1 -unit.1.0.port.3.s.12.visible=1 -unit.1.0.port.3.s.13.alias= -unit.1.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.13.name=TriggerPort3[13] -unit.1.0.port.3.s.13.orderindex=-1 -unit.1.0.port.3.s.13.visible=1 -unit.1.0.port.3.s.14.alias= -unit.1.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.14.name=TriggerPort3[14] -unit.1.0.port.3.s.14.orderindex=-1 -unit.1.0.port.3.s.14.visible=1 -unit.1.0.port.3.s.15.alias= -unit.1.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.15.name=TriggerPort3[15] -unit.1.0.port.3.s.15.orderindex=-1 -unit.1.0.port.3.s.15.visible=1 -unit.1.0.port.3.s.16.alias= -unit.1.0.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.16.name=TriggerPort3[16] -unit.1.0.port.3.s.16.orderindex=-1 -unit.1.0.port.3.s.16.visible=1 -unit.1.0.port.3.s.17.alias= -unit.1.0.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.17.name=TriggerPort3[17] -unit.1.0.port.3.s.17.orderindex=-1 -unit.1.0.port.3.s.17.visible=1 -unit.1.0.port.3.s.18.alias= -unit.1.0.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.18.name=TriggerPort3[18] -unit.1.0.port.3.s.18.orderindex=-1 -unit.1.0.port.3.s.18.visible=1 -unit.1.0.port.3.s.19.alias= -unit.1.0.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.19.name=TriggerPort3[19] -unit.1.0.port.3.s.19.orderindex=-1 -unit.1.0.port.3.s.19.visible=1 -unit.1.0.port.3.s.2.alias= -unit.1.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.2.name=TriggerPort3[2] -unit.1.0.port.3.s.2.orderindex=-1 -unit.1.0.port.3.s.2.visible=1 -unit.1.0.port.3.s.20.alias= -unit.1.0.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.20.name=TriggerPort3[20] -unit.1.0.port.3.s.20.orderindex=-1 -unit.1.0.port.3.s.20.visible=1 -unit.1.0.port.3.s.21.alias= -unit.1.0.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.21.name=TriggerPort3[21] -unit.1.0.port.3.s.21.orderindex=-1 -unit.1.0.port.3.s.21.visible=1 -unit.1.0.port.3.s.22.alias= -unit.1.0.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.22.name=TriggerPort3[22] -unit.1.0.port.3.s.22.orderindex=-1 -unit.1.0.port.3.s.22.visible=1 -unit.1.0.port.3.s.23.alias= -unit.1.0.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.23.name=TriggerPort3[23] -unit.1.0.port.3.s.23.orderindex=-1 -unit.1.0.port.3.s.23.visible=1 -unit.1.0.port.3.s.24.alias= -unit.1.0.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.24.name=TriggerPort3[24] -unit.1.0.port.3.s.24.orderindex=-1 -unit.1.0.port.3.s.24.visible=1 -unit.1.0.port.3.s.25.alias= -unit.1.0.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.25.name=TriggerPort3[25] -unit.1.0.port.3.s.25.orderindex=-1 -unit.1.0.port.3.s.25.visible=1 -unit.1.0.port.3.s.26.alias= -unit.1.0.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.26.name=TriggerPort3[26] -unit.1.0.port.3.s.26.orderindex=-1 -unit.1.0.port.3.s.26.visible=1 -unit.1.0.port.3.s.27.alias= -unit.1.0.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.27.name=TriggerPort3[27] -unit.1.0.port.3.s.27.orderindex=-1 -unit.1.0.port.3.s.27.visible=1 -unit.1.0.port.3.s.28.alias= -unit.1.0.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.28.name=TriggerPort3[28] -unit.1.0.port.3.s.28.orderindex=-1 -unit.1.0.port.3.s.28.visible=1 -unit.1.0.port.3.s.29.alias= -unit.1.0.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.29.name=TriggerPort3[29] -unit.1.0.port.3.s.29.orderindex=-1 -unit.1.0.port.3.s.29.visible=1 -unit.1.0.port.3.s.3.alias= -unit.1.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.3.name=TriggerPort3[3] -unit.1.0.port.3.s.3.orderindex=-1 -unit.1.0.port.3.s.3.visible=1 -unit.1.0.port.3.s.30.alias= -unit.1.0.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=MyILA0 -unit.1.0.waveform.count=4 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=adc_data_ch3 -unit.1.0.waveform.posn.0.radix=3 -unit.1.0.waveform.posn.0.type=bus -unit.1.0.waveform.posn.1.channel=2147483646 -unit.1.0.waveform.posn.1.name=adc_data_ch2 -unit.1.0.waveform.posn.1.radix=3 -unit.1.0.waveform.posn.1.type=bus -unit.1.0.waveform.posn.10.channel=2147483646 -unit.1.0.waveform.posn.10.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.10.radix=1 -unit.1.0.waveform.posn.10.type=bus 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-unit.1.0.waveform.posn.4.radix=1 -unit.1.0.waveform.posn.4.type=bus -unit.1.0.waveform.posn.5.channel=2147483646 -unit.1.0.waveform.posn.5.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.5.radix=1 -unit.1.0.waveform.posn.5.type=bus -unit.1.0.waveform.posn.6.channel=2147483646 -unit.1.0.waveform.posn.6.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.6.radix=1 -unit.1.0.waveform.posn.6.type=bus -unit.1.0.waveform.posn.7.channel=2147483646 -unit.1.0.waveform.posn.7.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.7.radix=1 -unit.1.0.waveform.posn.7.type=bus -unit.1.0.waveform.posn.8.channel=2147483646 -unit.1.0.waveform.posn.8.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.37398374 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 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-unit.1.1.port.-1.s.117.name=DataPort[117] -unit.1.1.port.-1.s.117.orderindex=-1 -unit.1.1.port.-1.s.117.visible=0 -unit.1.1.port.-1.s.118.alias= -unit.1.1.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.118.name=DataPort[118] -unit.1.1.port.-1.s.118.orderindex=-1 -unit.1.1.port.-1.s.118.visible=0 -unit.1.1.port.-1.s.119.alias= -unit.1.1.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.119.name=DataPort[119] -unit.1.1.port.-1.s.119.orderindex=-1 -unit.1.1.port.-1.s.119.visible=0 -unit.1.1.port.-1.s.12.alias= -unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=0 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=0 -unit.1.1.port.-1.s.121.alias= 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-unit.1.1.port.-1.s.13.name=DataPort[13] -unit.1.1.port.-1.s.13.orderindex=-1 -unit.1.1.port.-1.s.13.visible=0 -unit.1.1.port.-1.s.130.alias= -unit.1.1.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.130.name=DataPort[130] -unit.1.1.port.-1.s.130.orderindex=-1 -unit.1.1.port.-1.s.130.visible=1 -unit.1.1.port.-1.s.131.alias= -unit.1.1.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.131.name=DataPort[131] -unit.1.1.port.-1.s.131.orderindex=-1 -unit.1.1.port.-1.s.131.visible=1 -unit.1.1.port.-1.s.132.alias= -unit.1.1.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.132.name=DataPort[132] -unit.1.1.port.-1.s.132.orderindex=-1 -unit.1.1.port.-1.s.132.visible=1 -unit.1.1.port.-1.s.133.alias= -unit.1.1.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.133.name=DataPort[133] -unit.1.1.port.-1.s.133.orderindex=-1 -unit.1.1.port.-1.s.133.visible=1 -unit.1.1.port.-1.s.134.alias= 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-unit.1.1.port.-1.s.82.alias= -unit.1.1.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.82.name=DataPort[82] -unit.1.1.port.-1.s.82.orderindex=-1 -unit.1.1.port.-1.s.82.visible=0 -unit.1.1.port.-1.s.83.alias= -unit.1.1.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.83.name=DataPort[83] -unit.1.1.port.-1.s.83.orderindex=-1 -unit.1.1.port.-1.s.83.visible=0 -unit.1.1.port.-1.s.84.alias= -unit.1.1.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.84.name=DataPort[84] -unit.1.1.port.-1.s.84.orderindex=-1 -unit.1.1.port.-1.s.84.visible=0 -unit.1.1.port.-1.s.85.alias= -unit.1.1.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.85.name=DataPort[85] -unit.1.1.port.-1.s.85.orderindex=-1 -unit.1.1.port.-1.s.85.visible=0 -unit.1.1.port.-1.s.86.alias= -unit.1.1.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.86.name=DataPort[86] -unit.1.1.port.-1.s.86.orderindex=-1 -unit.1.1.port.-1.s.86.visible=0 -unit.1.1.port.-1.s.87.alias= -unit.1.1.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.87.name=DataPort[87] -unit.1.1.port.-1.s.87.orderindex=-1 -unit.1.1.port.-1.s.87.visible=0 -unit.1.1.port.-1.s.88.alias= -unit.1.1.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.88.name=DataPort[88] -unit.1.1.port.-1.s.88.orderindex=-1 -unit.1.1.port.-1.s.88.visible=0 -unit.1.1.port.-1.s.89.alias= -unit.1.1.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.89.name=DataPort[89] -unit.1.1.port.-1.s.89.orderindex=-1 -unit.1.1.port.-1.s.89.visible=0 -unit.1.1.port.-1.s.9.alias= -unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=0 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=0 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=0 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=0 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=0 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=0 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=8 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.port.4.b.0.alias= -unit.1.1.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.b.0.name=TriggerPort4 -unit.1.1.port.4.b.0.orderindex=-1 -unit.1.1.port.4.b.0.radix=Hex -unit.1.1.port.4.b.0.signedOffset=0.0 -unit.1.1.port.4.b.0.signedPrecision=0 -unit.1.1.port.4.b.0.signedScaleFactor=1.0 -unit.1.1.port.4.b.0.unsignedOffset=0.0 -unit.1.1.port.4.b.0.unsignedPrecision=0 -unit.1.1.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.4.b.0.visible=1 -unit.1.1.port.4.buscount=1 -unit.1.1.port.4.channelcount=32 -unit.1.1.port.4.s.0.alias= -unit.1.1.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.0.name=TriggerPort4[0] -unit.1.1.port.4.s.0.orderindex=-1 -unit.1.1.port.4.s.0.visible=1 -unit.1.1.port.4.s.1.alias= -unit.1.1.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.1.name=TriggerPort4[1] -unit.1.1.port.4.s.1.orderindex=-1 -unit.1.1.port.4.s.1.visible=1 -unit.1.1.port.4.s.10.alias= -unit.1.1.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.10.name=TriggerPort4[10] -unit.1.1.port.4.s.10.orderindex=-1 -unit.1.1.port.4.s.10.visible=1 -unit.1.1.port.4.s.11.alias= -unit.1.1.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.11.name=TriggerPort4[11] -unit.1.1.port.4.s.11.orderindex=-1 -unit.1.1.port.4.s.11.visible=1 -unit.1.1.port.4.s.12.alias= -unit.1.1.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.12.name=TriggerPort4[12] -unit.1.1.port.4.s.12.orderindex=-1 -unit.1.1.port.4.s.12.visible=1 -unit.1.1.port.4.s.13.alias= -unit.1.1.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.13.name=TriggerPort4[13] -unit.1.1.port.4.s.13.orderindex=-1 -unit.1.1.port.4.s.13.visible=1 -unit.1.1.port.4.s.14.alias= -unit.1.1.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.14.name=TriggerPort4[14] -unit.1.1.port.4.s.14.orderindex=-1 -unit.1.1.port.4.s.14.visible=1 -unit.1.1.port.4.s.15.alias= -unit.1.1.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.15.name=TriggerPort4[15] -unit.1.1.port.4.s.15.orderindex=-1 -unit.1.1.port.4.s.15.visible=1 -unit.1.1.port.4.s.16.alias= -unit.1.1.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.16.name=TriggerPort4[16] -unit.1.1.port.4.s.16.orderindex=-1 -unit.1.1.port.4.s.16.visible=1 -unit.1.1.port.4.s.17.alias= -unit.1.1.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.17.name=TriggerPort4[17] -unit.1.1.port.4.s.17.orderindex=-1 -unit.1.1.port.4.s.17.visible=1 -unit.1.1.port.4.s.18.alias= -unit.1.1.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.18.name=TriggerPort4[18] -unit.1.1.port.4.s.18.orderindex=-1 -unit.1.1.port.4.s.18.visible=1 -unit.1.1.port.4.s.19.alias= -unit.1.1.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.19.name=TriggerPort4[19] -unit.1.1.port.4.s.19.orderindex=-1 -unit.1.1.port.4.s.19.visible=1 -unit.1.1.port.4.s.2.alias= -unit.1.1.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.2.name=TriggerPort4[2] -unit.1.1.port.4.s.2.orderindex=-1 -unit.1.1.port.4.s.2.visible=1 -unit.1.1.port.4.s.20.alias= -unit.1.1.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.20.name=TriggerPort4[20] -unit.1.1.port.4.s.20.orderindex=-1 -unit.1.1.port.4.s.20.visible=1 -unit.1.1.port.4.s.21.alias= -unit.1.1.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.21.name=TriggerPort4[21] -unit.1.1.port.4.s.21.orderindex=-1 -unit.1.1.port.4.s.21.visible=1 -unit.1.1.port.4.s.22.alias= -unit.1.1.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.22.name=TriggerPort4[22] -unit.1.1.port.4.s.22.orderindex=-1 -unit.1.1.port.4.s.22.visible=1 -unit.1.1.port.4.s.23.alias= -unit.1.1.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.23.name=TriggerPort4[23] -unit.1.1.port.4.s.23.orderindex=-1 -unit.1.1.port.4.s.23.visible=1 -unit.1.1.port.4.s.24.alias= -unit.1.1.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.24.name=TriggerPort4[24] -unit.1.1.port.4.s.24.orderindex=-1 -unit.1.1.port.4.s.24.visible=1 -unit.1.1.port.4.s.25.alias= -unit.1.1.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.25.name=TriggerPort4[25] -unit.1.1.port.4.s.25.orderindex=-1 -unit.1.1.port.4.s.25.visible=1 -unit.1.1.port.4.s.26.alias= -unit.1.1.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.26.name=TriggerPort4[26] -unit.1.1.port.4.s.26.orderindex=-1 -unit.1.1.port.4.s.26.visible=1 -unit.1.1.port.4.s.27.alias= -unit.1.1.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.27.name=TriggerPort4[27] -unit.1.1.port.4.s.27.orderindex=-1 -unit.1.1.port.4.s.27.visible=1 -unit.1.1.port.4.s.28.alias= -unit.1.1.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.28.name=TriggerPort4[28] -unit.1.1.port.4.s.28.orderindex=-1 -unit.1.1.port.4.s.28.visible=1 -unit.1.1.port.4.s.29.alias= -unit.1.1.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.29.name=TriggerPort4[29] -unit.1.1.port.4.s.29.orderindex=-1 -unit.1.1.port.4.s.29.visible=1 -unit.1.1.port.4.s.3.alias= -unit.1.1.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.3.name=TriggerPort4[3] -unit.1.1.port.4.s.3.orderindex=-1 -unit.1.1.port.4.s.3.visible=1 -unit.1.1.port.4.s.30.alias= -unit.1.1.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.30.name=TriggerPort4[30] -unit.1.1.port.4.s.30.orderindex=-1 -unit.1.1.port.4.s.30.visible=1 -unit.1.1.port.4.s.31.alias= -unit.1.1.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.31.name=TriggerPort4[31] -unit.1.1.port.4.s.31.orderindex=-1 -unit.1.1.port.4.s.31.visible=1 -unit.1.1.port.4.s.4.alias= -unit.1.1.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.4.name=TriggerPort4[4] -unit.1.1.port.4.s.4.orderindex=-1 -unit.1.1.port.4.s.4.visible=1 -unit.1.1.port.4.s.5.alias= -unit.1.1.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.5.name=TriggerPort4[5] -unit.1.1.port.4.s.5.orderindex=-1 -unit.1.1.port.4.s.5.visible=1 -unit.1.1.port.4.s.6.alias= -unit.1.1.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.6.name=TriggerPort4[6] -unit.1.1.port.4.s.6.orderindex=-1 -unit.1.1.port.4.s.6.visible=1 -unit.1.1.port.4.s.7.alias= -unit.1.1.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.7.name=TriggerPort4[7] -unit.1.1.port.4.s.7.orderindex=-1 -unit.1.1.port.4.s.7.visible=1 -unit.1.1.port.4.s.8.alias= -unit.1.1.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.8.name=TriggerPort4[8] -unit.1.1.port.4.s.8.orderindex=-1 -unit.1.1.port.4.s.8.visible=1 -unit.1.1.port.4.s.9.alias= -unit.1.1.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.9.name=TriggerPort4[9] -unit.1.1.port.4.s.9.orderindex=-1 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12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.b.0.name=DataPort -unit.1.2.port.-1.b.0.orderindex=-1 -unit.1.2.port.-1.b.0.radix=Signed -unit.1.2.port.-1.b.0.signedOffset=0.0 -unit.1.2.port.-1.b.0.signedPrecision=0 -unit.1.2.port.-1.b.0.signedScaleFactor=1.0 -unit.1.2.port.-1.b.0.tokencount=0 -unit.1.2.port.-1.b.0.unsignedOffset=0.0 -unit.1.2.port.-1.b.0.unsignedPrecision=0 -unit.1.2.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.-1.b.0.visible=1 -unit.1.2.port.-1.b.1.alias=dsp_tbt_amp_ch1 -unit.1.2.port.-1.b.1.channellist=40 41 42 43 44 45 46 47 48 49 50 52 51 53 54 55 56 57 58 59 60 61 62 63 -unit.1.2.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.2.port.-1.b.1.name=DataPort -unit.1.2.port.-1.b.1.orderindex=-1 -unit.1.2.port.-1.b.1.radix=Signed -unit.1.2.port.-1.b.1.signedOffset=0.0 -unit.1.2.port.-1.b.1.signedPrecision=0 -unit.1.2.port.-1.b.1.signedScaleFactor=1.0 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125 126 127 -unit.1.2.port.-1.b.3.color=java.awt.Color[r\=153,g\=0,b\=153] -unit.1.2.port.-1.b.3.name=DataPort -unit.1.2.port.-1.b.3.orderindex=-1 -unit.1.2.port.-1.b.3.radix=Signed -unit.1.2.port.-1.b.3.signedOffset=0.0 -unit.1.2.port.-1.b.3.signedPrecision=0 -unit.1.2.port.-1.b.3.signedScaleFactor=1.0 -unit.1.2.port.-1.b.3.tokencount=0 -unit.1.2.port.-1.b.3.unsignedOffset=0.0 -unit.1.2.port.-1.b.3.unsignedPrecision=0 -unit.1.2.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.2.port.-1.b.3.visible=1 -unit.1.2.port.-1.buscount=4 -unit.1.2.port.-1.channelcount=136 -unit.1.2.port.-1.s.0.alias= -unit.1.2.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.0.name=DataPort[0] -unit.1.2.port.-1.s.0.orderindex=-1 -unit.1.2.port.-1.s.0.visible=1 -unit.1.2.port.-1.s.1.alias= -unit.1.2.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.1.name=DataPort[1] -unit.1.2.port.-1.s.1.orderindex=-1 -unit.1.2.port.-1.s.1.visible=1 -unit.1.2.port.-1.s.10.alias= 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-unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=0 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=0 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 -unit.1.2.port.-1.s.92.visible=0 -unit.1.2.port.-1.s.93.alias= -unit.1.2.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.93.name=DataPort[93] -unit.1.2.port.-1.s.93.orderindex=-1 -unit.1.2.port.-1.s.93.visible=0 -unit.1.2.port.-1.s.94.alias= -unit.1.2.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.94.name=DataPort[94] -unit.1.2.port.-1.s.94.orderindex=-1 -unit.1.2.port.-1.s.94.visible=0 -unit.1.2.port.-1.s.95.alias= -unit.1.2.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.95.name=DataPort[95] -unit.1.2.port.-1.s.95.orderindex=-1 -unit.1.2.port.-1.s.95.visible=0 -unit.1.2.port.-1.s.96.alias= -unit.1.2.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.96.name=DataPort[96] -unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=1 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex -unit.1.2.port.0.b.0.signedOffset=0.0 -unit.1.2.port.0.b.0.signedPrecision=0 -unit.1.2.port.0.b.0.signedScaleFactor=1.0 -unit.1.2.port.0.b.0.unsignedOffset=0.0 -unit.1.2.port.0.b.0.unsignedPrecision=0 -unit.1.2.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.0.b.0.visible=1 -unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=8 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 -unit.1.2.port.3.s.27.alias= -unit.1.2.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.27.name=TriggerPort3[27] -unit.1.2.port.3.s.27.orderindex=-1 -unit.1.2.port.3.s.27.visible=1 -unit.1.2.port.3.s.28.alias= -unit.1.2.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.28.name=TriggerPort3[28] -unit.1.2.port.3.s.28.orderindex=-1 -unit.1.2.port.3.s.28.visible=1 -unit.1.2.port.3.s.29.alias= -unit.1.2.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.29.name=TriggerPort3[29] -unit.1.2.port.3.s.29.orderindex=-1 -unit.1.2.port.3.s.29.visible=1 -unit.1.2.port.3.s.3.alias= -unit.1.2.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.3.name=TriggerPort3[3] -unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.port.4.b.0.alias= -unit.1.2.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.b.0.name=TriggerPort4 -unit.1.2.port.4.b.0.orderindex=-1 -unit.1.2.port.4.b.0.radix=Hex -unit.1.2.port.4.b.0.signedOffset=0.0 -unit.1.2.port.4.b.0.signedPrecision=0 -unit.1.2.port.4.b.0.signedScaleFactor=1.0 -unit.1.2.port.4.b.0.unsignedOffset=0.0 -unit.1.2.port.4.b.0.unsignedPrecision=0 -unit.1.2.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.4.b.0.visible=1 -unit.1.2.port.4.buscount=1 -unit.1.2.port.4.channelcount=32 -unit.1.2.port.4.s.0.alias= -unit.1.2.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.0.name=TriggerPort4[0] -unit.1.2.port.4.s.0.orderindex=-1 -unit.1.2.port.4.s.0.visible=1 -unit.1.2.port.4.s.1.alias= -unit.1.2.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.1.name=TriggerPort4[1] -unit.1.2.port.4.s.1.orderindex=-1 -unit.1.2.port.4.s.1.visible=1 -unit.1.2.port.4.s.10.alias= -unit.1.2.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.10.name=TriggerPort4[10] -unit.1.2.port.4.s.10.orderindex=-1 -unit.1.2.port.4.s.10.visible=1 -unit.1.2.port.4.s.11.alias= -unit.1.2.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.11.name=TriggerPort4[11] -unit.1.2.port.4.s.11.orderindex=-1 -unit.1.2.port.4.s.11.visible=1 -unit.1.2.port.4.s.12.alias= -unit.1.2.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.12.name=TriggerPort4[12] -unit.1.2.port.4.s.12.orderindex=-1 -unit.1.2.port.4.s.12.visible=1 -unit.1.2.port.4.s.13.alias= -unit.1.2.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.13.name=TriggerPort4[13] -unit.1.2.port.4.s.13.orderindex=-1 -unit.1.2.port.4.s.13.visible=1 -unit.1.2.port.4.s.14.alias= -unit.1.2.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.14.name=TriggerPort4[14] -unit.1.2.port.4.s.14.orderindex=-1 -unit.1.2.port.4.s.14.visible=1 -unit.1.2.port.4.s.15.alias= -unit.1.2.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.15.name=TriggerPort4[15] -unit.1.2.port.4.s.15.orderindex=-1 -unit.1.2.port.4.s.15.visible=1 -unit.1.2.port.4.s.16.alias= -unit.1.2.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.16.name=TriggerPort4[16] -unit.1.2.port.4.s.16.orderindex=-1 -unit.1.2.port.4.s.16.visible=1 -unit.1.2.port.4.s.17.alias= -unit.1.2.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.17.name=TriggerPort4[17] -unit.1.2.port.4.s.17.orderindex=-1 -unit.1.2.port.4.s.17.visible=1 -unit.1.2.port.4.s.18.alias= -unit.1.2.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.18.name=TriggerPort4[18] -unit.1.2.port.4.s.18.orderindex=-1 -unit.1.2.port.4.s.18.visible=1 -unit.1.2.port.4.s.19.alias= -unit.1.2.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.19.name=TriggerPort4[19] -unit.1.2.port.4.s.19.orderindex=-1 -unit.1.2.port.4.s.19.visible=1 -unit.1.2.port.4.s.2.alias= -unit.1.2.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.2.name=TriggerPort4[2] -unit.1.2.port.4.s.2.orderindex=-1 -unit.1.2.port.4.s.2.visible=1 -unit.1.2.port.4.s.20.alias= -unit.1.2.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.20.name=TriggerPort4[20] -unit.1.2.port.4.s.20.orderindex=-1 -unit.1.2.port.4.s.20.visible=1 -unit.1.2.port.4.s.21.alias= -unit.1.2.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.21.name=TriggerPort4[21] -unit.1.2.port.4.s.21.orderindex=-1 -unit.1.2.port.4.s.21.visible=1 -unit.1.2.port.4.s.22.alias= -unit.1.2.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.22.name=TriggerPort4[22] -unit.1.2.port.4.s.22.orderindex=-1 -unit.1.2.port.4.s.22.visible=1 -unit.1.2.port.4.s.23.alias= -unit.1.2.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.23.name=TriggerPort4[23] -unit.1.2.port.4.s.23.orderindex=-1 -unit.1.2.port.4.s.23.visible=1 -unit.1.2.port.4.s.24.alias= -unit.1.2.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.24.name=TriggerPort4[24] -unit.1.2.port.4.s.24.orderindex=-1 -unit.1.2.port.4.s.24.visible=1 -unit.1.2.port.4.s.25.alias= -unit.1.2.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.25.name=TriggerPort4[25] -unit.1.2.port.4.s.25.orderindex=-1 -unit.1.2.port.4.s.25.visible=1 -unit.1.2.port.4.s.26.alias= -unit.1.2.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.26.name=TriggerPort4[26] -unit.1.2.port.4.s.26.orderindex=-1 -unit.1.2.port.4.s.26.visible=1 -unit.1.2.port.4.s.27.alias= -unit.1.2.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.27.name=TriggerPort4[27] -unit.1.2.port.4.s.27.orderindex=-1 -unit.1.2.port.4.s.27.visible=1 -unit.1.2.port.4.s.28.alias= -unit.1.2.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.28.name=TriggerPort4[28] -unit.1.2.port.4.s.28.orderindex=-1 -unit.1.2.port.4.s.28.visible=1 -unit.1.2.port.4.s.29.alias= -unit.1.2.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.29.name=TriggerPort4[29] -unit.1.2.port.4.s.29.orderindex=-1 -unit.1.2.port.4.s.29.visible=1 -unit.1.2.port.4.s.3.alias= -unit.1.2.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.3.name=TriggerPort4[3] -unit.1.2.port.4.s.3.orderindex=-1 -unit.1.2.port.4.s.3.visible=1 -unit.1.2.port.4.s.30.alias= -unit.1.2.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.30.name=TriggerPort4[30] -unit.1.2.port.4.s.30.orderindex=-1 -unit.1.2.port.4.s.30.visible=1 -unit.1.2.port.4.s.31.alias= -unit.1.2.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.31.name=TriggerPort4[31] -unit.1.2.port.4.s.31.orderindex=-1 -unit.1.2.port.4.s.31.visible=1 -unit.1.2.port.4.s.4.alias= -unit.1.2.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.4.name=TriggerPort4[4] -unit.1.2.port.4.s.4.orderindex=-1 -unit.1.2.port.4.s.4.visible=1 -unit.1.2.port.4.s.5.alias= -unit.1.2.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.5.name=TriggerPort4[5] -unit.1.2.port.4.s.5.orderindex=-1 -unit.1.2.port.4.s.5.visible=1 -unit.1.2.port.4.s.6.alias= -unit.1.2.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.6.name=TriggerPort4[6] -unit.1.2.port.4.s.6.orderindex=-1 -unit.1.2.port.4.s.6.visible=1 -unit.1.2.port.4.s.7.alias= -unit.1.2.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.7.name=TriggerPort4[7] -unit.1.2.port.4.s.7.orderindex=-1 -unit.1.2.port.4.s.7.visible=1 -unit.1.2.port.4.s.8.alias= -unit.1.2.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.8.name=TriggerPort4[8] -unit.1.2.port.4.s.8.orderindex=-1 -unit.1.2.port.4.s.8.visible=1 -unit.1.2.port.4.s.9.alias= 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-unit.1.3.port.-1.s.68.name=DataPort[68] -unit.1.3.port.-1.s.68.orderindex=-1 -unit.1.3.port.-1.s.68.visible=1 -unit.1.3.port.-1.s.69.alias= -unit.1.3.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.69.name=DataPort[69] -unit.1.3.port.-1.s.69.orderindex=-1 -unit.1.3.port.-1.s.69.visible=1 -unit.1.3.port.-1.s.7.alias= -unit.1.3.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.7.name=DataPort[7] -unit.1.3.port.-1.s.7.orderindex=-1 -unit.1.3.port.-1.s.7.visible=1 -unit.1.3.port.-1.s.70.alias= -unit.1.3.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.70.name=DataPort[70] -unit.1.3.port.-1.s.70.orderindex=-1 -unit.1.3.port.-1.s.70.visible=1 -unit.1.3.port.-1.s.71.alias= -unit.1.3.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.71.name=DataPort[71] -unit.1.3.port.-1.s.71.orderindex=-1 -unit.1.3.port.-1.s.71.visible=1 -unit.1.3.port.-1.s.72.alias= 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-unit.1.3.port.0.s.1.alias= -unit.1.3.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.1.name=TriggerPort0[1] -unit.1.3.port.0.s.1.orderindex=-1 -unit.1.3.port.0.s.1.visible=1 -unit.1.3.port.0.s.10.alias= -unit.1.3.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.10.name=TriggerPort0[10] -unit.1.3.port.0.s.10.orderindex=-1 -unit.1.3.port.0.s.10.visible=1 -unit.1.3.port.0.s.11.alias= -unit.1.3.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.port.4.b.0.alias= -unit.1.3.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.b.0.name=TriggerPort4 -unit.1.3.port.4.b.0.orderindex=-1 -unit.1.3.port.4.b.0.radix=Hex -unit.1.3.port.4.b.0.signedOffset=0.0 -unit.1.3.port.4.b.0.signedPrecision=0 -unit.1.3.port.4.b.0.signedScaleFactor=1.0 -unit.1.3.port.4.b.0.unsignedOffset=0.0 -unit.1.3.port.4.b.0.unsignedPrecision=0 -unit.1.3.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.4.b.0.visible=1 -unit.1.3.port.4.buscount=1 -unit.1.3.port.4.channelcount=32 -unit.1.3.port.4.s.0.alias= -unit.1.3.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.0.name=TriggerPort4[0] -unit.1.3.port.4.s.0.orderindex=-1 -unit.1.3.port.4.s.0.visible=1 -unit.1.3.port.4.s.1.alias= -unit.1.3.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.1.name=TriggerPort4[1] -unit.1.3.port.4.s.1.orderindex=-1 -unit.1.3.port.4.s.1.visible=1 -unit.1.3.port.4.s.10.alias= -unit.1.3.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.10.name=TriggerPort4[10] -unit.1.3.port.4.s.10.orderindex=-1 -unit.1.3.port.4.s.10.visible=1 -unit.1.3.port.4.s.11.alias= -unit.1.3.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.11.name=TriggerPort4[11] -unit.1.3.port.4.s.11.orderindex=-1 -unit.1.3.port.4.s.11.visible=1 -unit.1.3.port.4.s.12.alias= -unit.1.3.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.12.name=TriggerPort4[12] -unit.1.3.port.4.s.12.orderindex=-1 -unit.1.3.port.4.s.12.visible=1 -unit.1.3.port.4.s.13.alias= -unit.1.3.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.13.name=TriggerPort4[13] -unit.1.3.port.4.s.13.orderindex=-1 -unit.1.3.port.4.s.13.visible=1 -unit.1.3.port.4.s.14.alias= -unit.1.3.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.14.name=TriggerPort4[14] -unit.1.3.port.4.s.14.orderindex=-1 -unit.1.3.port.4.s.14.visible=1 -unit.1.3.port.4.s.15.alias= -unit.1.3.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.15.name=TriggerPort4[15] -unit.1.3.port.4.s.15.orderindex=-1 -unit.1.3.port.4.s.15.visible=1 -unit.1.3.port.4.s.16.alias= -unit.1.3.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.16.name=TriggerPort4[16] -unit.1.3.port.4.s.16.orderindex=-1 -unit.1.3.port.4.s.16.visible=1 -unit.1.3.port.4.s.17.alias= -unit.1.3.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.17.name=TriggerPort4[17] -unit.1.3.port.4.s.17.orderindex=-1 -unit.1.3.port.4.s.17.visible=1 -unit.1.3.port.4.s.18.alias= -unit.1.3.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.18.name=TriggerPort4[18] -unit.1.3.port.4.s.18.orderindex=-1 -unit.1.3.port.4.s.18.visible=1 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-unit.1.3.port.4.s.31.name=TriggerPort4[31] -unit.1.3.port.4.s.31.orderindex=-1 -unit.1.3.port.4.s.31.visible=1 -unit.1.3.port.4.s.4.alias= -unit.1.3.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.4.name=TriggerPort4[4] -unit.1.3.port.4.s.4.orderindex=-1 -unit.1.3.port.4.s.4.visible=1 -unit.1.3.port.4.s.5.alias= -unit.1.3.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.5.name=TriggerPort4[5] -unit.1.3.port.4.s.5.orderindex=-1 -unit.1.3.port.4.s.5.visible=1 -unit.1.3.port.4.s.6.alias= -unit.1.3.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.6.name=TriggerPort4[6] -unit.1.3.port.4.s.6.orderindex=-1 -unit.1.3.port.4.s.6.visible=1 -unit.1.3.port.4.s.7.alias= -unit.1.3.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.7.name=TriggerPort4[7] -unit.1.3.port.4.s.7.orderindex=-1 -unit.1.3.port.4.s.7.visible=1 -unit.1.3.port.4.s.8.alias= -unit.1.3.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.8.name=TriggerPort4[8] -unit.1.3.port.4.s.8.orderindex=-1 -unit.1.3.port.4.s.8.visible=1 -unit.1.3.port.4.s.9.alias= -unit.1.3.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.9.name=TriggerPort4[9] -unit.1.3.port.4.s.9.orderindex=-1 -unit.1.3.port.4.s.9.visible=1 -unit.1.3.portcount=5 -unit.1.3.rep_trigger.clobber=1 -unit.1.3.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.3.rep_trigger.filename=waveform -unit.1.3.rep_trigger.format=ASCII -unit.1.3.rep_trigger.loggingEnabled=0 -unit.1.3.rep_trigger.signals=All Signals/Buses -unit.1.3.samplesPerTrigger=1 -unit.1.3.triggerCapture=1 -unit.1.3.triggerNSamplesTS=0 -unit.1.3.triggerPosition=0 -unit.1.3.triggerWindowCount=1 -unit.1.3.triggerWindowDepth=4096 -unit.1.3.triggerWindowTS=0 -unit.1.3.username=MyILA3 -unit.1.3.waveform.count=30 -unit.1.3.waveform.posn.0.channel=2147483646 -unit.1.3.waveform.posn.0.name=dsp_q_tbt -unit.1.3.waveform.posn.0.radix=3 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-unit.1.3.waveform.posn.19.channel=68 -unit.1.3.waveform.posn.19.name=DataPort[68] -unit.1.3.waveform.posn.19.type=signal -unit.1.3.waveform.posn.2.channel=2147483646 -unit.1.3.waveform.posn.2.name=dsp_x_tbt -unit.1.3.waveform.posn.2.radix=3 -unit.1.3.waveform.posn.2.type=bus -unit.1.3.waveform.posn.20.channel=69 -unit.1.3.waveform.posn.20.name=DataPort[69] -unit.1.3.waveform.posn.20.type=signal -unit.1.3.waveform.posn.21.channel=70 -unit.1.3.waveform.posn.21.name=DataPort[70] -unit.1.3.waveform.posn.21.type=signal -unit.1.3.waveform.posn.22.channel=71 -unit.1.3.waveform.posn.22.name=DataPort[71] -unit.1.3.waveform.posn.22.type=signal -unit.1.3.waveform.posn.23.channel=98 -unit.1.3.waveform.posn.23.name=DataPort[98] -unit.1.3.waveform.posn.23.type=signal -unit.1.3.waveform.posn.24.channel=99 -unit.1.3.waveform.posn.24.name=DataPort[99] -unit.1.3.waveform.posn.24.type=signal -unit.1.3.waveform.posn.25.channel=100 -unit.1.3.waveform.posn.25.name=DataPort[100] -unit.1.3.waveform.posn.25.type=signal -unit.1.3.waveform.posn.26.channel=101 -unit.1.3.waveform.posn.26.name=DataPort[101] -unit.1.3.waveform.posn.26.type=signal -unit.1.3.waveform.posn.27.channel=102 -unit.1.3.waveform.posn.27.name=DataPort[102] -unit.1.3.waveform.posn.27.radix=3 -unit.1.3.waveform.posn.27.type=signal -unit.1.3.waveform.posn.28.channel=103 -unit.1.3.waveform.posn.28.name=DataPort[103] -unit.1.3.waveform.posn.28.radix=3 -unit.1.3.waveform.posn.28.type=signal -unit.1.3.waveform.posn.29.channel=2147483646 -unit.1.3.waveform.posn.29.name=dsp_sum_tbt -unit.1.3.waveform.posn.29.radix=3 -unit.1.3.waveform.posn.29.type=bus -unit.1.3.waveform.posn.3.channel=0 -unit.1.3.waveform.posn.3.name=DataPort[0] -unit.1.3.waveform.posn.3.radix=3 -unit.1.3.waveform.posn.3.type=signal -unit.1.3.waveform.posn.30.channel=2147483646 -unit.1.3.waveform.posn.30.name=dsp_sum_tbt -unit.1.3.waveform.posn.30.radix=3 -unit.1.3.waveform.posn.30.type=bus -unit.1.3.waveform.posn.31.channel=2147483646 -unit.1.3.waveform.posn.31.name=dsp_sum_tbt -unit.1.3.waveform.posn.31.radix=3 -unit.1.3.waveform.posn.31.type=bus -unit.1.3.waveform.posn.32.channel=2147483646 -unit.1.3.waveform.posn.32.name=dsp_sum_tbt -unit.1.3.waveform.posn.32.radix=3 -unit.1.3.waveform.posn.32.type=bus -unit.1.3.waveform.posn.33.channel=2147483646 -unit.1.3.waveform.posn.33.name=dsp_sum_tbt -unit.1.3.waveform.posn.33.radix=3 -unit.1.3.waveform.posn.33.type=bus -unit.1.3.waveform.posn.34.channel=2147483646 -unit.1.3.waveform.posn.34.name=dsp_sum_tbt -unit.1.3.waveform.posn.34.radix=3 -unit.1.3.waveform.posn.34.type=bus -unit.1.3.waveform.posn.35.channel=2147483646 -unit.1.3.waveform.posn.35.name=dsp_sum_tbt -unit.1.3.waveform.posn.35.radix=3 -unit.1.3.waveform.posn.35.type=bus -unit.1.3.waveform.posn.36.channel=2147483646 -unit.1.3.waveform.posn.36.name=dsp_sum_tbt -unit.1.3.waveform.posn.36.radix=3 -unit.1.3.waveform.posn.36.type=bus -unit.1.3.waveform.posn.37.channel=2147483646 -unit.1.3.waveform.posn.37.name=dsp_sum_tbt -unit.1.3.waveform.posn.37.radix=3 -unit.1.3.waveform.posn.37.type=bus -unit.1.3.waveform.posn.38.channel=2147483646 -unit.1.3.waveform.posn.38.name=dsp_sum_tbt -unit.1.3.waveform.posn.38.radix=3 -unit.1.3.waveform.posn.38.type=bus -unit.1.3.waveform.posn.39.channel=127 -unit.1.3.waveform.posn.39.name=DataPort[127] -unit.1.3.waveform.posn.39.type=signal -unit.1.3.waveform.posn.4.channel=1 -unit.1.3.waveform.posn.4.name=DataPort[1] -unit.1.3.waveform.posn.4.type=signal -unit.1.3.waveform.posn.40.channel=127 -unit.1.3.waveform.posn.40.name=DataPort[127] -unit.1.3.waveform.posn.40.type=signal -unit.1.3.waveform.posn.41.channel=127 -unit.1.3.waveform.posn.41.name=DataPort[127] -unit.1.3.waveform.posn.41.type=signal -unit.1.3.waveform.posn.42.channel=127 -unit.1.3.waveform.posn.42.name=DataPort[127] -unit.1.3.waveform.posn.42.type=signal -unit.1.3.waveform.posn.43.channel=127 -unit.1.3.waveform.posn.43.name=DataPort[127] -unit.1.3.waveform.posn.43.type=signal -unit.1.3.waveform.posn.44.channel=127 -unit.1.3.waveform.posn.44.name=DataPort[127] -unit.1.3.waveform.posn.44.type=signal -unit.1.3.waveform.posn.45.channel=127 -unit.1.3.waveform.posn.45.name=DataPort[127] -unit.1.3.waveform.posn.45.type=signal -unit.1.3.waveform.posn.46.channel=127 -unit.1.3.waveform.posn.46.name=DataPort[127] -unit.1.3.waveform.posn.46.type=signal -unit.1.3.waveform.posn.47.channel=127 -unit.1.3.waveform.posn.47.name=DataPort[127] -unit.1.3.waveform.posn.47.type=signal -unit.1.3.waveform.posn.48.channel=127 -unit.1.3.waveform.posn.48.name=DataPort[127] -unit.1.3.waveform.posn.48.type=signal -unit.1.3.waveform.posn.49.channel=127 -unit.1.3.waveform.posn.49.name=DataPort[127] -unit.1.3.waveform.posn.49.type=signal -unit.1.3.waveform.posn.5.channel=2 -unit.1.3.waveform.posn.5.name=DataPort[2] -unit.1.3.waveform.posn.5.type=signal -unit.1.3.waveform.posn.50.channel=127 -unit.1.3.waveform.posn.50.name=DataPort[127] -unit.1.3.waveform.posn.50.type=signal -unit.1.3.waveform.posn.51.channel=127 -unit.1.3.waveform.posn.51.name=DataPort[127] -unit.1.3.waveform.posn.51.type=signal -unit.1.3.waveform.posn.52.channel=127 -unit.1.3.waveform.posn.52.name=DataPort[127] -unit.1.3.waveform.posn.52.type=signal -unit.1.3.waveform.posn.53.channel=127 -unit.1.3.waveform.posn.53.name=DataPort[127] -unit.1.3.waveform.posn.53.type=signal -unit.1.3.waveform.posn.54.channel=127 -unit.1.3.waveform.posn.54.name=DataPort[127] -unit.1.3.waveform.posn.54.type=signal -unit.1.3.waveform.posn.55.channel=127 -unit.1.3.waveform.posn.55.name=DataPort[127] -unit.1.3.waveform.posn.55.type=signal -unit.1.3.waveform.posn.56.channel=127 -unit.1.3.waveform.posn.56.name=DataPort[127] -unit.1.3.waveform.posn.56.type=signal -unit.1.3.waveform.posn.57.channel=127 -unit.1.3.waveform.posn.57.name=DataPort[127] -unit.1.3.waveform.posn.57.type=signal -unit.1.3.waveform.posn.58.channel=127 -unit.1.3.waveform.posn.58.name=DataPort[127] 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-unit.1.3.waveform.posn.8.radix=3 -unit.1.3.waveform.posn.8.type=signal -unit.1.3.waveform.posn.80.channel=127 -unit.1.3.waveform.posn.80.name=DataPort[127] -unit.1.3.waveform.posn.80.type=signal -unit.1.3.waveform.posn.81.channel=127 -unit.1.3.waveform.posn.81.name=DataPort[127] -unit.1.3.waveform.posn.81.type=signal -unit.1.3.waveform.posn.82.channel=127 -unit.1.3.waveform.posn.82.name=DataPort[127] -unit.1.3.waveform.posn.82.type=signal -unit.1.3.waveform.posn.83.channel=127 -unit.1.3.waveform.posn.83.name=DataPort[127] -unit.1.3.waveform.posn.83.type=signal -unit.1.3.waveform.posn.84.channel=127 -unit.1.3.waveform.posn.84.name=DataPort[127] -unit.1.3.waveform.posn.84.type=signal -unit.1.3.waveform.posn.85.channel=127 -unit.1.3.waveform.posn.85.name=DataPort[127] -unit.1.3.waveform.posn.85.type=signal -unit.1.3.waveform.posn.86.channel=127 -unit.1.3.waveform.posn.86.name=DataPort[127] -unit.1.3.waveform.posn.86.type=signal -unit.1.3.waveform.posn.87.channel=127 -unit.1.3.waveform.posn.87.name=DataPort[127] -unit.1.3.waveform.posn.87.type=signal -unit.1.3.waveform.posn.88.channel=127 -unit.1.3.waveform.posn.88.name=DataPort[127] -unit.1.3.waveform.posn.88.type=signal -unit.1.3.waveform.posn.89.channel=127 -unit.1.3.waveform.posn.89.name=DataPort[127] -unit.1.3.waveform.posn.89.type=signal -unit.1.3.waveform.posn.9.channel=6 -unit.1.3.waveform.posn.9.name=DataPort[6] -unit.1.3.waveform.posn.9.radix=3 -unit.1.3.waveform.posn.9.type=signal -unit.1.3.waveform.posn.90.channel=127 -unit.1.3.waveform.posn.90.name=DataPort[127] -unit.1.3.waveform.posn.90.type=signal -unit.1.3.waveform.posn.91.channel=127 -unit.1.3.waveform.posn.91.name=DataPort[127] -unit.1.3.waveform.posn.91.type=signal -unit.1.3.waveform.posn.92.channel=127 -unit.1.3.waveform.posn.92.name=DataPort[127] -unit.1.3.waveform.posn.92.type=signal -unit.1.3.waveform.posn.93.channel=127 -unit.1.3.waveform.posn.93.name=DataPort[127] -unit.1.3.waveform.posn.93.type=signal -unit.1.3.waveform.posn.94.channel=127 -unit.1.3.waveform.posn.94.name=DataPort[127] -unit.1.3.waveform.posn.94.type=signal -unit.1.3.waveform.posn.95.channel=127 -unit.1.3.waveform.posn.95.name=DataPort[127] -unit.1.3.waveform.posn.95.type=signal -unit.1.3.waveform.posn.96.channel=127 -unit.1.3.waveform.posn.96.name=DataPort[127] -unit.1.3.waveform.posn.96.type=signal -unit.1.3.waveform.posn.97.channel=127 -unit.1.3.waveform.posn.97.name=DataPort[127] -unit.1.3.waveform.posn.97.type=signal -unit.1.3.waveform.posn.98.channel=127 -unit.1.3.waveform.posn.98.name=DataPort[127] -unit.1.3.waveform.posn.98.type=signal -unit.1.3.waveform.posn.99.channel=127 -unit.1.3.waveform.posn.99.name=DataPort[127] -unit.1.3.waveform.posn.99.type=signal -unit.1.4.0.HEIGHT0=0.37398374 -unit.1.4.0.TriggerRow0=1 -unit.1.4.0.TriggerRow1=1 -unit.1.4.0.TriggerRow2=1 -unit.1.4.0.WIDTH0=0.63801897 -unit.1.4.0.X0=0.069919884 -unit.1.4.0.Y0=0.0 -unit.1.4.1.HEIGHT1=0.7804878 -unit.1.4.1.WIDTH1=0.6132556 -unit.1.4.1.X1=0.0 -unit.1.4.1.Y1=0.045528457 -unit.1.4.5.HEIGHT5=0.7804878 -unit.1.4.5.WIDTH5=0.6839039 -unit.1.4.5.X5=0.009468318 -unit.1.4.5.Y5=0.03902439 -unit.1.4.MFBitsA0=XX1XXXXX -unit.1.4.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsB0=00000000 -unit.1.4.MFBitsB1=00000000000000000000000000000000 -unit.1.4.MFBitsB2=00000000000000000000000000000000 -unit.1.4.MFBitsB3=00000000000000000000000000000000 -unit.1.4.MFBitsB4=00000000000000000000000000000000 -unit.1.4.MFCompareA0=0 -unit.1.4.MFCompareA1=0 -unit.1.4.MFCompareA2=0 -unit.1.4.MFCompareA3=0 -unit.1.4.MFCompareA4=0 -unit.1.4.MFCompareB0=999 -unit.1.4.MFCompareB1=999 -unit.1.4.MFCompareB2=999 -unit.1.4.MFCompareB3=999 -unit.1.4.MFCompareB4=999 -unit.1.4.MFCount=5 -unit.1.4.MFDisplay0=0 -unit.1.4.MFDisplay1=0 -unit.1.4.MFDisplay2=0 -unit.1.4.MFDisplay3=0 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-unit.1.4.port.-1.s.79.name=DataPort[79] -unit.1.4.port.-1.s.79.orderindex=-1 -unit.1.4.port.-1.s.79.visible=0 -unit.1.4.port.-1.s.8.alias= -unit.1.4.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.8.name=DataPort[8] -unit.1.4.port.-1.s.8.orderindex=-1 -unit.1.4.port.-1.s.8.visible=0 -unit.1.4.port.-1.s.80.alias= -unit.1.4.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.80.name=DataPort[80] -unit.1.4.port.-1.s.80.orderindex=-1 -unit.1.4.port.-1.s.80.visible=0 -unit.1.4.port.-1.s.81.alias= -unit.1.4.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.81.name=DataPort[81] -unit.1.4.port.-1.s.81.orderindex=-1 -unit.1.4.port.-1.s.81.visible=0 -unit.1.4.port.-1.s.82.alias= -unit.1.4.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.82.name=DataPort[82] -unit.1.4.port.-1.s.82.orderindex=-1 -unit.1.4.port.-1.s.82.visible=0 -unit.1.4.port.-1.s.83.alias= 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-unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex -unit.1.4.port.1.b.0.signedOffset=0.0 -unit.1.4.port.1.b.0.signedPrecision=0 -unit.1.4.port.1.b.0.signedScaleFactor=1.0 -unit.1.4.port.1.b.0.unsignedOffset=0.0 -unit.1.4.port.1.b.0.unsignedPrecision=0 -unit.1.4.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.1.b.0.visible=1 -unit.1.4.port.1.buscount=1 -unit.1.4.port.1.channelcount=32 -unit.1.4.port.1.s.0.alias= -unit.1.4.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.0.name=TriggerPort1[0] -unit.1.4.port.1.s.0.orderindex=-1 -unit.1.4.port.1.s.0.visible=1 -unit.1.4.port.1.s.1.alias= -unit.1.4.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.1.name=TriggerPort1[1] -unit.1.4.port.1.s.1.orderindex=-1 -unit.1.4.port.1.s.1.visible=1 -unit.1.4.port.1.s.10.alias= -unit.1.4.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.10.name=TriggerPort1[10] -unit.1.4.port.1.s.10.orderindex=-1 -unit.1.4.port.1.s.10.visible=1 -unit.1.4.port.1.s.11.alias= -unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 -unit.1.4.port.1.s.16.alias= -unit.1.4.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.16.name=TriggerPort1[16] -unit.1.4.port.1.s.16.orderindex=-1 -unit.1.4.port.1.s.16.visible=1 -unit.1.4.port.1.s.17.alias= -unit.1.4.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.17.name=TriggerPort1[17] -unit.1.4.port.1.s.17.orderindex=-1 -unit.1.4.port.1.s.17.visible=1 -unit.1.4.port.1.s.18.alias= -unit.1.4.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.18.name=TriggerPort1[18] -unit.1.4.port.1.s.18.orderindex=-1 -unit.1.4.port.1.s.18.visible=1 -unit.1.4.port.1.s.19.alias= -unit.1.4.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.19.name=TriggerPort1[19] -unit.1.4.port.1.s.19.orderindex=-1 -unit.1.4.port.1.s.19.visible=1 -unit.1.4.port.1.s.2.alias= -unit.1.4.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.2.name=TriggerPort1[2] -unit.1.4.port.1.s.2.orderindex=-1 -unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.18.name=TriggerPort3[18] -unit.1.4.port.3.s.18.orderindex=-1 -unit.1.4.port.3.s.18.visible=1 -unit.1.4.port.3.s.19.alias= -unit.1.4.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.19.name=TriggerPort3[19] -unit.1.4.port.3.s.19.orderindex=-1 -unit.1.4.port.3.s.19.visible=1 -unit.1.4.port.3.s.2.alias= -unit.1.4.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.2.name=TriggerPort3[2] -unit.1.4.port.3.s.2.orderindex=-1 -unit.1.4.port.3.s.2.visible=1 -unit.1.4.port.3.s.20.alias= -unit.1.4.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.20.name=TriggerPort3[20] -unit.1.4.port.3.s.20.orderindex=-1 -unit.1.4.port.3.s.20.visible=1 -unit.1.4.port.3.s.21.alias= -unit.1.4.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.21.name=TriggerPort3[21] -unit.1.4.port.3.s.21.orderindex=-1 -unit.1.4.port.3.s.21.visible=1 -unit.1.4.port.3.s.22.alias= -unit.1.4.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.22.name=TriggerPort3[22] -unit.1.4.port.3.s.22.orderindex=-1 -unit.1.4.port.3.s.22.visible=1 -unit.1.4.port.3.s.23.alias= -unit.1.4.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.23.name=TriggerPort3[23] -unit.1.4.port.3.s.23.orderindex=-1 -unit.1.4.port.3.s.23.visible=1 -unit.1.4.port.3.s.24.alias= -unit.1.4.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.24.name=TriggerPort3[24] -unit.1.4.port.3.s.24.orderindex=-1 -unit.1.4.port.3.s.24.visible=1 -unit.1.4.port.3.s.25.alias= -unit.1.4.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.25.name=TriggerPort3[25] -unit.1.4.port.3.s.25.orderindex=-1 -unit.1.4.port.3.s.25.visible=1 -unit.1.4.port.3.s.26.alias= -unit.1.4.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.26.name=TriggerPort3[26] -unit.1.4.port.3.s.26.orderindex=-1 -unit.1.4.port.3.s.26.visible=1 -unit.1.4.port.3.s.27.alias= -unit.1.4.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.27.name=TriggerPort3[27] -unit.1.4.port.3.s.27.orderindex=-1 -unit.1.4.port.3.s.27.visible=1 -unit.1.4.port.3.s.28.alias= -unit.1.4.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.28.name=TriggerPort3[28] -unit.1.4.port.3.s.28.orderindex=-1 -unit.1.4.port.3.s.28.visible=1 -unit.1.4.port.3.s.29.alias= -unit.1.4.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.29.name=TriggerPort3[29] -unit.1.4.port.3.s.29.orderindex=-1 -unit.1.4.port.3.s.29.visible=1 -unit.1.4.port.3.s.3.alias= -unit.1.4.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.3.name=TriggerPort3[3] -unit.1.4.port.3.s.3.orderindex=-1 -unit.1.4.port.3.s.3.visible=1 -unit.1.4.port.3.s.30.alias= -unit.1.4.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.30.name=TriggerPort3[30] -unit.1.4.port.3.s.30.orderindex=-1 -unit.1.4.port.3.s.30.visible=1 -unit.1.4.port.3.s.31.alias= -unit.1.4.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.31.name=TriggerPort3[31] -unit.1.4.port.3.s.31.orderindex=-1 -unit.1.4.port.3.s.31.visible=1 -unit.1.4.port.3.s.4.alias= -unit.1.4.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.4.name=TriggerPort3[4] -unit.1.4.port.3.s.4.orderindex=-1 -unit.1.4.port.3.s.4.visible=1 -unit.1.4.port.3.s.5.alias= -unit.1.4.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.5.name=TriggerPort3[5] -unit.1.4.port.3.s.5.orderindex=-1 -unit.1.4.port.3.s.5.visible=1 -unit.1.4.port.3.s.6.alias= -unit.1.4.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.6.name=TriggerPort3[6] -unit.1.4.port.3.s.6.orderindex=-1 -unit.1.4.port.3.s.6.visible=1 -unit.1.4.port.3.s.7.alias= -unit.1.4.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.7.name=TriggerPort3[7] -unit.1.4.port.3.s.7.orderindex=-1 -unit.1.4.port.3.s.7.visible=1 -unit.1.4.port.3.s.8.alias= -unit.1.4.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.8.name=TriggerPort3[8] -unit.1.4.port.3.s.8.orderindex=-1 -unit.1.4.port.3.s.8.visible=1 -unit.1.4.port.3.s.9.alias= -unit.1.4.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.9.name=TriggerPort3[9] -unit.1.4.port.3.s.9.orderindex=-1 -unit.1.4.port.3.s.9.visible=1 -unit.1.4.port.4.b.0.alias= -unit.1.4.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.b.0.name=TriggerPort4 -unit.1.4.port.4.b.0.orderindex=-1 -unit.1.4.port.4.b.0.radix=Hex -unit.1.4.port.4.b.0.signedOffset=0.0 -unit.1.4.port.4.b.0.signedPrecision=0 -unit.1.4.port.4.b.0.signedScaleFactor=1.0 -unit.1.4.port.4.b.0.unsignedOffset=0.0 -unit.1.4.port.4.b.0.unsignedPrecision=0 -unit.1.4.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.4.b.0.visible=1 -unit.1.4.port.4.buscount=1 -unit.1.4.port.4.channelcount=32 -unit.1.4.port.4.s.0.alias= -unit.1.4.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.0.name=TriggerPort4[0] -unit.1.4.port.4.s.0.orderindex=-1 -unit.1.4.port.4.s.0.visible=1 -unit.1.4.port.4.s.1.alias= -unit.1.4.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.1.name=TriggerPort4[1] -unit.1.4.port.4.s.1.orderindex=-1 -unit.1.4.port.4.s.1.visible=1 -unit.1.4.port.4.s.10.alias= -unit.1.4.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.10.name=TriggerPort4[10] -unit.1.4.port.4.s.10.orderindex=-1 -unit.1.4.port.4.s.10.visible=1 -unit.1.4.port.4.s.11.alias= -unit.1.4.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.11.name=TriggerPort4[11] -unit.1.4.port.4.s.11.orderindex=-1 -unit.1.4.port.4.s.11.visible=1 -unit.1.4.port.4.s.12.alias= -unit.1.4.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.12.name=TriggerPort4[12] -unit.1.4.port.4.s.12.orderindex=-1 -unit.1.4.port.4.s.12.visible=1 -unit.1.4.port.4.s.13.alias= -unit.1.4.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.13.name=TriggerPort4[13] -unit.1.4.port.4.s.13.orderindex=-1 -unit.1.4.port.4.s.13.visible=1 -unit.1.4.port.4.s.14.alias= -unit.1.4.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.14.name=TriggerPort4[14] -unit.1.4.port.4.s.14.orderindex=-1 -unit.1.4.port.4.s.14.visible=1 -unit.1.4.port.4.s.15.alias= -unit.1.4.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.15.name=TriggerPort4[15] -unit.1.4.port.4.s.15.orderindex=-1 -unit.1.4.port.4.s.15.visible=1 -unit.1.4.port.4.s.16.alias= -unit.1.4.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.16.name=TriggerPort4[16] -unit.1.4.port.4.s.16.orderindex=-1 -unit.1.4.port.4.s.16.visible=1 -unit.1.4.port.4.s.17.alias= -unit.1.4.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.17.name=TriggerPort4[17] -unit.1.4.port.4.s.17.orderindex=-1 -unit.1.4.port.4.s.17.visible=1 -unit.1.4.port.4.s.18.alias= -unit.1.4.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.18.name=TriggerPort4[18] -unit.1.4.port.4.s.18.orderindex=-1 -unit.1.4.port.4.s.18.visible=1 -unit.1.4.port.4.s.19.alias= -unit.1.4.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.19.name=TriggerPort4[19] -unit.1.4.port.4.s.19.orderindex=-1 -unit.1.4.port.4.s.19.visible=1 -unit.1.4.port.4.s.2.alias= -unit.1.4.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.2.name=TriggerPort4[2] -unit.1.4.port.4.s.2.orderindex=-1 -unit.1.4.port.4.s.2.visible=1 -unit.1.4.port.4.s.20.alias= -unit.1.4.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.20.name=TriggerPort4[20] -unit.1.4.port.4.s.20.orderindex=-1 -unit.1.4.port.4.s.20.visible=1 -unit.1.4.port.4.s.21.alias= -unit.1.4.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.21.name=TriggerPort4[21] -unit.1.4.port.4.s.21.orderindex=-1 -unit.1.4.port.4.s.21.visible=1 -unit.1.4.port.4.s.22.alias= -unit.1.4.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.22.name=TriggerPort4[22] -unit.1.4.port.4.s.22.orderindex=-1 -unit.1.4.port.4.s.22.visible=1 -unit.1.4.port.4.s.23.alias= -unit.1.4.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.23.name=TriggerPort4[23] -unit.1.4.port.4.s.23.orderindex=-1 -unit.1.4.port.4.s.23.visible=1 -unit.1.4.port.4.s.24.alias= -unit.1.4.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.4.s.24.name=TriggerPort4[24] -unit.1.4.port.4.s.24.orderindex=-1 -unit.1.4.port.4.s.24.visible=1 -unit.1.4.port.4.s.25.alias= -unit.1.4.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.5.port.-1.s.89.name=DataPort[89] -unit.1.5.port.-1.s.89.orderindex=-1 -unit.1.5.port.-1.s.89.visible=0 -unit.1.5.port.-1.s.9.alias= -unit.1.5.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.9.name=DataPort[9] -unit.1.5.port.-1.s.9.orderindex=-1 -unit.1.5.port.-1.s.9.visible=0 -unit.1.5.port.-1.s.90.alias= -unit.1.5.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.90.name=DataPort[90] -unit.1.5.port.-1.s.90.orderindex=-1 -unit.1.5.port.-1.s.90.visible=0 -unit.1.5.port.-1.s.91.alias= -unit.1.5.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.91.name=DataPort[91] -unit.1.5.port.-1.s.91.orderindex=-1 -unit.1.5.port.-1.s.91.visible=0 -unit.1.5.port.-1.s.92.alias= -unit.1.5.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.92.name=DataPort[92] -unit.1.5.port.-1.s.92.orderindex=-1 -unit.1.5.port.-1.s.92.visible=0 -unit.1.5.port.-1.s.93.alias= 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-unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 -unit.1.5.port.3.s.16.alias= -unit.1.5.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.16.name=TriggerPort3[16] -unit.1.5.port.3.s.16.orderindex=-1 -unit.1.5.port.3.s.16.visible=1 -unit.1.5.port.3.s.17.alias= -unit.1.5.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.17.name=TriggerPort3[17] -unit.1.5.port.3.s.17.orderindex=-1 -unit.1.5.port.3.s.17.visible=1 -unit.1.5.port.3.s.18.alias= -unit.1.5.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.18.name=TriggerPort3[18] -unit.1.5.port.3.s.18.orderindex=-1 -unit.1.5.port.3.s.18.visible=1 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-unit.1.5.triggerWindowTS=0 -unit.1.5.username=MyILA5 -unit.1.5.waveform.count=36 -unit.1.5.waveform.posn.0.channel=0 -unit.1.5.waveform.posn.0.name=DataPort[0] -unit.1.5.waveform.posn.0.type=signal -unit.1.5.waveform.posn.1.channel=1 -unit.1.5.waveform.posn.1.name=DataPort[1] -unit.1.5.waveform.posn.1.type=signal -unit.1.5.waveform.posn.10.channel=36 -unit.1.5.waveform.posn.10.name=DataPort[36] -unit.1.5.waveform.posn.10.type=signal -unit.1.5.waveform.posn.11.channel=37 -unit.1.5.waveform.posn.11.name=DataPort[37] -unit.1.5.waveform.posn.11.type=signal -unit.1.5.waveform.posn.12.channel=38 -unit.1.5.waveform.posn.12.name=DataPort[38] -unit.1.5.waveform.posn.12.type=signal -unit.1.5.waveform.posn.13.channel=39 -unit.1.5.waveform.posn.13.name=DataPort[39] -unit.1.5.waveform.posn.13.type=signal -unit.1.5.waveform.posn.14.channel=66 -unit.1.5.waveform.posn.14.name=DataPort[66] -unit.1.5.waveform.posn.14.type=signal -unit.1.5.waveform.posn.15.channel=67 -unit.1.5.waveform.posn.15.name=DataPort[67] -unit.1.5.waveform.posn.15.type=signal -unit.1.5.waveform.posn.16.channel=68 -unit.1.5.waveform.posn.16.name=DataPort[68] -unit.1.5.waveform.posn.16.type=signal -unit.1.5.waveform.posn.17.channel=69 -unit.1.5.waveform.posn.17.name=DataPort[69] -unit.1.5.waveform.posn.17.type=signal -unit.1.5.waveform.posn.18.channel=70 -unit.1.5.waveform.posn.18.name=DataPort[70] -unit.1.5.waveform.posn.18.type=signal -unit.1.5.waveform.posn.19.channel=71 -unit.1.5.waveform.posn.19.name=DataPort[71] -unit.1.5.waveform.posn.19.type=signal -unit.1.5.waveform.posn.2.channel=2 -unit.1.5.waveform.posn.2.name=DataPort[2] -unit.1.5.waveform.posn.2.type=signal -unit.1.5.waveform.posn.20.channel=98 -unit.1.5.waveform.posn.20.name=DataPort[98] -unit.1.5.waveform.posn.20.type=signal -unit.1.5.waveform.posn.21.channel=99 -unit.1.5.waveform.posn.21.name=DataPort[99] -unit.1.5.waveform.posn.21.type=signal -unit.1.5.waveform.posn.22.channel=100 -unit.1.5.waveform.posn.22.name=DataPort[100] -unit.1.5.waveform.posn.22.type=signal -unit.1.5.waveform.posn.23.channel=101 -unit.1.5.waveform.posn.23.name=DataPort[101] -unit.1.5.waveform.posn.23.type=signal -unit.1.5.waveform.posn.24.channel=102 -unit.1.5.waveform.posn.24.name=DataPort[102] -unit.1.5.waveform.posn.24.type=signal -unit.1.5.waveform.posn.25.channel=103 -unit.1.5.waveform.posn.25.name=DataPort[103] -unit.1.5.waveform.posn.25.type=signal -unit.1.5.waveform.posn.26.channel=130 -unit.1.5.waveform.posn.26.name=DataPort[130] -unit.1.5.waveform.posn.26.type=signal -unit.1.5.waveform.posn.27.channel=131 -unit.1.5.waveform.posn.27.name=DataPort[131] -unit.1.5.waveform.posn.27.type=signal -unit.1.5.waveform.posn.28.channel=132 -unit.1.5.waveform.posn.28.name=DataPort[132] -unit.1.5.waveform.posn.28.type=signal -unit.1.5.waveform.posn.29.channel=133 -unit.1.5.waveform.posn.29.name=DataPort[133] -unit.1.5.waveform.posn.29.type=signal -unit.1.5.waveform.posn.3.channel=3 -unit.1.5.waveform.posn.3.name=DataPort[3] -unit.1.5.waveform.posn.3.type=signal -unit.1.5.waveform.posn.30.channel=134 -unit.1.5.waveform.posn.30.name=DataPort[134] -unit.1.5.waveform.posn.30.type=signal -unit.1.5.waveform.posn.31.channel=135 -unit.1.5.waveform.posn.31.name=DataPort[135] -unit.1.5.waveform.posn.31.type=signal -unit.1.5.waveform.posn.32.channel=2147483646 -unit.1.5.waveform.posn.32.name=dsp_q_fofb -unit.1.5.waveform.posn.32.radix=3 -unit.1.5.waveform.posn.32.type=bus -unit.1.5.waveform.posn.33.channel=2147483646 -unit.1.5.waveform.posn.33.name=dsp_sum_fofb -unit.1.5.waveform.posn.33.radix=3 -unit.1.5.waveform.posn.33.type=bus -unit.1.5.waveform.posn.34.channel=2147483646 -unit.1.5.waveform.posn.34.name=dsp_x_fofb -unit.1.5.waveform.posn.34.radix=3 -unit.1.5.waveform.posn.34.type=bus -unit.1.5.waveform.posn.35.channel=2147483646 -unit.1.5.waveform.posn.35.name=dsp_y_fofb -unit.1.5.waveform.posn.35.radix=3 -unit.1.5.waveform.posn.35.type=bus -unit.1.5.waveform.posn.36.channel=2147483646 -unit.1.5.waveform.posn.36.name=dsp_y_fofb -unit.1.5.waveform.posn.36.radix=3 -unit.1.5.waveform.posn.36.type=bus -unit.1.5.waveform.posn.37.channel=2147483646 -unit.1.5.waveform.posn.37.name=dsp_y_fofb -unit.1.5.waveform.posn.37.radix=3 -unit.1.5.waveform.posn.37.type=bus -unit.1.5.waveform.posn.38.channel=2147483646 -unit.1.5.waveform.posn.38.name=dsp_y_fofb -unit.1.5.waveform.posn.38.radix=3 -unit.1.5.waveform.posn.38.type=bus -unit.1.5.waveform.posn.39.channel=2147483646 -unit.1.5.waveform.posn.39.name=dsp_y_fofb -unit.1.5.waveform.posn.39.radix=3 -unit.1.5.waveform.posn.39.type=bus -unit.1.5.waveform.posn.4.channel=4 -unit.1.5.waveform.posn.4.name=DataPort[4] -unit.1.5.waveform.posn.4.type=signal -unit.1.5.waveform.posn.40.channel=2147483646 -unit.1.5.waveform.posn.40.name=dsp_y_fofb -unit.1.5.waveform.posn.40.radix=3 -unit.1.5.waveform.posn.40.type=bus -unit.1.5.waveform.posn.41.channel=2147483646 -unit.1.5.waveform.posn.41.name=dsp_y_fofb -unit.1.5.waveform.posn.41.radix=3 -unit.1.5.waveform.posn.41.type=bus -unit.1.5.waveform.posn.42.channel=2147483646 -unit.1.5.waveform.posn.42.name=dsp_y_fofb -unit.1.5.waveform.posn.42.radix=3 -unit.1.5.waveform.posn.42.type=bus -unit.1.5.waveform.posn.43.channel=2147483646 -unit.1.5.waveform.posn.43.name=dsp_y_fofb -unit.1.5.waveform.posn.43.radix=3 -unit.1.5.waveform.posn.43.type=bus -unit.1.5.waveform.posn.44.channel=2147483646 -unit.1.5.waveform.posn.44.name=dsp_y_fofb -unit.1.5.waveform.posn.44.radix=3 -unit.1.5.waveform.posn.44.type=bus -unit.1.5.waveform.posn.45.channel=2147483646 -unit.1.5.waveform.posn.45.name=dsp_y_fofb -unit.1.5.waveform.posn.45.radix=3 -unit.1.5.waveform.posn.45.type=bus -unit.1.5.waveform.posn.46.channel=2147483646 -unit.1.5.waveform.posn.46.name=dsp_y_fofb -unit.1.5.waveform.posn.46.radix=3 -unit.1.5.waveform.posn.46.type=bus -unit.1.5.waveform.posn.5.channel=5 -unit.1.5.waveform.posn.5.name=DataPort[5] -unit.1.5.waveform.posn.5.type=signal -unit.1.5.waveform.posn.6.channel=6 -unit.1.5.waveform.posn.6.name=DataPort[6] -unit.1.5.waveform.posn.6.type=signal -unit.1.5.waveform.posn.7.channel=7 -unit.1.5.waveform.posn.7.name=DataPort[7] -unit.1.5.waveform.posn.7.type=signal -unit.1.5.waveform.posn.8.channel=34 -unit.1.5.waveform.posn.8.name=DataPort[34] -unit.1.5.waveform.posn.8.type=signal -unit.1.5.waveform.posn.9.channel=35 -unit.1.5.waveform.posn.9.name=DataPort[35] -unit.1.5.waveform.posn.9.type=signal -unit.1.6.0.HEIGHT0=0.37398374 -unit.1.6.0.TriggerRow0=1 -unit.1.6.0.TriggerRow1=1 -unit.1.6.0.TriggerRow2=1 -unit.1.6.0.WIDTH0=0.63801897 -unit.1.6.0.X0=0.069919884 -unit.1.6.0.Y0=0.0 -unit.1.6.1.HEIGHT1=0.7804878 -unit.1.6.1.WIDTH1=0.58557904 -unit.1.6.1.X1=0.024763292 -unit.1.6.1.Y1=0.068292685 -unit.1.6.5.HEIGHT5=0.7804878 -unit.1.6.5.WIDTH5=0.8550619 -unit.1.6.5.X5=0.076474875 -unit.1.6.5.Y5=0.037398376 -unit.1.6.MFBitsA0=XXXXX1XX -unit.1.6.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsB0=00000000 -unit.1.6.MFBitsB1=00000000000000000000000000000000 -unit.1.6.MFBitsB2=00000000000000000000000000000000 -unit.1.6.MFBitsB3=00000000000000000000000000000000 -unit.1.6.MFBitsB4=00000000000000000000000000000000 -unit.1.6.MFCompareA0=0 -unit.1.6.MFCompareA1=0 -unit.1.6.MFCompareA2=0 -unit.1.6.MFCompareA3=0 -unit.1.6.MFCompareA4=0 -unit.1.6.MFCompareB0=999 -unit.1.6.MFCompareB1=999 -unit.1.6.MFCompareB2=999 -unit.1.6.MFCompareB3=999 -unit.1.6.MFCompareB4=999 -unit.1.6.MFCount=5 -unit.1.6.MFDisplay0=0 -unit.1.6.MFDisplay1=0 -unit.1.6.MFDisplay2=0 -unit.1.6.MFDisplay3=0 -unit.1.6.MFDisplay4=0 -unit.1.6.MFEventType0=3 -unit.1.6.MFEventType1=3 -unit.1.6.MFEventType2=3 -unit.1.6.MFEventType3=3 -unit.1.6.MFEventType4=3 -unit.1.6.RunMode=SINGLE RUN -unit.1.6.SQCondition=M0 -unit.1.6.SQContiguous0=0 -unit.1.6.SequencerOn=0 -unit.1.6.TCActive=0 -unit.1.6.TCAdvanced0=0 -unit.1.6.TCCondition0_0=M0 -unit.1.6.TCCondition0_1= -unit.1.6.TCConditionType0=0 -unit.1.6.TCCount=1 -unit.1.6.TCEventCount0=1 -unit.1.6.TCEventType0=3 -unit.1.6.TCName0=TriggerCondition0 -unit.1.6.TCOutputEnable0=0 -unit.1.6.TCOutputHigh0=1 -unit.1.6.TCOutputMode0=0 -unit.1.6.browser_tree_state=1 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.coretype=ILA -unit.1.6.eventCount0=1 -unit.1.6.eventCount1=1 -unit.1.6.eventCount2=1 -unit.1.6.eventCount3=1 -unit.1.6.eventCount4=1 -unit.1.6.plotBusColor0=-10066177 -unit.1.6.plotBusColor1=-3355648 -unit.1.6.plotBusColor2=-16776961 -unit.1.6.plotBusColor3=-52429 -unit.1.6.plotBusCount=4 -unit.1.6.plotBusName0=dsp_q_monit -unit.1.6.plotBusName1=dsp_sum_monit -unit.1.6.plotBusName2=dsp_x_monit -unit.1.6.plotBusName3=dsp_y_monit -unit.1.6.plotBusX=dsp_q_monit -unit.1.6.plotBusY=dsp_sum_monit -unit.1.6.plotDataTimeMode=1 -unit.1.6.plotDisplayMode=line -unit.1.6.plotMaxX=0.0 -unit.1.6.plotMaxY=0.0 -unit.1.6.plotMinX=0.0 -unit.1.6.plotMinY=0.0 -unit.1.6.plotSelectedBus=0 -unit.1.6.port.-1.b.0.alias=dsp_q_monit -unit.1.6.port.-1.b.0.channellist=72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 -unit.1.6.port.-1.b.0.color=java.awt.Color[r\=102,g\=102,b\=255] -unit.1.6.port.-1.b.0.name=DataPort -unit.1.6.port.-1.b.0.orderindex=-1 -unit.1.6.port.-1.b.0.radix=Signed -unit.1.6.port.-1.b.0.signedOffset=0.0 -unit.1.6.port.-1.b.0.signedPrecision=0 -unit.1.6.port.-1.b.0.signedScaleFactor=1.0 -unit.1.6.port.-1.b.0.tokencount=0 -unit.1.6.port.-1.b.0.unsignedOffset=0.0 -unit.1.6.port.-1.b.0.unsignedPrecision=0 -unit.1.6.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.0.visible=1 -unit.1.6.port.-1.b.1.alias=dsp_sum_monit -unit.1.6.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 -unit.1.6.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.6.port.-1.b.1.name=DataPort -unit.1.6.port.-1.b.1.orderindex=-1 -unit.1.6.port.-1.b.1.radix=Signed -unit.1.6.port.-1.b.1.signedOffset=0.0 -unit.1.6.port.-1.b.1.signedPrecision=0 -unit.1.6.port.-1.b.1.signedScaleFactor=1.0 -unit.1.6.port.-1.b.1.tokencount=0 -unit.1.6.port.-1.b.1.unsignedOffset=0.0 -unit.1.6.port.-1.b.1.unsignedPrecision=0 -unit.1.6.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.1.visible=1 -unit.1.6.port.-1.b.2.alias=dsp_x_monit -unit.1.6.port.-1.b.2.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 -unit.1.6.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=255] -unit.1.6.port.-1.b.2.name=DataPort -unit.1.6.port.-1.b.2.orderindex=-1 -unit.1.6.port.-1.b.2.radix=Signed -unit.1.6.port.-1.b.2.signedOffset=0.0 -unit.1.6.port.-1.b.2.signedPrecision=0 -unit.1.6.port.-1.b.2.signedScaleFactor=1.0 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-unit.1.6.port.0.buscount=1 -unit.1.6.port.0.channelcount=8 -unit.1.6.port.0.s.0.alias= -unit.1.6.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.0.name=TriggerPort0[0] -unit.1.6.port.0.s.0.orderindex=-1 -unit.1.6.port.0.s.0.visible=1 -unit.1.6.port.0.s.1.alias= -unit.1.6.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.1.name=TriggerPort0[1] -unit.1.6.port.0.s.1.orderindex=-1 -unit.1.6.port.0.s.1.visible=1 -unit.1.6.port.0.s.2.alias= -unit.1.6.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.2.name=TriggerPort0[2] -unit.1.6.port.0.s.2.orderindex=-1 -unit.1.6.port.0.s.2.visible=1 -unit.1.6.port.0.s.3.alias= -unit.1.6.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.3.name=TriggerPort0[3] -unit.1.6.port.0.s.3.orderindex=-1 -unit.1.6.port.0.s.3.visible=1 -unit.1.6.port.0.s.4.alias= -unit.1.6.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.4.name=TriggerPort0[4] -unit.1.6.port.0.s.4.orderindex=-1 -unit.1.6.port.0.s.4.visible=1 -unit.1.6.port.0.s.5.alias= -unit.1.6.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.5.name=TriggerPort0[5] -unit.1.6.port.0.s.5.orderindex=-1 -unit.1.6.port.0.s.5.visible=1 -unit.1.6.port.0.s.6.alias= -unit.1.6.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.6.name=TriggerPort0[6] -unit.1.6.port.0.s.6.orderindex=-1 -unit.1.6.port.0.s.6.visible=1 -unit.1.6.port.0.s.7.alias= -unit.1.6.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.0.s.7.name=TriggerPort0[7] -unit.1.6.port.0.s.7.orderindex=-1 -unit.1.6.port.0.s.7.visible=1 -unit.1.6.port.1.b.0.alias= -unit.1.6.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.b.0.name=TriggerPort1 -unit.1.6.port.1.b.0.orderindex=-1 -unit.1.6.port.1.b.0.radix=Hex -unit.1.6.port.1.b.0.signedOffset=0.0 -unit.1.6.port.1.b.0.signedPrecision=0 -unit.1.6.port.1.b.0.signedScaleFactor=1.0 -unit.1.6.port.1.b.0.unsignedOffset=0.0 -unit.1.6.port.1.b.0.unsignedPrecision=0 -unit.1.6.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.1.b.0.visible=1 -unit.1.6.port.1.buscount=1 -unit.1.6.port.1.channelcount=32 -unit.1.6.port.1.s.0.alias= -unit.1.6.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.0.name=TriggerPort1[0] -unit.1.6.port.1.s.0.orderindex=-1 -unit.1.6.port.1.s.0.visible=1 -unit.1.6.port.1.s.1.alias= -unit.1.6.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.1.name=TriggerPort1[1] -unit.1.6.port.1.s.1.orderindex=-1 -unit.1.6.port.1.s.1.visible=1 -unit.1.6.port.1.s.10.alias= -unit.1.6.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.10.name=TriggerPort1[10] -unit.1.6.port.1.s.10.orderindex=-1 -unit.1.6.port.1.s.10.visible=1 -unit.1.6.port.1.s.11.alias= -unit.1.6.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.11.name=TriggerPort1[11] -unit.1.6.port.1.s.11.orderindex=-1 -unit.1.6.port.1.s.11.visible=1 -unit.1.6.port.1.s.12.alias= -unit.1.6.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.12.name=TriggerPort1[12] -unit.1.6.port.1.s.12.orderindex=-1 -unit.1.6.port.1.s.12.visible=1 -unit.1.6.port.1.s.13.alias= -unit.1.6.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.13.name=TriggerPort1[13] -unit.1.6.port.1.s.13.orderindex=-1 -unit.1.6.port.1.s.13.visible=1 -unit.1.6.port.1.s.14.alias= -unit.1.6.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.14.name=TriggerPort1[14] -unit.1.6.port.1.s.14.orderindex=-1 -unit.1.6.port.1.s.14.visible=1 -unit.1.6.port.1.s.15.alias= -unit.1.6.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.15.name=TriggerPort1[15] -unit.1.6.port.1.s.15.orderindex=-1 -unit.1.6.port.1.s.15.visible=1 -unit.1.6.port.1.s.16.alias= -unit.1.6.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.16.name=TriggerPort1[16] -unit.1.6.port.1.s.16.orderindex=-1 -unit.1.6.port.1.s.16.visible=1 -unit.1.6.port.1.s.17.alias= -unit.1.6.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.17.name=TriggerPort1[17] -unit.1.6.port.1.s.17.orderindex=-1 -unit.1.6.port.1.s.17.visible=1 -unit.1.6.port.1.s.18.alias= -unit.1.6.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.18.name=TriggerPort1[18] -unit.1.6.port.1.s.18.orderindex=-1 -unit.1.6.port.1.s.18.visible=1 -unit.1.6.port.1.s.19.alias= -unit.1.6.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.19.name=TriggerPort1[19] -unit.1.6.port.1.s.19.orderindex=-1 -unit.1.6.port.1.s.19.visible=1 -unit.1.6.port.1.s.2.alias= -unit.1.6.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.2.name=TriggerPort1[2] -unit.1.6.port.1.s.2.orderindex=-1 -unit.1.6.port.1.s.2.visible=1 -unit.1.6.port.1.s.20.alias= -unit.1.6.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.20.name=TriggerPort1[20] -unit.1.6.port.1.s.20.orderindex=-1 -unit.1.6.port.1.s.20.visible=1 -unit.1.6.port.1.s.21.alias= -unit.1.6.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.21.name=TriggerPort1[21] -unit.1.6.port.1.s.21.orderindex=-1 -unit.1.6.port.1.s.21.visible=1 -unit.1.6.port.1.s.22.alias= -unit.1.6.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.22.name=TriggerPort1[22] -unit.1.6.port.1.s.22.orderindex=-1 -unit.1.6.port.1.s.22.visible=1 -unit.1.6.port.1.s.23.alias= -unit.1.6.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.23.name=TriggerPort1[23] -unit.1.6.port.1.s.23.orderindex=-1 -unit.1.6.port.1.s.23.visible=1 -unit.1.6.port.1.s.24.alias= -unit.1.6.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.24.name=TriggerPort1[24] -unit.1.6.port.1.s.24.orderindex=-1 -unit.1.6.port.1.s.24.visible=1 -unit.1.6.port.1.s.25.alias= -unit.1.6.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.25.name=TriggerPort1[25] -unit.1.6.port.1.s.25.orderindex=-1 -unit.1.6.port.1.s.25.visible=1 -unit.1.6.port.1.s.26.alias= -unit.1.6.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.26.name=TriggerPort1[26] -unit.1.6.port.1.s.26.orderindex=-1 -unit.1.6.port.1.s.26.visible=1 -unit.1.6.port.1.s.27.alias= -unit.1.6.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.27.name=TriggerPort1[27] -unit.1.6.port.1.s.27.orderindex=-1 -unit.1.6.port.1.s.27.visible=1 -unit.1.6.port.1.s.28.alias= -unit.1.6.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.28.name=TriggerPort1[28] -unit.1.6.port.1.s.28.orderindex=-1 -unit.1.6.port.1.s.28.visible=1 -unit.1.6.port.1.s.29.alias= -unit.1.6.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.29.name=TriggerPort1[29] -unit.1.6.port.1.s.29.orderindex=-1 -unit.1.6.port.1.s.29.visible=1 -unit.1.6.port.1.s.3.alias= -unit.1.6.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.3.name=TriggerPort1[3] -unit.1.6.port.1.s.3.orderindex=-1 -unit.1.6.port.1.s.3.visible=1 -unit.1.6.port.1.s.30.alias= -unit.1.6.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.30.name=TriggerPort1[30] -unit.1.6.port.1.s.30.orderindex=-1 -unit.1.6.port.1.s.30.visible=1 -unit.1.6.port.1.s.31.alias= -unit.1.6.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.31.name=TriggerPort1[31] -unit.1.6.port.1.s.31.orderindex=-1 -unit.1.6.port.1.s.31.visible=1 -unit.1.6.port.1.s.4.alias= -unit.1.6.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.4.name=TriggerPort1[4] -unit.1.6.port.1.s.4.orderindex=-1 -unit.1.6.port.1.s.4.visible=1 -unit.1.6.port.1.s.5.alias= -unit.1.6.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.5.name=TriggerPort1[5] -unit.1.6.port.1.s.5.orderindex=-1 -unit.1.6.port.1.s.5.visible=1 -unit.1.6.port.1.s.6.alias= -unit.1.6.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.6.name=TriggerPort1[6] -unit.1.6.port.1.s.6.orderindex=-1 -unit.1.6.port.1.s.6.visible=1 -unit.1.6.port.1.s.7.alias= -unit.1.6.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.7.name=TriggerPort1[7] -unit.1.6.port.1.s.7.orderindex=-1 -unit.1.6.port.1.s.7.visible=1 -unit.1.6.port.1.s.8.alias= -unit.1.6.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.8.name=TriggerPort1[8] -unit.1.6.port.1.s.8.orderindex=-1 -unit.1.6.port.1.s.8.visible=1 -unit.1.6.port.1.s.9.alias= -unit.1.6.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.9.name=TriggerPort1[9] -unit.1.6.port.1.s.9.orderindex=-1 -unit.1.6.port.1.s.9.visible=1 -unit.1.6.port.2.b.0.alias= -unit.1.6.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.b.0.name=TriggerPort2 -unit.1.6.port.2.b.0.orderindex=-1 -unit.1.6.port.2.b.0.radix=Hex -unit.1.6.port.2.b.0.signedOffset=0.0 -unit.1.6.port.2.b.0.signedPrecision=0 -unit.1.6.port.2.b.0.signedScaleFactor=1.0 -unit.1.6.port.2.b.0.unsignedOffset=0.0 -unit.1.6.port.2.b.0.unsignedPrecision=0 -unit.1.6.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.2.b.0.visible=1 -unit.1.6.port.2.buscount=1 -unit.1.6.port.2.channelcount=32 -unit.1.6.port.2.s.0.alias= -unit.1.6.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.0.name=TriggerPort2[0] -unit.1.6.port.2.s.0.orderindex=-1 -unit.1.6.port.2.s.0.visible=1 -unit.1.6.port.2.s.1.alias= -unit.1.6.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.1.name=TriggerPort2[1] -unit.1.6.port.2.s.1.orderindex=-1 -unit.1.6.port.2.s.1.visible=1 -unit.1.6.port.2.s.10.alias= -unit.1.6.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.10.name=TriggerPort2[10] -unit.1.6.port.2.s.10.orderindex=-1 -unit.1.6.port.2.s.10.visible=1 -unit.1.6.port.2.s.11.alias= -unit.1.6.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.11.name=TriggerPort2[11] -unit.1.6.port.2.s.11.orderindex=-1 -unit.1.6.port.2.s.11.visible=1 -unit.1.6.port.2.s.12.alias= -unit.1.6.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.12.name=TriggerPort2[12] -unit.1.6.port.2.s.12.orderindex=-1 -unit.1.6.port.2.s.12.visible=1 -unit.1.6.port.2.s.13.alias= -unit.1.6.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.13.name=TriggerPort2[13] -unit.1.6.port.2.s.13.orderindex=-1 -unit.1.6.port.2.s.13.visible=1 -unit.1.6.port.2.s.14.alias= -unit.1.6.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.14.name=TriggerPort2[14] -unit.1.6.port.2.s.14.orderindex=-1 -unit.1.6.port.2.s.14.visible=1 -unit.1.6.port.2.s.15.alias= -unit.1.6.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.15.name=TriggerPort2[15] -unit.1.6.port.2.s.15.orderindex=-1 -unit.1.6.port.2.s.15.visible=1 -unit.1.6.port.2.s.16.alias= -unit.1.6.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.16.name=TriggerPort2[16] -unit.1.6.port.2.s.16.orderindex=-1 -unit.1.6.port.2.s.16.visible=1 -unit.1.6.port.2.s.17.alias= -unit.1.6.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.17.name=TriggerPort2[17] -unit.1.6.port.2.s.17.orderindex=-1 -unit.1.6.port.2.s.17.visible=1 -unit.1.6.port.2.s.18.alias= -unit.1.6.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.18.name=TriggerPort2[18] -unit.1.6.port.2.s.18.orderindex=-1 -unit.1.6.port.2.s.18.visible=1 -unit.1.6.port.2.s.19.alias= -unit.1.6.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.19.name=TriggerPort2[19] -unit.1.6.port.2.s.19.orderindex=-1 -unit.1.6.port.2.s.19.visible=1 -unit.1.6.port.2.s.2.alias= -unit.1.6.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.2.name=TriggerPort2[2] -unit.1.6.port.2.s.2.orderindex=-1 -unit.1.6.port.2.s.2.visible=1 -unit.1.6.port.2.s.20.alias= -unit.1.6.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.20.name=TriggerPort2[20] -unit.1.6.port.2.s.20.orderindex=-1 -unit.1.6.port.2.s.20.visible=1 -unit.1.6.port.2.s.21.alias= -unit.1.6.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.21.name=TriggerPort2[21] -unit.1.6.port.2.s.21.orderindex=-1 -unit.1.6.port.2.s.21.visible=1 -unit.1.6.port.2.s.22.alias= -unit.1.6.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.22.name=TriggerPort2[22] -unit.1.6.port.2.s.22.orderindex=-1 -unit.1.6.port.2.s.22.visible=1 -unit.1.6.port.2.s.23.alias= -unit.1.6.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.23.name=TriggerPort2[23] -unit.1.6.port.2.s.23.orderindex=-1 -unit.1.6.port.2.s.23.visible=1 -unit.1.6.port.2.s.24.alias= -unit.1.6.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.24.name=TriggerPort2[24] -unit.1.6.port.2.s.24.orderindex=-1 -unit.1.6.port.2.s.24.visible=1 -unit.1.6.port.2.s.25.alias= -unit.1.6.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.25.name=TriggerPort2[25] -unit.1.6.port.2.s.25.orderindex=-1 -unit.1.6.port.2.s.25.visible=1 -unit.1.6.port.2.s.26.alias= -unit.1.6.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.26.name=TriggerPort2[26] -unit.1.6.port.2.s.26.orderindex=-1 -unit.1.6.port.2.s.26.visible=1 -unit.1.6.port.2.s.27.alias= -unit.1.6.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.27.name=TriggerPort2[27] -unit.1.6.port.2.s.27.orderindex=-1 -unit.1.6.port.2.s.27.visible=1 -unit.1.6.port.2.s.28.alias= -unit.1.6.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.28.name=TriggerPort2[28] -unit.1.6.port.2.s.28.orderindex=-1 -unit.1.6.port.2.s.28.visible=1 -unit.1.6.port.2.s.29.alias= -unit.1.6.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.29.name=TriggerPort2[29] -unit.1.6.port.2.s.29.orderindex=-1 -unit.1.6.port.2.s.29.visible=1 -unit.1.6.port.2.s.3.alias= -unit.1.6.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.3.name=TriggerPort2[3] -unit.1.6.port.2.s.3.orderindex=-1 -unit.1.6.port.2.s.3.visible=1 -unit.1.6.port.2.s.30.alias= -unit.1.6.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.30.name=TriggerPort2[30] -unit.1.6.port.2.s.30.orderindex=-1 -unit.1.6.port.2.s.30.visible=1 -unit.1.6.port.2.s.31.alias= -unit.1.6.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.31.name=TriggerPort2[31] -unit.1.6.port.2.s.31.orderindex=-1 -unit.1.6.port.2.s.31.visible=1 -unit.1.6.port.2.s.4.alias= -unit.1.6.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.4.name=TriggerPort2[4] -unit.1.6.port.2.s.4.orderindex=-1 -unit.1.6.port.2.s.4.visible=1 -unit.1.6.port.2.s.5.alias= -unit.1.6.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.5.name=TriggerPort2[5] -unit.1.6.port.2.s.5.orderindex=-1 -unit.1.6.port.2.s.5.visible=1 -unit.1.6.port.2.s.6.alias= -unit.1.6.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.6.name=TriggerPort2[6] -unit.1.6.port.2.s.6.orderindex=-1 -unit.1.6.port.2.s.6.visible=1 -unit.1.6.port.2.s.7.alias= -unit.1.6.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.7.name=TriggerPort2[7] -unit.1.6.port.2.s.7.orderindex=-1 -unit.1.6.port.2.s.7.visible=1 -unit.1.6.port.2.s.8.alias= -unit.1.6.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.8.name=TriggerPort2[8] -unit.1.6.port.2.s.8.orderindex=-1 -unit.1.6.port.2.s.8.visible=1 -unit.1.6.port.2.s.9.alias= -unit.1.6.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.9.name=TriggerPort2[9] -unit.1.6.port.2.s.9.orderindex=-1 -unit.1.6.port.2.s.9.visible=1 -unit.1.6.port.3.b.0.alias= -unit.1.6.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.b.0.name=TriggerPort3 -unit.1.6.port.3.b.0.orderindex=-1 -unit.1.6.port.3.b.0.radix=Hex -unit.1.6.port.3.b.0.signedOffset=0.0 -unit.1.6.port.3.b.0.signedPrecision=0 -unit.1.6.port.3.b.0.signedScaleFactor=1.0 -unit.1.6.port.3.b.0.unsignedOffset=0.0 -unit.1.6.port.3.b.0.unsignedPrecision=0 -unit.1.6.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.3.b.0.visible=1 -unit.1.6.port.3.buscount=1 -unit.1.6.port.3.channelcount=32 -unit.1.6.port.3.s.0.alias= -unit.1.6.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.0.name=TriggerPort3[0] -unit.1.6.port.3.s.0.orderindex=-1 -unit.1.6.port.3.s.0.visible=1 -unit.1.6.port.3.s.1.alias= -unit.1.6.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.1.name=TriggerPort3[1] -unit.1.6.port.3.s.1.orderindex=-1 -unit.1.6.port.3.s.1.visible=1 -unit.1.6.port.3.s.10.alias= -unit.1.6.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.10.name=TriggerPort3[10] -unit.1.6.port.3.s.10.orderindex=-1 -unit.1.6.port.3.s.10.visible=1 -unit.1.6.port.3.s.11.alias= -unit.1.6.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.11.name=TriggerPort3[11] -unit.1.6.port.3.s.11.orderindex=-1 -unit.1.6.port.3.s.11.visible=1 -unit.1.6.port.3.s.12.alias= -unit.1.6.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.12.name=TriggerPort3[12] -unit.1.6.port.3.s.12.orderindex=-1 -unit.1.6.port.3.s.12.visible=1 -unit.1.6.port.3.s.13.alias= -unit.1.6.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.13.name=TriggerPort3[13] -unit.1.6.port.3.s.13.orderindex=-1 -unit.1.6.port.3.s.13.visible=1 -unit.1.6.port.3.s.14.alias= -unit.1.6.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.14.name=TriggerPort3[14] -unit.1.6.port.3.s.14.orderindex=-1 -unit.1.6.port.3.s.14.visible=1 -unit.1.6.port.3.s.15.alias= -unit.1.6.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.15.name=TriggerPort3[15] -unit.1.6.port.3.s.15.orderindex=-1 -unit.1.6.port.3.s.15.visible=1 -unit.1.6.port.3.s.16.alias= -unit.1.6.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.16.name=TriggerPort3[16] -unit.1.6.port.3.s.16.orderindex=-1 -unit.1.6.port.3.s.16.visible=1 -unit.1.6.port.3.s.17.alias= -unit.1.6.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.17.name=TriggerPort3[17] -unit.1.6.port.3.s.17.orderindex=-1 -unit.1.6.port.3.s.17.visible=1 -unit.1.6.port.3.s.18.alias= -unit.1.6.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.18.name=TriggerPort3[18] -unit.1.6.port.3.s.18.orderindex=-1 -unit.1.6.port.3.s.18.visible=1 -unit.1.6.port.3.s.19.alias= -unit.1.6.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.19.name=TriggerPort3[19] -unit.1.6.port.3.s.19.orderindex=-1 -unit.1.6.port.3.s.19.visible=1 -unit.1.6.port.3.s.2.alias= -unit.1.6.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.2.name=TriggerPort3[2] -unit.1.6.port.3.s.2.orderindex=-1 -unit.1.6.port.3.s.2.visible=1 -unit.1.6.port.3.s.20.alias= -unit.1.6.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.20.name=TriggerPort3[20] -unit.1.6.port.3.s.20.orderindex=-1 -unit.1.6.port.3.s.20.visible=1 -unit.1.6.port.3.s.21.alias= -unit.1.6.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.21.name=TriggerPort3[21] -unit.1.6.port.3.s.21.orderindex=-1 -unit.1.6.port.3.s.21.visible=1 -unit.1.6.port.3.s.22.alias= -unit.1.6.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.22.name=TriggerPort3[22] -unit.1.6.port.3.s.22.orderindex=-1 -unit.1.6.port.3.s.22.visible=1 -unit.1.6.port.3.s.23.alias= -unit.1.6.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.23.name=TriggerPort3[23] -unit.1.6.port.3.s.23.orderindex=-1 -unit.1.6.port.3.s.23.visible=1 -unit.1.6.port.3.s.24.alias= -unit.1.6.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.24.name=TriggerPort3[24] -unit.1.6.port.3.s.24.orderindex=-1 -unit.1.6.port.3.s.24.visible=1 -unit.1.6.port.3.s.25.alias= -unit.1.6.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.25.name=TriggerPort3[25] -unit.1.6.port.3.s.25.orderindex=-1 -unit.1.6.port.3.s.25.visible=1 -unit.1.6.port.3.s.26.alias= -unit.1.6.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.26.name=TriggerPort3[26] -unit.1.6.port.3.s.26.orderindex=-1 -unit.1.6.port.3.s.26.visible=1 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-unit.1.6.port.3.s.30.visible=1 -unit.1.6.port.3.s.31.alias= -unit.1.6.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.31.name=TriggerPort3[31] -unit.1.6.port.3.s.31.orderindex=-1 -unit.1.6.port.3.s.31.visible=1 -unit.1.6.port.3.s.4.alias= -unit.1.6.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.4.name=TriggerPort3[4] -unit.1.6.port.3.s.4.orderindex=-1 -unit.1.6.port.3.s.4.visible=1 -unit.1.6.port.3.s.5.alias= -unit.1.6.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.5.name=TriggerPort3[5] -unit.1.6.port.3.s.5.orderindex=-1 -unit.1.6.port.3.s.5.visible=1 -unit.1.6.port.3.s.6.alias= -unit.1.6.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.6.name=TriggerPort3[6] -unit.1.6.port.3.s.6.orderindex=-1 -unit.1.6.port.3.s.6.visible=1 -unit.1.6.port.3.s.7.alias= -unit.1.6.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.7.name=TriggerPort3[7] -unit.1.6.port.3.s.7.orderindex=-1 -unit.1.6.port.3.s.7.visible=1 -unit.1.6.port.3.s.8.alias= -unit.1.6.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.8.name=TriggerPort3[8] -unit.1.6.port.3.s.8.orderindex=-1 -unit.1.6.port.3.s.8.visible=1 -unit.1.6.port.3.s.9.alias= -unit.1.6.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.9.name=TriggerPort3[9] -unit.1.6.port.3.s.9.orderindex=-1 -unit.1.6.port.3.s.9.visible=1 -unit.1.6.port.4.b.0.alias= -unit.1.6.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.b.0.name=TriggerPort4 -unit.1.6.port.4.b.0.orderindex=-1 -unit.1.6.port.4.b.0.radix=Hex -unit.1.6.port.4.b.0.signedOffset=0.0 -unit.1.6.port.4.b.0.signedPrecision=0 -unit.1.6.port.4.b.0.signedScaleFactor=1.0 -unit.1.6.port.4.b.0.unsignedOffset=0.0 -unit.1.6.port.4.b.0.unsignedPrecision=0 -unit.1.6.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.4.b.0.visible=1 -unit.1.6.port.4.buscount=1 -unit.1.6.port.4.channelcount=32 -unit.1.6.port.4.s.0.alias= -unit.1.6.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.0.name=TriggerPort4[0] -unit.1.6.port.4.s.0.orderindex=-1 -unit.1.6.port.4.s.0.visible=1 -unit.1.6.port.4.s.1.alias= -unit.1.6.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.1.name=TriggerPort4[1] -unit.1.6.port.4.s.1.orderindex=-1 -unit.1.6.port.4.s.1.visible=1 -unit.1.6.port.4.s.10.alias= -unit.1.6.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.10.name=TriggerPort4[10] -unit.1.6.port.4.s.10.orderindex=-1 -unit.1.6.port.4.s.10.visible=1 -unit.1.6.port.4.s.11.alias= -unit.1.6.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.11.name=TriggerPort4[11] -unit.1.6.port.4.s.11.orderindex=-1 -unit.1.6.port.4.s.11.visible=1 -unit.1.6.port.4.s.12.alias= -unit.1.6.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.12.name=TriggerPort4[12] -unit.1.6.port.4.s.12.orderindex=-1 -unit.1.6.port.4.s.12.visible=1 -unit.1.6.port.4.s.13.alias= -unit.1.6.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.13.name=TriggerPort4[13] -unit.1.6.port.4.s.13.orderindex=-1 -unit.1.6.port.4.s.13.visible=1 -unit.1.6.port.4.s.14.alias= -unit.1.6.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.14.name=TriggerPort4[14] -unit.1.6.port.4.s.14.orderindex=-1 -unit.1.6.port.4.s.14.visible=1 -unit.1.6.port.4.s.15.alias= -unit.1.6.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.15.name=TriggerPort4[15] -unit.1.6.port.4.s.15.orderindex=-1 -unit.1.6.port.4.s.15.visible=1 -unit.1.6.port.4.s.16.alias= -unit.1.6.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.16.name=TriggerPort4[16] -unit.1.6.port.4.s.16.orderindex=-1 -unit.1.6.port.4.s.16.visible=1 -unit.1.6.port.4.s.17.alias= -unit.1.6.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.17.name=TriggerPort4[17] -unit.1.6.port.4.s.17.orderindex=-1 -unit.1.6.port.4.s.17.visible=1 -unit.1.6.port.4.s.18.alias= -unit.1.6.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.18.name=TriggerPort4[18] -unit.1.6.port.4.s.18.orderindex=-1 -unit.1.6.port.4.s.18.visible=1 -unit.1.6.port.4.s.19.alias= -unit.1.6.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.19.name=TriggerPort4[19] -unit.1.6.port.4.s.19.orderindex=-1 -unit.1.6.port.4.s.19.visible=1 -unit.1.6.port.4.s.2.alias= -unit.1.6.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.2.name=TriggerPort4[2] -unit.1.6.port.4.s.2.orderindex=-1 -unit.1.6.port.4.s.2.visible=1 -unit.1.6.port.4.s.20.alias= -unit.1.6.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.20.name=TriggerPort4[20] -unit.1.6.port.4.s.20.orderindex=-1 -unit.1.6.port.4.s.20.visible=1 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-unit.1.6.port.4.s.25.visible=1 -unit.1.6.port.4.s.26.alias= -unit.1.6.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.26.name=TriggerPort4[26] -unit.1.6.port.4.s.26.orderindex=-1 -unit.1.6.port.4.s.26.visible=1 -unit.1.6.port.4.s.27.alias= -unit.1.6.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.27.name=TriggerPort4[27] -unit.1.6.port.4.s.27.orderindex=-1 -unit.1.6.port.4.s.27.visible=1 -unit.1.6.port.4.s.28.alias= -unit.1.6.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.28.name=TriggerPort4[28] -unit.1.6.port.4.s.28.orderindex=-1 -unit.1.6.port.4.s.28.visible=1 -unit.1.6.port.4.s.29.alias= -unit.1.6.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.29.name=TriggerPort4[29] -unit.1.6.port.4.s.29.orderindex=-1 -unit.1.6.port.4.s.29.visible=1 -unit.1.6.port.4.s.3.alias= -unit.1.6.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.3.name=TriggerPort4[3] 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-unit.1.6.waveform.posn.35.channel=2147483646 -unit.1.6.waveform.posn.35.name=dsp_y_monit -unit.1.6.waveform.posn.35.radix=3 -unit.1.6.waveform.posn.35.type=bus -unit.1.6.waveform.posn.36.channel=2147483646 -unit.1.6.waveform.posn.36.name=dsp_y_monit -unit.1.6.waveform.posn.36.radix=3 -unit.1.6.waveform.posn.36.type=bus -unit.1.6.waveform.posn.37.channel=2147483646 -unit.1.6.waveform.posn.37.name=dsp_y_monit -unit.1.6.waveform.posn.37.radix=3 -unit.1.6.waveform.posn.37.type=bus -unit.1.6.waveform.posn.38.channel=2147483646 -unit.1.6.waveform.posn.38.name=dsp_y_monit -unit.1.6.waveform.posn.38.radix=3 -unit.1.6.waveform.posn.38.type=bus -unit.1.6.waveform.posn.39.channel=2147483646 -unit.1.6.waveform.posn.39.name=dsp_y_monit -unit.1.6.waveform.posn.39.radix=3 -unit.1.6.waveform.posn.39.type=bus -unit.1.6.waveform.posn.4.channel=4 -unit.1.6.waveform.posn.4.name=DataPort[4] -unit.1.6.waveform.posn.4.type=signal -unit.1.6.waveform.posn.40.channel=2147483646 -unit.1.6.waveform.posn.40.name=dsp_y_monit -unit.1.6.waveform.posn.40.radix=3 -unit.1.6.waveform.posn.40.type=bus -unit.1.6.waveform.posn.41.channel=2147483646 -unit.1.6.waveform.posn.41.name=dsp_y_monit -unit.1.6.waveform.posn.41.radix=3 -unit.1.6.waveform.posn.41.type=bus -unit.1.6.waveform.posn.42.channel=2147483646 -unit.1.6.waveform.posn.42.name=dsp_y_monit -unit.1.6.waveform.posn.42.radix=3 -unit.1.6.waveform.posn.42.type=bus -unit.1.6.waveform.posn.43.channel=2147483646 -unit.1.6.waveform.posn.43.name=dsp_y_monit -unit.1.6.waveform.posn.43.radix=3 -unit.1.6.waveform.posn.43.type=bus -unit.1.6.waveform.posn.44.channel=2147483646 -unit.1.6.waveform.posn.44.name=dsp_y_monit -unit.1.6.waveform.posn.44.radix=3 -unit.1.6.waveform.posn.44.type=bus -unit.1.6.waveform.posn.45.channel=2147483646 -unit.1.6.waveform.posn.45.name=dsp_y_monit -unit.1.6.waveform.posn.45.radix=3 -unit.1.6.waveform.posn.45.type=bus -unit.1.6.waveform.posn.46.channel=2147483646 -unit.1.6.waveform.posn.46.name=dsp_y_monit -unit.1.6.waveform.posn.46.radix=3 -unit.1.6.waveform.posn.46.type=bus -unit.1.6.waveform.posn.5.channel=5 -unit.1.6.waveform.posn.5.name=DataPort[5] -unit.1.6.waveform.posn.5.type=signal -unit.1.6.waveform.posn.6.channel=6 -unit.1.6.waveform.posn.6.name=DataPort[6] -unit.1.6.waveform.posn.6.type=signal -unit.1.6.waveform.posn.7.channel=7 -unit.1.6.waveform.posn.7.name=DataPort[7] -unit.1.6.waveform.posn.7.type=signal -unit.1.6.waveform.posn.8.channel=34 -unit.1.6.waveform.posn.8.name=DataPort[34] -unit.1.6.waveform.posn.8.type=signal -unit.1.6.waveform.posn.9.channel=35 -unit.1.6.waveform.posn.9.name=DataPort[35] -unit.1.6.waveform.posn.9.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/chipscope_2.cpj b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/chipscope_2.cpj deleted file mode 100644 index e10675b4..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/chipscope_2.cpj +++ /dev/null @@ -1,13480 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Tue Apr 23 13:17:37 BRT 2013 -avoidUserRegDevice1=2,3,4 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109364250093 -mdiAreaHeight=0.7114942528735633 -mdiAreaHeightLast=0.6540229885057471 -mdiCount=20 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice10=1 -mdiDevice11=1 -mdiDevice12=1 -mdiDevice13=1 -mdiDevice14=1 -mdiDevice15=1 -mdiDevice16=1 -mdiDevice17=1 -mdiDevice18=1 -mdiDevice19=1 -mdiDevice2=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiDevice6=1 -mdiDevice7=1 -mdiDevice8=1 -mdiDevice9=1 -mdiType0=5 -mdiType1=1 -mdiType10=5 -mdiType11=0 -mdiType12=1 -mdiType13=5 -mdiType14=0 -mdiType15=1 -mdiType16=5 -mdiType17=0 -mdiType18=1 -mdiType19=5 -mdiType2=5 -mdiType3=0 -mdiType4=0 -mdiType5=0 -mdiType6=1 -mdiType7=5 -mdiType8=0 -mdiType9=1 -mdiUnit0=1 -mdiUnit1=0 -mdiUnit10=3 -mdiUnit11=4 -mdiUnit12=4 -mdiUnit13=4 -mdiUnit14=5 -mdiUnit15=5 -mdiUnit16=5 -mdiUnit17=6 -mdiUnit18=6 -mdiUnit19=6 -mdiUnit2=0 -mdiUnit3=1 -mdiUnit4=0 -mdiUnit5=2 -mdiUnit6=2 -mdiUnit7=2 -mdiUnit8=3 -mdiUnit9=3 -navigatorHeight=0.16666666666666666 -navigatorHeightLast=0.16666666666666666 -navigatorWidth=0.13320825515947468 -navigatorWidthLast=0.13320825515947468 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.44805196 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=0.70772594 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5211039 -unit.1.0.1.WIDTH1=0.70772594 -unit.1.0.1.X1=0.0 -unit.1.0.1.Y1=0.34902596 -unit.1.0.2.HEIGHT2=0.39219016 -unit.1.0.2.WIDTH2=0.92604005 -unit.1.0.2.X2=0.07395994 -unit.1.0.2.Y2=0.55348045 -unit.1.0.5.HEIGHT5=0.8603896 -unit.1.0.5.WIDTH5=0.6727405 -unit.1.0.5.X5=0.011661808 -unit.1.0.5.Y5=0.012987013 -unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXX0XXXXXXXX -unit.1.0.MFBitsA3=XXXXXXXXXXXXXXXXXX01XXXXXXXXXXXX -unit.1.0.MFBitsB0=00000000000000000000000000000000 -unit.1.0.MFBitsB1=00000000000000000000000000000000 -unit.1.0.MFBitsB2=00000000000000000000000000000000 -unit.1.0.MFBitsB3=00000000000000000000000000000000 -unit.1.0.MFCompareA0=0 -unit.1.0.MFCompareA1=0 -unit.1.0.MFCompareA2=0 -unit.1.0.MFCompareA3=0 -unit.1.0.MFCompareB0=999 -unit.1.0.MFCompareB1=999 -unit.1.0.MFCompareB2=999 -unit.1.0.MFCompareB3=999 -unit.1.0.MFCount=4 -unit.1.0.MFDisplay0=0 -unit.1.0.MFDisplay1=0 -unit.1.0.MFDisplay2=0 -unit.1.0.MFDisplay3=0 -unit.1.0.MFEventType0=3 -unit.1.0.MFEventType1=3 -unit.1.0.MFEventType2=3 -unit.1.0.MFEventType3=3 -unit.1.0.RunMode=SINGLE RUN -unit.1.0.SQCondition=All Data -unit.1.0.SQContiguous0=0 -unit.1.0.SequencerOn=0 -unit.1.0.TCActive=0 -unit.1.0.TCAdvanced0=0 -unit.1.0.TCCondition0_0=M2 -unit.1.0.TCCondition0_1= -unit.1.0.TCConditionType0=0 -unit.1.0.TCCount=1 -unit.1.0.TCEventCount0=1 -unit.1.0.TCEventType0=3 -unit.1.0.TCName0=TriggerCondition0 -unit.1.0.TCOutputEnable0=0 -unit.1.0.TCOutputHigh0=1 -unit.1.0.TCOutputMode0=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.browser_tree_state=0 -unit.1.0.coretype=ILA -unit.1.0.eventCount0=1 -unit.1.0.eventCount1=1 -unit.1.0.eventCount2=1 -unit.1.0.eventCount3=1 -unit.1.0.export.format=2 -unit.1.0.export.signals=Bus Plot Buses -unit.1.0.export.unitName=DEV\:1 MyDevice1 (XC6VLX240T) UNIT\:0 MyILA0 (ILA) -unit.1.0.listing.count=0 -unit.1.0.plotBusColor0=-16777092 -unit.1.0.plotBusColor1=-3407821 -unit.1.0.plotBusColor10=-16777092 -unit.1.0.plotBusColor11=-16777092 -unit.1.0.plotBusColor12=-16777092 -unit.1.0.plotBusColor13=-16777092 -unit.1.0.plotBusColor14=-16777092 -unit.1.0.plotBusColor2=-6710785 -unit.1.0.plotBusColor3=-3355648 -unit.1.0.plotBusColor4=-16777092 -unit.1.0.plotBusColor5=-16777092 -unit.1.0.plotBusColor6=-16777092 -unit.1.0.plotBusColor7=-16777092 -unit.1.0.plotBusColor8=-16777092 -unit.1.0.plotBusColor9=-16777092 -unit.1.0.plotBusCount=4 -unit.1.0.plotBusName0=adc_data_ch0 -unit.1.0.plotBusName1=adc_data_ch1 -unit.1.0.plotBusName10=fmc516_debug_valid -unit.1.0.plotBusName11=fmc_adc_valid -unit.1.0.plotBusName12=fmc_lmk_lock -unit.1.0.plotBusName13=fmc_mmcm_lock -unit.1.0.plotBusName14=fmc_rst_adcs_n -unit.1.0.plotBusName2=adc_data_ch2 -unit.1.0.plotBusName3=adc_data_ch3 -unit.1.0.plotBusName4=fmc516_ch1_clk_dly -unit.1.0.plotBusName5=fmc516_ch1_clk_load -unit.1.0.plotBusName6=fmc516_ch1_data_dly -unit.1.0.plotBusName7=fmc516_ch1_data_load -unit.1.0.plotBusName8=fmc516_debug_dull -unit.1.0.plotBusName9=fmc516_debug_empty -unit.1.0.plotBusX=adc_data_ch0 -unit.1.0.plotBusY=adc_data_ch0 -unit.1.0.plotDataTimeMode=1 -unit.1.0.plotDisplayMode=line -unit.1.0.plotMaxX=0.0 -unit.1.0.plotMaxY=0.0 -unit.1.0.plotMinX=0.0 -unit.1.0.plotMinY=0.0 -unit.1.0.plotSelectedBus=f -unit.1.0.port.-1.b.0.alias=adc_data_ch0 -unit.1.0.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.1.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.0.name=DataPort -unit.1.0.port.-1.b.0.orderindex=-1 -unit.1.0.port.-1.b.0.radix=Signed -unit.1.0.port.-1.b.0.signedOffset=0.0 -unit.1.0.port.-1.b.0.signedPrecision=0 -unit.1.0.port.-1.b.0.signedScaleFactor=1.0 -unit.1.0.port.-1.b.0.tokencount=0 -unit.1.0.port.-1.b.0.unsignedOffset=0.0 -unit.1.0.port.-1.b.0.unsignedPrecision=0 -unit.1.0.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.0.visible=1 -unit.1.0.port.-1.b.1.alias=adc_data_ch1 -unit.1.0.port.-1.b.1.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.-1.b.1.color=java.awt.Color[r\=204,g\=0,b\=51] -unit.1.0.port.-1.b.1.name=DataPort -unit.1.0.port.-1.b.1.orderindex=-1 -unit.1.0.port.-1.b.1.radix=Signed -unit.1.0.port.-1.b.1.signedOffset=0.0 -unit.1.0.port.-1.b.1.signedPrecision=0 -unit.1.0.port.-1.b.1.signedScaleFactor=1.0 -unit.1.0.port.-1.b.1.tokencount=0 -unit.1.0.port.-1.b.1.unsignedOffset=0.0 -unit.1.0.port.-1.b.1.unsignedPrecision=0 -unit.1.0.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.1.visible=1 -unit.1.0.port.-1.b.10.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.10.channellist=82 -unit.1.0.port.-1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.10.name=DataPort -unit.1.0.port.-1.b.10.orderindex=-1 -unit.1.0.port.-1.b.10.radix=Hex -unit.1.0.port.-1.b.10.signedOffset=0.0 -unit.1.0.port.-1.b.10.signedPrecision=0 -unit.1.0.port.-1.b.10.signedScaleFactor=1.0 -unit.1.0.port.-1.b.10.tokencount=0 -unit.1.0.port.-1.b.10.unsignedOffset=0.0 -unit.1.0.port.-1.b.10.unsignedPrecision=0 -unit.1.0.port.-1.b.10.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.10.visible=1 -unit.1.0.port.-1.b.11.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.11.channellist=82 -unit.1.0.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.11.name=DataPort -unit.1.0.port.-1.b.11.orderindex=-1 -unit.1.0.port.-1.b.11.radix=Hex -unit.1.0.port.-1.b.11.signedOffset=0.0 -unit.1.0.port.-1.b.11.signedPrecision=0 -unit.1.0.port.-1.b.11.signedScaleFactor=1.0 -unit.1.0.port.-1.b.11.tokencount=0 -unit.1.0.port.-1.b.11.unsignedOffset=0.0 -unit.1.0.port.-1.b.11.unsignedPrecision=0 -unit.1.0.port.-1.b.11.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.11.visible=1 -unit.1.0.port.-1.b.12.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.12.channellist=82 -unit.1.0.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.12.name=DataPort -unit.1.0.port.-1.b.12.orderindex=-1 -unit.1.0.port.-1.b.12.radix=Hex -unit.1.0.port.-1.b.12.signedOffset=0.0 -unit.1.0.port.-1.b.12.signedPrecision=0 -unit.1.0.port.-1.b.12.signedScaleFactor=1.0 -unit.1.0.port.-1.b.12.tokencount=0 -unit.1.0.port.-1.b.12.unsignedOffset=0.0 -unit.1.0.port.-1.b.12.unsignedPrecision=0 -unit.1.0.port.-1.b.12.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.12.visible=1 -unit.1.0.port.-1.b.13.alias=fmc_rst_adcs_n -unit.1.0.port.-1.b.13.channellist=82 -unit.1.0.port.-1.b.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.13.name=DataPort -unit.1.0.port.-1.b.13.orderindex=-1 -unit.1.0.port.-1.b.13.radix=Hex -unit.1.0.port.-1.b.13.signedOffset=0.0 -unit.1.0.port.-1.b.13.signedPrecision=0 -unit.1.0.port.-1.b.13.signedScaleFactor=1.0 -unit.1.0.port.-1.b.13.tokencount=0 -unit.1.0.port.-1.b.13.unsignedOffset=0.0 -unit.1.0.port.-1.b.13.unsignedPrecision=0 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-unit.1.0.port.-1.s.85.name=DataPort[85] -unit.1.0.port.-1.s.85.orderindex=-1 -unit.1.0.port.-1.s.85.visible=1 -unit.1.0.port.-1.s.86.alias= -unit.1.0.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.86.name=DataPort[86] -unit.1.0.port.-1.s.86.orderindex=-1 -unit.1.0.port.-1.s.86.visible=1 -unit.1.0.port.-1.s.87.alias= -unit.1.0.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.87.name=DataPort[87] -unit.1.0.port.-1.s.87.orderindex=-1 -unit.1.0.port.-1.s.87.visible=1 -unit.1.0.port.-1.s.88.alias= -unit.1.0.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.88.name=DataPort[88] -unit.1.0.port.-1.s.88.orderindex=-1 -unit.1.0.port.-1.s.88.visible=1 -unit.1.0.port.-1.s.89.alias= -unit.1.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.89.name=DataPort[89] -unit.1.0.port.-1.s.89.orderindex=-1 -unit.1.0.port.-1.s.89.visible=1 -unit.1.0.port.-1.s.9.alias= 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-unit.1.0.port.-1.s.94.alias= -unit.1.0.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.94.name=DataPort[94] -unit.1.0.port.-1.s.94.orderindex=-1 -unit.1.0.port.-1.s.94.visible=1 -unit.1.0.port.-1.s.95.alias= -unit.1.0.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.95.name=DataPort[95] -unit.1.0.port.-1.s.95.orderindex=-1 -unit.1.0.port.-1.s.95.visible=1 -unit.1.0.port.-1.s.96.alias= -unit.1.0.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.96.name=DataPort[96] -unit.1.0.port.-1.s.96.orderindex=-1 -unit.1.0.port.-1.s.96.visible=1 -unit.1.0.port.-1.s.97.alias= -unit.1.0.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.97.name=DataPort[97] -unit.1.0.port.-1.s.97.orderindex=-1 -unit.1.0.port.-1.s.97.visible=1 -unit.1.0.port.-1.s.98.alias= -unit.1.0.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.98.name=DataPort[98] -unit.1.0.port.-1.s.98.orderindex=-1 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-unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= -unit.1.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.10.name=TriggerPort0[10] -unit.1.0.port.0.s.10.orderindex=-1 -unit.1.0.port.0.s.10.visible=1 -unit.1.0.port.0.s.11.alias= -unit.1.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.11.name=TriggerPort0[11] -unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] 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19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= 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-unit.1.0.waveform.posn.112.name=DataPort[127] -unit.1.0.waveform.posn.112.type=signal -unit.1.0.waveform.posn.113.channel=127 -unit.1.0.waveform.posn.113.name=DataPort[127] -unit.1.0.waveform.posn.113.type=signal -unit.1.0.waveform.posn.114.channel=127 -unit.1.0.waveform.posn.114.name=DataPort[127] -unit.1.0.waveform.posn.114.type=signal -unit.1.0.waveform.posn.115.channel=127 -unit.1.0.waveform.posn.115.name=DataPort[127] -unit.1.0.waveform.posn.115.type=signal -unit.1.0.waveform.posn.116.channel=127 -unit.1.0.waveform.posn.116.name=DataPort[127] -unit.1.0.waveform.posn.116.type=signal -unit.1.0.waveform.posn.117.channel=127 -unit.1.0.waveform.posn.117.name=DataPort[127] -unit.1.0.waveform.posn.117.type=signal -unit.1.0.waveform.posn.118.channel=127 -unit.1.0.waveform.posn.118.name=DataPort[127] -unit.1.0.waveform.posn.118.type=signal -unit.1.0.waveform.posn.119.channel=127 -unit.1.0.waveform.posn.119.name=DataPort[127] -unit.1.0.waveform.posn.119.type=signal -unit.1.0.waveform.posn.12.channel=2147483646 -unit.1.0.waveform.posn.12.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.12.radix=1 -unit.1.0.waveform.posn.12.type=bus -unit.1.0.waveform.posn.120.channel=127 -unit.1.0.waveform.posn.120.name=DataPort[127] -unit.1.0.waveform.posn.120.type=signal -unit.1.0.waveform.posn.121.channel=127 -unit.1.0.waveform.posn.121.name=DataPort[127] -unit.1.0.waveform.posn.121.type=signal -unit.1.0.waveform.posn.122.channel=127 -unit.1.0.waveform.posn.122.name=DataPort[127] -unit.1.0.waveform.posn.122.type=signal -unit.1.0.waveform.posn.123.channel=127 -unit.1.0.waveform.posn.123.name=DataP -unit.1.0.waveform.posn.13.channel=2147483646 -unit.1.0.waveform.posn.13.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.13.radix=1 -unit.1.0.waveform.posn.13.type=bus -unit.1.0.waveform.posn.2.channel=2147483646 -unit.1.0.waveform.posn.2.name=adc_data_ch1 -unit.1.0.waveform.posn.2.radix=3 -unit.1.0.waveform.posn.2.type=bus -unit.1.0.waveform.posn.3.channel=2147483646 -unit.1.0.waveform.posn.3.name=adc_data_ch0 -unit.1.0.waveform.posn.3.radix=3 -unit.1.0.waveform.posn.3.type=bus -unit.1.0.waveform.posn.4.channel=2147483646 -unit.1.0.waveform.posn.4.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.4.radix=1 -unit.1.0.waveform.posn.4.type=bus -unit.1.0.waveform.posn.5.channel=2147483646 -unit.1.0.waveform.posn.5.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.5.radix=1 -unit.1.0.waveform.posn.5.type=bus -unit.1.0.waveform.posn.6.channel=2147483646 -unit.1.0.waveform.posn.6.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.6.radix=1 -unit.1.0.waveform.posn.6.type=bus -unit.1.0.waveform.posn.7.channel=2147483646 -unit.1.0.waveform.posn.7.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.7.radix=1 -unit.1.0.waveform.posn.7.type=bus -unit.1.0.waveform.posn.8.channel=2147483646 -unit.1.0.waveform.posn.8.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.37337664 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.6727405 -unit.1.1.0.X0=0.034985423 -unit.1.1.0.Y0=0.0 -unit.1.1.1.HEIGHT1=0.84889644 -unit.1.1.1.WIDTH1=0.90138674 -unit.1.1.1.X1=0.07395994 -unit.1.1.1.Y1=0.3344652 -unit.1.1.5.HEIGHT5=0.77922076 -unit.1.1.5.WIDTH5=0.6202624 -unit.1.1.5.X5=0.029154519 -unit.1.1.5.Y5=0.15746753 -unit.1.1.MFBitsA0=XXXXX1XX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 -unit.1.1.MFBitsB2=00000000000000000000000000000000 -unit.1.1.MFBitsB3=00000000000000000000000000000000 -unit.1.1.MFBitsB4=00000000000000000000000000000000 -unit.1.1.MFCompareA0=0 -unit.1.1.MFCompareA1=0 -unit.1.1.MFCompareA2=0 -unit.1.1.MFCompareA3=0 -unit.1.1.MFCompareA4=0 -unit.1.1.MFCompareB0=999 -unit.1.1.MFCompareB1=999 -unit.1.1.MFCompareB2=999 -unit.1.1.MFCompareB3=999 -unit.1.1.MFCompareB4=999 -unit.1.1.MFCount=5 -unit.1.1.MFDisplay0=0 -unit.1.1.MFDisplay1=0 -unit.1.1.MFDisplay2=0 -unit.1.1.MFDisplay3=0 -unit.1.1.MFDisplay4=0 -unit.1.1.MFEventType0=3 -unit.1.1.MFEventType1=3 -unit.1.1.MFEventType2=3 -unit.1.1.MFEventType3=3 -unit.1.1.MFEventType4=3 -unit.1.1.RunMode=SINGLE RUN -unit.1.1.SQCondition=M0 -unit.1.1.SQContiguous0=0 -unit.1.1.SequencerOn=0 -unit.1.1.TCActive=0 -unit.1.1.TCAdvanced0=0 -unit.1.1.TCCondition0_0=M0 -unit.1.1.TCCondition0_1= -unit.1.1.TCConditionType0=0 -unit.1.1.TCCount=1 -unit.1.1.TCEventCount0=1 -unit.1.1.TCEventType0=3 -unit.1.1.TCName0=TriggerCondition0 -unit.1.1.TCOutputEnable0=0 -unit.1.1.TCOutputHigh0=1 -unit.1.1.TCOutputMode0=0 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.coretype=ILA -unit.1.1.eventCount0=1 -unit.1.1.eventCount1=1 -unit.1.1.eventCount2=1 -unit.1.1.eventCount3=1 -unit.1.1.eventCount4=1 -unit.1.1.plotBusColor0=-16777092 -unit.1.1.plotBusColor1=-3407770 -unit.1.1.plotBusColor2=-6723841 -unit.1.1.plotBusColor3=-6711040 -unit.1.1.plotBusCount=4 -unit.1.1.plotBusName0=dsp_poly35_ch0 -unit.1.1.plotBusName1=dsp_poly35_ch2 -unit.1.1.plotBusName2=dsp_mix_ch0 -unit.1.1.plotBusName3=dsp_mix_ch2 -unit.1.1.plotBusX=dsp_poly35_ch0 -unit.1.1.plotBusY=dsp_poly35_ch0 -unit.1.1.plotDataTimeMode=1 -unit.1.1.plotDisplayMode=line -unit.1.1.plotMaxX=0.0 -unit.1.1.plotMaxY=0.0 -unit.1.1.plotMinX=0.0 -unit.1.1.plotMinY=0.0 -unit.1.1.plotSelectedBus=0 -unit.1.1.port.-1.b.0.alias=dsp_mix_ch0 -unit.1.1.port.-1.b.0.channellist=72 73 74 76 75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.1.port.-1.b.0.color=java.awt.Color[r\=153,g\=102,b\=255] -unit.1.1.port.-1.b.0.name=DataPort -unit.1.1.port.-1.b.0.orderindex=-1 -unit.1.1.port.-1.b.0.radix=Signed -unit.1.1.port.-1.b.0.signedOffset=0.0 -unit.1.1.port.-1.b.0.signedPrecision=0 -unit.1.1.port.-1.b.0.signedScaleFactor=1.0 -unit.1.1.port.-1.b.0.tokencount=0 -unit.1.1.port.-1.b.0.unsignedOffset=0.0 -unit.1.1.port.-1.b.0.unsignedPrecision=0 -unit.1.1.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.0.visible=1 -unit.1.1.port.-1.b.1.alias=dsp_mix_ch2 -unit.1.1.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 -unit.1.1.port.-1.b.1.color=java.awt.Color[r\=153,g\=153,b\=0] -unit.1.1.port.-1.b.1.name=DataPort -unit.1.1.port.-1.b.1.orderindex=-1 -unit.1.1.port.-1.b.1.radix=Signed -unit.1.1.port.-1.b.1.signedOffset=0.0 -unit.1.1.port.-1.b.1.signedPrecision=0 -unit.1.1.port.-1.b.1.signedScaleFactor=1.0 -unit.1.1.port.-1.b.1.tokencount=0 -unit.1.1.port.-1.b.1.unsignedOffset=0.0 -unit.1.1.port.-1.b.1.unsignedPrecision=0 -unit.1.1.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.1.visible=1 -unit.1.1.port.-1.b.2.alias=dsp_poly35_ch0 -unit.1.1.port.-1.b.2.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.b.2.name=DataPort -unit.1.1.port.-1.b.2.orderindex=-1 -unit.1.1.port.-1.b.2.radix=Signed -unit.1.1.port.-1.b.2.signedOffset=0.0 -unit.1.1.port.-1.b.2.signedPrecision=0 -unit.1.1.port.-1.b.2.signedScaleFactor=1.0 -unit.1.1.port.-1.b.2.tokencount=0 -unit.1.1.port.-1.b.2.unsignedOffset=0.0 -unit.1.1.port.-1.b.2.unsignedPrecision=0 -unit.1.1.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.2.visible=1 -unit.1.1.port.-1.b.3.alias=dsp_poly35_ch2 -unit.1.1.port.-1.b.3.channellist=40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.1.port.-1.b.3.color=java.awt.Color[r\=204,g\=0,b\=102] -unit.1.1.port.-1.b.3.name=DataPort -unit.1.1.port.-1.b.3.orderindex=-1 -unit.1.1.port.-1.b.3.radix=Signed -unit.1.1.port.-1.b.3.signedOffset=0.0 -unit.1.1.port.-1.b.3.signedPrecision=0 -unit.1.1.port.-1.b.3.signedScaleFactor=1.0 -unit.1.1.port.-1.b.3.tokencount=0 -unit.1.1.port.-1.b.3.unsignedOffset=0.0 -unit.1.1.port.-1.b.3.unsignedPrecision=0 -unit.1.1.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.3.visible=1 -unit.1.1.port.-1.buscount=4 -unit.1.1.port.-1.channelcount=136 -unit.1.1.port.-1.s.0.alias= -unit.1.1.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.0.name=DataPort[0] -unit.1.1.port.-1.s.0.orderindex=-1 -unit.1.1.port.-1.s.0.visible=1 -unit.1.1.port.-1.s.1.alias= -unit.1.1.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.1.name=DataPort[1] -unit.1.1.port.-1.s.1.orderindex=-1 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-unit.1.1.port.-1.s.103.orderindex=-1 -unit.1.1.port.-1.s.103.visible=1 -unit.1.1.port.-1.s.104.alias= -unit.1.1.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.104.name=DataPort[104] -unit.1.1.port.-1.s.104.orderindex=-1 -unit.1.1.port.-1.s.104.visible=0 -unit.1.1.port.-1.s.105.alias= -unit.1.1.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.105.name=DataPort[105] -unit.1.1.port.-1.s.105.orderindex=-1 -unit.1.1.port.-1.s.105.visible=0 -unit.1.1.port.-1.s.106.alias= -unit.1.1.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.106.name=DataPort[106] -unit.1.1.port.-1.s.106.orderindex=-1 -unit.1.1.port.-1.s.106.visible=0 -unit.1.1.port.-1.s.107.alias= -unit.1.1.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.107.name=DataPort[107] -unit.1.1.port.-1.s.107.orderindex=-1 -unit.1.1.port.-1.s.107.visible=0 -unit.1.1.port.-1.s.108.alias= -unit.1.1.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.108.name=DataPort[108] -unit.1.1.port.-1.s.108.orderindex=-1 -unit.1.1.port.-1.s.108.visible=0 -unit.1.1.port.-1.s.109.alias= -unit.1.1.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.109.name=DataPort[109] -unit.1.1.port.-1.s.109.orderindex=-1 -unit.1.1.port.-1.s.109.visible=0 -unit.1.1.port.-1.s.11.alias= -unit.1.1.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.11.name=DataPort[11] -unit.1.1.port.-1.s.11.orderindex=-1 -unit.1.1.port.-1.s.11.visible=0 -unit.1.1.port.-1.s.110.alias= -unit.1.1.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.110.name=DataPort[110] -unit.1.1.port.-1.s.110.orderindex=-1 -unit.1.1.port.-1.s.110.visible=0 -unit.1.1.port.-1.s.111.alias= -unit.1.1.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.111.name=DataPort[111] -unit.1.1.port.-1.s.111.orderindex=-1 -unit.1.1.port.-1.s.111.visible=0 -unit.1.1.port.-1.s.112.alias= -unit.1.1.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.112.name=DataPort[112] -unit.1.1.port.-1.s.112.orderindex=-1 -unit.1.1.port.-1.s.112.visible=0 -unit.1.1.port.-1.s.113.alias= -unit.1.1.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.113.name=DataPort[113] -unit.1.1.port.-1.s.113.orderindex=-1 -unit.1.1.port.-1.s.113.visible=0 -unit.1.1.port.-1.s.114.alias= -unit.1.1.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.114.name=DataPort[114] -unit.1.1.port.-1.s.114.orderindex=-1 -unit.1.1.port.-1.s.114.visible=0 -unit.1.1.port.-1.s.115.alias= -unit.1.1.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.115.name=DataPort[115] -unit.1.1.port.-1.s.115.orderindex=-1 -unit.1.1.port.-1.s.115.visible=0 -unit.1.1.port.-1.s.116.alias= -unit.1.1.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.116.name=DataPort[116] -unit.1.1.port.-1.s.116.orderindex=-1 -unit.1.1.port.-1.s.116.visible=0 -unit.1.1.port.-1.s.117.alias= -unit.1.1.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.117.name=DataPort[117] -unit.1.1.port.-1.s.117.orderindex=-1 -unit.1.1.port.-1.s.117.visible=0 -unit.1.1.port.-1.s.118.alias= -unit.1.1.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.118.name=DataPort[118] -unit.1.1.port.-1.s.118.orderindex=-1 -unit.1.1.port.-1.s.118.visible=0 -unit.1.1.port.-1.s.119.alias= -unit.1.1.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.119.name=DataPort[119] -unit.1.1.port.-1.s.119.orderindex=-1 -unit.1.1.port.-1.s.119.visible=0 -unit.1.1.port.-1.s.12.alias= -unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=0 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=0 -unit.1.1.port.-1.s.121.alias= -unit.1.1.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.121.name=DataPort[121] -unit.1.1.port.-1.s.121.orderindex=-1 -unit.1.1.port.-1.s.121.visible=0 -unit.1.1.port.-1.s.122.alias= -unit.1.1.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.122.name=DataPort[122] -unit.1.1.port.-1.s.122.orderindex=-1 -unit.1.1.port.-1.s.122.visible=0 -unit.1.1.port.-1.s.123.alias= -unit.1.1.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.123.name=DataPort[123] -unit.1.1.port.-1.s.123.orderindex=-1 -unit.1.1.port.-1.s.123.visible=0 -unit.1.1.port.-1.s.124.alias= -unit.1.1.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.124.name=DataPort[124] -unit.1.1.port.-1.s.124.orderindex=-1 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-unit.1.1.port.-1.s.129.name=DataPort[129] -unit.1.1.port.-1.s.129.orderindex=-1 -unit.1.1.port.-1.s.129.visible=1 -unit.1.1.port.-1.s.13.alias= -unit.1.1.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.13.name=DataPort[13] -unit.1.1.port.-1.s.13.orderindex=-1 -unit.1.1.port.-1.s.13.visible=0 -unit.1.1.port.-1.s.130.alias= -unit.1.1.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.130.name=DataPort[130] -unit.1.1.port.-1.s.130.orderindex=-1 -unit.1.1.port.-1.s.130.visible=1 -unit.1.1.port.-1.s.131.alias= -unit.1.1.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.131.name=DataPort[131] -unit.1.1.port.-1.s.131.orderindex=-1 -unit.1.1.port.-1.s.131.visible=1 -unit.1.1.port.-1.s.132.alias= -unit.1.1.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.132.name=DataPort[132] -unit.1.1.port.-1.s.132.orderindex=-1 -unit.1.1.port.-1.s.132.visible=1 -unit.1.1.port.-1.s.133.alias= -unit.1.1.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.133.name=DataPort[133] -unit.1.1.port.-1.s.133.orderindex=-1 -unit.1.1.port.-1.s.133.visible=1 -unit.1.1.port.-1.s.134.alias= -unit.1.1.port.-1.s.134.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.134.name=DataPort[134] -unit.1.1.port.-1.s.134.orderindex=-1 -unit.1.1.port.-1.s.134.visible=1 -unit.1.1.port.-1.s.135.alias= -unit.1.1.port.-1.s.135.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.135.name=DataPort[135] -unit.1.1.port.-1.s.135.orderindex=-1 -unit.1.1.port.-1.s.135.visible=1 -unit.1.1.port.-1.s.14.alias= -unit.1.1.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.14.name=DataPort[14] -unit.1.1.port.-1.s.14.orderindex=-1 -unit.1.1.port.-1.s.14.visible=0 -unit.1.1.port.-1.s.15.alias= -unit.1.1.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.15.name=DataPort[15] -unit.1.1.port.-1.s.15.orderindex=-1 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-unit.1.1.port.-1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.29.name=DataPort[29] -unit.1.1.port.-1.s.29.orderindex=-1 -unit.1.1.port.-1.s.29.visible=0 -unit.1.1.port.-1.s.3.alias= -unit.1.1.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.3.name=DataPort[3] -unit.1.1.port.-1.s.3.orderindex=-1 -unit.1.1.port.-1.s.3.visible=1 -unit.1.1.port.-1.s.30.alias= -unit.1.1.port.-1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.30.name=DataPort[30] -unit.1.1.port.-1.s.30.orderindex=-1 -unit.1.1.port.-1.s.30.visible=0 -unit.1.1.port.-1.s.31.alias= -unit.1.1.port.-1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.31.name=DataPort[31] -unit.1.1.port.-1.s.31.orderindex=-1 -unit.1.1.port.-1.s.31.visible=0 -unit.1.1.port.-1.s.32.alias= -unit.1.1.port.-1.s.32.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.32.name=DataPort[32] -unit.1.1.port.-1.s.32.orderindex=-1 -unit.1.1.port.-1.s.32.visible=1 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-unit.1.1.port.-1.s.50.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.50.name=DataPort[50] -unit.1.1.port.-1.s.50.orderindex=-1 -unit.1.1.port.-1.s.50.visible=0 -unit.1.1.port.-1.s.51.alias= -unit.1.1.port.-1.s.51.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.51.name=DataPort[51] -unit.1.1.port.-1.s.51.orderindex=-1 -unit.1.1.port.-1.s.51.visible=0 -unit.1.1.port.-1.s.52.alias= -unit.1.1.port.-1.s.52.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.52.name=DataPort[52] -unit.1.1.port.-1.s.52.orderindex=-1 -unit.1.1.port.-1.s.52.visible=0 -unit.1.1.port.-1.s.53.alias= -unit.1.1.port.-1.s.53.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.53.name=DataPort[53] -unit.1.1.port.-1.s.53.orderindex=-1 -unit.1.1.port.-1.s.53.visible=0 -unit.1.1.port.-1.s.54.alias= -unit.1.1.port.-1.s.54.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.54.name=DataPort[54] -unit.1.1.port.-1.s.54.orderindex=-1 -unit.1.1.port.-1.s.54.visible=0 -unit.1.1.port.-1.s.55.alias= -unit.1.1.port.-1.s.55.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.55.name=DataPort[55] -unit.1.1.port.-1.s.55.orderindex=-1 -unit.1.1.port.-1.s.55.visible=0 -unit.1.1.port.-1.s.56.alias= -unit.1.1.port.-1.s.56.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.56.name=DataPort[56] -unit.1.1.port.-1.s.56.orderindex=-1 -unit.1.1.port.-1.s.56.visible=0 -unit.1.1.port.-1.s.57.alias= -unit.1.1.port.-1.s.57.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.57.name=DataPort[57] -unit.1.1.port.-1.s.57.orderindex=-1 -unit.1.1.port.-1.s.57.visible=0 -unit.1.1.port.-1.s.58.alias= -unit.1.1.port.-1.s.58.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.58.name=DataPort[58] -unit.1.1.port.-1.s.58.orderindex=-1 -unit.1.1.port.-1.s.58.visible=0 -unit.1.1.port.-1.s.59.alias= -unit.1.1.port.-1.s.59.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.59.name=DataPort[59] -unit.1.1.port.-1.s.59.orderindex=-1 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-unit.1.1.port.-1.s.68.name=DataPort[68] -unit.1.1.port.-1.s.68.orderindex=-1 -unit.1.1.port.-1.s.68.visible=1 -unit.1.1.port.-1.s.69.alias= -unit.1.1.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.69.name=DataPort[69] -unit.1.1.port.-1.s.69.orderindex=-1 -unit.1.1.port.-1.s.69.visible=1 -unit.1.1.port.-1.s.7.alias= -unit.1.1.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.7.name=DataPort[7] -unit.1.1.port.-1.s.7.orderindex=-1 -unit.1.1.port.-1.s.7.visible=1 -unit.1.1.port.-1.s.70.alias= -unit.1.1.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.70.name=DataPort[70] -unit.1.1.port.-1.s.70.orderindex=-1 -unit.1.1.port.-1.s.70.visible=1 -unit.1.1.port.-1.s.71.alias= -unit.1.1.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.71.name=DataPort[71] -unit.1.1.port.-1.s.71.orderindex=-1 -unit.1.1.port.-1.s.71.visible=1 -unit.1.1.port.-1.s.72.alias= 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-unit.1.1.port.-1.s.77.alias= -unit.1.1.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.77.name=DataPort[77] -unit.1.1.port.-1.s.77.orderindex=-1 -unit.1.1.port.-1.s.77.visible=0 -unit.1.1.port.-1.s.78.alias= -unit.1.1.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.78.name=DataPort[78] -unit.1.1.port.-1.s.78.orderindex=-1 -unit.1.1.port.-1.s.78.visible=0 -unit.1.1.port.-1.s.79.alias= -unit.1.1.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.79.name=DataPort[79] -unit.1.1.port.-1.s.79.orderindex=-1 -unit.1.1.port.-1.s.79.visible=0 -unit.1.1.port.-1.s.8.alias= -unit.1.1.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.8.name=DataPort[8] -unit.1.1.port.-1.s.8.orderindex=-1 -unit.1.1.port.-1.s.8.visible=0 -unit.1.1.port.-1.s.80.alias= -unit.1.1.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.80.name=DataPort[80] -unit.1.1.port.-1.s.80.orderindex=-1 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-unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=0 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=0 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=0 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=0 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=0 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=0 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 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-unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.port.4.b.0.alias= -unit.1.1.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.b.0.name=TriggerPort4 -unit.1.1.port.4.b.0.orderindex=-1 -unit.1.1.port.4.b.0.radix=Hex -unit.1.1.port.4.b.0.signedOffset=0.0 -unit.1.1.port.4.b.0.signedPrecision=0 -unit.1.1.port.4.b.0.signedScaleFactor=1.0 -unit.1.1.port.4.b.0.unsignedOffset=0.0 -unit.1.1.port.4.b.0.unsignedPrecision=0 -unit.1.1.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.4.b.0.visible=1 -unit.1.1.port.4.buscount=1 -unit.1.1.port.4.channelcount=32 -unit.1.1.port.4.s.0.alias= -unit.1.1.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.0.name=TriggerPort4[0] -unit.1.1.port.4.s.0.orderindex=-1 -unit.1.1.port.4.s.0.visible=1 -unit.1.1.port.4.s.1.alias= -unit.1.1.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.1.name=TriggerPort4[1] -unit.1.1.port.4.s.1.orderindex=-1 -unit.1.1.port.4.s.1.visible=1 -unit.1.1.port.4.s.10.alias= -unit.1.1.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.10.name=TriggerPort4[10] -unit.1.1.port.4.s.10.orderindex=-1 -unit.1.1.port.4.s.10.visible=1 -unit.1.1.port.4.s.11.alias= -unit.1.1.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.11.name=TriggerPort4[11] -unit.1.1.port.4.s.11.orderindex=-1 -unit.1.1.port.4.s.11.visible=1 -unit.1.1.port.4.s.12.alias= -unit.1.1.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.12.name=TriggerPort4[12] -unit.1.1.port.4.s.12.orderindex=-1 -unit.1.1.port.4.s.12.visible=1 -unit.1.1.port.4.s.13.alias= -unit.1.1.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.13.name=TriggerPort4[13] -unit.1.1.port.4.s.13.orderindex=-1 -unit.1.1.port.4.s.13.visible=1 -unit.1.1.port.4.s.14.alias= -unit.1.1.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.14.name=TriggerPort4[14] -unit.1.1.port.4.s.14.orderindex=-1 -unit.1.1.port.4.s.14.visible=1 -unit.1.1.port.4.s.15.alias= -unit.1.1.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.15.name=TriggerPort4[15] -unit.1.1.port.4.s.15.orderindex=-1 -unit.1.1.port.4.s.15.visible=1 -unit.1.1.port.4.s.16.alias= -unit.1.1.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.16.name=TriggerPort4[16] -unit.1.1.port.4.s.16.orderindex=-1 -unit.1.1.port.4.s.16.visible=1 -unit.1.1.port.4.s.17.alias= -unit.1.1.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.17.name=TriggerPort4[17] -unit.1.1.port.4.s.17.orderindex=-1 -unit.1.1.port.4.s.17.visible=1 -unit.1.1.port.4.s.18.alias= -unit.1.1.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.18.name=TriggerPort4[18] -unit.1.1.port.4.s.18.orderindex=-1 -unit.1.1.port.4.s.18.visible=1 -unit.1.1.port.4.s.19.alias= -unit.1.1.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.19.name=TriggerPort4[19] -unit.1.1.port.4.s.19.orderindex=-1 -unit.1.1.port.4.s.19.visible=1 -unit.1.1.port.4.s.2.alias= -unit.1.1.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.2.name=TriggerPort4[2] -unit.1.1.port.4.s.2.orderindex=-1 -unit.1.1.port.4.s.2.visible=1 -unit.1.1.port.4.s.20.alias= -unit.1.1.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.20.name=TriggerPort4[20] -unit.1.1.port.4.s.20.orderindex=-1 -unit.1.1.port.4.s.20.visible=1 -unit.1.1.port.4.s.21.alias= -unit.1.1.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.21.name=TriggerPort4[21] -unit.1.1.port.4.s.21.orderindex=-1 -unit.1.1.port.4.s.21.visible=1 -unit.1.1.port.4.s.22.alias= -unit.1.1.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.22.name=TriggerPort4[22] -unit.1.1.port.4.s.22.orderindex=-1 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-unit.1.1.port.4.s.27.orderindex=-1 -unit.1.1.port.4.s.27.visible=1 -unit.1.1.port.4.s.28.alias= -unit.1.1.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.28.name=TriggerPort4[28] -unit.1.1.port.4.s.28.orderindex=-1 -unit.1.1.port.4.s.28.visible=1 -unit.1.1.port.4.s.29.alias= -unit.1.1.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.29.name=TriggerPort4[29] -unit.1.1.port.4.s.29.orderindex=-1 -unit.1.1.port.4.s.29.visible=1 -unit.1.1.port.4.s.3.alias= -unit.1.1.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.3.name=TriggerPort4[3] -unit.1.1.port.4.s.3.orderindex=-1 -unit.1.1.port.4.s.3.visible=1 -unit.1.1.port.4.s.30.alias= -unit.1.1.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.30.name=TriggerPort4[30] -unit.1.1.port.4.s.30.orderindex=-1 -unit.1.1.port.4.s.30.visible=1 -unit.1.1.port.4.s.31.alias= -unit.1.1.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.31.name=TriggerPort4[31] -unit.1.1.port.4.s.31.orderindex=-1 -unit.1.1.port.4.s.31.visible=1 -unit.1.1.port.4.s.4.alias= -unit.1.1.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.4.name=TriggerPort4[4] -unit.1.1.port.4.s.4.orderindex=-1 -unit.1.1.port.4.s.4.visible=1 -unit.1.1.port.4.s.5.alias= -unit.1.1.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.5.name=TriggerPort4[5] -unit.1.1.port.4.s.5.orderindex=-1 -unit.1.1.port.4.s.5.visible=1 -unit.1.1.port.4.s.6.alias= -unit.1.1.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.6.name=TriggerPort4[6] -unit.1.1.port.4.s.6.orderindex=-1 -unit.1.1.port.4.s.6.visible=1 -unit.1.1.port.4.s.7.alias= -unit.1.1.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.7.name=TriggerPort4[7] -unit.1.1.port.4.s.7.orderindex=-1 -unit.1.1.port.4.s.7.visible=1 -unit.1.1.port.4.s.8.alias= -unit.1.1.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.8.name=TriggerPort4[8] -unit.1.1.port.4.s.8.orderindex=-1 -unit.1.1.port.4.s.8.visible=1 -unit.1.1.port.4.s.9.alias= -unit.1.1.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.4.s.9.name=TriggerPort4[9] -unit.1.1.port.4.s.9.orderindex=-1 -unit.1.1.port.4.s.9.visible=1 -unit.1.1.portcount=5 -unit.1.1.rep_trigger.clobber=1 -unit.1.1.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.1.rep_trigger.filename=waveform -unit.1.1.rep_trigger.format=ASCII -unit.1.1.rep_trigger.loggingEnabled=0 -unit.1.1.rep_trigger.signals=All Signals/Buses -unit.1.1.samplesPerTrigger=1 -unit.1.1.triggerCapture=1 -unit.1.1.triggerNSamplesTS=0 -unit.1.1.triggerPosition=0 -unit.1.1.triggerWindowCount=1 -unit.1.1.triggerWindowDepth=2048 -unit.1.1.triggerWindowTS=0 -unit.1.1.username=MyILA1 -unit.1.1.waveform.count=11 -unit.1.1.waveform.posn.0.channel=2147483646 -unit.1.1.waveform.posn.0.name=dsp_mix_ch2_i -unit.1.1.waveform.posn.0.radix=3 -unit.1.1.waveform.posn.0.type=bus -unit.1.1.waveform.posn.1.channel=2147483646 -unit.1.1.waveform.posn.1.name=dsp_mix_ch0_i -unit.1.1.waveform.posn.1.radix=3 -unit.1.1.waveform.posn.1.type=bus -unit.1.1.waveform.posn.10.channel=103 -unit.1.1.waveform.posn.10.name=DataPort[103] -unit.1.1.waveform.posn.10.radix=3 -unit.1.1.waveform.posn.10.type=signal -unit.1.1.waveform.posn.100.channel=127 -unit.1.1.waveform.posn.100.name=DataPort[127] -unit.1.1.waveform.posn.100.type=signal -unit.1.1.waveform.posn.101.channel=127 -unit.1.1.waveform.posn.101.name=DataPort[127] -unit.1.1.waveform.posn.101.type=signal -unit.1.1.waveform.posn.102.channel=127 -unit.1.1.waveform.posn.102.name=DataPort[127] -unit.1.1.waveform.posn.102.type=signal -unit.1.1.waveform.posn.103.channel=127 -unit.1.1.waveform.posn.103.name=DataPort[127] -unit.1.1.waveform.posn.103.type=signal -unit.1.1.waveform.posn.104.channel=127 -unit.1.1.waveform.posn.104.name=DataPort[127] -unit.1.1.waveform.posn.104.type=signal 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-unit.1.1.waveform.posn.89.type=signal -unit.1.1.waveform.posn.9.channel=102 -unit.1.1.waveform.posn.9.name=DataPort[102] -unit.1.1.waveform.posn.9.radix=3 -unit.1.1.waveform.posn.9.type=signal -unit.1.1.waveform.posn.90.channel=127 -unit.1.1.waveform.posn.90.name=DataPort[127] -unit.1.1.waveform.posn.90.type=signal -unit.1.1.waveform.posn.91.channel=127 -unit.1.1.waveform.posn.91.name=DataPort[127] -unit.1.1.waveform.posn.91.type=signal -unit.1.1.waveform.posn.92.channel=127 -unit.1.1.waveform.posn.92.name=DataPort[127] -unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=127 -unit.1.1.waveform.posn.93.name=DataPort[127] -unit.1.1.waveform.posn.93.type=signal -unit.1.1.waveform.posn.94.channel=127 -unit.1.1.waveform.posn.94.name=DataPort[127] -unit.1.1.waveform.posn.94.type=signal -unit.1.1.waveform.posn.95.channel=127 -unit.1.1.waveform.posn.95.name=DataPort[127] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=127 -unit.1.1.waveform.posn.96.name=DataPort[127] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal -unit.1.2.0.HEIGHT0=0.37337664 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 -unit.1.2.0.TriggerRow2=1 -unit.1.2.0.WIDTH0=0.6552478 -unit.1.2.0.X0=0.052478135 -unit.1.2.0.Y0=0.0 -unit.1.2.1.HEIGHT1=0.77922076 -unit.1.2.1.WIDTH1=0.6027697 -unit.1.2.1.X1=0.0051020407 -unit.1.2.1.Y1=0.12662338 -unit.1.2.5.HEIGHT5=0.85227275 -unit.1.2.5.WIDTH5=0.6851312 -unit.1.2.5.X5=0.0036443148 -unit.1.2.5.Y5=0.06655844 -unit.1.2.MFBitsA0=X1XXXXXX -unit.1.2.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsB0=00000000 -unit.1.2.MFBitsB1=00000000000000000000000000000000 -unit.1.2.MFBitsB2=00000000000000000000000000000000 -unit.1.2.MFBitsB3=00000000000000000000000000000000 -unit.1.2.MFBitsB4=00000000000000000000000000000000 -unit.1.2.MFCompareA0=0 -unit.1.2.MFCompareA1=0 -unit.1.2.MFCompareA2=0 -unit.1.2.MFCompareA3=0 -unit.1.2.MFCompareA4=0 -unit.1.2.MFCompareB0=999 -unit.1.2.MFCompareB1=999 -unit.1.2.MFCompareB2=999 -unit.1.2.MFCompareB3=999 -unit.1.2.MFCompareB4=999 -unit.1.2.MFCount=5 -unit.1.2.MFDisplay0=0 -unit.1.2.MFDisplay1=0 -unit.1.2.MFDisplay2=0 -unit.1.2.MFDisplay3=0 -unit.1.2.MFDisplay4=0 -unit.1.2.MFEventType0=3 -unit.1.2.MFEventType1=3 -unit.1.2.MFEventType2=3 -unit.1.2.MFEventType3=3 -unit.1.2.MFEventType4=3 -unit.1.2.RunMode=SINGLE RUN -unit.1.2.SQCondition=M0 -unit.1.2.SQContiguous0=0 -unit.1.2.SequencerOn=0 -unit.1.2.TCActive=0 -unit.1.2.TCAdvanced0=0 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-unit.1.2.port.-1.s.67.alias= -unit.1.2.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.67.name=DataPort[67] -unit.1.2.port.-1.s.67.orderindex=-1 -unit.1.2.port.-1.s.67.visible=1 -unit.1.2.port.-1.s.68.alias= -unit.1.2.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.68.name=DataPort[68] -unit.1.2.port.-1.s.68.orderindex=-1 -unit.1.2.port.-1.s.68.visible=1 -unit.1.2.port.-1.s.69.alias= -unit.1.2.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.69.name=DataPort[69] -unit.1.2.port.-1.s.69.orderindex=-1 -unit.1.2.port.-1.s.69.visible=1 -unit.1.2.port.-1.s.7.alias= -unit.1.2.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.7.name=DataPort[7] -unit.1.2.port.-1.s.7.orderindex=-1 -unit.1.2.port.-1.s.7.visible=1 -unit.1.2.port.-1.s.70.alias= -unit.1.2.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.70.name=DataPort[70] -unit.1.2.port.-1.s.70.orderindex=-1 -unit.1.2.port.-1.s.70.visible=1 -unit.1.2.port.-1.s.71.alias= -unit.1.2.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.71.name=DataPort[71] -unit.1.2.port.-1.s.71.orderindex=-1 -unit.1.2.port.-1.s.71.visible=1 -unit.1.2.port.-1.s.72.alias= -unit.1.2.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.72.name=DataPort[72] -unit.1.2.port.-1.s.72.orderindex=-1 -unit.1.2.port.-1.s.72.visible=0 -unit.1.2.port.-1.s.73.alias= -unit.1.2.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.73.name=DataPort[73] -unit.1.2.port.-1.s.73.orderindex=-1 -unit.1.2.port.-1.s.73.visible=0 -unit.1.2.port.-1.s.74.alias= -unit.1.2.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.74.name=DataPort[74] -unit.1.2.port.-1.s.74.orderindex=-1 -unit.1.2.port.-1.s.74.visible=0 -unit.1.2.port.-1.s.75.alias= -unit.1.2.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.75.name=DataPort[75] -unit.1.2.port.-1.s.75.orderindex=-1 -unit.1.2.port.-1.s.75.visible=0 -unit.1.2.port.-1.s.76.alias= -unit.1.2.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.76.name=DataPort[76] -unit.1.2.port.-1.s.76.orderindex=-1 -unit.1.2.port.-1.s.76.visible=0 -unit.1.2.port.-1.s.77.alias= -unit.1.2.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.77.name=DataPort[77] -unit.1.2.port.-1.s.77.orderindex=-1 -unit.1.2.port.-1.s.77.visible=0 -unit.1.2.port.-1.s.78.alias= -unit.1.2.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.78.name=DataPort[78] -unit.1.2.port.-1.s.78.orderindex=-1 -unit.1.2.port.-1.s.78.visible=0 -unit.1.2.port.-1.s.79.alias= -unit.1.2.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.79.name=DataPort[79] -unit.1.2.port.-1.s.79.orderindex=-1 -unit.1.2.port.-1.s.79.visible=0 -unit.1.2.port.-1.s.8.alias= -unit.1.2.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.8.name=DataPort[8] -unit.1.2.port.-1.s.8.orderindex=-1 -unit.1.2.port.-1.s.8.visible=0 -unit.1.2.port.-1.s.80.alias= -unit.1.2.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.80.name=DataPort[80] -unit.1.2.port.-1.s.80.orderindex=-1 -unit.1.2.port.-1.s.80.visible=0 -unit.1.2.port.-1.s.81.alias= -unit.1.2.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.81.name=DataPort[81] -unit.1.2.port.-1.s.81.orderindex=-1 -unit.1.2.port.-1.s.81.visible=0 -unit.1.2.port.-1.s.82.alias= -unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=0 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=0 -unit.1.2.port.-1.s.84.alias= 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-unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 -unit.1.2.port.3.s.27.alias= -unit.1.2.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.27.name=TriggerPort3[27] -unit.1.2.port.3.s.27.orderindex=-1 -unit.1.2.port.3.s.27.visible=1 -unit.1.2.port.3.s.28.alias= -unit.1.2.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.28.name=TriggerPort3[28] -unit.1.2.port.3.s.28.orderindex=-1 -unit.1.2.port.3.s.28.visible=1 -unit.1.2.port.3.s.29.alias= -unit.1.2.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.29.name=TriggerPort3[29] -unit.1.2.port.3.s.29.orderindex=-1 -unit.1.2.port.3.s.29.visible=1 -unit.1.2.port.3.s.3.alias= -unit.1.2.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.3.name=TriggerPort3[3] -unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.port.4.b.0.alias= -unit.1.2.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.b.0.name=TriggerPort4 -unit.1.2.port.4.b.0.orderindex=-1 -unit.1.2.port.4.b.0.radix=Hex -unit.1.2.port.4.b.0.signedOffset=0.0 -unit.1.2.port.4.b.0.signedPrecision=0 -unit.1.2.port.4.b.0.signedScaleFactor=1.0 -unit.1.2.port.4.b.0.unsignedOffset=0.0 -unit.1.2.port.4.b.0.unsignedPrecision=0 -unit.1.2.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.4.b.0.visible=1 -unit.1.2.port.4.buscount=1 -unit.1.2.port.4.channelcount=32 -unit.1.2.port.4.s.0.alias= -unit.1.2.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.0.name=TriggerPort4[0] -unit.1.2.port.4.s.0.orderindex=-1 -unit.1.2.port.4.s.0.visible=1 -unit.1.2.port.4.s.1.alias= -unit.1.2.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.1.name=TriggerPort4[1] -unit.1.2.port.4.s.1.orderindex=-1 -unit.1.2.port.4.s.1.visible=1 -unit.1.2.port.4.s.10.alias= -unit.1.2.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.10.name=TriggerPort4[10] -unit.1.2.port.4.s.10.orderindex=-1 -unit.1.2.port.4.s.10.visible=1 -unit.1.2.port.4.s.11.alias= -unit.1.2.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.11.name=TriggerPort4[11] -unit.1.2.port.4.s.11.orderindex=-1 -unit.1.2.port.4.s.11.visible=1 -unit.1.2.port.4.s.12.alias= -unit.1.2.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.12.name=TriggerPort4[12] -unit.1.2.port.4.s.12.orderindex=-1 -unit.1.2.port.4.s.12.visible=1 -unit.1.2.port.4.s.13.alias= -unit.1.2.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.13.name=TriggerPort4[13] -unit.1.2.port.4.s.13.orderindex=-1 -unit.1.2.port.4.s.13.visible=1 -unit.1.2.port.4.s.14.alias= -unit.1.2.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.14.name=TriggerPort4[14] -unit.1.2.port.4.s.14.orderindex=-1 -unit.1.2.port.4.s.14.visible=1 -unit.1.2.port.4.s.15.alias= -unit.1.2.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.15.name=TriggerPort4[15] -unit.1.2.port.4.s.15.orderindex=-1 -unit.1.2.port.4.s.15.visible=1 -unit.1.2.port.4.s.16.alias= -unit.1.2.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.16.name=TriggerPort4[16] -unit.1.2.port.4.s.16.orderindex=-1 -unit.1.2.port.4.s.16.visible=1 -unit.1.2.port.4.s.17.alias= -unit.1.2.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.17.name=TriggerPort4[17] -unit.1.2.port.4.s.17.orderindex=-1 -unit.1.2.port.4.s.17.visible=1 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-unit.1.2.port.4.s.21.visible=1 -unit.1.2.port.4.s.22.alias= -unit.1.2.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.22.name=TriggerPort4[22] -unit.1.2.port.4.s.22.orderindex=-1 -unit.1.2.port.4.s.22.visible=1 -unit.1.2.port.4.s.23.alias= -unit.1.2.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.23.name=TriggerPort4[23] -unit.1.2.port.4.s.23.orderindex=-1 -unit.1.2.port.4.s.23.visible=1 -unit.1.2.port.4.s.24.alias= -unit.1.2.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.24.name=TriggerPort4[24] -unit.1.2.port.4.s.24.orderindex=-1 -unit.1.2.port.4.s.24.visible=1 -unit.1.2.port.4.s.25.alias= -unit.1.2.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.25.name=TriggerPort4[25] -unit.1.2.port.4.s.25.orderindex=-1 -unit.1.2.port.4.s.25.visible=1 -unit.1.2.port.4.s.26.alias= -unit.1.2.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.26.name=TriggerPort4[26] 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-unit.1.2.port.4.s.30.name=TriggerPort4[30] -unit.1.2.port.4.s.30.orderindex=-1 -unit.1.2.port.4.s.30.visible=1 -unit.1.2.port.4.s.31.alias= -unit.1.2.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.31.name=TriggerPort4[31] -unit.1.2.port.4.s.31.orderindex=-1 -unit.1.2.port.4.s.31.visible=1 -unit.1.2.port.4.s.4.alias= -unit.1.2.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.4.name=TriggerPort4[4] -unit.1.2.port.4.s.4.orderindex=-1 -unit.1.2.port.4.s.4.visible=1 -unit.1.2.port.4.s.5.alias= -unit.1.2.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.5.name=TriggerPort4[5] -unit.1.2.port.4.s.5.orderindex=-1 -unit.1.2.port.4.s.5.visible=1 -unit.1.2.port.4.s.6.alias= -unit.1.2.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.6.name=TriggerPort4[6] -unit.1.2.port.4.s.6.orderindex=-1 -unit.1.2.port.4.s.6.visible=1 -unit.1.2.port.4.s.7.alias= -unit.1.2.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.7.name=TriggerPort4[7] -unit.1.2.port.4.s.7.orderindex=-1 -unit.1.2.port.4.s.7.visible=1 -unit.1.2.port.4.s.8.alias= -unit.1.2.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.8.name=TriggerPort4[8] -unit.1.2.port.4.s.8.orderindex=-1 -unit.1.2.port.4.s.8.visible=1 -unit.1.2.port.4.s.9.alias= -unit.1.2.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.4.s.9.name=TriggerPort4[9] -unit.1.2.port.4.s.9.orderindex=-1 -unit.1.2.port.4.s.9.visible=1 -unit.1.2.portcount=5 -unit.1.2.rep_trigger.clobber=1 -unit.1.2.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.2.rep_trigger.filename=waveform -unit.1.2.rep_trigger.format=ASCII -unit.1.2.rep_trigger.loggingEnabled=0 -unit.1.2.rep_trigger.signals=All Signals/Buses -unit.1.2.samplesPerTrigger=1 -unit.1.2.triggerCapture=1 -unit.1.2.triggerNSamplesTS=0 -unit.1.2.triggerPosition=0 -unit.1.2.triggerWindowCount=1 -unit.1.2.triggerWindowDepth=4096 -unit.1.2.triggerWindowTS=0 -unit.1.2.username=MyILA2 -unit.1.2.waveform.count=33 -unit.1.2.waveform.posn.0.channel=2147483646 -unit.1.2.waveform.posn.0.name=dsp_tbt_amp_ch3 -unit.1.2.waveform.posn.0.radix=3 -unit.1.2.waveform.posn.0.type=bus -unit.1.2.waveform.posn.1.channel=2147483646 -unit.1.2.waveform.posn.1.name=dsp_tbt_amp_ch2 -unit.1.2.waveform.posn.1.radix=3 -unit.1.2.waveform.posn.1.type=bus -unit.1.2.waveform.posn.10.channel=7 -unit.1.2.waveform.posn.10.name=DataPort[7] -unit.1.2.waveform.posn.10.radix=3 -unit.1.2.waveform.posn.10.type=signal -unit.1.2.waveform.posn.100.channel=127 -unit.1.2.waveform.posn.100.name=DataPort[127] -unit.1.2.waveform.posn.100.type=signal -unit.1.2.waveform.posn.101.channel=127 -unit.1.2.waveform.posn.101.name=DataPort[127] -unit.1.2.waveform.posn.101.type=signal -unit.1.2.waveform.posn.102.channel=127 -unit.1.2.waveform.posn.102.name=DataPort[127] -unit.1.2.waveform.posn.102.type=signal -unit.1.2.waveform.posn.103.channel=127 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-unit.1.2.waveform.posn.16.type=signal -unit.1.2.waveform.posn.17.channel=38 -unit.1.2.waveform.posn.17.name=DataPort[38] -unit.1.2.waveform.posn.17.type=signal -unit.1.2.waveform.posn.18.channel=39 -unit.1.2.waveform.posn.18.name=DataPort[39] -unit.1.2.waveform.posn.18.type=signal -unit.1.2.waveform.posn.19.channel=65 -unit.1.2.waveform.posn.19.name=DataPort[65] -unit.1.2.waveform.posn.19.type=signal -unit.1.2.waveform.posn.2.channel=2147483646 -unit.1.2.waveform.posn.2.name=dsp_tbt_amp_ch1 -unit.1.2.waveform.posn.2.radix=3 -unit.1.2.waveform.posn.2.type=bus -unit.1.2.waveform.posn.20.channel=66 -unit.1.2.waveform.posn.20.name=DataPort[66] -unit.1.2.waveform.posn.20.type=signal -unit.1.2.waveform.posn.21.channel=67 -unit.1.2.waveform.posn.21.name=DataPort[67] -unit.1.2.waveform.posn.21.type=signal -unit.1.2.waveform.posn.22.channel=68 -unit.1.2.waveform.posn.22.name=DataPort[68] -unit.1.2.waveform.posn.22.type=signal -unit.1.2.waveform.posn.23.channel=69 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-unit.1.3.port.-1.buscount=4 -unit.1.3.port.-1.channelcount=136 -unit.1.3.port.-1.s.0.alias= -unit.1.3.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.0.name=DataPort[0] -unit.1.3.port.-1.s.0.orderindex=-1 -unit.1.3.port.-1.s.0.visible=1 -unit.1.3.port.-1.s.1.alias= -unit.1.3.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.1.name=DataPort[1] -unit.1.3.port.-1.s.1.orderindex=-1 -unit.1.3.port.-1.s.1.visible=1 -unit.1.3.port.-1.s.10.alias= -unit.1.3.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.10.name=DataPort[10] -unit.1.3.port.-1.s.10.orderindex=-1 -unit.1.3.port.-1.s.10.visible=0 -unit.1.3.port.-1.s.100.alias= -unit.1.3.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.100.name=DataPort[100] -unit.1.3.port.-1.s.100.orderindex=-1 -unit.1.3.port.-1.s.100.visible=1 -unit.1.3.port.-1.s.101.alias= -unit.1.3.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.101.name=DataPort[101] -unit.1.3.port.-1.s.101.orderindex=-1 -unit.1.3.port.-1.s.101.visible=1 -unit.1.3.port.-1.s.102.alias= -unit.1.3.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.102.name=DataPort[102] -unit.1.3.port.-1.s.102.orderindex=-1 -unit.1.3.port.-1.s.102.visible=1 -unit.1.3.port.-1.s.103.alias= -unit.1.3.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.103.name=DataPort[103] -unit.1.3.port.-1.s.103.orderindex=-1 -unit.1.3.port.-1.s.103.visible=1 -unit.1.3.port.-1.s.104.alias= -unit.1.3.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.104.name=DataPort[104] -unit.1.3.port.-1.s.104.orderindex=-1 -unit.1.3.port.-1.s.104.visible=0 -unit.1.3.port.-1.s.105.alias= -unit.1.3.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.105.name=DataPort[105] -unit.1.3.port.-1.s.105.orderindex=-1 -unit.1.3.port.-1.s.105.visible=0 -unit.1.3.port.-1.s.106.alias= -unit.1.3.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.106.name=DataPort[106] -unit.1.3.port.-1.s.106.orderindex=-1 -unit.1.3.port.-1.s.106.visible=0 -unit.1.3.port.-1.s.107.alias= -unit.1.3.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.107.name=DataPort[107] -unit.1.3.port.-1.s.107.orderindex=-1 -unit.1.3.port.-1.s.107.visible=0 -unit.1.3.port.-1.s.108.alias= -unit.1.3.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.108.name=DataPort[108] -unit.1.3.port.-1.s.108.orderindex=-1 -unit.1.3.port.-1.s.108.visible=0 -unit.1.3.port.-1.s.109.alias= -unit.1.3.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.109.name=DataPort[109] -unit.1.3.port.-1.s.109.orderindex=-1 -unit.1.3.port.-1.s.109.visible=0 -unit.1.3.port.-1.s.11.alias= -unit.1.3.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.11.name=DataPort[11] -unit.1.3.port.-1.s.11.orderindex=-1 -unit.1.3.port.-1.s.11.visible=0 -unit.1.3.port.-1.s.110.alias= -unit.1.3.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.110.name=DataPort[110] -unit.1.3.port.-1.s.110.orderindex=-1 -unit.1.3.port.-1.s.110.visible=0 -unit.1.3.port.-1.s.111.alias= -unit.1.3.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.111.name=DataPort[111] -unit.1.3.port.-1.s.111.orderindex=-1 -unit.1.3.port.-1.s.111.visible=0 -unit.1.3.port.-1.s.112.alias= -unit.1.3.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.112.name=DataPort[112] -unit.1.3.port.-1.s.112.orderindex=-1 -unit.1.3.port.-1.s.112.visible=0 -unit.1.3.port.-1.s.113.alias= -unit.1.3.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.113.name=DataPort[113] -unit.1.3.port.-1.s.113.orderindex=-1 -unit.1.3.port.-1.s.113.visible=0 -unit.1.3.port.-1.s.114.alias= -unit.1.3.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.114.name=DataPort[114] -unit.1.3.port.-1.s.114.orderindex=-1 -unit.1.3.port.-1.s.114.visible=0 -unit.1.3.port.-1.s.115.alias= -unit.1.3.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.115.name=DataPort[115] -unit.1.3.port.-1.s.115.orderindex=-1 -unit.1.3.port.-1.s.115.visible=0 -unit.1.3.port.-1.s.116.alias= -unit.1.3.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.116.name=DataPort[116] -unit.1.3.port.-1.s.116.orderindex=-1 -unit.1.3.port.-1.s.116.visible=0 -unit.1.3.port.-1.s.117.alias= -unit.1.3.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.117.name=DataPort[117] -unit.1.3.port.-1.s.117.orderindex=-1 -unit.1.3.port.-1.s.117.visible=0 -unit.1.3.port.-1.s.118.alias= -unit.1.3.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.118.name=DataPort[118] -unit.1.3.port.-1.s.118.orderindex=-1 -unit.1.3.port.-1.s.118.visible=0 -unit.1.3.port.-1.s.119.alias= -unit.1.3.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.119.name=DataPort[119] -unit.1.3.port.-1.s.119.orderindex=-1 -unit.1.3.port.-1.s.119.visible=0 -unit.1.3.port.-1.s.12.alias= -unit.1.3.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.12.name=DataPort[12] -unit.1.3.port.-1.s.12.orderindex=-1 -unit.1.3.port.-1.s.12.visible=0 -unit.1.3.port.-1.s.120.alias= -unit.1.3.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.120.name=DataPort[120] -unit.1.3.port.-1.s.120.orderindex=-1 -unit.1.3.port.-1.s.120.visible=0 -unit.1.3.port.-1.s.121.alias= -unit.1.3.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.121.name=DataPort[121] -unit.1.3.port.-1.s.121.orderindex=-1 -unit.1.3.port.-1.s.121.visible=0 -unit.1.3.port.-1.s.122.alias= -unit.1.3.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.122.name=DataPort[122] -unit.1.3.port.-1.s.122.orderindex=-1 -unit.1.3.port.-1.s.122.visible=0 -unit.1.3.port.-1.s.123.alias= -unit.1.3.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.123.name=DataPort[123] -unit.1.3.port.-1.s.123.orderindex=-1 -unit.1.3.port.-1.s.123.visible=0 -unit.1.3.port.-1.s.124.alias= -unit.1.3.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.124.name=DataPort[124] -unit.1.3.port.-1.s.124.orderindex=-1 -unit.1.3.port.-1.s.124.visible=0 -unit.1.3.port.-1.s.125.alias= -unit.1.3.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.125.name=DataPort[125] -unit.1.3.port.-1.s.125.orderindex=-1 -unit.1.3.port.-1.s.125.visible=0 -unit.1.3.port.-1.s.126.alias= -unit.1.3.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.126.name=DataPort[126] -unit.1.3.port.-1.s.126.orderindex=-1 -unit.1.3.port.-1.s.126.visible=0 -unit.1.3.port.-1.s.127.alias= -unit.1.3.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.127.name=DataPort[127] -unit.1.3.port.-1.s.127.orderindex=-1 -unit.1.3.port.-1.s.127.visible=0 -unit.1.3.port.-1.s.128.alias= -unit.1.3.port.-1.s.128.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.128.name=DataPort[128] -unit.1.3.port.-1.s.128.orderindex=-1 -unit.1.3.port.-1.s.128.visible=0 -unit.1.3.port.-1.s.129.alias= -unit.1.3.port.-1.s.129.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.129.name=DataPort[129] -unit.1.3.port.-1.s.129.orderindex=-1 -unit.1.3.port.-1.s.129.visible=0 -unit.1.3.port.-1.s.13.alias= -unit.1.3.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.13.name=DataPort[13] -unit.1.3.port.-1.s.13.orderindex=-1 -unit.1.3.port.-1.s.13.visible=0 -unit.1.3.port.-1.s.130.alias= -unit.1.3.port.-1.s.130.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.130.name=DataPort[130] -unit.1.3.port.-1.s.130.orderindex=-1 -unit.1.3.port.-1.s.130.visible=1 -unit.1.3.port.-1.s.131.alias= -unit.1.3.port.-1.s.131.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.131.name=DataPort[131] -unit.1.3.port.-1.s.131.orderindex=-1 -unit.1.3.port.-1.s.131.visible=1 -unit.1.3.port.-1.s.132.alias= -unit.1.3.port.-1.s.132.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.132.name=DataPort[132] -unit.1.3.port.-1.s.132.orderindex=-1 -unit.1.3.port.-1.s.132.visible=1 -unit.1.3.port.-1.s.133.alias= -unit.1.3.port.-1.s.133.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.133.name=DataPort[133] -unit.1.3.port.-1.s.133.orderindex=-1 -unit.1.3.port.-1.s.133.visible=1 -unit.1.3.port.-1.s.134.alias= -unit.1.3.port.-1.s.134.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.134.name=DataPort[134] -unit.1.3.port.-1.s.134.orderindex=-1 -unit.1.3.port.-1.s.134.visible=1 -unit.1.3.port.-1.s.135.alias= -unit.1.3.port.-1.s.135.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.135.name=DataPort[135] -unit.1.3.port.-1.s.135.orderindex=-1 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-unit.1.3.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.70.name=DataPort[70] -unit.1.3.port.-1.s.70.orderindex=-1 -unit.1.3.port.-1.s.70.visible=1 -unit.1.3.port.-1.s.71.alias= -unit.1.3.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.71.name=DataPort[71] -unit.1.3.port.-1.s.71.orderindex=-1 -unit.1.3.port.-1.s.71.visible=1 -unit.1.3.port.-1.s.72.alias= -unit.1.3.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.72.name=DataPort[72] -unit.1.3.port.-1.s.72.orderindex=-1 -unit.1.3.port.-1.s.72.visible=0 -unit.1.3.port.-1.s.73.alias= -unit.1.3.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.73.name=DataPort[73] -unit.1.3.port.-1.s.73.orderindex=-1 -unit.1.3.port.-1.s.73.visible=0 -unit.1.3.port.-1.s.74.alias= -unit.1.3.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.74.name=DataPort[74] -unit.1.3.port.-1.s.74.orderindex=-1 -unit.1.3.port.-1.s.74.visible=0 -unit.1.3.port.-1.s.75.alias= -unit.1.3.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.75.name=DataPort[75] -unit.1.3.port.-1.s.75.orderindex=-1 -unit.1.3.port.-1.s.75.visible=0 -unit.1.3.port.-1.s.76.alias= -unit.1.3.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.76.name=DataPort[76] -unit.1.3.port.-1.s.76.orderindex=-1 -unit.1.3.port.-1.s.76.visible=0 -unit.1.3.port.-1.s.77.alias= -unit.1.3.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.77.name=DataPort[77] -unit.1.3.port.-1.s.77.orderindex=-1 -unit.1.3.port.-1.s.77.visible=0 -unit.1.3.port.-1.s.78.alias= -unit.1.3.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.78.name=DataPort[78] -unit.1.3.port.-1.s.78.orderindex=-1 -unit.1.3.port.-1.s.78.visible=0 -unit.1.3.port.-1.s.79.alias= -unit.1.3.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.79.name=DataPort[79] -unit.1.3.port.-1.s.79.orderindex=-1 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-unit.1.3.port.-1.s.83.orderindex=-1 -unit.1.3.port.-1.s.83.visible=0 -unit.1.3.port.-1.s.84.alias= -unit.1.3.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.84.name=DataPort[84] -unit.1.3.port.-1.s.84.orderindex=-1 -unit.1.3.port.-1.s.84.visible=0 -unit.1.3.port.-1.s.85.alias= -unit.1.3.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.85.name=DataPort[85] -unit.1.3.port.-1.s.85.orderindex=-1 -unit.1.3.port.-1.s.85.visible=0 -unit.1.3.port.-1.s.86.alias= -unit.1.3.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.86.name=DataPort[86] -unit.1.3.port.-1.s.86.orderindex=-1 -unit.1.3.port.-1.s.86.visible=0 -unit.1.3.port.-1.s.87.alias= -unit.1.3.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.87.name=DataPort[87] -unit.1.3.port.-1.s.87.orderindex=-1 -unit.1.3.port.-1.s.87.visible=0 -unit.1.3.port.-1.s.88.alias= -unit.1.3.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.88.name=DataPort[88] -unit.1.3.port.-1.s.88.orderindex=-1 -unit.1.3.port.-1.s.88.visible=0 -unit.1.3.port.-1.s.89.alias= -unit.1.3.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.89.name=DataPort[89] -unit.1.3.port.-1.s.89.orderindex=-1 -unit.1.3.port.-1.s.89.visible=0 -unit.1.3.port.-1.s.9.alias= -unit.1.3.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.9.name=DataPort[9] -unit.1.3.port.-1.s.9.orderindex=-1 -unit.1.3.port.-1.s.9.visible=0 -unit.1.3.port.-1.s.90.alias= -unit.1.3.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.90.name=DataPort[90] -unit.1.3.port.-1.s.90.orderindex=-1 -unit.1.3.port.-1.s.90.visible=0 -unit.1.3.port.-1.s.91.alias= -unit.1.3.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.91.name=DataPort[91] -unit.1.3.port.-1.s.91.orderindex=-1 -unit.1.3.port.-1.s.91.visible=0 -unit.1.3.port.-1.s.92.alias= -unit.1.3.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.92.name=DataPort[92] -unit.1.3.port.-1.s.92.orderindex=-1 -unit.1.3.port.-1.s.92.visible=0 -unit.1.3.port.-1.s.93.alias= -unit.1.3.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.93.name=DataPort[93] -unit.1.3.port.-1.s.93.orderindex=-1 -unit.1.3.port.-1.s.93.visible=0 -unit.1.3.port.-1.s.94.alias= -unit.1.3.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.94.name=DataPort[94] -unit.1.3.port.-1.s.94.orderindex=-1 -unit.1.3.port.-1.s.94.visible=0 -unit.1.3.port.-1.s.95.alias= -unit.1.3.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.95.name=DataPort[95] -unit.1.3.port.-1.s.95.orderindex=-1 -unit.1.3.port.-1.s.95.visible=0 -unit.1.3.port.-1.s.96.alias= -unit.1.3.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.96.name=DataPort[96] -unit.1.3.port.-1.s.96.orderindex=-1 -unit.1.3.port.-1.s.96.visible=1 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-unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.port.4.b.0.alias= -unit.1.3.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.b.0.name=TriggerPort4 -unit.1.3.port.4.b.0.orderindex=-1 -unit.1.3.port.4.b.0.radix=Hex -unit.1.3.port.4.b.0.signedOffset=0.0 -unit.1.3.port.4.b.0.signedPrecision=0 -unit.1.3.port.4.b.0.signedScaleFactor=1.0 -unit.1.3.port.4.b.0.unsignedOffset=0.0 -unit.1.3.port.4.b.0.unsignedPrecision=0 -unit.1.3.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.4.b.0.visible=1 -unit.1.3.port.4.buscount=1 -unit.1.3.port.4.channelcount=32 -unit.1.3.port.4.s.0.alias= -unit.1.3.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.0.name=TriggerPort4[0] -unit.1.3.port.4.s.0.orderindex=-1 -unit.1.3.port.4.s.0.visible=1 -unit.1.3.port.4.s.1.alias= -unit.1.3.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.1.name=TriggerPort4[1] -unit.1.3.port.4.s.1.orderindex=-1 -unit.1.3.port.4.s.1.visible=1 -unit.1.3.port.4.s.10.alias= -unit.1.3.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.10.name=TriggerPort4[10] -unit.1.3.port.4.s.10.orderindex=-1 -unit.1.3.port.4.s.10.visible=1 -unit.1.3.port.4.s.11.alias= -unit.1.3.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.11.name=TriggerPort4[11] -unit.1.3.port.4.s.11.orderindex=-1 -unit.1.3.port.4.s.11.visible=1 -unit.1.3.port.4.s.12.alias= -unit.1.3.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.12.name=TriggerPort4[12] -unit.1.3.port.4.s.12.orderindex=-1 -unit.1.3.port.4.s.12.visible=1 -unit.1.3.port.4.s.13.alias= -unit.1.3.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.13.name=TriggerPort4[13] -unit.1.3.port.4.s.13.orderindex=-1 -unit.1.3.port.4.s.13.visible=1 -unit.1.3.port.4.s.14.alias= -unit.1.3.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.14.name=TriggerPort4[14] -unit.1.3.port.4.s.14.orderindex=-1 -unit.1.3.port.4.s.14.visible=1 -unit.1.3.port.4.s.15.alias= -unit.1.3.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.15.name=TriggerPort4[15] -unit.1.3.port.4.s.15.orderindex=-1 -unit.1.3.port.4.s.15.visible=1 -unit.1.3.port.4.s.16.alias= -unit.1.3.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.16.name=TriggerPort4[16] -unit.1.3.port.4.s.16.orderindex=-1 -unit.1.3.port.4.s.16.visible=1 -unit.1.3.port.4.s.17.alias= -unit.1.3.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.17.name=TriggerPort4[17] -unit.1.3.port.4.s.17.orderindex=-1 -unit.1.3.port.4.s.17.visible=1 -unit.1.3.port.4.s.18.alias= -unit.1.3.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.18.name=TriggerPort4[18] -unit.1.3.port.4.s.18.orderindex=-1 -unit.1.3.port.4.s.18.visible=1 -unit.1.3.port.4.s.19.alias= -unit.1.3.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.19.name=TriggerPort4[19] -unit.1.3.port.4.s.19.orderindex=-1 -unit.1.3.port.4.s.19.visible=1 -unit.1.3.port.4.s.2.alias= -unit.1.3.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.2.name=TriggerPort4[2] -unit.1.3.port.4.s.2.orderindex=-1 -unit.1.3.port.4.s.2.visible=1 -unit.1.3.port.4.s.20.alias= -unit.1.3.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.20.name=TriggerPort4[20] -unit.1.3.port.4.s.20.orderindex=-1 -unit.1.3.port.4.s.20.visible=1 -unit.1.3.port.4.s.21.alias= -unit.1.3.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.21.name=TriggerPort4[21] -unit.1.3.port.4.s.21.orderindex=-1 -unit.1.3.port.4.s.21.visible=1 -unit.1.3.port.4.s.22.alias= -unit.1.3.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.22.name=TriggerPort4[22] -unit.1.3.port.4.s.22.orderindex=-1 -unit.1.3.port.4.s.22.visible=1 -unit.1.3.port.4.s.23.alias= -unit.1.3.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.23.name=TriggerPort4[23] -unit.1.3.port.4.s.23.orderindex=-1 -unit.1.3.port.4.s.23.visible=1 -unit.1.3.port.4.s.24.alias= -unit.1.3.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.24.name=TriggerPort4[24] -unit.1.3.port.4.s.24.orderindex=-1 -unit.1.3.port.4.s.24.visible=1 -unit.1.3.port.4.s.25.alias= -unit.1.3.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.25.name=TriggerPort4[25] -unit.1.3.port.4.s.25.orderindex=-1 -unit.1.3.port.4.s.25.visible=1 -unit.1.3.port.4.s.26.alias= -unit.1.3.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.26.name=TriggerPort4[26] -unit.1.3.port.4.s.26.orderindex=-1 -unit.1.3.port.4.s.26.visible=1 -unit.1.3.port.4.s.27.alias= -unit.1.3.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.27.name=TriggerPort4[27] -unit.1.3.port.4.s.27.orderindex=-1 -unit.1.3.port.4.s.27.visible=1 -unit.1.3.port.4.s.28.alias= -unit.1.3.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.28.name=TriggerPort4[28] -unit.1.3.port.4.s.28.orderindex=-1 -unit.1.3.port.4.s.28.visible=1 -unit.1.3.port.4.s.29.alias= -unit.1.3.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.29.name=TriggerPort4[29] -unit.1.3.port.4.s.29.orderindex=-1 -unit.1.3.port.4.s.29.visible=1 -unit.1.3.port.4.s.3.alias= -unit.1.3.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.3.name=TriggerPort4[3] -unit.1.3.port.4.s.3.orderindex=-1 -unit.1.3.port.4.s.3.visible=1 -unit.1.3.port.4.s.30.alias= -unit.1.3.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.30.name=TriggerPort4[30] -unit.1.3.port.4.s.30.orderindex=-1 -unit.1.3.port.4.s.30.visible=1 -unit.1.3.port.4.s.31.alias= -unit.1.3.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.31.name=TriggerPort4[31] -unit.1.3.port.4.s.31.orderindex=-1 -unit.1.3.port.4.s.31.visible=1 -unit.1.3.port.4.s.4.alias= -unit.1.3.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.4.name=TriggerPort4[4] -unit.1.3.port.4.s.4.orderindex=-1 -unit.1.3.port.4.s.4.visible=1 -unit.1.3.port.4.s.5.alias= -unit.1.3.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.4.s.5.name=TriggerPort4[5] -unit.1.3.port.4.s.5.orderindex=-1 -unit.1.3.port.4.s.5.visible=1 -unit.1.3.port.4.s.6.alias= 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-unit.1.4.port.-1.s.82.alias= -unit.1.4.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.82.name=DataPort[82] -unit.1.4.port.-1.s.82.orderindex=-1 -unit.1.4.port.-1.s.82.visible=0 -unit.1.4.port.-1.s.83.alias= -unit.1.4.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.83.name=DataPort[83] -unit.1.4.port.-1.s.83.orderindex=-1 -unit.1.4.port.-1.s.83.visible=0 -unit.1.4.port.-1.s.84.alias= -unit.1.4.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.84.name=DataPort[84] -unit.1.4.port.-1.s.84.orderindex=-1 -unit.1.4.port.-1.s.84.visible=0 -unit.1.4.port.-1.s.85.alias= -unit.1.4.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.85.name=DataPort[85] -unit.1.4.port.-1.s.85.orderindex=-1 -unit.1.4.port.-1.s.85.visible=0 -unit.1.4.port.-1.s.86.alias= -unit.1.4.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.86.name=DataPort[86] -unit.1.4.port.-1.s.86.orderindex=-1 -unit.1.4.port.-1.s.86.visible=0 -unit.1.4.port.-1.s.87.alias= -unit.1.4.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.87.name=DataPort[87] -unit.1.4.port.-1.s.87.orderindex=-1 -unit.1.4.port.-1.s.87.visible=0 -unit.1.4.port.-1.s.88.alias= -unit.1.4.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.88.name=DataPort[88] -unit.1.4.port.-1.s.88.orderindex=-1 -unit.1.4.port.-1.s.88.visible=0 -unit.1.4.port.-1.s.89.alias= -unit.1.4.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.89.name=DataPort[89] -unit.1.4.port.-1.s.89.orderindex=-1 -unit.1.4.port.-1.s.89.visible=0 -unit.1.4.port.-1.s.9.alias= -unit.1.4.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.9.name=DataPort[9] -unit.1.4.port.-1.s.9.orderindex=-1 -unit.1.4.port.-1.s.9.visible=0 -unit.1.4.port.-1.s.90.alias= -unit.1.4.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.90.name=DataPort[90] -unit.1.4.port.-1.s.90.orderindex=-1 -unit.1.4.port.-1.s.90.visible=0 -unit.1.4.port.-1.s.91.alias= -unit.1.4.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.91.name=DataPort[91] -unit.1.4.port.-1.s.91.orderindex=-1 -unit.1.4.port.-1.s.91.visible=0 -unit.1.4.port.-1.s.92.alias= -unit.1.4.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.92.name=DataPort[92] -unit.1.4.port.-1.s.92.orderindex=-1 -unit.1.4.port.-1.s.92.visible=0 -unit.1.4.port.-1.s.93.alias= -unit.1.4.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.93.name=DataPort[93] -unit.1.4.port.-1.s.93.orderindex=-1 -unit.1.4.port.-1.s.93.visible=0 -unit.1.4.port.-1.s.94.alias= -unit.1.4.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.94.name=DataPort[94] -unit.1.4.port.-1.s.94.orderindex=-1 -unit.1.4.port.-1.s.94.visible=0 -unit.1.4.port.-1.s.95.alias= -unit.1.4.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.95.name=DataPort[95] -unit.1.4.port.-1.s.95.orderindex=-1 -unit.1.4.port.-1.s.95.visible=0 -unit.1.4.port.-1.s.96.alias= -unit.1.4.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.96.name=DataPort[96] -unit.1.4.port.-1.s.96.orderindex=-1 -unit.1.4.port.-1.s.96.visible=0 -unit.1.4.port.-1.s.97.alias= -unit.1.4.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.97.name=DataPort[97] -unit.1.4.port.-1.s.97.orderindex=-1 -unit.1.4.port.-1.s.97.visible=1 -unit.1.4.port.-1.s.98.alias= -unit.1.4.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.98.name=DataPort[98] -unit.1.4.port.-1.s.98.orderindex=-1 -unit.1.4.port.-1.s.98.visible=1 -unit.1.4.port.-1.s.99.alias= -unit.1.4.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.99.name=DataPort[99] -unit.1.4.port.-1.s.99.orderindex=-1 -unit.1.4.port.-1.s.99.visible=1 -unit.1.4.port.0.b.0.alias= -unit.1.4.port.0.b.0.channellist=0 1 2 3 4 5 6 7 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-unit.1.4.port.0.s.2.name=TriggerPort0[2] -unit.1.4.port.0.s.2.orderindex=-1 -unit.1.4.port.0.s.2.visible=1 -unit.1.4.port.0.s.3.alias= -unit.1.4.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.3.name=TriggerPort0[3] -unit.1.4.port.0.s.3.orderindex=-1 -unit.1.4.port.0.s.3.visible=1 -unit.1.4.port.0.s.4.alias= -unit.1.4.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.4.name=TriggerPort0[4] -unit.1.4.port.0.s.4.orderindex=-1 -unit.1.4.port.0.s.4.visible=1 -unit.1.4.port.0.s.5.alias= -unit.1.4.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.5.name=TriggerPort0[5] -unit.1.4.port.0.s.5.orderindex=-1 -unit.1.4.port.0.s.5.visible=1 -unit.1.4.port.0.s.6.alias= -unit.1.4.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.6.name=TriggerPort0[6] -unit.1.4.port.0.s.6.orderindex=-1 -unit.1.4.port.0.s.6.visible=1 -unit.1.4.port.0.s.7.alias= -unit.1.4.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.7.name=TriggerPort0[7] -unit.1.4.port.0.s.7.orderindex=-1 -unit.1.4.port.0.s.7.visible=1 -unit.1.4.port.1.b.0.alias= -unit.1.4.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex -unit.1.4.port.1.b.0.signedOffset=0.0 -unit.1.4.port.1.b.0.signedPrecision=0 -unit.1.4.port.1.b.0.signedScaleFactor=1.0 -unit.1.4.port.1.b.0.unsignedOffset=0.0 -unit.1.4.port.1.b.0.unsignedPrecision=0 -unit.1.4.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.1.b.0.visible=1 -unit.1.4.port.1.buscount=1 -unit.1.4.port.1.channelcount=32 -unit.1.4.port.1.s.0.alias= -unit.1.4.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.0.name=TriggerPort1[0] -unit.1.4.port.1.s.0.orderindex=-1 -unit.1.4.port.1.s.0.visible=1 -unit.1.4.port.1.s.1.alias= -unit.1.4.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.1.name=TriggerPort1[1] -unit.1.4.port.1.s.1.orderindex=-1 -unit.1.4.port.1.s.1.visible=1 -unit.1.4.port.1.s.10.alias= -unit.1.4.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.10.name=TriggerPort1[10] -unit.1.4.port.1.s.10.orderindex=-1 -unit.1.4.port.1.s.10.visible=1 -unit.1.4.port.1.s.11.alias= -unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 -unit.1.4.port.1.s.16.alias= -unit.1.4.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.16.name=TriggerPort1[16] -unit.1.4.port.1.s.16.orderindex=-1 -unit.1.4.port.1.s.16.visible=1 -unit.1.4.port.1.s.17.alias= -unit.1.4.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.17.name=TriggerPort1[17] -unit.1.4.port.1.s.17.orderindex=-1 -unit.1.4.port.1.s.17.visible=1 -unit.1.4.port.1.s.18.alias= -unit.1.4.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.18.name=TriggerPort1[18] -unit.1.4.port.1.s.18.orderindex=-1 -unit.1.4.port.1.s.18.visible=1 -unit.1.4.port.1.s.19.alias= -unit.1.4.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.19.name=TriggerPort1[19] -unit.1.4.port.1.s.19.orderindex=-1 -unit.1.4.port.1.s.19.visible=1 -unit.1.4.port.1.s.2.alias= -unit.1.4.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.2.name=TriggerPort1[2] -unit.1.4.port.1.s.2.orderindex=-1 -unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.18.name=TriggerPort3[18] -unit.1.4.port.3.s.18.orderindex=-1 -unit.1.4.port.3.s.18.visible=1 -unit.1.4.port.3.s.19.alias= -unit.1.4.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.19.name=TriggerPort3[19] -unit.1.4.port.3.s.19.orderindex=-1 -unit.1.4.port.3.s.19.visible=1 -unit.1.4.port.3.s.2.alias= -unit.1.4.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.2.name=TriggerPort3[2] -unit.1.4.port.3.s.2.orderindex=-1 -unit.1.4.port.3.s.2.visible=1 -unit.1.4.port.3.s.20.alias= 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-unit.1.4.waveform.posn.39.type=bus -unit.1.4.waveform.posn.4.channel=4 -unit.1.4.waveform.posn.4.name=DataPort[4] -unit.1.4.waveform.posn.4.type=signal -unit.1.4.waveform.posn.5.channel=5 -unit.1.4.waveform.posn.5.name=DataPort[5] -unit.1.4.waveform.posn.5.type=signal -unit.1.4.waveform.posn.6.channel=6 -unit.1.4.waveform.posn.6.name=DataPort[6] -unit.1.4.waveform.posn.6.type=signal -unit.1.4.waveform.posn.7.channel=7 -unit.1.4.waveform.posn.7.name=DataPort[7] -unit.1.4.waveform.posn.7.type=signal -unit.1.4.waveform.posn.8.channel=33 -unit.1.4.waveform.posn.8.name=DataPort[33] -unit.1.4.waveform.posn.8.type=signal -unit.1.4.waveform.posn.9.channel=34 -unit.1.4.waveform.posn.9.name=DataPort[34] -unit.1.4.waveform.posn.9.type=signal -unit.1.5.0.HEIGHT0=0.37337664 -unit.1.5.0.TriggerRow0=1 -unit.1.5.0.TriggerRow1=1 -unit.1.5.0.TriggerRow2=1 -unit.1.5.0.WIDTH0=0.6727405 -unit.1.5.0.X0=0.034985423 -unit.1.5.0.Y0=0.0 -unit.1.5.1.HEIGHT1=0.77922076 -unit.1.5.1.WIDTH1=0.6202624 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-unit.1.5.port.0.s.4.alias= -unit.1.5.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.4.name=TriggerPort0[4] -unit.1.5.port.0.s.4.orderindex=-1 -unit.1.5.port.0.s.4.visible=1 -unit.1.5.port.0.s.5.alias= -unit.1.5.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.5.name=TriggerPort0[5] -unit.1.5.port.0.s.5.orderindex=-1 -unit.1.5.port.0.s.5.visible=1 -unit.1.5.port.0.s.6.alias= -unit.1.5.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.6.name=TriggerPort0[6] -unit.1.5.port.0.s.6.orderindex=-1 -unit.1.5.port.0.s.6.visible=1 -unit.1.5.port.0.s.7.alias= -unit.1.5.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.7.name=TriggerPort0[7] -unit.1.5.port.0.s.7.orderindex=-1 -unit.1.5.port.0.s.7.visible=1 -unit.1.5.port.1.b.0.alias= -unit.1.5.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.b.0.name=TriggerPort1 -unit.1.5.port.1.b.0.orderindex=-1 -unit.1.5.port.1.b.0.radix=Hex -unit.1.5.port.1.b.0.signedOffset=0.0 -unit.1.5.port.1.b.0.signedPrecision=0 -unit.1.5.port.1.b.0.signedScaleFactor=1.0 -unit.1.5.port.1.b.0.unsignedOffset=0.0 -unit.1.5.port.1.b.0.unsignedPrecision=0 -unit.1.5.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.1.b.0.visible=1 -unit.1.5.port.1.buscount=1 -unit.1.5.port.1.channelcount=32 -unit.1.5.port.1.s.0.alias= -unit.1.5.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.0.name=TriggerPort1[0] -unit.1.5.port.1.s.0.orderindex=-1 -unit.1.5.port.1.s.0.visible=1 -unit.1.5.port.1.s.1.alias= -unit.1.5.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.1.name=TriggerPort1[1] -unit.1.5.port.1.s.1.orderindex=-1 -unit.1.5.port.1.s.1.visible=1 -unit.1.5.port.1.s.10.alias= -unit.1.5.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.10.name=TriggerPort1[10] -unit.1.5.port.1.s.10.orderindex=-1 -unit.1.5.port.1.s.10.visible=1 -unit.1.5.port.1.s.11.alias= -unit.1.5.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.11.name=TriggerPort1[11] -unit.1.5.port.1.s.11.orderindex=-1 -unit.1.5.port.1.s.11.visible=1 -unit.1.5.port.1.s.12.alias= -unit.1.5.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.12.name=TriggerPort1[12] -unit.1.5.port.1.s.12.orderindex=-1 -unit.1.5.port.1.s.12.visible=1 -unit.1.5.port.1.s.13.alias= -unit.1.5.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.13.name=TriggerPort1[13] -unit.1.5.port.1.s.13.orderindex=-1 -unit.1.5.port.1.s.13.visible=1 -unit.1.5.port.1.s.14.alias= -unit.1.5.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.14.name=TriggerPort1[14] -unit.1.5.port.1.s.14.orderindex=-1 -unit.1.5.port.1.s.14.visible=1 -unit.1.5.port.1.s.15.alias= -unit.1.5.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.15.name=TriggerPort1[15] -unit.1.5.port.1.s.15.orderindex=-1 -unit.1.5.port.1.s.15.visible=1 -unit.1.5.port.1.s.16.alias= -unit.1.5.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.16.name=TriggerPort1[16] -unit.1.5.port.1.s.16.orderindex=-1 -unit.1.5.port.1.s.16.visible=1 -unit.1.5.port.1.s.17.alias= -unit.1.5.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.17.name=TriggerPort1[17] -unit.1.5.port.1.s.17.orderindex=-1 -unit.1.5.port.1.s.17.visible=1 -unit.1.5.port.1.s.18.alias= -unit.1.5.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.18.name=TriggerPort1[18] -unit.1.5.port.1.s.18.orderindex=-1 -unit.1.5.port.1.s.18.visible=1 -unit.1.5.port.1.s.19.alias= -unit.1.5.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.19.name=TriggerPort1[19] -unit.1.5.port.1.s.19.orderindex=-1 -unit.1.5.port.1.s.19.visible=1 -unit.1.5.port.1.s.2.alias= -unit.1.5.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.2.name=TriggerPort1[2] -unit.1.5.port.1.s.2.orderindex=-1 -unit.1.5.port.1.s.2.visible=1 -unit.1.5.port.1.s.20.alias= -unit.1.5.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.20.name=TriggerPort1[20] -unit.1.5.port.1.s.20.orderindex=-1 -unit.1.5.port.1.s.20.visible=1 -unit.1.5.port.1.s.21.alias= -unit.1.5.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.21.name=TriggerPort1[21] -unit.1.5.port.1.s.21.orderindex=-1 -unit.1.5.port.1.s.21.visible=1 -unit.1.5.port.1.s.22.alias= -unit.1.5.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.22.name=TriggerPort1[22] -unit.1.5.port.1.s.22.orderindex=-1 -unit.1.5.port.1.s.22.visible=1 -unit.1.5.port.1.s.23.alias= -unit.1.5.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.23.name=TriggerPort1[23] -unit.1.5.port.1.s.23.orderindex=-1 -unit.1.5.port.1.s.23.visible=1 -unit.1.5.port.1.s.24.alias= -unit.1.5.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.24.name=TriggerPort1[24] -unit.1.5.port.1.s.24.orderindex=-1 -unit.1.5.port.1.s.24.visible=1 -unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 -unit.1.5.port.3.s.16.alias= -unit.1.5.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.16.name=TriggerPort3[16] -unit.1.5.port.3.s.16.orderindex=-1 -unit.1.5.port.3.s.16.visible=1 -unit.1.5.port.3.s.17.alias= -unit.1.5.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.17.name=TriggerPort3[17] -unit.1.5.port.3.s.17.orderindex=-1 -unit.1.5.port.3.s.17.visible=1 -unit.1.5.port.3.s.18.alias= -unit.1.5.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.18.name=TriggerPort3[18] -unit.1.5.port.3.s.18.orderindex=-1 -unit.1.5.port.3.s.18.visible=1 -unit.1.5.port.3.s.19.alias= -unit.1.5.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.19.name=TriggerPort3[19] -unit.1.5.port.3.s.19.orderindex=-1 -unit.1.5.port.3.s.19.visible=1 -unit.1.5.port.3.s.2.alias= -unit.1.5.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.2.name=TriggerPort3[2] -unit.1.5.port.3.s.2.orderindex=-1 -unit.1.5.port.3.s.2.visible=1 -unit.1.5.port.3.s.20.alias= -unit.1.5.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.20.name=TriggerPort3[20] -unit.1.5.port.3.s.20.orderindex=-1 -unit.1.5.port.3.s.20.visible=1 -unit.1.5.port.3.s.21.alias= -unit.1.5.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.21.name=TriggerPort3[21] -unit.1.5.port.3.s.21.orderindex=-1 -unit.1.5.port.3.s.21.visible=1 -unit.1.5.port.3.s.22.alias= -unit.1.5.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.22.name=TriggerPort3[22] -unit.1.5.port.3.s.22.orderindex=-1 -unit.1.5.port.3.s.22.visible=1 -unit.1.5.port.3.s.23.alias= -unit.1.5.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.23.name=TriggerPort3[23] -unit.1.5.port.3.s.23.orderindex=-1 -unit.1.5.port.3.s.23.visible=1 -unit.1.5.port.3.s.24.alias= -unit.1.5.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.24.name=TriggerPort3[24] -unit.1.5.port.3.s.24.orderindex=-1 -unit.1.5.port.3.s.24.visible=1 -unit.1.5.port.3.s.25.alias= -unit.1.5.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.25.name=TriggerPort3[25] -unit.1.5.port.3.s.25.orderindex=-1 -unit.1.5.port.3.s.25.visible=1 -unit.1.5.port.3.s.26.alias= -unit.1.5.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.26.name=TriggerPort3[26] -unit.1.5.port.3.s.26.orderindex=-1 -unit.1.5.port.3.s.26.visible=1 -unit.1.5.port.3.s.27.alias= -unit.1.5.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.27.name=TriggerPort3[27] -unit.1.5.port.3.s.27.orderindex=-1 -unit.1.5.port.3.s.27.visible=1 -unit.1.5.port.3.s.28.alias= -unit.1.5.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.28.name=TriggerPort3[28] -unit.1.5.port.3.s.28.orderindex=-1 -unit.1.5.port.3.s.28.visible=1 -unit.1.5.port.3.s.29.alias= -unit.1.5.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.29.name=TriggerPort3[29] -unit.1.5.port.3.s.29.orderindex=-1 -unit.1.5.port.3.s.29.visible=1 -unit.1.5.port.3.s.3.alias= -unit.1.5.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.3.name=TriggerPort3[3] -unit.1.5.port.3.s.3.orderindex=-1 -unit.1.5.port.3.s.3.visible=1 -unit.1.5.port.3.s.30.alias= -unit.1.5.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.30.name=TriggerPort3[30] -unit.1.5.port.3.s.30.orderindex=-1 -unit.1.5.port.3.s.30.visible=1 -unit.1.5.port.3.s.31.alias= -unit.1.5.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.31.name=TriggerPort3[31] -unit.1.5.port.3.s.31.orderindex=-1 -unit.1.5.port.3.s.31.visible=1 -unit.1.5.port.3.s.4.alias= -unit.1.5.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.4.name=TriggerPort3[4] -unit.1.5.port.3.s.4.orderindex=-1 -unit.1.5.port.3.s.4.visible=1 -unit.1.5.port.3.s.5.alias= -unit.1.5.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.5.name=TriggerPort3[5] -unit.1.5.port.3.s.5.orderindex=-1 -unit.1.5.port.3.s.5.visible=1 -unit.1.5.port.3.s.6.alias= -unit.1.5.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.6.name=TriggerPort3[6] -unit.1.5.port.3.s.6.orderindex=-1 -unit.1.5.port.3.s.6.visible=1 -unit.1.5.port.3.s.7.alias= -unit.1.5.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.7.name=TriggerPort3[7] -unit.1.5.port.3.s.7.orderindex=-1 -unit.1.5.port.3.s.7.visible=1 -unit.1.5.port.3.s.8.alias= -unit.1.5.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.8.name=TriggerPort3[8] -unit.1.5.port.3.s.8.orderindex=-1 -unit.1.5.port.3.s.8.visible=1 -unit.1.5.port.3.s.9.alias= -unit.1.5.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.9.name=TriggerPort3[9] -unit.1.5.port.3.s.9.orderindex=-1 -unit.1.5.port.3.s.9.visible=1 -unit.1.5.port.4.b.0.alias= -unit.1.5.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.b.0.name=TriggerPort4 -unit.1.5.port.4.b.0.orderindex=-1 -unit.1.5.port.4.b.0.radix=Hex -unit.1.5.port.4.b.0.signedOffset=0.0 -unit.1.5.port.4.b.0.signedPrecision=0 -unit.1.5.port.4.b.0.signedScaleFactor=1.0 -unit.1.5.port.4.b.0.unsignedOffset=0.0 -unit.1.5.port.4.b.0.unsignedPrecision=0 -unit.1.5.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.4.b.0.visible=1 -unit.1.5.port.4.buscount=1 -unit.1.5.port.4.channelcount=32 -unit.1.5.port.4.s.0.alias= -unit.1.5.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.0.name=TriggerPort4[0] -unit.1.5.port.4.s.0.orderindex=-1 -unit.1.5.port.4.s.0.visible=1 -unit.1.5.port.4.s.1.alias= -unit.1.5.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.1.name=TriggerPort4[1] -unit.1.5.port.4.s.1.orderindex=-1 -unit.1.5.port.4.s.1.visible=1 -unit.1.5.port.4.s.10.alias= -unit.1.5.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.10.name=TriggerPort4[10] -unit.1.5.port.4.s.10.orderindex=-1 -unit.1.5.port.4.s.10.visible=1 -unit.1.5.port.4.s.11.alias= -unit.1.5.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.11.name=TriggerPort4[11] -unit.1.5.port.4.s.11.orderindex=-1 -unit.1.5.port.4.s.11.visible=1 -unit.1.5.port.4.s.12.alias= -unit.1.5.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.12.name=TriggerPort4[12] -unit.1.5.port.4.s.12.orderindex=-1 -unit.1.5.port.4.s.12.visible=1 -unit.1.5.port.4.s.13.alias= -unit.1.5.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.13.name=TriggerPort4[13] -unit.1.5.port.4.s.13.orderindex=-1 -unit.1.5.port.4.s.13.visible=1 -unit.1.5.port.4.s.14.alias= -unit.1.5.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.14.name=TriggerPort4[14] -unit.1.5.port.4.s.14.orderindex=-1 -unit.1.5.port.4.s.14.visible=1 -unit.1.5.port.4.s.15.alias= -unit.1.5.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.15.name=TriggerPort4[15] -unit.1.5.port.4.s.15.orderindex=-1 -unit.1.5.port.4.s.15.visible=1 -unit.1.5.port.4.s.16.alias= -unit.1.5.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.16.name=TriggerPort4[16] -unit.1.5.port.4.s.16.orderindex=-1 -unit.1.5.port.4.s.16.visible=1 -unit.1.5.port.4.s.17.alias= -unit.1.5.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.17.name=TriggerPort4[17] -unit.1.5.port.4.s.17.orderindex=-1 -unit.1.5.port.4.s.17.visible=1 -unit.1.5.port.4.s.18.alias= -unit.1.5.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.18.name=TriggerPort4[18] -unit.1.5.port.4.s.18.orderindex=-1 -unit.1.5.port.4.s.18.visible=1 -unit.1.5.port.4.s.19.alias= -unit.1.5.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.19.name=TriggerPort4[19] -unit.1.5.port.4.s.19.orderindex=-1 -unit.1.5.port.4.s.19.visible=1 -unit.1.5.port.4.s.2.alias= -unit.1.5.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.2.name=TriggerPort4[2] -unit.1.5.port.4.s.2.orderindex=-1 -unit.1.5.port.4.s.2.visible=1 -unit.1.5.port.4.s.20.alias= -unit.1.5.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.20.name=TriggerPort4[20] -unit.1.5.port.4.s.20.orderindex=-1 -unit.1.5.port.4.s.20.visible=1 -unit.1.5.port.4.s.21.alias= -unit.1.5.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.21.name=TriggerPort4[21] -unit.1.5.port.4.s.21.orderindex=-1 -unit.1.5.port.4.s.21.visible=1 -unit.1.5.port.4.s.22.alias= -unit.1.5.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.22.name=TriggerPort4[22] -unit.1.5.port.4.s.22.orderindex=-1 -unit.1.5.port.4.s.22.visible=1 -unit.1.5.port.4.s.23.alias= -unit.1.5.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.23.name=TriggerPort4[23] -unit.1.5.port.4.s.23.orderindex=-1 -unit.1.5.port.4.s.23.visible=1 -unit.1.5.port.4.s.24.alias= -unit.1.5.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.24.name=TriggerPort4[24] -unit.1.5.port.4.s.24.orderindex=-1 -unit.1.5.port.4.s.24.visible=1 -unit.1.5.port.4.s.25.alias= -unit.1.5.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.25.name=TriggerPort4[25] -unit.1.5.port.4.s.25.orderindex=-1 -unit.1.5.port.4.s.25.visible=1 -unit.1.5.port.4.s.26.alias= -unit.1.5.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.26.name=TriggerPort4[26] -unit.1.5.port.4.s.26.orderindex=-1 -unit.1.5.port.4.s.26.visible=1 -unit.1.5.port.4.s.27.alias= -unit.1.5.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.27.name=TriggerPort4[27] -unit.1.5.port.4.s.27.orderindex=-1 -unit.1.5.port.4.s.27.visible=1 -unit.1.5.port.4.s.28.alias= -unit.1.5.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.28.name=TriggerPort4[28] -unit.1.5.port.4.s.28.orderindex=-1 -unit.1.5.port.4.s.28.visible=1 -unit.1.5.port.4.s.29.alias= -unit.1.5.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.29.name=TriggerPort4[29] -unit.1.5.port.4.s.29.orderindex=-1 -unit.1.5.port.4.s.29.visible=1 -unit.1.5.port.4.s.3.alias= -unit.1.5.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.3.name=TriggerPort4[3] -unit.1.5.port.4.s.3.orderindex=-1 -unit.1.5.port.4.s.3.visible=1 -unit.1.5.port.4.s.30.alias= -unit.1.5.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.30.name=TriggerPort4[30] -unit.1.5.port.4.s.30.orderindex=-1 -unit.1.5.port.4.s.30.visible=1 -unit.1.5.port.4.s.31.alias= -unit.1.5.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.31.name=TriggerPort4[31] -unit.1.5.port.4.s.31.orderindex=-1 -unit.1.5.port.4.s.31.visible=1 -unit.1.5.port.4.s.4.alias= -unit.1.5.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.4.name=TriggerPort4[4] -unit.1.5.port.4.s.4.orderindex=-1 -unit.1.5.port.4.s.4.visible=1 -unit.1.5.port.4.s.5.alias= -unit.1.5.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.5.name=TriggerPort4[5] -unit.1.5.port.4.s.5.orderindex=-1 -unit.1.5.port.4.s.5.visible=1 -unit.1.5.port.4.s.6.alias= -unit.1.5.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.6.name=TriggerPort4[6] -unit.1.5.port.4.s.6.orderindex=-1 -unit.1.5.port.4.s.6.visible=1 -unit.1.5.port.4.s.7.alias= -unit.1.5.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.7.name=TriggerPort4[7] -unit.1.5.port.4.s.7.orderindex=-1 -unit.1.5.port.4.s.7.visible=1 -unit.1.5.port.4.s.8.alias= -unit.1.5.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.8.name=TriggerPort4[8] -unit.1.5.port.4.s.8.orderindex=-1 -unit.1.5.port.4.s.8.visible=1 -unit.1.5.port.4.s.9.alias= -unit.1.5.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.4.s.9.name=TriggerPort4[9] -unit.1.5.port.4.s.9.orderindex=-1 -unit.1.5.port.4.s.9.visible=1 -unit.1.5.portcount=5 -unit.1.5.rep_trigger.clobber=1 -unit.1.5.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp -unit.1.5.rep_trigger.filename=waveform -unit.1.5.rep_trigger.format=ASCII -unit.1.5.rep_trigger.loggingEnabled=0 -unit.1.5.rep_trigger.signals=All Signals/Buses -unit.1.5.samplesPerTrigger=1 -unit.1.5.triggerCapture=1 -unit.1.5.triggerNSamplesTS=0 -unit.1.5.triggerPosition=0 -unit.1.5.triggerWindowCount=1 -unit.1.5.triggerWindowDepth=4096 -unit.1.5.triggerWindowTS=0 -unit.1.5.username=MyILA5 -unit.1.5.waveform.count=42 -unit.1.5.waveform.posn.0.channel=0 -unit.1.5.waveform.posn.0.name=DataPort[0] -unit.1.5.waveform.posn.0.type=signal -unit.1.5.waveform.posn.1.channel=1 -unit.1.5.waveform.posn.1.name=DataPort[1] -unit.1.5.waveform.posn.1.type=signal -unit.1.5.waveform.posn.10.channel=34 -unit.1.5.waveform.posn.10.name=DataPort[34] -unit.1.5.waveform.posn.10.type=signal -unit.1.5.waveform.posn.11.channel=35 -unit.1.5.waveform.posn.11.name=DataPort[35] -unit.1.5.waveform.posn.11.type=signal -unit.1.5.waveform.posn.12.channel=36 -unit.1.5.waveform.posn.12.name=DataPort[36] -unit.1.5.waveform.posn.12.type=signal -unit.1.5.waveform.posn.13.channel=37 -unit.1.5.waveform.posn.13.name=DataPort[37] -unit.1.5.waveform.posn.13.type=signal -unit.1.5.waveform.posn.14.channel=38 -unit.1.5.waveform.posn.14.name=DataPort[38] -unit.1.5.waveform.posn.14.type=signal -unit.1.5.waveform.posn.15.channel=39 -unit.1.5.waveform.posn.15.name=DataPort[39] -unit.1.5.waveform.posn.15.type=signal -unit.1.5.waveform.posn.16.channel=64 -unit.1.5.waveform.posn.16.name=DataPort[64] -unit.1.5.waveform.posn.16.type=signal -unit.1.5.waveform.posn.17.channel=65 -unit.1.5.waveform.posn.17.name=DataPort[65] -unit.1.5.waveform.posn.17.type=signal -unit.1.5.waveform.posn.18.channel=66 -unit.1.5.waveform.posn.18.name=DataPort[66] -unit.1.5.waveform.posn.18.type=signal -unit.1.5.waveform.posn.19.channel=67 -unit.1.5.waveform.posn.19.name=DataPort[67] -unit.1.5.waveform.posn.19.type=signal -unit.1.5.waveform.posn.2.channel=2 -unit.1.5.waveform.posn.2.name=DataPort[2] -unit.1.5.waveform.posn.2.type=signal -unit.1.5.waveform.posn.20.channel=68 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-unit.1.5.waveform.posn.41.name=dsp_y_fofb -unit.1.5.waveform.posn.41.radix=3 -unit.1.5.waveform.posn.41.type=bus -unit.1.5.waveform.posn.42.channel=2147483646 -unit.1.5.waveform.posn.42.name=dsp_y_fofb -unit.1.5.waveform.posn.42.radix=3 -unit.1.5.waveform.posn.42.type=bus -unit.1.5.waveform.posn.43.channel=2147483646 -unit.1.5.waveform.posn.43.name=dsp_y_fofb -unit.1.5.waveform.posn.43.radix=3 -unit.1.5.waveform.posn.43.type=bus -unit.1.5.waveform.posn.44.channel=2147483646 -unit.1.5.waveform.posn.44.name=dsp_y_fofb -unit.1.5.waveform.posn.44.radix=3 -unit.1.5.waveform.posn.44.type=bus -unit.1.5.waveform.posn.45.channel=2147483646 -unit.1.5.waveform.posn.45.name=dsp_y_fofb -unit.1.5.waveform.posn.45.radix=3 -unit.1.5.waveform.posn.45.type=bus -unit.1.5.waveform.posn.46.channel=2147483646 -unit.1.5.waveform.posn.46.name=dsp_y_fofb -unit.1.5.waveform.posn.46.radix=3 -unit.1.5.waveform.posn.46.type=bus -unit.1.5.waveform.posn.5.channel=5 -unit.1.5.waveform.posn.5.name=DataPort[5] -unit.1.5.waveform.posn.5.type=signal -unit.1.5.waveform.posn.6.channel=6 -unit.1.5.waveform.posn.6.name=DataPort[6] -unit.1.5.waveform.posn.6.type=signal -unit.1.5.waveform.posn.7.channel=7 -unit.1.5.waveform.posn.7.name=DataPort[7] -unit.1.5.waveform.posn.7.type=signal -unit.1.5.waveform.posn.8.channel=32 -unit.1.5.waveform.posn.8.name=DataPort[32] -unit.1.5.waveform.posn.8.type=signal -unit.1.5.waveform.posn.9.channel=33 -unit.1.5.waveform.posn.9.name=DataPort[33] -unit.1.5.waveform.posn.9.type=signal -unit.1.6.0.HEIGHT0=0.37337664 -unit.1.6.0.TriggerRow0=1 -unit.1.6.0.TriggerRow1=1 -unit.1.6.0.TriggerRow2=1 -unit.1.6.0.WIDTH0=0.6377551 -unit.1.6.0.X0=0.069970846 -unit.1.6.0.Y0=0.0 -unit.1.6.1.HEIGHT1=0.77922076 -unit.1.6.1.WIDTH1=0.58527696 -unit.1.6.1.X1=0.02478134 -unit.1.6.1.Y1=0.06818182 -unit.1.6.5.HEIGHT5=0.77922076 -unit.1.6.5.WIDTH5=0.85495627 -unit.1.6.5.X5=0.07653061 -unit.1.6.5.Y5=0.03733766 -unit.1.6.MFBitsA0=XXXXX1XX -unit.1.6.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsA4=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.6.MFBitsB0=00000000 -unit.1.6.MFBitsB1=00000000000000000000000000000000 -unit.1.6.MFBitsB2=00000000000000000000000000000000 -unit.1.6.MFBitsB3=00000000000000000000000000000000 -unit.1.6.MFBitsB4=00000000000000000000000000000000 -unit.1.6.MFCompareA0=0 -unit.1.6.MFCompareA1=0 -unit.1.6.MFCompareA2=0 -unit.1.6.MFCompareA3=0 -unit.1.6.MFCompareA4=0 -unit.1.6.MFCompareB0=999 -unit.1.6.MFCompareB1=999 -unit.1.6.MFCompareB2=999 -unit.1.6.MFCompareB3=999 -unit.1.6.MFCompareB4=999 -unit.1.6.MFCount=5 -unit.1.6.MFDisplay0=0 -unit.1.6.MFDisplay1=0 -unit.1.6.MFDisplay2=0 -unit.1.6.MFDisplay3=0 -unit.1.6.MFDisplay4=0 -unit.1.6.MFEventType0=3 -unit.1.6.MFEventType1=3 -unit.1.6.MFEventType2=3 -unit.1.6.MFEventType3=3 -unit.1.6.MFEventType4=3 -unit.1.6.RunMode=SINGLE RUN -unit.1.6.SQCondition=M0 -unit.1.6.SQContiguous0=0 -unit.1.6.SequencerOn=0 -unit.1.6.TCActive=0 -unit.1.6.TCAdvanced0=0 -unit.1.6.TCCondition0_0=M0 -unit.1.6.TCCondition0_1= -unit.1.6.TCConditionType0=0 -unit.1.6.TCCount=1 -unit.1.6.TCEventCount0=1 -unit.1.6.TCEventType0=3 -unit.1.6.TCName0=TriggerCondition0 -unit.1.6.TCOutputEnable0=0 -unit.1.6.TCOutputHigh0=1 -unit.1.6.TCOutputMode0=0 -unit.1.6.browser_tree_state=1 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.browser_tree_state=0 -unit.1.6.coretype=ILA -unit.1.6.eventCount0=1 -unit.1.6.eventCount1=1 -unit.1.6.eventCount2=1 -unit.1.6.eventCount3=1 -unit.1.6.eventCount4=1 -unit.1.6.plotBusColor0=-10066177 -unit.1.6.plotBusColor1=-3355648 -unit.1.6.plotBusColor2=-16776961 -unit.1.6.plotBusColor3=-52429 -unit.1.6.plotBusCount=4 -unit.1.6.plotBusName0=dsp_q_monit -unit.1.6.plotBusName1=dsp_sum_monit -unit.1.6.plotBusName2=dsp_x_monit -unit.1.6.plotBusName3=dsp_y_monit -unit.1.6.plotBusX=dsp_q_monit -unit.1.6.plotBusY=dsp_sum_monit -unit.1.6.plotDataTimeMode=1 -unit.1.6.plotDisplayMode=line -unit.1.6.plotMaxX=0.0 -unit.1.6.plotMaxY=0.0 -unit.1.6.plotMinX=0.0 -unit.1.6.plotMinY=0.0 -unit.1.6.plotSelectedBus=8 -unit.1.6.port.-1.b.0.alias=dsp_q_monit -unit.1.6.port.-1.b.0.channellist=72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.6.port.-1.b.0.color=java.awt.Color[r\=102,g\=102,b\=255] -unit.1.6.port.-1.b.0.name=DataPort -unit.1.6.port.-1.b.0.orderindex=-1 -unit.1.6.port.-1.b.0.radix=Signed -unit.1.6.port.-1.b.0.signedOffset=0.0 -unit.1.6.port.-1.b.0.signedPrecision=0 -unit.1.6.port.-1.b.0.signedScaleFactor=1.0 -unit.1.6.port.-1.b.0.tokencount=0 -unit.1.6.port.-1.b.0.unsignedOffset=0.0 -unit.1.6.port.-1.b.0.unsignedPrecision=0 -unit.1.6.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.0.visible=1 -unit.1.6.port.-1.b.1.alias=dsp_sum_monit -unit.1.6.port.-1.b.1.channellist=104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 -unit.1.6.port.-1.b.1.color=java.awt.Color[r\=204,g\=204,b\=0] -unit.1.6.port.-1.b.1.name=DataPort -unit.1.6.port.-1.b.1.orderindex=-1 -unit.1.6.port.-1.b.1.radix=Signed -unit.1.6.port.-1.b.1.signedOffset=0.0 -unit.1.6.port.-1.b.1.signedPrecision=0 -unit.1.6.port.-1.b.1.signedScaleFactor=1.0 -unit.1.6.port.-1.b.1.tokencount=0 -unit.1.6.port.-1.b.1.unsignedOffset=0.0 -unit.1.6.port.-1.b.1.unsignedPrecision=0 -unit.1.6.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.6.port.-1.b.1.visible=1 -unit.1.6.port.-1.b.2.alias=dsp_x_monit -unit.1.6.port.-1.b.2.channellist=8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=255] -unit.1.6.port.-1.b.2.name=DataPort -unit.1.6.port.-1.b.2.orderindex=-1 -unit.1.6.port.-1.b.2.radix=Signed -unit.1.6.port.-1.b.2.signedOffset=0.0 -unit.1.6.port.-1.b.2.signedPrecision=0 -unit.1.6.port.-1.b.2.signedScaleFactor=1.0 -unit.1.6.port.-1.b.2.tokencount=0 -unit.1.6.port.-1.b.2.unsignedOffset=0.0 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-unit.1.6.port.1.s.11.orderindex=-1 -unit.1.6.port.1.s.11.visible=1 -unit.1.6.port.1.s.12.alias= -unit.1.6.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.12.name=TriggerPort1[12] -unit.1.6.port.1.s.12.orderindex=-1 -unit.1.6.port.1.s.12.visible=1 -unit.1.6.port.1.s.13.alias= -unit.1.6.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.13.name=TriggerPort1[13] -unit.1.6.port.1.s.13.orderindex=-1 -unit.1.6.port.1.s.13.visible=1 -unit.1.6.port.1.s.14.alias= -unit.1.6.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.14.name=TriggerPort1[14] -unit.1.6.port.1.s.14.orderindex=-1 -unit.1.6.port.1.s.14.visible=1 -unit.1.6.port.1.s.15.alias= -unit.1.6.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.15.name=TriggerPort1[15] -unit.1.6.port.1.s.15.orderindex=-1 -unit.1.6.port.1.s.15.visible=1 -unit.1.6.port.1.s.16.alias= -unit.1.6.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.16.name=TriggerPort1[16] -unit.1.6.port.1.s.16.orderindex=-1 -unit.1.6.port.1.s.16.visible=1 -unit.1.6.port.1.s.17.alias= -unit.1.6.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.17.name=TriggerPort1[17] -unit.1.6.port.1.s.17.orderindex=-1 -unit.1.6.port.1.s.17.visible=1 -unit.1.6.port.1.s.18.alias= -unit.1.6.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.18.name=TriggerPort1[18] -unit.1.6.port.1.s.18.orderindex=-1 -unit.1.6.port.1.s.18.visible=1 -unit.1.6.port.1.s.19.alias= -unit.1.6.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.19.name=TriggerPort1[19] -unit.1.6.port.1.s.19.orderindex=-1 -unit.1.6.port.1.s.19.visible=1 -unit.1.6.port.1.s.2.alias= -unit.1.6.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.2.name=TriggerPort1[2] -unit.1.6.port.1.s.2.orderindex=-1 -unit.1.6.port.1.s.2.visible=1 -unit.1.6.port.1.s.20.alias= -unit.1.6.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.20.name=TriggerPort1[20] -unit.1.6.port.1.s.20.orderindex=-1 -unit.1.6.port.1.s.20.visible=1 -unit.1.6.port.1.s.21.alias= -unit.1.6.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.21.name=TriggerPort1[21] -unit.1.6.port.1.s.21.orderindex=-1 -unit.1.6.port.1.s.21.visible=1 -unit.1.6.port.1.s.22.alias= -unit.1.6.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.22.name=TriggerPort1[22] -unit.1.6.port.1.s.22.orderindex=-1 -unit.1.6.port.1.s.22.visible=1 -unit.1.6.port.1.s.23.alias= -unit.1.6.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.23.name=TriggerPort1[23] -unit.1.6.port.1.s.23.orderindex=-1 -unit.1.6.port.1.s.23.visible=1 -unit.1.6.port.1.s.24.alias= -unit.1.6.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.24.name=TriggerPort1[24] -unit.1.6.port.1.s.24.orderindex=-1 -unit.1.6.port.1.s.24.visible=1 -unit.1.6.port.1.s.25.alias= -unit.1.6.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.25.name=TriggerPort1[25] -unit.1.6.port.1.s.25.orderindex=-1 -unit.1.6.port.1.s.25.visible=1 -unit.1.6.port.1.s.26.alias= -unit.1.6.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.26.name=TriggerPort1[26] -unit.1.6.port.1.s.26.orderindex=-1 -unit.1.6.port.1.s.26.visible=1 -unit.1.6.port.1.s.27.alias= -unit.1.6.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.27.name=TriggerPort1[27] -unit.1.6.port.1.s.27.orderindex=-1 -unit.1.6.port.1.s.27.visible=1 -unit.1.6.port.1.s.28.alias= -unit.1.6.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.28.name=TriggerPort1[28] -unit.1.6.port.1.s.28.orderindex=-1 -unit.1.6.port.1.s.28.visible=1 -unit.1.6.port.1.s.29.alias= -unit.1.6.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.29.name=TriggerPort1[29] -unit.1.6.port.1.s.29.orderindex=-1 -unit.1.6.port.1.s.29.visible=1 -unit.1.6.port.1.s.3.alias= -unit.1.6.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.3.name=TriggerPort1[3] -unit.1.6.port.1.s.3.orderindex=-1 -unit.1.6.port.1.s.3.visible=1 -unit.1.6.port.1.s.30.alias= -unit.1.6.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.30.name=TriggerPort1[30] -unit.1.6.port.1.s.30.orderindex=-1 -unit.1.6.port.1.s.30.visible=1 -unit.1.6.port.1.s.31.alias= -unit.1.6.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.31.name=TriggerPort1[31] -unit.1.6.port.1.s.31.orderindex=-1 -unit.1.6.port.1.s.31.visible=1 -unit.1.6.port.1.s.4.alias= -unit.1.6.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.4.name=TriggerPort1[4] -unit.1.6.port.1.s.4.orderindex=-1 -unit.1.6.port.1.s.4.visible=1 -unit.1.6.port.1.s.5.alias= -unit.1.6.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.5.name=TriggerPort1[5] -unit.1.6.port.1.s.5.orderindex=-1 -unit.1.6.port.1.s.5.visible=1 -unit.1.6.port.1.s.6.alias= -unit.1.6.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.6.name=TriggerPort1[6] -unit.1.6.port.1.s.6.orderindex=-1 -unit.1.6.port.1.s.6.visible=1 -unit.1.6.port.1.s.7.alias= -unit.1.6.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.7.name=TriggerPort1[7] -unit.1.6.port.1.s.7.orderindex=-1 -unit.1.6.port.1.s.7.visible=1 -unit.1.6.port.1.s.8.alias= -unit.1.6.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.8.name=TriggerPort1[8] -unit.1.6.port.1.s.8.orderindex=-1 -unit.1.6.port.1.s.8.visible=1 -unit.1.6.port.1.s.9.alias= -unit.1.6.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.1.s.9.name=TriggerPort1[9] -unit.1.6.port.1.s.9.orderindex=-1 -unit.1.6.port.1.s.9.visible=1 -unit.1.6.port.2.b.0.alias= -unit.1.6.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.b.0.name=TriggerPort2 -unit.1.6.port.2.b.0.orderindex=-1 -unit.1.6.port.2.b.0.radix=Hex -unit.1.6.port.2.b.0.signedOffset=0.0 -unit.1.6.port.2.b.0.signedPrecision=0 -unit.1.6.port.2.b.0.signedScaleFactor=1.0 -unit.1.6.port.2.b.0.unsignedOffset=0.0 -unit.1.6.port.2.b.0.unsignedPrecision=0 -unit.1.6.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.2.b.0.visible=1 -unit.1.6.port.2.buscount=1 -unit.1.6.port.2.channelcount=32 -unit.1.6.port.2.s.0.alias= -unit.1.6.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.0.name=TriggerPort2[0] -unit.1.6.port.2.s.0.orderindex=-1 -unit.1.6.port.2.s.0.visible=1 -unit.1.6.port.2.s.1.alias= -unit.1.6.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.1.name=TriggerPort2[1] -unit.1.6.port.2.s.1.orderindex=-1 -unit.1.6.port.2.s.1.visible=1 -unit.1.6.port.2.s.10.alias= -unit.1.6.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.10.name=TriggerPort2[10] -unit.1.6.port.2.s.10.orderindex=-1 -unit.1.6.port.2.s.10.visible=1 -unit.1.6.port.2.s.11.alias= -unit.1.6.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.11.name=TriggerPort2[11] -unit.1.6.port.2.s.11.orderindex=-1 -unit.1.6.port.2.s.11.visible=1 -unit.1.6.port.2.s.12.alias= -unit.1.6.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.12.name=TriggerPort2[12] -unit.1.6.port.2.s.12.orderindex=-1 -unit.1.6.port.2.s.12.visible=1 -unit.1.6.port.2.s.13.alias= -unit.1.6.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.13.name=TriggerPort2[13] -unit.1.6.port.2.s.13.orderindex=-1 -unit.1.6.port.2.s.13.visible=1 -unit.1.6.port.2.s.14.alias= -unit.1.6.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.14.name=TriggerPort2[14] -unit.1.6.port.2.s.14.orderindex=-1 -unit.1.6.port.2.s.14.visible=1 -unit.1.6.port.2.s.15.alias= -unit.1.6.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.15.name=TriggerPort2[15] -unit.1.6.port.2.s.15.orderindex=-1 -unit.1.6.port.2.s.15.visible=1 -unit.1.6.port.2.s.16.alias= -unit.1.6.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.16.name=TriggerPort2[16] -unit.1.6.port.2.s.16.orderindex=-1 -unit.1.6.port.2.s.16.visible=1 -unit.1.6.port.2.s.17.alias= -unit.1.6.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.17.name=TriggerPort2[17] -unit.1.6.port.2.s.17.orderindex=-1 -unit.1.6.port.2.s.17.visible=1 -unit.1.6.port.2.s.18.alias= -unit.1.6.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.18.name=TriggerPort2[18] -unit.1.6.port.2.s.18.orderindex=-1 -unit.1.6.port.2.s.18.visible=1 -unit.1.6.port.2.s.19.alias= -unit.1.6.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.19.name=TriggerPort2[19] -unit.1.6.port.2.s.19.orderindex=-1 -unit.1.6.port.2.s.19.visible=1 -unit.1.6.port.2.s.2.alias= -unit.1.6.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.2.name=TriggerPort2[2] -unit.1.6.port.2.s.2.orderindex=-1 -unit.1.6.port.2.s.2.visible=1 -unit.1.6.port.2.s.20.alias= -unit.1.6.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.20.name=TriggerPort2[20] -unit.1.6.port.2.s.20.orderindex=-1 -unit.1.6.port.2.s.20.visible=1 -unit.1.6.port.2.s.21.alias= -unit.1.6.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.21.name=TriggerPort2[21] -unit.1.6.port.2.s.21.orderindex=-1 -unit.1.6.port.2.s.21.visible=1 -unit.1.6.port.2.s.22.alias= -unit.1.6.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.22.name=TriggerPort2[22] -unit.1.6.port.2.s.22.orderindex=-1 -unit.1.6.port.2.s.22.visible=1 -unit.1.6.port.2.s.23.alias= -unit.1.6.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.23.name=TriggerPort2[23] -unit.1.6.port.2.s.23.orderindex=-1 -unit.1.6.port.2.s.23.visible=1 -unit.1.6.port.2.s.24.alias= -unit.1.6.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.24.name=TriggerPort2[24] -unit.1.6.port.2.s.24.orderindex=-1 -unit.1.6.port.2.s.24.visible=1 -unit.1.6.port.2.s.25.alias= -unit.1.6.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.25.name=TriggerPort2[25] -unit.1.6.port.2.s.25.orderindex=-1 -unit.1.6.port.2.s.25.visible=1 -unit.1.6.port.2.s.26.alias= -unit.1.6.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.26.name=TriggerPort2[26] -unit.1.6.port.2.s.26.orderindex=-1 -unit.1.6.port.2.s.26.visible=1 -unit.1.6.port.2.s.27.alias= -unit.1.6.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.27.name=TriggerPort2[27] -unit.1.6.port.2.s.27.orderindex=-1 -unit.1.6.port.2.s.27.visible=1 -unit.1.6.port.2.s.28.alias= -unit.1.6.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.28.name=TriggerPort2[28] -unit.1.6.port.2.s.28.orderindex=-1 -unit.1.6.port.2.s.28.visible=1 -unit.1.6.port.2.s.29.alias= -unit.1.6.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.29.name=TriggerPort2[29] -unit.1.6.port.2.s.29.orderindex=-1 -unit.1.6.port.2.s.29.visible=1 -unit.1.6.port.2.s.3.alias= -unit.1.6.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.3.name=TriggerPort2[3] -unit.1.6.port.2.s.3.orderindex=-1 -unit.1.6.port.2.s.3.visible=1 -unit.1.6.port.2.s.30.alias= -unit.1.6.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.30.name=TriggerPort2[30] -unit.1.6.port.2.s.30.orderindex=-1 -unit.1.6.port.2.s.30.visible=1 -unit.1.6.port.2.s.31.alias= -unit.1.6.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.31.name=TriggerPort2[31] -unit.1.6.port.2.s.31.orderindex=-1 -unit.1.6.port.2.s.31.visible=1 -unit.1.6.port.2.s.4.alias= -unit.1.6.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.4.name=TriggerPort2[4] -unit.1.6.port.2.s.4.orderindex=-1 -unit.1.6.port.2.s.4.visible=1 -unit.1.6.port.2.s.5.alias= -unit.1.6.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.5.name=TriggerPort2[5] -unit.1.6.port.2.s.5.orderindex=-1 -unit.1.6.port.2.s.5.visible=1 -unit.1.6.port.2.s.6.alias= -unit.1.6.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.6.name=TriggerPort2[6] -unit.1.6.port.2.s.6.orderindex=-1 -unit.1.6.port.2.s.6.visible=1 -unit.1.6.port.2.s.7.alias= -unit.1.6.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.7.name=TriggerPort2[7] -unit.1.6.port.2.s.7.orderindex=-1 -unit.1.6.port.2.s.7.visible=1 -unit.1.6.port.2.s.8.alias= -unit.1.6.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.8.name=TriggerPort2[8] -unit.1.6.port.2.s.8.orderindex=-1 -unit.1.6.port.2.s.8.visible=1 -unit.1.6.port.2.s.9.alias= -unit.1.6.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.2.s.9.name=TriggerPort2[9] -unit.1.6.port.2.s.9.orderindex=-1 -unit.1.6.port.2.s.9.visible=1 -unit.1.6.port.3.b.0.alias= -unit.1.6.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.b.0.name=TriggerPort3 -unit.1.6.port.3.b.0.orderindex=-1 -unit.1.6.port.3.b.0.radix=Hex -unit.1.6.port.3.b.0.signedOffset=0.0 -unit.1.6.port.3.b.0.signedPrecision=0 -unit.1.6.port.3.b.0.signedScaleFactor=1.0 -unit.1.6.port.3.b.0.unsignedOffset=0.0 -unit.1.6.port.3.b.0.unsignedPrecision=0 -unit.1.6.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.3.b.0.visible=1 -unit.1.6.port.3.buscount=1 -unit.1.6.port.3.channelcount=32 -unit.1.6.port.3.s.0.alias= -unit.1.6.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.0.name=TriggerPort3[0] -unit.1.6.port.3.s.0.orderindex=-1 -unit.1.6.port.3.s.0.visible=1 -unit.1.6.port.3.s.1.alias= -unit.1.6.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.1.name=TriggerPort3[1] -unit.1.6.port.3.s.1.orderindex=-1 -unit.1.6.port.3.s.1.visible=1 -unit.1.6.port.3.s.10.alias= -unit.1.6.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.10.name=TriggerPort3[10] -unit.1.6.port.3.s.10.orderindex=-1 -unit.1.6.port.3.s.10.visible=1 -unit.1.6.port.3.s.11.alias= -unit.1.6.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.11.name=TriggerPort3[11] -unit.1.6.port.3.s.11.orderindex=-1 -unit.1.6.port.3.s.11.visible=1 -unit.1.6.port.3.s.12.alias= -unit.1.6.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.12.name=TriggerPort3[12] -unit.1.6.port.3.s.12.orderindex=-1 -unit.1.6.port.3.s.12.visible=1 -unit.1.6.port.3.s.13.alias= -unit.1.6.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.13.name=TriggerPort3[13] -unit.1.6.port.3.s.13.orderindex=-1 -unit.1.6.port.3.s.13.visible=1 -unit.1.6.port.3.s.14.alias= -unit.1.6.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.14.name=TriggerPort3[14] -unit.1.6.port.3.s.14.orderindex=-1 -unit.1.6.port.3.s.14.visible=1 -unit.1.6.port.3.s.15.alias= -unit.1.6.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.15.name=TriggerPort3[15] -unit.1.6.port.3.s.15.orderindex=-1 -unit.1.6.port.3.s.15.visible=1 -unit.1.6.port.3.s.16.alias= -unit.1.6.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.16.name=TriggerPort3[16] -unit.1.6.port.3.s.16.orderindex=-1 -unit.1.6.port.3.s.16.visible=1 -unit.1.6.port.3.s.17.alias= -unit.1.6.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.17.name=TriggerPort3[17] -unit.1.6.port.3.s.17.orderindex=-1 -unit.1.6.port.3.s.17.visible=1 -unit.1.6.port.3.s.18.alias= -unit.1.6.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.18.name=TriggerPort3[18] -unit.1.6.port.3.s.18.orderindex=-1 -unit.1.6.port.3.s.18.visible=1 -unit.1.6.port.3.s.19.alias= -unit.1.6.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.19.name=TriggerPort3[19] -unit.1.6.port.3.s.19.orderindex=-1 -unit.1.6.port.3.s.19.visible=1 -unit.1.6.port.3.s.2.alias= -unit.1.6.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.2.name=TriggerPort3[2] -unit.1.6.port.3.s.2.orderindex=-1 -unit.1.6.port.3.s.2.visible=1 -unit.1.6.port.3.s.20.alias= -unit.1.6.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.20.name=TriggerPort3[20] -unit.1.6.port.3.s.20.orderindex=-1 -unit.1.6.port.3.s.20.visible=1 -unit.1.6.port.3.s.21.alias= -unit.1.6.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.21.name=TriggerPort3[21] -unit.1.6.port.3.s.21.orderindex=-1 -unit.1.6.port.3.s.21.visible=1 -unit.1.6.port.3.s.22.alias= -unit.1.6.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.22.name=TriggerPort3[22] -unit.1.6.port.3.s.22.orderindex=-1 -unit.1.6.port.3.s.22.visible=1 -unit.1.6.port.3.s.23.alias= -unit.1.6.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.23.name=TriggerPort3[23] -unit.1.6.port.3.s.23.orderindex=-1 -unit.1.6.port.3.s.23.visible=1 -unit.1.6.port.3.s.24.alias= -unit.1.6.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.24.name=TriggerPort3[24] -unit.1.6.port.3.s.24.orderindex=-1 -unit.1.6.port.3.s.24.visible=1 -unit.1.6.port.3.s.25.alias= -unit.1.6.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.25.name=TriggerPort3[25] -unit.1.6.port.3.s.25.orderindex=-1 -unit.1.6.port.3.s.25.visible=1 -unit.1.6.port.3.s.26.alias= -unit.1.6.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.26.name=TriggerPort3[26] -unit.1.6.port.3.s.26.orderindex=-1 -unit.1.6.port.3.s.26.visible=1 -unit.1.6.port.3.s.27.alias= -unit.1.6.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.27.name=TriggerPort3[27] -unit.1.6.port.3.s.27.orderindex=-1 -unit.1.6.port.3.s.27.visible=1 -unit.1.6.port.3.s.28.alias= -unit.1.6.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.28.name=TriggerPort3[28] -unit.1.6.port.3.s.28.orderindex=-1 -unit.1.6.port.3.s.28.visible=1 -unit.1.6.port.3.s.29.alias= -unit.1.6.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.29.name=TriggerPort3[29] -unit.1.6.port.3.s.29.orderindex=-1 -unit.1.6.port.3.s.29.visible=1 -unit.1.6.port.3.s.3.alias= -unit.1.6.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.3.name=TriggerPort3[3] -unit.1.6.port.3.s.3.orderindex=-1 -unit.1.6.port.3.s.3.visible=1 -unit.1.6.port.3.s.30.alias= -unit.1.6.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.30.name=TriggerPort3[30] -unit.1.6.port.3.s.30.orderindex=-1 -unit.1.6.port.3.s.30.visible=1 -unit.1.6.port.3.s.31.alias= -unit.1.6.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.31.name=TriggerPort3[31] -unit.1.6.port.3.s.31.orderindex=-1 -unit.1.6.port.3.s.31.visible=1 -unit.1.6.port.3.s.4.alias= -unit.1.6.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.4.name=TriggerPort3[4] -unit.1.6.port.3.s.4.orderindex=-1 -unit.1.6.port.3.s.4.visible=1 -unit.1.6.port.3.s.5.alias= -unit.1.6.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.5.name=TriggerPort3[5] -unit.1.6.port.3.s.5.orderindex=-1 -unit.1.6.port.3.s.5.visible=1 -unit.1.6.port.3.s.6.alias= -unit.1.6.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.6.name=TriggerPort3[6] -unit.1.6.port.3.s.6.orderindex=-1 -unit.1.6.port.3.s.6.visible=1 -unit.1.6.port.3.s.7.alias= -unit.1.6.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.7.name=TriggerPort3[7] -unit.1.6.port.3.s.7.orderindex=-1 -unit.1.6.port.3.s.7.visible=1 -unit.1.6.port.3.s.8.alias= -unit.1.6.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.8.name=TriggerPort3[8] -unit.1.6.port.3.s.8.orderindex=-1 -unit.1.6.port.3.s.8.visible=1 -unit.1.6.port.3.s.9.alias= -unit.1.6.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.3.s.9.name=TriggerPort3[9] -unit.1.6.port.3.s.9.orderindex=-1 -unit.1.6.port.3.s.9.visible=1 -unit.1.6.port.4.b.0.alias= -unit.1.6.port.4.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.6.port.4.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.b.0.name=TriggerPort4 -unit.1.6.port.4.b.0.orderindex=-1 -unit.1.6.port.4.b.0.radix=Hex -unit.1.6.port.4.b.0.signedOffset=0.0 -unit.1.6.port.4.b.0.signedPrecision=0 -unit.1.6.port.4.b.0.signedScaleFactor=1.0 -unit.1.6.port.4.b.0.unsignedOffset=0.0 -unit.1.6.port.4.b.0.unsignedPrecision=0 -unit.1.6.port.4.b.0.unsignedScaleFactor=1.0 -unit.1.6.port.4.b.0.visible=1 -unit.1.6.port.4.buscount=1 -unit.1.6.port.4.channelcount=32 -unit.1.6.port.4.s.0.alias= -unit.1.6.port.4.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.0.name=TriggerPort4[0] -unit.1.6.port.4.s.0.orderindex=-1 -unit.1.6.port.4.s.0.visible=1 -unit.1.6.port.4.s.1.alias= -unit.1.6.port.4.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.1.name=TriggerPort4[1] -unit.1.6.port.4.s.1.orderindex=-1 -unit.1.6.port.4.s.1.visible=1 -unit.1.6.port.4.s.10.alias= -unit.1.6.port.4.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.10.name=TriggerPort4[10] -unit.1.6.port.4.s.10.orderindex=-1 -unit.1.6.port.4.s.10.visible=1 -unit.1.6.port.4.s.11.alias= -unit.1.6.port.4.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.11.name=TriggerPort4[11] -unit.1.6.port.4.s.11.orderindex=-1 -unit.1.6.port.4.s.11.visible=1 -unit.1.6.port.4.s.12.alias= -unit.1.6.port.4.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.12.name=TriggerPort4[12] -unit.1.6.port.4.s.12.orderindex=-1 -unit.1.6.port.4.s.12.visible=1 -unit.1.6.port.4.s.13.alias= -unit.1.6.port.4.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.13.name=TriggerPort4[13] -unit.1.6.port.4.s.13.orderindex=-1 -unit.1.6.port.4.s.13.visible=1 -unit.1.6.port.4.s.14.alias= -unit.1.6.port.4.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.14.name=TriggerPort4[14] -unit.1.6.port.4.s.14.orderindex=-1 -unit.1.6.port.4.s.14.visible=1 -unit.1.6.port.4.s.15.alias= -unit.1.6.port.4.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.15.name=TriggerPort4[15] -unit.1.6.port.4.s.15.orderindex=-1 -unit.1.6.port.4.s.15.visible=1 -unit.1.6.port.4.s.16.alias= -unit.1.6.port.4.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.16.name=TriggerPort4[16] -unit.1.6.port.4.s.16.orderindex=-1 -unit.1.6.port.4.s.16.visible=1 -unit.1.6.port.4.s.17.alias= -unit.1.6.port.4.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.17.name=TriggerPort4[17] -unit.1.6.port.4.s.17.orderindex=-1 -unit.1.6.port.4.s.17.visible=1 -unit.1.6.port.4.s.18.alias= -unit.1.6.port.4.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.18.name=TriggerPort4[18] -unit.1.6.port.4.s.18.orderindex=-1 -unit.1.6.port.4.s.18.visible=1 -unit.1.6.port.4.s.19.alias= -unit.1.6.port.4.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.19.name=TriggerPort4[19] -unit.1.6.port.4.s.19.orderindex=-1 -unit.1.6.port.4.s.19.visible=1 -unit.1.6.port.4.s.2.alias= -unit.1.6.port.4.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.2.name=TriggerPort4[2] -unit.1.6.port.4.s.2.orderindex=-1 -unit.1.6.port.4.s.2.visible=1 -unit.1.6.port.4.s.20.alias= -unit.1.6.port.4.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.20.name=TriggerPort4[20] -unit.1.6.port.4.s.20.orderindex=-1 -unit.1.6.port.4.s.20.visible=1 -unit.1.6.port.4.s.21.alias= -unit.1.6.port.4.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.21.name=TriggerPort4[21] -unit.1.6.port.4.s.21.orderindex=-1 -unit.1.6.port.4.s.21.visible=1 -unit.1.6.port.4.s.22.alias= -unit.1.6.port.4.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.22.name=TriggerPort4[22] -unit.1.6.port.4.s.22.orderindex=-1 -unit.1.6.port.4.s.22.visible=1 -unit.1.6.port.4.s.23.alias= -unit.1.6.port.4.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.23.name=TriggerPort4[23] -unit.1.6.port.4.s.23.orderindex=-1 -unit.1.6.port.4.s.23.visible=1 -unit.1.6.port.4.s.24.alias= -unit.1.6.port.4.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.24.name=TriggerPort4[24] -unit.1.6.port.4.s.24.orderindex=-1 -unit.1.6.port.4.s.24.visible=1 -unit.1.6.port.4.s.25.alias= -unit.1.6.port.4.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.25.name=TriggerPort4[25] -unit.1.6.port.4.s.25.orderindex=-1 -unit.1.6.port.4.s.25.visible=1 -unit.1.6.port.4.s.26.alias= -unit.1.6.port.4.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.26.name=TriggerPort4[26] -unit.1.6.port.4.s.26.orderindex=-1 -unit.1.6.port.4.s.26.visible=1 -unit.1.6.port.4.s.27.alias= -unit.1.6.port.4.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.27.name=TriggerPort4[27] -unit.1.6.port.4.s.27.orderindex=-1 -unit.1.6.port.4.s.27.visible=1 -unit.1.6.port.4.s.28.alias= -unit.1.6.port.4.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.28.name=TriggerPort4[28] -unit.1.6.port.4.s.28.orderindex=-1 -unit.1.6.port.4.s.28.visible=1 -unit.1.6.port.4.s.29.alias= -unit.1.6.port.4.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.29.name=TriggerPort4[29] -unit.1.6.port.4.s.29.orderindex=-1 -unit.1.6.port.4.s.29.visible=1 -unit.1.6.port.4.s.3.alias= -unit.1.6.port.4.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.3.name=TriggerPort4[3] -unit.1.6.port.4.s.3.orderindex=-1 -unit.1.6.port.4.s.3.visible=1 -unit.1.6.port.4.s.30.alias= -unit.1.6.port.4.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.30.name=TriggerPort4[30] -unit.1.6.port.4.s.30.orderindex=-1 -unit.1.6.port.4.s.30.visible=1 -unit.1.6.port.4.s.31.alias= -unit.1.6.port.4.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.31.name=TriggerPort4[31] -unit.1.6.port.4.s.31.orderindex=-1 -unit.1.6.port.4.s.31.visible=1 -unit.1.6.port.4.s.4.alias= -unit.1.6.port.4.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.4.name=TriggerPort4[4] -unit.1.6.port.4.s.4.orderindex=-1 -unit.1.6.port.4.s.4.visible=1 -unit.1.6.port.4.s.5.alias= -unit.1.6.port.4.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.5.name=TriggerPort4[5] -unit.1.6.port.4.s.5.orderindex=-1 -unit.1.6.port.4.s.5.visible=1 -unit.1.6.port.4.s.6.alias= -unit.1.6.port.4.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.6.name=TriggerPort4[6] -unit.1.6.port.4.s.6.orderindex=-1 -unit.1.6.port.4.s.6.visible=1 -unit.1.6.port.4.s.7.alias= -unit.1.6.port.4.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.7.name=TriggerPort4[7] -unit.1.6.port.4.s.7.orderindex=-1 -unit.1.6.port.4.s.7.visible=1 -unit.1.6.port.4.s.8.alias= -unit.1.6.port.4.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.8.name=TriggerPort4[8] -unit.1.6.port.4.s.8.orderindex=-1 -unit.1.6.port.4.s.8.visible=1 -unit.1.6.port.4.s.9.alias= -unit.1.6.port.4.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.6.port.4.s.9.name=TriggerPort4[9] -unit.1.6.port.4.s.9.orderindex=-1 -unit.1.6.port.4.s.9.visible=1 -unit.1.6.portcount=5 -unit.1.6.rep_trigger.clobber=1 -unit.1.6.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp -unit.1.6.rep_trigger.filename=waveform -unit.1.6.rep_trigger.format=ASCII -unit.1.6.rep_trigger.loggingEnabled=0 -unit.1.6.rep_trigger.signals=All Signals/Buses -unit.1.6.samplesPerTrigger=1 -unit.1.6.triggerCapture=1 -unit.1.6.triggerNSamplesTS=0 -unit.1.6.triggerPosition=0 -unit.1.6.triggerWindowCount=1 -unit.1.6.triggerWindowDepth=4096 -unit.1.6.triggerWindowTS=0 -unit.1.6.username=MyILA6 -unit.1.6.waveform.count=42 -unit.1.6.waveform.posn.0.channel=0 -unit.1.6.waveform.posn.0.name=DataPort[0] -unit.1.6.waveform.posn.0.type=signal -unit.1.6.waveform.posn.1.channel=1 -unit.1.6.waveform.posn.1.name=DataPort[1] -unit.1.6.waveform.posn.1.type=signal -unit.1.6.waveform.posn.10.channel=34 -unit.1.6.waveform.posn.10.name=DataPort[34] -unit.1.6.waveform.posn.10.type=signal -unit.1.6.waveform.posn.11.channel=35 -unit.1.6.waveform.posn.11.name=DataPort[35] -unit.1.6.waveform.posn.11.type=signal -unit.1.6.waveform.posn.12.channel=36 -unit.1.6.waveform.posn.12.name=DataPort[36] -unit.1.6.waveform.posn.12.type=signal -unit.1.6.waveform.posn.13.channel=37 -unit.1.6.waveform.posn.13.name=DataPort[37] -unit.1.6.waveform.posn.13.type=signal -unit.1.6.waveform.posn.14.channel=38 -unit.1.6.waveform.posn.14.name=DataPort[38] -unit.1.6.waveform.posn.14.type=signal -unit.1.6.waveform.posn.15.channel=39 -unit.1.6.waveform.posn.15.name=DataPort[39] -unit.1.6.waveform.posn.15.type=signal -unit.1.6.waveform.posn.16.channel=64 -unit.1.6.waveform.posn.16.name=DataPort[64] -unit.1.6.waveform.posn.16.type=signal -unit.1.6.waveform.posn.17.channel=65 -unit.1.6.waveform.posn.17.name=DataPort[65] -unit.1.6.waveform.posn.17.type=signal -unit.1.6.waveform.posn.18.channel=66 -unit.1.6.waveform.posn.18.name=DataPort[66] -unit.1.6.waveform.posn.18.type=signal -unit.1.6.waveform.posn.19.channel=67 -unit.1.6.waveform.posn.19.name=DataPort[67] -unit.1.6.waveform.posn.19.type=signal -unit.1.6.waveform.posn.2.channel=2 -unit.1.6.waveform.posn.2.name=DataPort[2] -unit.1.6.waveform.posn.2.type=signal -unit.1.6.waveform.posn.20.channel=68 -unit.1.6.waveform.posn.20.name=DataPort[68] -unit.1.6.waveform.posn.20.type=signal -unit.1.6.waveform.posn.21.channel=69 -unit.1.6.waveform.posn.21.name=DataPort[69] -unit.1.6.waveform.posn.21.type=signal -unit.1.6.waveform.posn.22.channel=70 -unit.1.6.waveform.posn.22.name=DataPort[70] -unit.1.6.waveform.posn.22.type=signal -unit.1.6.waveform.posn.23.channel=71 -unit.1.6.waveform.posn.23.name=DataPort[71] -unit.1.6.waveform.posn.23.type=signal -unit.1.6.waveform.posn.24.channel=96 -unit.1.6.waveform.posn.24.name=DataPort[96] -unit.1.6.waveform.posn.24.type=signal -unit.1.6.waveform.posn.25.channel=97 -unit.1.6.waveform.posn.25.name=DataPort[97] -unit.1.6.waveform.posn.25.type=signal -unit.1.6.waveform.posn.26.channel=98 -unit.1.6.waveform.posn.26.name=DataPort[98] -unit.1.6.waveform.posn.26.type=signal -unit.1.6.waveform.posn.27.channel=99 -unit.1.6.waveform.posn.27.name=DataPort[99] -unit.1.6.waveform.posn.27.type=signal -unit.1.6.waveform.posn.28.channel=100 -unit.1.6.waveform.posn.28.name=DataPort[100] -unit.1.6.waveform.posn.28.type=signal -unit.1.6.waveform.posn.29.channel=101 -unit.1.6.waveform.posn.29.name=DataPort[101] -unit.1.6.waveform.posn.29.type=signal -unit.1.6.waveform.posn.3.channel=3 -unit.1.6.waveform.posn.3.name=DataPort[3] -unit.1.6.waveform.posn.3.type=signal -unit.1.6.waveform.posn.30.channel=102 -unit.1.6.waveform.posn.30.name=DataPort[102] -unit.1.6.waveform.posn.30.type=signal -unit.1.6.waveform.posn.31.channel=103 -unit.1.6.waveform.posn.31.name=DataPort[103] -unit.1.6.waveform.posn.31.type=signal -unit.1.6.waveform.posn.32.channel=130 -unit.1.6.waveform.posn.32.name=DataPort[130] -unit.1.6.waveform.posn.32.type=signal -unit.1.6.waveform.posn.33.channel=131 -unit.1.6.waveform.posn.33.name=DataPort[131] -unit.1.6.waveform.posn.33.type=signal -unit.1.6.waveform.posn.34.channel=132 -unit.1.6.waveform.posn.34.name=DataPort[132] -unit.1.6.waveform.posn.34.type=signal -unit.1.6.waveform.posn.35.channel=133 -unit.1.6.waveform.posn.35.name=DataPort[133] -unit.1.6.waveform.posn.35.type=signal -unit.1.6.waveform.posn.36.channel=134 -unit.1.6.waveform.posn.36.name=DataPort[134] -unit.1.6.waveform.posn.36.type=signal -unit.1.6.waveform.posn.37.channel=135 -unit.1.6.waveform.posn.37.name=DataPort[135] -unit.1.6.waveform.posn.37.type=signal -unit.1.6.waveform.posn.38.channel=2147483646 -unit.1.6.waveform.posn.38.name=dsp_q_monit -unit.1.6.waveform.posn.38.radix=3 -unit.1.6.waveform.posn.38.type=bus -unit.1.6.waveform.posn.39.channel=2147483646 -unit.1.6.waveform.posn.39.name=dsp_sum_monit -unit.1.6.waveform.posn.39.radix=3 -unit.1.6.waveform.posn.39.type=bus -unit.1.6.waveform.posn.4.channel=4 -unit.1.6.waveform.posn.4.name=DataPort[4] -unit.1.6.waveform.posn.4.type=signal -unit.1.6.waveform.posn.40.channel=2147483646 -unit.1.6.waveform.posn.40.name=dsp_x_monit -unit.1.6.waveform.posn.40.radix=3 -unit.1.6.waveform.posn.40.type=bus -unit.1.6.waveform.posn.41.channel=2147483646 -unit.1.6.waveform.posn.41.name=dsp_y_monit -unit.1.6.waveform.posn.41.radix=3 -unit.1.6.waveform.posn.41.type=bus -unit.1.6.waveform.posn.42.channel=2147483646 -unit.1.6.waveform.posn.42.name=dsp_y_monit -unit.1.6.waveform.posn.42.radix=3 -unit.1.6.waveform.posn.42.type=bus -unit.1.6.waveform.posn.43.channel=2147483646 -unit.1.6.waveform.posn.43.name=dsp_y_monit -unit.1.6.waveform.posn.43.radix=3 -unit.1.6.waveform.posn.43.type=bus -unit.1.6.waveform.posn.44.channel=2147483646 -unit.1.6.waveform.posn.44.name=dsp_y_monit -unit.1.6.waveform.posn.44.radix=3 -unit.1.6.waveform.posn.44.type=bus -unit.1.6.waveform.posn.45.channel=2147483646 -unit.1.6.waveform.posn.45.name=dsp_y_monit -unit.1.6.waveform.posn.45.radix=3 -unit.1.6.waveform.posn.45.type=bus -unit.1.6.waveform.posn.46.channel=2147483646 -unit.1.6.waveform.posn.46.name=dsp_y_monit -unit.1.6.waveform.posn.46.radix=3 -unit.1.6.waveform.posn.46.type=bus -unit.1.6.waveform.posn.5.channel=5 -unit.1.6.waveform.posn.5.name=DataPort[5] -unit.1.6.waveform.posn.5.type=signal -unit.1.6.waveform.posn.6.channel=6 -unit.1.6.waveform.posn.6.name=DataPort[6] -unit.1.6.waveform.posn.6.type=signal -unit.1.6.waveform.posn.7.channel=7 -unit.1.6.waveform.posn.7.name=DataPort[7] -unit.1.6.waveform.posn.7.type=signal -unit.1.6.waveform.posn.8.channel=32 -unit.1.6.waveform.posn.8.name=DataPort[32] -unit.1.6.waveform.posn.8.type=signal -unit.1.6.waveform.posn.9.channel=33 -unit.1.6.waveform.posn.9.name=DataPort[33] -unit.1.6.waveform.posn.9.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/clk_gen.vhd deleted file mode 100644 index 21542e5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/clk_gen.vhd +++ /dev/null @@ -1,47 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.ucf b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.ucf deleted file mode 100644 index 5afd47f4..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.ucf +++ /dev/null @@ -1,350 +0,0 @@ -####################################################################### -# FMC516 Constraints -####################################################################### - -NET "adc_data_ch0_p_i[0]" LOC = AB32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[0]" LOC = AC32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[1]" LOC = AC33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[1]" LOC = AB33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[2]" LOC = AD32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[2]" LOC = AE32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[3]" LOC = AD34 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[3]" LOC = AC34 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[4]" LOC = AG31 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[4]" LOC = AF31 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[5]" LOC = AA26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[5]" LOC = AB26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[6]" LOC = AA25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[6]" LOC = Y26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[7]" LOC = AB28 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[7]" LOC = AC28 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; - -NET "adc_data_ch1_p_i[0]" LOC = AN19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[0]" LOC = AN20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[1]" LOC = AP19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[1]" LOC = AN18 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[2]" LOC = AM20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[2]" LOC = AL20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[3]" LOC = AM18 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[3]" LOC = AL18 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[4]" LOC = AK22 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[4]" LOC = AJ22 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[5]" LOC = AF19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[5]" LOC = AE19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[6]" LOC = AC20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[6]" LOC = AD20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[7]" LOC = AF20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[7]" LOC = AF21 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; - -NET "adc_data_ch2_p_i[0]" LOC = AJ24 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[0]" LOC = AK24 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[1]" LOC = AL29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[1]" LOC = AK29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[2]" LOC = AK27 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[2]" LOC = AJ27 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[3]" LOC = AN30 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[3]" LOC = AM30 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[4]" LOC = AM25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[4]" LOC = AL25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[5]" LOC = AP27 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[5]" LOC = AP26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[6]" LOC = AK23 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[6]" LOC = AL24 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[7]" LOC = AH25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[7]" LOC = AJ25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; - -NET "adc_data_ch3_p_i[0]" LOC = AJ31 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[0]" LOC = AJ32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[1]" LOC = AH33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[1]" LOC = AH32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[2]" LOC = AE28 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[2]" LOC = AE29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[3]" LOC = AJ29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[3]" LOC = AJ30 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[4]" LOC = AF26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[4]" LOC = AE26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[5]" LOC = AM33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[5]" LOC = AL33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[6]" LOC = AN33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[6]" LOC = AN34 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[7]" LOC = AP32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[7]" LOC = AP33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; - -NET "sys_i2c_scl_b" LOC = AK9; # Not directly connected to FMC HPC pins. There is a level shifter in the middle -NET "sys_i2c_sda_b" LOC = AE9; # Not directly connected to FMC HPC pins. There is a level shifter in the middle - -NET "adc_clk_div_rst_p_o" LOC = AM23 | IOSTANDARD = LVDS_25; -NET "adc_clk_div_rst_n_o" LOC = AL23 | IOSTANDARD = LVDS_25; - -NET "fmc_leds_o[0]" LOC = AP22 | IOSTANDARD = LVCMOS25; -NET "fmc_leds_o[1]" LOC = AN23 | IOSTANDARD = LVCMOS25; - -NET "sys_spi_clk_o" LOC = AG25 | IOSTANDARD = LVCMOS25; -NET "sys_spi_data_b" LOC = AG26 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc0_n_o" LOC = AE27 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc1_n_o" LOC = AD27 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc2_n_o" LOC = AH30 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc3_n_o" LOC = AH29 | IOSTANDARD = LVCMOS25; - -NET "m2c_trig_p_i" LOC = AE33 | IOSTANDARD = LVDS_25; -NET "m2c_trig_n_i" LOC = AF33 | IOSTANDARD = LVDS_25; -NET "c2m_trig_p_o" LOC = AD29 | IOSTANDARD = LVDS_25; -NET "c2m_trig_n_o" LOC = AC29 | IOSTANDARD = LVDS_25; - -NET "lmk_lock_i" LOC = T33 | IOSTANDARD = LVCMOS25; -NET "lmk_sync_o" LOC = T34 | IOSTANDARD = LVCMOS25; -NET "lmk_uwire_latch_en_o" LOC = U31 | IOSTANDARD = LVCMOS25; -NET "lmk_uwire_data_o" LOC = U30 | IOSTANDARD = LVCMOS25; -NET "lmk_uwire_clock_o" LOC = U28 | IOSTANDARD = LVCMOS25; - -NET "vcxo_i2c_sda_b" LOC = V32 | IOSTANDARD = LVCMOS25; -NET "vcxo_i2c_scl_o" LOC = U33 | IOSTANDARD = LVCMOS25; -NET "vcxo_pd_l_o" LOC = V33 | IOSTANDARD = LVCMOS25; - -NET "fmc_id_dq_b" LOC = V30 | IOSTANDARD = LVCMOS25; -NET "fmc_key_dq_b" LOC = W30 | IOSTANDARD = LVCMOS25; - -NET "fmc_pwr_good_i" LOC = AH23 | IOSTANDARD = LVCMOS25; -NET "fmc_clk_sel_o" LOC = V29 | IOSTANDARD = LVCMOS25; -NET "fmc_reset_adcs_n_o" LOC = U32 | IOSTANDARD = LVCMOS25; -NET "fmc_prsnt_m2c_l_i" LOC = AP25; - -# MMCM Status <-> Led signals GPIO_LED_C -NET "fmc_mmcm_lock_o" LOC="AP24" | IOSTANDARD = "LVCMOS25"; -# LMK clock distribution Status <-> Led signals GPIO_LED_W -NET "fmc_lmk_lock_o" LOC="AD21" | IOSTANDARD = "LVCMOS25"; - -####################################################################### -# ADC Clock Assignments (ISLA216P) -####################################################################### - -# 250 MHz Clock -# 112 MHz Clock -# The CLOCK_DEDICATED_ROUTE=FALSE workaround is typically for source clocks which -# are not assigned to global clock input pins - -#NET "adc_clk0_p_i" TNM_NET = "adc_clk0_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -#TIMESPEC "TS_adc_clk0_p_i" = PERIOD "adc_clk0_p_i" 4 ns HIGH 50%; -NET "adc_clk0_p_i" TNM_NET = "adc_clk0_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -TIMESPEC "TS_adc_clk0_p_i" = PERIOD "adc_clk0_p_i" 8.882 ns HIGH 50%; - -#NET "adc_clk1_p_i" TNM_NET = "adc_clk1_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -#TIMESPEC "TS_adc_clk1_p_i" = PERIOD "adc_clk1_p_i" 4 ns HIGH 50%; -NET "adc_clk1_p_i" TNM_NET = "adc_clk1_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -TIMESPEC "TS_adc_clk1_p_i" = PERIOD "adc_clk1_p_i" 8.882 ns HIGH 50%; - -#NET "adc_clk2_p_i" TNM_NET = "adc_clk2_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -#TIMESPEC "TS_adc_clk2_p_i" = PERIOD "adc_clk2_p_i" 4 ns HIGH 50%; -NET "adc_clk2_p_i" TNM_NET = "adc_clk2_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -TIMESPEC "TS_adc_clk2_p_i" = PERIOD "adc_clk2_p_i" 8.882 ns HIGH 50%; - -#NET "adc_clk3_p_i" TNM_NET = "adc_clk3_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -#TIMESPEC "TS_adc_clk3_p_i" = PERIOD "adc_clk3_p_i" 4 ns HIGH 50%; -NET "adc_clk3_p_i" TNM_NET = "adc_clk3_p_i" | CLOCK_DEDICATED_ROUTE=FALSE; -TIMESPEC "TS_adc_clk3_p_i" = PERIOD "adc_clk3_p_i" 8.882 ns HIGH 50%; - -NET "adc_clk0_p_i" LOC = "AP20" | IOSTANDARD = LVDS_25; -NET "adc_clk0_n_i" LOC = "AP21" | IOSTANDARD = LVDS_25; - -NET "adc_clk1_p_i" LOC = "AD30" | IOSTANDARD = LVDS_25; -NET "adc_clk1_n_i" LOC = "AC30" | IOSTANDARD = LVDS_25; - -NET "adc_clk2_p_i" LOC = "K24" | IOSTANDARD = LVDS_25; -NET "adc_clk2_n_i" LOC = "K23" | IOSTANDARD = LVDS_25; - -NET "adc_clk3_p_i" LOC = "AE34" | IOSTANDARD = LVDS_25; -NET "adc_clk3_n_i" LOC = "AF34" | IOSTANDARD = LVDS_25; - -####################################################################### -# ADC Data <-> Clocks Constraints (ISLA216P) -# -# From the data sheet (page 11) -# -#Output Clock to Data Propagation Delay (LVDS Mode): -# tdc Rising/Falling Edge -0.1 (min) 0.16 (typ) 0.5 (max) ns -# -#Constraint recommended by Intersil -# -#TIMEGRP "datain18_p_group" OFFSET = IN -200 ps VALID 1200 ps BEFORE "clkin18_p" RISING; -# -#This is setup for a 250MHz clock (4ns period).  The ISLA216P25 specifies -# tDC as -0.1 to +0.5 ns.  The constraint adds an additional 100ps to each side -# to account for potential skew due to the pcb.  So, the tDC ends up being -0.2 -# to 0.6 ns.  The value after IN in the constraint equal tDC min (-200ps).  -# The  value after VALID = Period/2 + tDC min – tDC max (4000ps/2 + -200ps – -# 600ps = 1200ps).  (The period is divided by two because the data is DDR.) -# -# -# OFFSET -# +---+ -# -# -------- -------- -# CLK | | | | | -# -------- -------- -# -------------------------------- -# DATA | || || || | -# -------------------------------- -# -# +------+ -# VALID -# -####################################################################### - -TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk0_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk0_p_i" FALLING; -#TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk0_p_i" RISING; -#TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk0_p_i" FALLING; - -TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk1_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk1_p_i" FALLING; -#TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk1_p_i" RISING; -#TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk1_p_i" FALLING; - -TIMEGRP "TNM_ADC_DATA_2" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk2_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_2" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk2_p_i" FALLING; -#TIMEGRP "TNM_ADC_DATA_2" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk2_p_i" RISING; -#TIMEGRP "TNM_ADC_DATA_2" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk2_p_i" FALLING; - -TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk3_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk3_p_i" FALLING; -#TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk3_p_i" RISING; -#TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 2000 ps BEFORE "adc_clk3_p_i" FALLING; - -####################################################################### -# CDC FIFO Constraints -####################################################################### - -# NET "RD_CLK" TNM_NET = "RD_CLK"; -# NET "WR_CLK" TNM_NET = "WR_CLK"; -# TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; -# TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; - -####################################################################### -# Other Constraints -####################################################################### - -# Group all IDELAY-related blocks to use a single IDELAYCTRL -INST "*cmp_fmc516_adc_iface/cmp_idelayctrl" IODELAY_GROUP = adc_idelay; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IODELAY_GROUP = adc_idelay; -INST "*cmp_fmc516_adc_iface/gen_clock_chains[?].*.*/*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = adc_idelay; - -# Overrides default_delay hdl parameter for the VARIABLE mode. -# For Virtex-6: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; - -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; - -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; - -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; - -# Overrides default_delay hdl parameter - INST "*cmp_fmc516_adc_iface/gen_clock_chains[0].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; - INST "*cmp_fmc516_adc_iface/gen_clock_chains[1].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; -# INST "*cmp_fmc516_adc_iface/gen_clock_chains[2].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; -# INST "*cmp_fmc516_adc_iface/gen_clock_chains[3].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; - -####################################################################### -# Button/LEDs Contraints -####################################################################### - -NET "buttons_i[0]" LOC = D22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[1]" LOC = C22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[2]" LOC = L21 | IOSTANDARD = LVCMOS25; -NET "buttons_i[3]" LOC = L20 | IOSTANDARD = LVCMOS25; -NET "buttons_i[4]" LOC = C18 | IOSTANDARD = LVCMOS25; -NET "buttons_i[5]" LOC = B18 | IOSTANDARD = LVCMOS25; -NET "buttons_i[6]" LOC = K22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[7]" LOC = K21 | IOSTANDARD = LVCMOS25; -NET "leds_o[0]" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[1]" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[2]" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[3]" LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[4]" LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[5]" LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[6]" LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[7]" LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; - -####################################################################### -# UART Constraints -####################################################################### - -NET "uart_rxd_i" LOC = J24 | IOSTANDARD = LVCMOS25; -NET "uart_txd_o" LOC = J25 | IOSTANDARD = LVCMOS25; - -####################################################################### -# Clock and Reset Contraints -####################################################################### - -NET "sys_clk_n_i" LOC = H9 | IOSTANDARD = LVDS_25; -NET "sys_clk_p_i" LOC = J9 | IOSTANDARD = LVDS_25; -NET "sys_rst_button_i" LOC = H10 | IOSTANDARD = SSTL15 | TIG; - -NET "clk_sys" TNM_NET = "sys_clk_group"; -NET "clk_200mhz" TNM_NET = "sys_clk200_group"; - -TIMESPEC "TS_sys_clk_group" = PERIOD "sys_clk_group" 10 ns; # 100 MHz -TIMESPEC "TS_sys_clk200_group" = PERIOD "sys_clk200_group" 5 ns; # 200 MHz - -####################################################################### -# Ethernet Contraints. MII 10/100 Mode -####################################################################### - -NET "mrstn_o" LOC = AH13; -NET "mcoll_pad_i" LOC = AK13; ## 114 on U80 -NET "mcrs_pad_i" LOC = AL13; ## 115 on U80 -# NET "PHY_INT" LOC = AH14; ## 32 on U80 -NET "mdc_pad_o" LOC = AP14; ## 35 on U80 -NET "md_pad_b" LOC = AN14; ## 33 on U80 -# NET "PHY_RESET" LOC = AH13; ## 36 on U80 -NET "mrx_clk_pad_i" LOC = AP11; ## 7 on U80 -NET "mrxdv_pad_i" LOC = AM13; ## 4 on U80 -NET "mrxd_pad_i[0]" LOC = AN13; ## 3 on U80 -NET "mrxd_pad_i[1]" LOC = AF14; ## 128 on U80 -NET "mrxd_pad_i[2]" LOC = AE14; ## 126 on U80 -NET "mrxd_pad_i[3]" LOC = AN12; ## 125 on U80 -# NET "PHY_RXD4" LOC = AM12; ## 124 on U80 -# NET "PHY_RXD5" LOC = AD11; ## 123 on U80 -# NET "PHY_RXD6" LOC = AC12; ## 121 on U80 -# NET "PHY_RXD7" LOC = AC13; ## 120 on U80 -NET "mrxerr_pad_i" LOC = AG12; ## 9 on U80 -NET "mtx_clk_pad_i" LOC = AD12; ## 10 on U80 -NET "mtxen_pad_o" LOC = AJ10; ## 16 on U80 -# NET "PHY_TXC_GTXCLK" LOC = AH12; ## 14 on U80 -NET "mtxd_pad_o[0]" LOC = AM11; ## 18 on U80 -NET "mtxd_pad_o[1]" LOC = AL11; ## 19 on U80 -NET "mtxd_pad_o[2]" LOC = AG10; ## 20 on U80 -NET "mtxd_pad_o[3]" LOC = AG11; ## 24 on U80 -# NET "PHY_TXD4" LOC = AL10; ## 25 on U80 -# NET "PHY_TXD5" LOC = AM10; ## 26 on U80 -# NET "PHY_TXD6" LOC = AE11; ## 28 on U80 -# NET "PHY_TXD7" LOC = AF11; ## 29 on U80 -NET "mtxerr_pad_o" LOC = AH10; ## 13 on U80 diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.vhd b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.vhd deleted file mode 100755 index add88057..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dbe_bpm_dsp.vhd +++ /dev/null @@ -1,1561 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top DSP design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2013-02-25 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control of the DSP -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2013-02-25 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Custom common cores -use work.ifc_common_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_generic_pkg.all; --- Ethernet MAC Modules and SDB structure -use work.ethmac_pkg.all; --- Wishbone Fabric interface -use work.wr_fabric_pkg.all; --- Etherbone slave core -use work.etherbone_pkg.all; --- FMC516 definitions -use work.fmc_adc_pkg.all; --- DSP definitions -use work.dsp_cores_pkg.all; --- BPM definitions -use work.bpm_cores_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_dsp is -port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - uart_txd_o : out std_logic; - uart_rxd_i : in std_logic; - - ----------------------------------------- - -- PHY pins - ----------------------------------------- - - -- Clock and resets to PHY (GMII). Not used in MII mode (10/100) - mgtx_clk_o : out std_logic; - mrstn_o : out std_logic; - - -- PHY TX - mtx_clk_pad_i : in std_logic; - mtxd_pad_o : out std_logic_vector(3 downto 0); - mtxen_pad_o : out std_logic; - mtxerr_pad_o : out std_logic; - - -- PHY RX - mrx_clk_pad_i : in std_logic; - mrxd_pad_i : in std_logic_vector(3 downto 0); - mrxdv_pad_i : in std_logic; - mrxerr_pad_i : in std_logic; - mcoll_pad_i : in std_logic; - mcrs_pad_i : in std_logic; - - -- MII - mdc_pad_o : out std_logic; - md_pad_b : inout std_logic; - - ----------------------------- - -- FMC516 ports - ----------------------------- - - -- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM, - -- AD7417 temperature diodes and AD7417 supply rails - sys_i2c_scl_b : inout std_logic; - sys_i2c_sda_b : inout std_logic; - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - adc_clk0_p_i : in std_logic; - adc_clk0_n_i : in std_logic; - adc_clk1_p_i : in std_logic; - adc_clk1_n_i : in std_logic; - adc_clk2_p_i : in std_logic; - adc_clk2_n_i : in std_logic; - adc_clk3_p_i : in std_logic; - adc_clk3_n_i : in std_logic; - - -- DDR ADC data channels. - adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - - -- ADC clock (half of the sampling frequency) divider reset - adc_clk_div_rst_p_o : out std_logic; - adc_clk_div_rst_n_o : out std_logic; - - -- FMC Front leds. Typical uses: Over Range or Full Scale - -- condition. - fmc_leds_o : out std_logic_vector(1 downto 0); - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - sys_spi_clk_o : out std_logic; - sys_spi_data_b : inout std_logic; - sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0 - sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1 - sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2 - sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3 - - -- External Trigger To/From FMC - m2c_trig_p_i : in std_logic; - m2c_trig_n_i : in std_logic; - c2m_trig_p_o : out std_logic; - c2m_trig_n_o : out std_logic; - - -- LMK (National Semiconductor) is the clock and distribution IC, - -- programmable via Microwire Interface - lmk_lock_i : in std_logic; - lmk_sync_o : out std_logic; - lmk_uwire_latch_en_o : out std_logic; - lmk_uwire_data_o : out std_logic; - lmk_uwire_clock_o : out std_logic; - - -- Programable VCXO via I2C - vcxo_i2c_sda_b : inout std_logic; - vcxo_i2c_scl_o : out std_logic; - vcxo_pd_l_o : out std_logic; - - -- One-wire To/From DS2431 (VMETRO Data) - fmc_id_dq_b : inout std_logic; - -- One-wire To/From DS2432 SHA-1 (SP-Devices key) - fmc_key_dq_b : inout std_logic; - - -- General board pins - fmc_pwr_good_i : in std_logic; - -- Internal/External clock distribution selection - fmc_clk_sel_o : out std_logic; - -- Reset ADCs - fmc_reset_adcs_n_o : out std_logic; - --FMC Present status - fmc_prsnt_m2c_l_i : in std_logic; - - -- General board status - fmc_mmcm_lock_o : out std_logic; - fmc_lmk_lock_o : out std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - leds_o : out std_logic_vector(7 downto 0) -); -end dbe_bpm_dsp; - -architecture rtl of dbe_bpm_dsp is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 10; - -- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC, - --Etherbone, FMC516, Peripherals - -- Number of masters - constant c_masters : natural := 8; -- LM32 master, Data + Instruction, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone - - --constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB) - constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB) - --constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB) - --constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB) - constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB) - - -- GPIO num pinscalc - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- TICs counter period. 100MHz clock -> msec granularity - constant c_tics_cntr_period : natural := 100000; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - -- number of the ADC reference clock used for all downstream - -- FPGA logic - constant c_adc_ref_clk : natural := 1; - - -- DSP constants - constant c_dsp_ref_num_bits : natural := 24; - constant c_dsp_pos_num_bits : natural := 26; - - constant c_xwb_etherbone_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"0000000000000651", -- GSI - device_id => x"68202b22", - version => x"00000001", - date => x"20120912", - name => "GSI_ETHERBONE_CFG "))); - - constant c_xwb_ethmac_adapter_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"1000000000001215", -- LNLS - device_id => x"2ff9a28e", - version => x"00000001", - date => x"20130701", - name => "ETHMAC_ADAPTER "))); - - -- FMC516 layout. Size (0x00000FFF) is larger than needed. Just to be sure - -- no address overlaps will occur - constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - - -- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter - constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400"); - - -- WB SDB (Self describing bus) layout - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory - 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - x"20000000"), -- 64KB RAM - 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port - 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port - 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port - 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port - 7 => f_sdb_embed_device(c_xwb_position_calc_core_sdb, - x"30008000"), -- Position Calc Core control port - 8 => f_sdb_embed_bridge(c_fmc516_bridge_sdb, x"30010000"), -- FMC516 control port - 9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well - constant c_sdb_address : t_wishbone_address := x"30000000"; - - -- FMC516 ADC data constants - constant c_adc_data_ch0_lsb : natural := 0; - constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb; - - constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1; - constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb; - - constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1; - constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb; - - constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1; - constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - -- Only one clock domain - signal reset_clks : std_logic_vector(0 downto 0); - signal reset_rstn : std_logic_vector(0 downto 0); - - -- 200 Mhz clocck for iodelay_ctrl - signal clk_200mhz : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - - -- Ethernet MAC signals - signal ethmac_int : std_logic; - signal ethmac_md_in : std_logic; - signal ethmac_md_out : std_logic; - signal ethmac_md_oe : std_logic; - - signal mtxd_pad_int : std_logic_vector(3 downto 0); - signal mtxen_pad_int : std_logic; - signal mtxerr_pad_int : std_logic; - signal mdc_pad_int : std_logic; - - -- Ethrnet MAC adapter signals - signal irq_rx_done : std_logic; - signal irq_tx_done : std_logic; - - -- Etherbone signals - signal wb_ebone_out : t_wishbone_master_out; - signal wb_ebone_in : t_wishbone_master_in; - - signal eb_src_i : t_wrf_source_in; - signal eb_src_o : t_wrf_source_out; - signal eb_snk_i : t_wrf_sink_in; - signal eb_snk_o : t_wrf_sink_out; - - -- DMA signals - signal dma_int : std_logic; - - -- FMC516 Signals - signal wbs_fmc516_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0); - signal wbs_fmc516_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0); - - signal fmc516_mmcm_lock_int : std_logic; - signal fmc516_lmk_lock_int : std_logic; - - signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0); - signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0); - - --signal fmc_debug : std_logic; - --signal reset_adc_counter : unsigned(6 downto 0) := (others => '0'); - signal fs_rst_sync_n : std_logic; - signal fs_rst_n : std_logic; - - -- FMC516 Debug - signal fmc516_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0); - - signal sys_spi_clk_int : std_logic; - --signal sys_spi_data_int : std_logic; - signal sys_spi_dout_int : std_logic; - signal sys_spi_din_int : std_logic; - signal sys_spi_miosio_oe_n_int : std_logic; - signal sys_spi_cs_adc0_n_int : std_logic; - signal sys_spi_cs_adc1_n_int : std_logic; - signal sys_spi_cs_adc2_n_int : std_logic; - signal sys_spi_cs_adc3_n_int : std_logic; - - signal lmk_lock_int : std_logic; - signal lmk_sync_int : std_logic; - signal lmk_uwire_latch_en_int : std_logic; - signal lmk_uwire_data_int : std_logic; - signal lmk_uwire_clock_int : std_logic; - - signal fmc_reset_adcs_n_int : std_logic; - signal fmc_reset_adcs_n_out : std_logic; - - -- DSP signals - signal dsp_sysce : std_logic; - signal dsp_sysce_clr : std_logic; - signal dsp_sysclk : std_logic; - signal dsp_sysclk2x : std_logic; - signal dsp_rst_n : std_logic; - - signal dsp_kx : std_logic_vector(24 downto 0); - signal dsp_ky : std_logic_vector(24 downto 0); - signal dsp_ksum : std_logic_vector(24 downto 0); - - signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0); - - signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0); - signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0); - - signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0); - - signal dsp_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - - signal dsp_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - - signal dsp_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - signal dsp_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0); - - signal dsp_tbt_decim_q_ch01_incorrect : std_logic; - signal dsp_tbt_decim_q_ch23_incorrect : std_logic; - signal dsp_fofb_decim_q_01_missing : std_logic; - signal dsp_fofb_decim_q_23_missing : std_logic; - signal dsp_monit_cic_unexpected : std_logic; - signal dsp_monit_cfir_incorrect : std_logic; - signal dsp_monit_pfir_incorrect : std_logic; - - signal dsp_clk_ce_1 : std_logic; - signal dsp_clk_ce_2 : std_logic; - signal dsp_clk_ce_35 : std_logic; - signal dsp_clk_ce_70 : std_logic; - signal dsp_clk_ce_1390000 : std_logic; - signal dsp_clk_ce_1112 : std_logic; - signal dsp_clk_ce_2224 : std_logic; - signal dsp_clk_ce_11120000 : std_logic; - signal dsp_clk_ce_22240000 : std_logic; - signal dsp_clk_ce_5000 : std_logic; - signal dsp_clk_ce_556 : std_logic; - signal dsp_clk_ce_2780000 : std_logic; - signal dsp_clk_ce_5560000 : std_logic; - - signal clk_rffe_swap : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - -- Counter signal - --signal s_counter : unsigned(c_counter_width-1 downto 0); - -- 100MHz period or 1 second - --constant s_counter_full : integer := 100000000; - - -- Chipscope control signals - signal CONTROL0 : std_logic_vector(35 downto 0); - signal CONTROL1 : std_logic_vector(35 downto 0); - signal CONTROL2 : std_logic_vector(35 downto 0); - signal CONTROL3 : std_logic_vector(35 downto 0); - signal CONTROL4 : std_logic_vector(35 downto 0); - signal CONTROL5 : std_logic_vector(35 downto 0); - signal CONTROL6 : std_logic_vector(35 downto 0); - - -- Chipscope ILA 0 signals - signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 1 signals - signal TRIG_ILA1_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_4 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 2 signals - signal TRIG_ILA2_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA2_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_3 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_4 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 3 signals - signal TRIG_ILA3_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA3_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_3 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_4 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 4 signals - signal TRIG_ILA4_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA4_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA4_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA4_3 : std_logic_vector(31 downto 0); - signal TRIG_ILA4_4 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 5 signals - signal TRIG_ILA5_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA5_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA5_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA5_3 : std_logic_vector(31 downto 0); - signal TRIG_ILA5_4 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 6 signals - signal TRIG_ILA6_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA6_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA6_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA6_3 : std_logic_vector(31 downto 0); - signal TRIG_ILA6_4 : std_logic_vector(31 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic - ); - end component; - - -- Xilinx Megafunction - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Controller 2 port - --component chipscope_icon_2_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0) - --); - --end component; - - --component chipscope_icon_4_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0); - -- CONTROL2 : inout std_logic_vector(35 downto 0); - -- CONTROL3 : inout std_logic_vector(35 downto 0) - --); - --end component; - - --component chipscope_icon_8_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0); - -- CONTROL2 : inout std_logic_vector(35 downto 0); - -- CONTROL3 : inout std_logic_vector(35 downto 0); - -- CONTROL4 : inout std_logic_vector(35 downto 0); - -- CONTROL5 : inout std_logic_vector(35 downto 0); - -- CONTROL6 : inout std_logic_vector(35 downto 0); - -- CONTROL7 : inout std_logic_vector(35 downto 0) - --); - --end component; - - component chipscope_icon_7_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0); - CONTROL2 : inout std_logic_vector(35 downto 0); - CONTROL3 : inout std_logic_vector(35 downto 0); - CONTROL4 : inout std_logic_vector(35 downto 0); - CONTROL5 : inout std_logic_vector(35 downto 0); - CONTROL6 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0) - ); - end component; - - component chipscope_ila_8192 - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(7 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0); - TRIG4 : in std_logic_vector(31 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; - -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - clk_i => sys_clk_gen, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => 1 -- CLK_SYS - ) - port map( - free_clk_i => sys_clk_gen, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(0) <= clk_sys; - clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n; - clk_sys_rst <= not clk_sys_rstn; - mrstn_o <= clk_sys_rstn; - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => true, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - lm32_rstn <= clk_sys_rstn; - - cmp_lm32 : xwb_lm32 - generic map( - g_profile => "medium_icache_debug" - ) -- Including JTAG and I-cache (no divide) - port map( - clk_sys_i => clk_sys, - rst_n_i => lm32_rstn, - irq_i => lm32_interrupt, - dwb_o => cbar_slave_i(0), -- Data bus - dwb_i => cbar_slave_o(0), - iwb_o => cbar_slave_i(1), -- Instruction bus - iwb_i => cbar_slave_o(1) - ); - - -- Interrupt '0' is Ethmac. - -- Interrupt '1' is DMA completion. - -- Interrupt '2' is Button(0). - -- Interrupt '3' is Ethernet Adapter RX completion. - -- Interrupt '4' is Ethernet Adapter TX completion. - -- Interrupts 31 downto 5 are disabled - - lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done, - 4 => irq_tx_done, others => '0'); - - -- A DMA controller is master 2+3, slave 3, and interrupt 1 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(3), - slave_o => cbar_master_i(3), - r_master_i => cbar_slave_o(2), - r_master_o => cbar_slave_i(2), - w_master_i => cbar_slave_o(3), - w_master_o => cbar_slave_i(3), - interrupt_o => dma_int - ); - - -- Slave 0+1 is the RAM. Load a input file containing the embedded software - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - g_init_file => "../../../embedded-sw/dbe.ram", - --"../../top/ml_605/dbe_bpm_simple/sw/main.ram", - g_must_have_init_file => true, - g_slave1_interface_mode => PIPELINED, - g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE, - g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - ); - - -- Slave 2 is the RAM Buffer for Ethernet MAC. - cmp_ethmac_buf_ram : xwb_dpram - generic map( - g_size => c_dpram_ethbuf_size, - g_init_file => "", - g_must_have_init_file => false, - g_slave1_interface_mode => CLASSIC, - --g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE - --g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(2), - slave1_o => cbar_master_i(2), - -- Second port connected to the crossbar - slave2_i => cc_dummy_slave_in, -- CYC always low - slave2_o => open - ); - - -- The Ethernet MAC is master 4, slave 4 - cmp_xwb_ethmac : xwb_ethmac - generic map ( - --g_ma_interface_mode => PIPELINED, - g_ma_interface_mode => CLASSIC, -- NOT used for now - --g_ma_address_granularity => WORD, - g_ma_address_granularity => BYTE, -- NOT used for now - g_sl_interface_mode => PIPELINED, - --g_sl_interface_mode => CLASSIC, - --g_sl_address_granularity => WORD - g_sl_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - - -- WISHBONE slave - wb_slave_in => cbar_master_o(4), - wb_slave_out => cbar_master_i(4), - - -- WISHBONE master - wb_master_in => cbar_slave_o(4), - wb_master_out => cbar_slave_i(4), - - -- PHY TX - mtx_clk_pad_i => mtx_clk_pad_i, - --mtxd_pad_o => mtxd_pad_o, - mtxd_pad_o => mtxd_pad_int, - --mtxen_pad_o => mtxen_pad_o, - mtxen_pad_o => mtxen_pad_int, - --mtxerr_pad_o => mtxerr_pad_o, - mtxerr_pad_o => mtxerr_pad_int, - - -- PHY RX - mrx_clk_pad_i => mrx_clk_pad_i, - mrxd_pad_i => mrxd_pad_i, - mrxdv_pad_i => mrxdv_pad_i, - mrxerr_pad_i => mrxerr_pad_i, - mcoll_pad_i => mcoll_pad_i, - mcrs_pad_i => mcrs_pad_i, - - -- MII - --mdc_pad_o => mdc_pad_o, - mdc_pad_o => mdc_pad_int, - md_pad_i => ethmac_md_in, - md_pad_o => ethmac_md_out, - md_padoe_o => ethmac_md_oe, - - -- Interrupt - int_o => ethmac_int - ); - - ---- Tri-state buffer for MII config - md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z'; - ethmac_md_in <= md_pad_b; - - mtxd_pad_o <= mtxd_pad_int; - mtxen_pad_o <= mtxen_pad_int; - mtxerr_pad_o <= mtxerr_pad_int; - mdc_pad_o <= mdc_pad_int; - - --The Ethernet MAC Adapter is master 5+6, slave 5 - cmp_xwb_ethmac_adapter : xwb_ethmac_adapter - port map( - clk_i => clk_sys, - rstn_i => clk_sys_rstn, - - wb_slave_o => cbar_master_i(5), - wb_slave_i => cbar_master_o(5), - - tx_ram_o => cbar_slave_i(5), - tx_ram_i => cbar_slave_o(5), - - rx_ram_o => cbar_slave_i(6), - rx_ram_i => cbar_slave_o(6), - - rx_eb_o => eb_snk_i, - rx_eb_i => eb_snk_o, - - tx_eb_o => eb_src_i, - tx_eb_i => eb_src_o, - - irq_tx_done_o => irq_tx_done, - irq_rx_done_o => irq_rx_done - ); - - -- The Etherbone is slave 6 - cmp_eb_slave_core : eb_slave_core - generic map( - g_sdb_address => x"00000000" & c_sdb_address - ) - port map - ( - clk_i => clk_sys, - nRst_i => clk_sys_rstn, - - -- EB streaming sink - snk_i => eb_snk_i, - snk_o => eb_snk_o, - - -- EB streaming source - src_i => eb_src_i, - src_o => eb_src_o, - - -- WB slave - Cfg IF - cfg_slave_o => cbar_master_i(6), - cfg_slave_i => cbar_master_o(6), - - -- WB master - Bus IF - master_o => wb_ebone_out, - master_i => wb_ebone_in - ); - - cbar_slave_i(7) <= wb_ebone_out; - wb_ebone_in <= cbar_slave_o(7); - - -- The FMC516 is slave 8 - cmp_xwb_fmc516 : xwb_fmc516 - generic map( - g_fpga_device => "VIRTEX6", - g_interface_mode => PIPELINED, - --g_address_granularity => WORD, - g_address_granularity => BYTE, - --g_adc_clk_period_values => default_adc_clk_period_values, - g_adc_clk_period_values => (0.0, 0.0, 8.882, 8.882), --476.066*35/148 aprox 112.583 MHz - --g_use_clk_chains => default_clk_use_chain, - -- using clock1 from FMC516 (CLK2_ M2C_P, CLK2_ M2C_M pair) - -- using clock0 from FMC516. - -- BUFIO can drive half-bank only, not the full IO bank - g_use_clk_chains => "0011", - g_use_data_chains => "1111", - g_map_clk_data_chains => (1,0,0,1), - -- Clock 1 is the adc reference clock - g_ref_clk => c_adc_ref_clk, - g_packet_size => 32, - g_sim => 0 - ) - port map( - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - sys_clk_200Mhz_i => clk_200mhz, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(8), - wb_slv_o => cbar_master_i(8), - - ----------------------------- - -- External ports - ----------------------------- - -- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM, - -- AD7417 temperature diodes and AD7417 supply rails - sys_i2c_scl_b => sys_i2c_scl_b, - sys_i2c_sda_b => sys_i2c_sda_b, - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - adc_clk0_p_i => adc_clk0_p_i, - adc_clk0_n_i => adc_clk0_n_i, - adc_clk1_p_i => adc_clk1_p_i, - adc_clk1_n_i => adc_clk1_n_i, - adc_clk2_p_i => adc_clk2_p_i, - adc_clk2_n_i => adc_clk2_n_i, - adc_clk3_p_i => adc_clk3_p_i, - adc_clk3_n_i => adc_clk3_n_i, - - -- DDR ADC data channels. - adc_data_ch0_p_i => adc_data_ch0_p_i, - adc_data_ch0_n_i => adc_data_ch0_n_i, - adc_data_ch1_p_i => adc_data_ch1_p_i, - adc_data_ch1_n_i => adc_data_ch1_n_i, - adc_data_ch2_p_i => adc_data_ch2_p_i, - adc_data_ch2_n_i => adc_data_ch2_n_i, - adc_data_ch3_p_i => adc_data_ch3_p_i, - adc_data_ch3_n_i => adc_data_ch3_n_i, - - -- ADC clock (half of the sampling frequency) divider reset - adc_clk_div_rst_p_o => adc_clk_div_rst_p_o, - adc_clk_div_rst_n_o => adc_clk_div_rst_n_o, - - -- FMC Front leds. Typical uses: Over Range or Full Scale - -- condition. - fmc_leds_o => fmc_leds_o, - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - sys_spi_clk_o => sys_spi_clk_int,--sys_spi_clk_o, - sys_spi_data_b => sys_spi_data_b, - --sys_spi_dout_o => sys_spi_dout_int, - --sys_spi_din_i => sys_spi_din_int, - sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0 - sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1 - sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2 - sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3 - --sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int, - - -- External Trigger To/From FMC - m2c_trig_p_i => m2c_trig_p_i, - m2c_trig_n_i => m2c_trig_n_i, - c2m_trig_p_o => c2m_trig_p_o, - c2m_trig_n_o => c2m_trig_n_o, - - -- LMK (National Semiconductor) is the clock and distribution IC. - -- uWire interface - lmk_lock_i => lmk_lock_int,--lmk_lock_i, - lmk_sync_o => lmk_sync_int,--lmk_sync_o, - lmk_uwire_latch_en_o => lmk_uwire_latch_en_int,--lmk_uwire_latch_en_o, - lmk_uwire_data_o => lmk_uwire_data_int,--lmk_uwire_data_o, - lmk_uwire_clock_o => lmk_uwire_clock_int,--lmk_uwire_clock_o, - - -- Programable VCXO via I2C - vcxo_i2c_sda_b => vcxo_i2c_sda_b, - vcxo_i2c_scl_o => vcxo_i2c_scl_o, - vcxo_pd_l_o => vcxo_pd_l_o, - - -- One-wire To/From DS2431 (VMETRO Data) - fmc_id_dq_b => fmc_id_dq_b, - -- One-wire To/From DS2432 SHA-1 (SP-Devices key) - fmc_key_dq_b => fmc_key_dq_b, - - -- General board pins - fmc_pwr_good_i => fmc_pwr_good_i, - -- Internal/External clock distribution selection - fmc_clk_sel_o => fmc_clk_sel_o, - -- Reset ADCs - fmc_reset_adcs_n_o => fmc_reset_adcs_n_o,--fmc_reset_adcs_n_int, - --FMC Present status - fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i, - - ----------------------------- - -- ADC output signals. Continuous flow. - ----------------------------- - adc_clk_o => fmc516_fs_clk, - adc_clk2x_o => fmc516_fs_clk2x, - adc_rst_n_o => open, - adc_data_o => fmc516_adc_data, - adc_data_valid_o => fmc516_adc_valid, - - ----------------------------- - -- General ADC output signals - ----------------------------- - -- Trigger to other FPGA logic - trig_hw_o => open, - trig_hw_i => clk_rffe_swap, -- from Position Calculation Core - -- General board status - fmc_mmcm_lock_o => fmc516_mmcm_lock_int, - fmc_lmk_lock_o => fmc516_lmk_lock_int, - - ----------------------------- - -- Wishbone Streaming Interface Source - ----------------------------- - wbs_source_i => wbs_fmc516_in_array, - wbs_source_o => wbs_fmc516_out_array, - - adc_dly_debug_o => adc_dly_debug_int, - - fifo_debug_valid_o => fmc516_debug_valid_int, - fifo_debug_full_o => fmc516_debug_full_int, - fifo_debug_empty_o => fmc516_debug_empty_int - ); - - gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate - wbs_fmc516_in_array(i) <= cc_dummy_src_com_in; - end generate; - - fmc_mmcm_lock_o <= fmc516_mmcm_lock_int; - fmc_lmk_lock_o <= fmc516_lmk_lock_int; - - sys_spi_clk_o <= sys_spi_clk_int; - sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int; - sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int; - sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int; - sys_spi_cs_adc3_n_o <= sys_spi_cs_adc3_n_int; - - lmk_lock_int <= lmk_lock_i; - lmk_sync_o <= lmk_sync_int; - lmk_uwire_latch_en_o <= lmk_uwire_latch_en_int; - lmk_uwire_data_o <= lmk_uwire_data_int; - lmk_uwire_clock_o <= lmk_uwire_clock_int; - - -- Position calc core is slave 7 - cmp_xwb_position_calc_core : xwb_position_calc_core - generic map ( - g_interface_mode => PIPELINED, - g_address_granularity => WORD - ) - port map ( - rst_n_i => clk_sys_rstn, - clk_i => clk_sys, -- wishbone clock - fs_clk_i => dsp_sysclk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz) - - ----------------------------- - -- Wishbone signals - ----------------------------- - wb_slv_i => cbar_master_o(7), - wb_slv_o => cbar_master_i(7), - - ----------------------------- - -- Raw ADC signals - ----------------------------- - adc_ch0_i => fmc516_adc_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb), - adc_ch1_i => fmc516_adc_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb), - adc_ch2_i => fmc516_adc_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb), - adc_ch3_i => fmc516_adc_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb), - - ----------------------------- - -- DSP config parameter signals - ----------------------------- - kx => dsp_kx, - ky => dsp_ky, - ksum => dsp_ksum, - - del_sig_div_fofb_thres_i => dsp_del_sig_div_thres, - del_sig_div_tbt_thres_i => dsp_del_sig_div_thres, - del_sig_div_monit_thres_i => dsp_del_sig_div_thres, - - ----------------------------- - -- Position calculation at various rates - ----------------------------- - adc_ch0_dbg_data_o => dsp_adc_ch0_data, - adc_ch1_dbg_data_o => dsp_adc_ch1_data, - adc_ch2_dbg_data_o => dsp_adc_ch2_data, - adc_ch3_dbg_data_o => dsp_adc_ch3_data, - - bpf_ch0_o => dsp_bpf_ch0, - --bpf_ch1_o => out std_logic_vector(23 downto 0); - bpf_ch2_o => dsp_bpf_ch2, - --bpf_ch3_o => out std_logic_vector(23 downto 0); - - mix_ch0_i_o => dsp_mix_ch0, - --mix_ch0_q_o => out std_logic_vector(23 downto 0); - --mix_ch1_i_o => out std_logic_vector(23 downto 0); - --mix_ch1_q_o => out std_logic_vector(23 downto 0); - mix_ch2_i_o => dsp_mix_ch2, - --mix_ch2_q_o => out std_logic_vector(23 downto 0); - --mix_ch3_i_o => out std_logic_vector(23 downto 0); - --mix_ch3_q_o => out std_logic_vector(23 downto 0); - - tbt_decim_ch0_i_o => dsp_poly35_ch0, - --tbt_decim_ch0_i_o => open, - --poly35_ch0_q_o => out std_logic_vector(23 downto 0); - --poly35_ch1_i_o => out std_logic_vector(23 downto 0); - --poly35_ch1_q_o => out std_logic_vector(23 downto 0); - tbt_decim_ch2_i_o => dsp_poly35_ch2, - --tbt_decim_ch2_i_o => open, - --poly35_ch2_q_o => out std_logic_vector(23 downto 0); - --poly35_ch3_i_o => out std_logic_vector(23 downto 0); - --poly35_ch3_q_o => out std_logic_vector(23 downto 0); - - tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect, - tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect, - - tbt_amp_ch0_o => dsp_tbt_amp_ch0, - tbt_amp_ch1_o => dsp_tbt_amp_ch1, - tbt_amp_ch2_o => dsp_tbt_amp_ch2, - tbt_amp_ch3_o => dsp_tbt_amp_ch3, - - fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0); - --cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0); - fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0); - --cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0); - --cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0); - - fofb_decim_q_01_missing_o => dsp_fofb_decim_q_01_missing, - fofb_decim_q_23_missing_o => dsp_fofb_decim_q_23_missing, - - fofb_amp_ch0_o => dsp_fofb_amp_ch0, - fofb_amp_ch1_o => dsp_fofb_amp_ch1, - fofb_amp_ch2_o => dsp_fofb_amp_ch2, - fofb_amp_ch3_o => dsp_fofb_amp_ch3, - - monit_amp_ch0_o => dsp_monit_amp_ch0, - monit_amp_ch1_o => dsp_monit_amp_ch1, - monit_amp_ch2_o => dsp_monit_amp_ch2, - monit_amp_ch3_o => dsp_monit_amp_ch3, - - x_tbt_o => dsp_x_tbt, - y_tbt_o => dsp_y_tbt, - q_tbt_o => dsp_q_tbt, - sum_tbt_o => dsp_sum_tbt, - - x_fofb_o => dsp_x_fofb, - y_fofb_o => dsp_y_fofb, - q_fofb_o => dsp_q_fofb, - sum_fofb_o => dsp_sum_fofb, - - x_monit_o => dsp_x_monit, - y_monit_o => dsp_y_monit, - q_monit_o => dsp_q_monit, - sum_monit_o => dsp_sum_monit, - - monit_cic_unexpected_o => dsp_monit_cic_unexpected, - monit_cfir_incorrect_o => dsp_monit_cfir_incorrect, - monit_pfir_incorrect_o => dsp_monit_pfir_incorrect, - - ----------------------------- - -- Output to RFFE board - ----------------------------- - clk_swap_o => clk_rffe_swap, - ctrl1_o => open, - ctrl2_o => open, - - ----------------------------- - -- Clock drivers for various rates - ----------------------------- - clk_ce_1_o => dsp_clk_ce_1, - clk_ce_1112_o => dsp_clk_ce_1112, - clk_ce_11120000_o => dsp_clk_ce_11120000, - clk_ce_1390000_o => dsp_clk_ce_1390000, - clk_ce_2_o => dsp_clk_ce_2, - clk_ce_2224_o => dsp_clk_ce_2224, - clk_ce_22240000_o => dsp_clk_ce_22240000, - clk_ce_2780000_o => dsp_clk_ce_2780000, - clk_ce_35_o => dsp_clk_ce_35, - clk_ce_5000_o => dsp_clk_ce_5000, - clk_ce_556_o => dsp_clk_ce_556, - clk_ce_5560000_o => dsp_clk_ce_5560000, - clk_ce_70_o => dsp_clk_ce_70 - ); - - --dsp_poly35_ch0 <= (others => '0'); - --dsp_poly35_ch2 <= (others => '0'); - -- - --dsp_monit_amp_ch0 <= (others => '0'); - --dsp_monit_amp_ch1 <= (others => '0'); - --dsp_monit_amp_ch2 <= (others => '0'); - --dsp_monit_amp_ch3 <= (others => '0'); - - -- Signals for the DSP chain - dsp_sysce <= '1'; - dsp_sysce_clr <= '0'; - --dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk); - dsp_sysclk2x <= fmc516_fs_clk2x(c_adc_ref_clk); -- oversampled DSP chain - dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk); -- oversampled DSP chain - --dsp_rst_n <= fmc516_fs_rst_n(c_adc_ref_clk); - dsp_del_sig_div_thres <= "00000000000000001000000000"; -- aprox 1.22e-4 FIX26_22 - - --dsp_kx <= "100110001001011010000000"; -- 10000000 UFIX24_0 - dsp_kx <= "0100000000000000000000000"; -- ??? UFIX25_0 - --dsp_kx <= "00100110001001011010000000"; -- 10000000 UFIX26_0 - --dsp_ky <= "100110001001011010000000"; -- 10000000 UFIX24_0 - dsp_ky <= "0100000000000000000000000"; -- ??? UFIX25_0 - --dsp_ky <= "00100110001001011010000000"; -- 10000000 UFIX26_0 - dsp_ksum <= "0111111111111111111111111"; -- 1.0 FIX25_24 - --dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25 - --dsp_ksum <= "100000000000000000000000"; -- 1.0 FIX24_23 - --dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25 - - -- The board peripherals components is slave 9 - cmp_xwb_dbe_periph : xwb_dbe_periph - generic map( - -- NOT used! - --g_interface_mode : t_wishbone_interface_mode := CLASSIC; - -- NOT used! - --g_address_granularity : t_wishbone_address_granularity := WORD; - g_cntr_period => c_tics_cntr_period, - g_num_leds => c_leds_num_pins, - g_num_buttons => c_buttons_num_pins - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- UART - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o, - - -- LEDs - led_out_o => gpio_leds_int, - led_in_i => gpio_leds_int, - led_oen_o => open, - - -- Buttons - button_out_o => open, - button_in_i => buttons_i, - button_oen_o => open, - - -- Wishbone - slave_i => cbar_master_o(9), - slave_o => cbar_master_i(9) - ); - - leds_o <= gpio_leds_int; - - ---- Xilinx Chipscope - --cmp_chipscope_icon_0 : chipscope_icon_4_port - --port map ( - -- CONTROL0 => CONTROL0, - -- CONTROL1 => CONTROL1, - -- CONTROL2 => CONTROL2, - -- CONTROL3 => CONTROL3 - --); - - cmp_chipscope_icon_7_port : chipscope_icon_7_port - port map ( - CONTROL0 => CONTROL0, - CONTROL1 => CONTROL1, - CONTROL2 => CONTROL2, - CONTROL3 => CONTROL3, - CONTROL4 => CONTROL4, - CONTROL5 => CONTROL5, - CONTROL6 => CONTROL6 - ); - - cmp_chipscope_ila_0_fmc516_adc : chipscope_ila - port map ( - CONTROL => CONTROL0, - CLK => fmc516_fs_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA0_0, - TRIG1 => TRIG_ILA0_1, - TRIG2 => TRIG_ILA0_2, - TRIG3 => TRIG_ILA0_3 - ); - - -- FMC516 WBS master output data - --TRIG_ILA0_0 <= fmc516_adc_data(31 downto 16) & - -- fmc516_adc_data(47 downto 32); - TRIG_ILA0_0 <= dsp_adc_ch1_data & - dsp_adc_ch0_data; - - TRIG_ILA0_1 <= dsp_adc_ch3_data & - dsp_adc_ch2_data; - - TRIG_ILA0_2 <= (others => '0'); - TRIG_ILA0_3 <= (others => '0'); - -- FMC516 WBS master output data - --TRIG_ILA0_1(11 downto 0) <= adc_dly_reg_debug_int(1).clk_load & - -- adc_dly_reg_debug_int(1).data_load & - -- adc_dly_reg_debug_int(1).clk_dly_reg & - -- adc_dly_reg_debug_int(1).data_dly_reg; - --TRIG_ILA0_1(31 downto 12) <= (others => '0'); - - ---- FMC516 WBS master output control signals - --TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc & - -- wbs_fmc516_out_array(1).stb & - -- wbs_fmc516_out_array(1).adr & - -- wbs_fmc516_out_array(1).sel & - -- wbs_fmc516_out_array(1).we & - -- wbs_fmc516_out_array(2).cyc & - -- wbs_fmc516_out_array(2).stb & - -- wbs_fmc516_out_array(2).adr & - -- wbs_fmc516_out_array(2).sel & - -- wbs_fmc516_out_array(2).we; - --TRIG_ILA0_2(18) <= fmc_reset_adcs_n_out; - --TRIG_ILA0_2(22 downto 19) <= fmc516_adc_valid; - --TRIG_ILA0_2(23) <= fmc516_mmcm_lock_int; - --TRIG_ILA0_2(24) <= fmc516_lmk_lock_int; - --TRIG_ILA0_2(25) <= fmc516_debug_valid_int(1); - --TRIG_ILA0_2(26) <= fmc516_debug_full_int(1); - --TRIG_ILA0_2(27) <= fmc516_debug_empty_int(1); - --TRIG_ILA0_2(31 downto 28) <= (others => '0'); - -- - --TRIG_ILA0_3 <= dsp_adc_ch3_data & - -- dsp_adc_ch2_data; - - -- Mix and BPF data - cmp_chipscope_ila_8192_bpf_mix : chipscope_ila_8192 - port map ( - CONTROL => CONTROL1, - CLK => dsp_sysclk, - TRIG0 => TRIG_ILA1_0, - TRIG1 => TRIG_ILA1_1, - TRIG2 => TRIG_ILA1_2, - TRIG3 => TRIG_ILA1_3, - TRIG4 => TRIG_ILA1_4 - ); - - TRIG_ILA1_0(0) <= dsp_clk_ce_1; - TRIG_ILA1_0(1) <= dsp_clk_ce_35; - TRIG_ILA1_0(2) <= dsp_clk_ce_1112; - TRIG_ILA1_0(3) <= dsp_clk_ce_1390000; -- not used - TRIG_ILA1_0(4) <= dsp_clk_ce_2780000; - TRIG_ILA1_0(5) <= dsp_clk_ce_11120000; - TRIG_ILA1_0(7 downto 6) <= (others => '0'); - - --TRIG_ILA1_1(dsp_bpf_ch0'range) <= dsp_bpf_ch0; - --TRIG_ILA1_2(dsp_bpf_ch2'range) <= dsp_bpf_ch2; - --TRIG_ILA1_1(dsp_poly35_ch0'range) <= dsp_poly35_ch0; - --TRIG_ILA1_2(dsp_poly35_ch2'range) <= dsp_poly35_ch2; - --TRIG_ILA1_3(dsp_cic_fofb_ch0'range) <= dsp_cic_fofb_ch0; - --TRIG_ILA1_4(dsp_cic_fofb_ch2'range) <= dsp_cic_fofb_ch2; - TRIG_ILA1_1(dsp_monit_amp_ch0'range) <= dsp_monit_amp_ch0; - TRIG_ILA1_2(dsp_monit_amp_ch1'range) <= dsp_monit_amp_ch1; - TRIG_ILA1_3(dsp_monit_amp_ch2'range) <= dsp_monit_amp_ch2; - TRIG_ILA1_4(dsp_monit_amp_ch3'range) <= dsp_monit_amp_ch3; - - TRIG_ILA1_4(dsp_monit_amp_ch3'left+3 downto - dsp_monit_amp_ch3'left+1) <= dsp_monit_cic_unexpected & - dsp_monit_cfir_incorrect & - dsp_monit_pfir_incorrect; - - -- TBT amplitudes data - cmp_chipscope_ila_8192_tbt_amp : chipscope_ila_8192 - port map ( - CONTROL => CONTROL2, - CLK => dsp_sysclk, - TRIG0 => TRIG_ILA2_0, - TRIG1 => TRIG_ILA2_1, - TRIG2 => TRIG_ILA2_2, - TRIG3 => TRIG_ILA2_3, - TRIG4 => TRIG_ILA2_4 - ); - - TRIG_ILA2_0(0) <= dsp_clk_ce_1; - TRIG_ILA2_0(1) <= dsp_clk_ce_35; - TRIG_ILA2_0(2) <= dsp_clk_ce_1112; - TRIG_ILA2_0(3) <= dsp_clk_ce_1390000; - TRIG_ILA2_0(4) <= dsp_clk_ce_2780000; -- not used - TRIG_ILA2_0(5) <= dsp_clk_ce_11120000; - TRIG_ILA2_0(7 downto 6) <= (others => '0'); - - TRIG_ILA2_1(dsp_tbt_amp_ch0'range) <= dsp_tbt_amp_ch0; - TRIG_ILA2_2(dsp_tbt_amp_ch1'range) <= dsp_tbt_amp_ch1; - TRIG_ILA2_3(dsp_tbt_amp_ch2'range) <= dsp_tbt_amp_ch2; - TRIG_ILA2_4(dsp_tbt_amp_ch3'range) <= dsp_tbt_amp_ch3; - TRIG_ILA2_4(dsp_tbt_amp_ch3'left+2 downto - dsp_tbt_amp_ch3'left+1) <= dsp_tbt_decim_q_ch01_incorrect & - dsp_tbt_decim_q_ch23_incorrect; - - -- TBT position data - cmp_chipscope_ila_8192_tbt_pos : chipscope_ila_8192 - port map ( - CONTROL => CONTROL3, - CLK => dsp_sysclk, - TRIG0 => TRIG_ILA3_0, - TRIG1 => TRIG_ILA3_1, - TRIG2 => TRIG_ILA3_2, - TRIG3 => TRIG_ILA3_3, - TRIG4 => TRIG_ILA3_4 - ); - - TRIG_ILA3_0(0) <= dsp_clk_ce_1; - TRIG_ILA3_0(1) <= dsp_clk_ce_35; - TRIG_ILA3_0(2) <= dsp_clk_ce_1112; - TRIG_ILA3_0(3) <= dsp_clk_ce_1390000; - TRIG_ILA3_0(4) <= dsp_clk_ce_2780000; -- not used - TRIG_ILA3_0(5) <= dsp_clk_ce_11120000; - TRIG_ILA3_0(7 downto 6) <= (others => '0'); - - TRIG_ILA3_1(dsp_x_tbt'range) <= dsp_x_tbt; - TRIG_ILA3_2(dsp_y_tbt'range) <= dsp_y_tbt; - TRIG_ILA3_3(dsp_q_tbt'range) <= dsp_q_tbt; - TRIG_ILA3_4(dsp_sum_tbt'range) <= dsp_sum_tbt; - - -- FOFB amplitudes data - cmp_chipscope_ila_8192_fofb_amp : chipscope_ila_8192 - port map ( - CONTROL => CONTROL4, - CLK => dsp_sysclk, - TRIG0 => TRIG_ILA4_0, - TRIG1 => TRIG_ILA4_1, - TRIG2 => TRIG_ILA4_2, - TRIG3 => TRIG_ILA4_3, - TRIG4 => TRIG_ILA4_4 - ); - - TRIG_ILA4_0(0) <= dsp_clk_ce_1; - TRIG_ILA4_0(1) <= dsp_clk_ce_35; - TRIG_ILA4_0(2) <= dsp_clk_ce_1112; - TRIG_ILA4_0(3) <= dsp_clk_ce_1390000; - TRIG_ILA4_0(4) <= dsp_clk_ce_2780000; -- not used - TRIG_ILA4_0(5) <= dsp_clk_ce_11120000; - TRIG_ILA4_0(7 downto 6) <= (others => '0'); - - TRIG_ILA4_1(dsp_fofb_amp_ch0'range) <= dsp_fofb_amp_ch0; - TRIG_ILA4_2(dsp_fofb_amp_ch1'range) <= dsp_fofb_amp_ch1; - TRIG_ILA4_3(dsp_fofb_amp_ch2'range) <= dsp_fofb_amp_ch2; - TRIG_ILA4_4(dsp_fofb_amp_ch3'range) <= dsp_fofb_amp_ch3; - TRIG_ILA4_4(dsp_fofb_amp_ch3'left+2 downto - dsp_fofb_amp_ch3'left+1) <= dsp_fofb_decim_q_01_missing & - dsp_fofb_decim_q_23_missing; - -- FOFB position data - cmp_chipscope_ila_8192_fofb_pos : chipscope_ila_8192 - port map ( - CONTROL => CONTROL5, - CLK => dsp_sysclk, - TRIG0 => TRIG_ILA5_0, - TRIG1 => TRIG_ILA5_1, - TRIG2 => TRIG_ILA5_2, - TRIG3 => TRIG_ILA5_3, - TRIG4 => TRIG_ILA5_4 - ); - - TRIG_ILA5_0(0) <= dsp_clk_ce_1; - TRIG_ILA5_0(1) <= dsp_clk_ce_35; - TRIG_ILA5_0(2) <= dsp_clk_ce_1112; - TRIG_ILA5_0(3) <= dsp_clk_ce_1390000; - TRIG_ILA5_0(4) <= dsp_clk_ce_2780000; -- not used - TRIG_ILA5_0(5) <= dsp_clk_ce_11120000; - TRIG_ILA5_0(7 downto 6) <= (others => '0'); - - TRIG_ILA5_1(dsp_x_fofb'range) <= dsp_x_fofb; - TRIG_ILA5_2(dsp_y_fofb'range) <= dsp_y_fofb; - TRIG_ILA5_3(dsp_q_fofb'range) <= dsp_q_fofb; - TRIG_ILA5_4(dsp_sum_fofb'range) <= dsp_sum_fofb; - - -- Monitoring position data - cmp_chipscope_ila_8192_monit_pos : chipscope_ila_8192 - port map ( - CONTROL => CONTROL6, - CLK => dsp_sysclk, - TRIG0 => TRIG_ILA6_0, - TRIG1 => TRIG_ILA6_1, - TRIG2 => TRIG_ILA6_2, - TRIG3 => TRIG_ILA6_3, - TRIG4 => TRIG_ILA6_4 - ); - - TRIG_ILA6_0(0) <= dsp_clk_ce_1; - TRIG_ILA6_0(1) <= dsp_clk_ce_35; - TRIG_ILA6_0(2) <= dsp_clk_ce_1112; - TRIG_ILA6_0(3) <= dsp_clk_ce_1390000; - TRIG_ILA6_0(4) <= dsp_clk_ce_2780000; -- not used - TRIG_ILA6_0(5) <= dsp_clk_ce_11120000; - TRIG_ILA6_0(7 downto 6) <= (others => '0'); - - TRIG_ILA6_1(dsp_x_monit'range) <= dsp_x_monit; - TRIG_ILA6_2(dsp_y_monit'range) <= dsp_y_monit; - TRIG_ILA6_3(dsp_q_monit'range) <= dsp_q_monit; - TRIG_ILA6_4(dsp_sum_monit'range) <= dsp_sum_monit; -end rtl; diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dsp_chipscope.cpj b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dsp_chipscope.cpj deleted file mode 100644 index c0a73ae1..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/dsp_chipscope.cpj +++ /dev/null @@ -1,6869 +0,0 @@ -#ChipScope Pro Analyzer Project File, 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-unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias= -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= -unit.1.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.10.name=TriggerPort3[10] -unit.1.0.port.3.s.10.orderindex=-1 -unit.1.0.port.3.s.10.visible=1 -unit.1.0.port.3.s.11.alias= -unit.1.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.11.name=TriggerPort3[11] -unit.1.0.port.3.s.11.orderindex=-1 -unit.1.0.port.3.s.11.visible=1 -unit.1.0.port.3.s.12.alias= -unit.1.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.12.name=TriggerPort3[12] -unit.1.0.port.3.s.12.orderindex=-1 -unit.1.0.port.3.s.12.visible=1 -unit.1.0.port.3.s.13.alias= -unit.1.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.13.name=TriggerPort3[13] -unit.1.0.port.3.s.13.orderindex=-1 -unit.1.0.port.3.s.13.visible=1 -unit.1.0.port.3.s.14.alias= -unit.1.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.14.name=TriggerPort3[14] -unit.1.0.port.3.s.14.orderindex=-1 -unit.1.0.port.3.s.14.visible=1 -unit.1.0.port.3.s.15.alias= -unit.1.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.15.name=TriggerPort3[15] -unit.1.0.port.3.s.15.orderindex=-1 -unit.1.0.port.3.s.15.visible=1 -unit.1.0.port.3.s.16.alias= -unit.1.0.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.16.name=TriggerPort3[16] -unit.1.0.port.3.s.16.orderindex=-1 -unit.1.0.port.3.s.16.visible=1 -unit.1.0.port.3.s.17.alias= -unit.1.0.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.17.name=TriggerPort3[17] -unit.1.0.port.3.s.17.orderindex=-1 -unit.1.0.port.3.s.17.visible=1 -unit.1.0.port.3.s.18.alias= -unit.1.0.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.18.name=TriggerPort3[18] -unit.1.0.port.3.s.18.orderindex=-1 -unit.1.0.port.3.s.18.visible=1 -unit.1.0.port.3.s.19.alias= -unit.1.0.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.19.name=TriggerPort3[19] -unit.1.0.port.3.s.19.orderindex=-1 -unit.1.0.port.3.s.19.visible=1 -unit.1.0.port.3.s.2.alias= -unit.1.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.2.name=TriggerPort3[2] -unit.1.0.port.3.s.2.orderindex=-1 -unit.1.0.port.3.s.2.visible=1 -unit.1.0.port.3.s.20.alias= -unit.1.0.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.20.name=TriggerPort3[20] -unit.1.0.port.3.s.20.orderindex=-1 -unit.1.0.port.3.s.20.visible=1 -unit.1.0.port.3.s.21.alias= -unit.1.0.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.21.name=TriggerPort3[21] -unit.1.0.port.3.s.21.orderindex=-1 -unit.1.0.port.3.s.21.visible=1 -unit.1.0.port.3.s.22.alias= -unit.1.0.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.22.name=TriggerPort3[22] -unit.1.0.port.3.s.22.orderindex=-1 -unit.1.0.port.3.s.22.visible=1 -unit.1.0.port.3.s.23.alias= -unit.1.0.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.23.name=TriggerPort3[23] -unit.1.0.port.3.s.23.orderindex=-1 -unit.1.0.port.3.s.23.visible=1 -unit.1.0.port.3.s.24.alias= -unit.1.0.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.24.name=TriggerPort3[24] -unit.1.0.port.3.s.24.orderindex=-1 -unit.1.0.port.3.s.24.visible=1 -unit.1.0.port.3.s.25.alias= -unit.1.0.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.25.name=TriggerPort3[25] -unit.1.0.port.3.s.25.orderindex=-1 -unit.1.0.port.3.s.25.visible=1 -unit.1.0.port.3.s.26.alias= -unit.1.0.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.26.name=TriggerPort3[26] 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-unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.0.waveform.posn.98.name=DataPort[98] -unit.1.0.waveform.posn.98.type=signal -unit.1.0.waveform.posn.99.channel=99 -unit.1.0.waveform.posn.99.name=DataPort[99] -unit.1.0.waveform.posn.99.type=signal -unit.1.1.0.HEIGHT0=0.39049235 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.925983 -unit.1.1.0.X0=0.074016966 -unit.1.1.0.Y0=0.0 -unit.1.1.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000000000000000000000000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 -unit.1.1.MFBitsB2=00000000000000000000000000000000 -unit.1.1.MFBitsB3=00000000000000000000000000000000 -unit.1.1.MFCompareA0=0 -unit.1.1.MFCompareA1=0 -unit.1.1.MFCompareA2=0 -unit.1.1.MFCompareA3=0 -unit.1.1.MFCompareB0=999 -unit.1.1.MFCompareB1=999 -unit.1.1.MFCompareB2=999 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-unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=1 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=1 -unit.1.1.port.-1.s.121.alias= -unit.1.1.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.121.name=DataPort[121] -unit.1.1.port.-1.s.121.orderindex=-1 -unit.1.1.port.-1.s.121.visible=1 -unit.1.1.port.-1.s.122.alias= -unit.1.1.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.122.name=DataPort[122] -unit.1.1.port.-1.s.122.orderindex=-1 -unit.1.1.port.-1.s.122.visible=1 -unit.1.1.port.-1.s.123.alias= -unit.1.1.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.123.name=DataPort[123] -unit.1.1.port.-1.s.123.orderindex=-1 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-unit.1.1.port.-1.s.13.name=DataPort[13] -unit.1.1.port.-1.s.13.orderindex=-1 -unit.1.1.port.-1.s.13.visible=1 -unit.1.1.port.-1.s.14.alias= -unit.1.1.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.14.name=DataPort[14] -unit.1.1.port.-1.s.14.orderindex=-1 -unit.1.1.port.-1.s.14.visible=1 -unit.1.1.port.-1.s.15.alias= -unit.1.1.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.15.name=DataPort[15] -unit.1.1.port.-1.s.15.orderindex=-1 -unit.1.1.port.-1.s.15.visible=1 -unit.1.1.port.-1.s.16.alias= -unit.1.1.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.16.name=DataPort[16] -unit.1.1.port.-1.s.16.orderindex=-1 -unit.1.1.port.-1.s.16.visible=1 -unit.1.1.port.-1.s.17.alias= -unit.1.1.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.17.name=DataPort[17] -unit.1.1.port.-1.s.17.orderindex=-1 -unit.1.1.port.-1.s.17.visible=1 -unit.1.1.port.-1.s.18.alias= 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-unit.1.1.port.-1.s.57.name=DataPort[57] -unit.1.1.port.-1.s.57.orderindex=-1 -unit.1.1.port.-1.s.57.visible=1 -unit.1.1.port.-1.s.58.alias= -unit.1.1.port.-1.s.58.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.58.name=DataPort[58] -unit.1.1.port.-1.s.58.orderindex=-1 -unit.1.1.port.-1.s.58.visible=1 -unit.1.1.port.-1.s.59.alias= -unit.1.1.port.-1.s.59.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.59.name=DataPort[59] -unit.1.1.port.-1.s.59.orderindex=-1 -unit.1.1.port.-1.s.59.visible=1 -unit.1.1.port.-1.s.6.alias= -unit.1.1.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.6.name=DataPort[6] -unit.1.1.port.-1.s.6.orderindex=-1 -unit.1.1.port.-1.s.6.visible=1 -unit.1.1.port.-1.s.60.alias= -unit.1.1.port.-1.s.60.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.60.name=DataPort[60] -unit.1.1.port.-1.s.60.orderindex=-1 -unit.1.1.port.-1.s.60.visible=1 -unit.1.1.port.-1.s.61.alias= -unit.1.1.port.-1.s.61.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.61.name=DataPort[61] -unit.1.1.port.-1.s.61.orderindex=-1 -unit.1.1.port.-1.s.61.visible=1 -unit.1.1.port.-1.s.62.alias= -unit.1.1.port.-1.s.62.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.62.name=DataPort[62] -unit.1.1.port.-1.s.62.orderindex=-1 -unit.1.1.port.-1.s.62.visible=1 -unit.1.1.port.-1.s.63.alias= -unit.1.1.port.-1.s.63.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.63.name=DataPort[63] -unit.1.1.port.-1.s.63.orderindex=-1 -unit.1.1.port.-1.s.63.visible=1 -unit.1.1.port.-1.s.64.alias= -unit.1.1.port.-1.s.64.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.64.name=DataPort[64] -unit.1.1.port.-1.s.64.orderindex=-1 -unit.1.1.port.-1.s.64.visible=1 -unit.1.1.port.-1.s.65.alias= -unit.1.1.port.-1.s.65.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.65.name=DataPort[65] -unit.1.1.port.-1.s.65.orderindex=-1 -unit.1.1.port.-1.s.65.visible=1 -unit.1.1.port.-1.s.66.alias= -unit.1.1.port.-1.s.66.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.66.name=DataPort[66] -unit.1.1.port.-1.s.66.orderindex=-1 -unit.1.1.port.-1.s.66.visible=1 -unit.1.1.port.-1.s.67.alias= -unit.1.1.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.67.name=DataPort[67] -unit.1.1.port.-1.s.67.orderindex=-1 -unit.1.1.port.-1.s.67.visible=1 -unit.1.1.port.-1.s.68.alias= -unit.1.1.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.68.name=DataPort[68] -unit.1.1.port.-1.s.68.orderindex=-1 -unit.1.1.port.-1.s.68.visible=1 -unit.1.1.port.-1.s.69.alias= -unit.1.1.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.69.name=DataPort[69] -unit.1.1.port.-1.s.69.orderindex=-1 -unit.1.1.port.-1.s.69.visible=1 -unit.1.1.port.-1.s.7.alias= -unit.1.1.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.7.name=DataPort[7] -unit.1.1.port.-1.s.7.orderindex=-1 -unit.1.1.port.-1.s.7.visible=1 -unit.1.1.port.-1.s.70.alias= -unit.1.1.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.70.name=DataPort[70] -unit.1.1.port.-1.s.70.orderindex=-1 -unit.1.1.port.-1.s.70.visible=1 -unit.1.1.port.-1.s.71.alias= -unit.1.1.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.71.name=DataPort[71] -unit.1.1.port.-1.s.71.orderindex=-1 -unit.1.1.port.-1.s.71.visible=1 -unit.1.1.port.-1.s.72.alias= -unit.1.1.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.72.name=DataPort[72] -unit.1.1.port.-1.s.72.orderindex=-1 -unit.1.1.port.-1.s.72.visible=1 -unit.1.1.port.-1.s.73.alias= -unit.1.1.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.73.name=DataPort[73] -unit.1.1.port.-1.s.73.orderindex=-1 -unit.1.1.port.-1.s.73.visible=1 -unit.1.1.port.-1.s.74.alias= -unit.1.1.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.74.name=DataPort[74] -unit.1.1.port.-1.s.74.orderindex=-1 -unit.1.1.port.-1.s.74.visible=1 -unit.1.1.port.-1.s.75.alias= -unit.1.1.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.75.name=DataPort[75] -unit.1.1.port.-1.s.75.orderindex=-1 -unit.1.1.port.-1.s.75.visible=1 -unit.1.1.port.-1.s.76.alias= -unit.1.1.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.76.name=DataPort[76] -unit.1.1.port.-1.s.76.orderindex=-1 -unit.1.1.port.-1.s.76.visible=1 -unit.1.1.port.-1.s.77.alias= -unit.1.1.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.77.name=DataPort[77] -unit.1.1.port.-1.s.77.orderindex=-1 -unit.1.1.port.-1.s.77.visible=1 -unit.1.1.port.-1.s.78.alias= -unit.1.1.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.78.name=DataPort[78] -unit.1.1.port.-1.s.78.orderindex=-1 -unit.1.1.port.-1.s.78.visible=1 -unit.1.1.port.-1.s.79.alias= -unit.1.1.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.79.name=DataPort[79] -unit.1.1.port.-1.s.79.orderindex=-1 -unit.1.1.port.-1.s.79.visible=1 -unit.1.1.port.-1.s.8.alias= -unit.1.1.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.8.name=DataPort[8] -unit.1.1.port.-1.s.8.orderindex=-1 -unit.1.1.port.-1.s.8.visible=1 -unit.1.1.port.-1.s.80.alias= -unit.1.1.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.80.name=DataPort[80] -unit.1.1.port.-1.s.80.orderindex=-1 -unit.1.1.port.-1.s.80.visible=1 -unit.1.1.port.-1.s.81.alias= -unit.1.1.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.81.name=DataPort[81] -unit.1.1.port.-1.s.81.orderindex=-1 -unit.1.1.port.-1.s.81.visible=1 -unit.1.1.port.-1.s.82.alias= -unit.1.1.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.82.name=DataPort[82] -unit.1.1.port.-1.s.82.orderindex=-1 -unit.1.1.port.-1.s.82.visible=1 -unit.1.1.port.-1.s.83.alias= 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-unit.1.1.port.-1.s.88.alias= -unit.1.1.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.88.name=DataPort[88] -unit.1.1.port.-1.s.88.orderindex=-1 -unit.1.1.port.-1.s.88.visible=1 -unit.1.1.port.-1.s.89.alias= -unit.1.1.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.89.name=DataPort[89] -unit.1.1.port.-1.s.89.orderindex=-1 -unit.1.1.port.-1.s.89.visible=1 -unit.1.1.port.-1.s.9.alias= -unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=1 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=1 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 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-unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=32 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] 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-unit.1.2.port.-1.s.79.name=DataPort[79] -unit.1.2.port.-1.s.79.orderindex=-1 -unit.1.2.port.-1.s.79.visible=1 -unit.1.2.port.-1.s.8.alias= -unit.1.2.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.8.name=DataPort[8] -unit.1.2.port.-1.s.8.orderindex=-1 -unit.1.2.port.-1.s.8.visible=1 -unit.1.2.port.-1.s.80.alias= -unit.1.2.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.80.name=DataPort[80] -unit.1.2.port.-1.s.80.orderindex=-1 -unit.1.2.port.-1.s.80.visible=1 -unit.1.2.port.-1.s.81.alias= -unit.1.2.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.81.name=DataPort[81] -unit.1.2.port.-1.s.81.orderindex=-1 -unit.1.2.port.-1.s.81.visible=1 -unit.1.2.port.-1.s.82.alias= -unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=1 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=1 -unit.1.2.port.-1.s.84.alias= -unit.1.2.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.84.name=DataPort[84] -unit.1.2.port.-1.s.84.orderindex=-1 -unit.1.2.port.-1.s.84.visible=1 -unit.1.2.port.-1.s.85.alias= -unit.1.2.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.85.name=DataPort[85] -unit.1.2.port.-1.s.85.orderindex=-1 -unit.1.2.port.-1.s.85.visible=1 -unit.1.2.port.-1.s.86.alias= -unit.1.2.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.86.name=DataPort[86] -unit.1.2.port.-1.s.86.orderindex=-1 -unit.1.2.port.-1.s.86.visible=1 -unit.1.2.port.-1.s.87.alias= -unit.1.2.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.87.name=DataPort[87] -unit.1.2.port.-1.s.87.orderindex=-1 -unit.1.2.port.-1.s.87.visible=1 -unit.1.2.port.-1.s.88.alias= -unit.1.2.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.88.name=DataPort[88] -unit.1.2.port.-1.s.88.orderindex=-1 -unit.1.2.port.-1.s.88.visible=1 -unit.1.2.port.-1.s.89.alias= -unit.1.2.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.89.name=DataPort[89] -unit.1.2.port.-1.s.89.orderindex=-1 -unit.1.2.port.-1.s.89.visible=1 -unit.1.2.port.-1.s.9.alias= -unit.1.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.9.name=DataPort[9] -unit.1.2.port.-1.s.9.orderindex=-1 -unit.1.2.port.-1.s.9.visible=1 -unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=1 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 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-unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=1 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex 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-unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 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-unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 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-unit.1.2.port.3.s.3.orderindex=-1 -unit.1.2.port.3.s.3.visible=1 -unit.1.2.port.3.s.30.alias= -unit.1.2.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.30.name=TriggerPort3[30] -unit.1.2.port.3.s.30.orderindex=-1 -unit.1.2.port.3.s.30.visible=1 -unit.1.2.port.3.s.31.alias= -unit.1.2.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.31.name=TriggerPort3[31] -unit.1.2.port.3.s.31.orderindex=-1 -unit.1.2.port.3.s.31.visible=1 -unit.1.2.port.3.s.4.alias= -unit.1.2.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.4.name=TriggerPort3[4] -unit.1.2.port.3.s.4.orderindex=-1 -unit.1.2.port.3.s.4.visible=1 -unit.1.2.port.3.s.5.alias= -unit.1.2.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.portcount=4 -unit.1.2.rep_trigger.clobber=1 -unit.1.2.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp -unit.1.2.rep_trigger.filename=waveform -unit.1.2.rep_trigger.format=ASCII -unit.1.2.rep_trigger.loggingEnabled=0 -unit.1.2.rep_trigger.signals=All Signals/Buses -unit.1.2.samplesPerTrigger=1 -unit.1.2.triggerCapture=1 -unit.1.2.triggerNSamplesTS=0 -unit.1.2.triggerPosition=0 -unit.1.2.triggerWindowCount=1 -unit.1.2.triggerWindowDepth=4096 -unit.1.2.triggerWindowTS=0 -unit.1.2.username=MyILA2 -unit.1.2.waveform.count=128 -unit.1.2.waveform.posn.0.channel=0 -unit.1.2.waveform.posn.0.name=DataPort[0] -unit.1.2.waveform.posn.0.type=signal -unit.1.2.waveform.posn.1.channel=1 -unit.1.2.waveform.posn.1.name=DataPort[1] -unit.1.2.waveform.posn.1.type=signal -unit.1.2.waveform.posn.10.channel=10 -unit.1.2.waveform.posn.10.name=DataPort[10] -unit.1.2.waveform.posn.10.type=signal -unit.1.2.waveform.posn.100.channel=100 -unit.1.2.waveform.posn.100.name=DataPort[100] -unit.1.2.waveform.posn.100.type=signal -unit.1.2.waveform.posn.101.channel=101 -unit.1.2.waveform.posn.101.name=DataPort[101] -unit.1.2.waveform.posn.101.type=signal -unit.1.2.waveform.posn.102.channel=102 -unit.1.2.waveform.posn.102.name=DataPort[102] -unit.1.2.waveform.posn.102.type=signal -unit.1.2.waveform.posn.103.channel=103 -unit.1.2.waveform.posn.103.name=DataPort[103] -unit.1.2.waveform.posn.103.type=signal -unit.1.2.waveform.posn.104.channel=104 -unit.1.2.waveform.posn.104.name=DataPort[104] -unit.1.2.waveform.posn.104.type=signal -unit.1.2.waveform.posn.105.channel=105 -unit.1.2.waveform.posn.105.name=DataPort[105] -unit.1.2.waveform.posn.105.type=signal -unit.1.2.waveform.posn.106.channel=106 -unit.1.2.waveform.posn.106.name=DataPort[106] -unit.1.2.waveform.posn.106.type=signal -unit.1.2.waveform.posn.107.channel=107 -unit.1.2.waveform.posn.107.name=DataPort[107] -unit.1.2.waveform.posn.107.type=signal -unit.1.2.waveform.posn.108.channel=108 -unit.1.2.waveform.posn.108.name=DataPort[108] -unit.1.2.waveform.posn.108.type=signal -unit.1.2.waveform.posn.109.channel=109 -unit.1.2.waveform.posn.109.name=DataPort[109] -unit.1.2.waveform.posn.109.type=signal -unit.1.2.waveform.posn.11.channel=11 -unit.1.2.waveform.posn.11.name=DataPort[11] -unit.1.2.waveform.posn.11.type=signal -unit.1.2.waveform.posn.110.channel=110 -unit.1.2.waveform.posn.110.name=DataPort[110] -unit.1.2.waveform.posn.110.type=signal -unit.1.2.waveform.posn.111.channel=111 -unit.1.2.waveform.posn.111.name=DataPort[111] -unit.1.2.waveform.posn.111.type=signal -unit.1.2.waveform.posn.112.channel=112 -unit.1.2.waveform.posn.112.name=DataPort[112] -unit.1.2.waveform.posn.112.type=signal -unit.1.2.waveform.posn.113.channel=113 -unit.1.2.waveform.posn.113.name=DataPort[113] -unit.1.2.waveform.posn.113.type=signal -unit.1.2.waveform.posn.114.channel=114 -unit.1.2.waveform.posn.114.name=DataPort[114] -unit.1.2.waveform.posn.114.type=signal -unit.1.2.waveform.posn.115.channel=115 -unit.1.2.waveform.posn.115.name=DataPort[115] -unit.1.2.waveform.posn.115.type=signal -unit.1.2.waveform.posn.116.channel=116 -unit.1.2.waveform.posn.116.name=DataPort[116] -unit.1.2.waveform.posn.116.type=signal -unit.1.2.waveform.posn.117.channel=117 -unit.1.2.waveform.posn.117.name=DataPort[117] -unit.1.2.waveform.posn.117.type=signal -unit.1.2.waveform.posn.118.channel=118 -unit.1.2.waveform.posn.118.name=DataPort[118] -unit.1.2.waveform.posn.118.type=signal -unit.1.2.waveform.posn.119.channel=119 -unit.1.2.waveform.posn.119.name=DataPort[119] -unit.1.2.waveform.posn.119.type=signal -unit.1.2.waveform.posn.12.channel=12 -unit.1.2.waveform.posn.12.name=DataPort[12] -unit.1.2.waveform.posn.12.type=signal -unit.1.2.waveform.posn.120.channel=120 -unit.1.2.waveform.posn.120.name=DataPort[120] -unit.1.2.waveform.posn.120.type=signal -unit.1.2.waveform.posn.121.channel=121 -unit.1.2.waveform.posn.121.name=DataPort[121] -unit.1.2.waveform.posn.121.type=signal -unit.1.2.waveform.posn.122.channel=122 -unit.1.2.waveform.posn.122.name=DataPort[122] -unit.1.2.waveform.posn.122.type=signal -unit.1.2.waveform.posn.123.channel=123 -unit.1.2.waveform.posn.123.name=DataPort[123] -unit.1.2.waveform.posn.123.type=signal -unit.1.2.waveform.posn.124.channel=124 -unit.1.2.waveform.posn.124.name=DataPort[124] -unit.1.2.waveform.posn.124.type=signal -unit.1.2.waveform.posn.125.channel=125 -unit.1.2.waveform.posn.125.name=DataPort[125] -unit.1.2.waveform.posn.125.type=signal -unit.1.2.waveform.posn.126.channel=126 -unit.1.2.waveform.posn.126.name=DataPort[126] -unit.1.2.waveform.posn.126.type=signal -unit.1.2.waveform.posn.127.channel=127 -unit.1.2.waveform.posn.127.name=DataPort[127] -unit.1.2.waveform.posn.127.type=signal -unit.1.2.waveform.posn.13.channel=13 -unit.1.2.waveform.posn.13.name=DataPort[13] -unit.1.2.waveform.posn.13.type=signal -unit.1.2.waveform.posn.14.channel=14 -unit.1.2.waveform.posn.14.name=DataPort[14] -unit.1.2.waveform.posn.14.type=signal -unit.1.2.waveform.posn.15.channel=15 -unit.1.2.waveform.posn.15.name=DataPort[15] -unit.1.2.waveform.posn.15.type=signal -unit.1.2.waveform.posn.16.channel=16 -unit.1.2.waveform.posn.16.name=DataPort[16] -unit.1.2.waveform.posn.16.type=signal -unit.1.2.waveform.posn.17.channel=17 -unit.1.2.waveform.posn.17.name=DataPort[17] -unit.1.2.waveform.posn.17.type=signal -unit.1.2.waveform.posn.18.channel=18 -unit.1.2.waveform.posn.18.name=DataPort[18] -unit.1.2.waveform.posn.18.type=signal -unit.1.2.waveform.posn.19.channel=19 -unit.1.2.waveform.posn.19.name=DataPort[19] -unit.1.2.waveform.posn.19.type=signal -unit.1.2.waveform.posn.2.channel=2 -unit.1.2.waveform.posn.2.name=DataPort[2] -unit.1.2.waveform.posn.2.type=signal -unit.1.2.waveform.posn.20.channel=20 -unit.1.2.waveform.posn.20.name=DataPort[20] -unit.1.2.waveform.posn.20.type=signal -unit.1.2.waveform.posn.21.channel=21 -unit.1.2.waveform.posn.21.name=DataPort[21] -unit.1.2.waveform.posn.21.type=signal -unit.1.2.waveform.posn.22.channel=22 -unit.1.2.waveform.posn.22.name=DataPort[22] -unit.1.2.waveform.posn.22.type=signal -unit.1.2.waveform.posn.23.channel=23 -unit.1.2.waveform.posn.23.name=DataPort[23] -unit.1.2.waveform.posn.23.type=signal -unit.1.2.waveform.posn.24.channel=24 -unit.1.2.waveform.posn.24.name=DataPort[24] -unit.1.2.waveform.posn.24.type=signal -unit.1.2.waveform.posn.25.channel=25 -unit.1.2.waveform.posn.25.name=DataPort[25] -unit.1.2.waveform.posn.25.type=signal -unit.1.2.waveform.posn.26.channel=26 -unit.1.2.waveform.posn.26.name=DataPort[26] -unit.1.2.waveform.posn.26.type=signal -unit.1.2.waveform.posn.27.channel=27 -unit.1.2.waveform.posn.27.name=DataPort[27] -unit.1.2.waveform.posn.27.type=signal -unit.1.2.waveform.posn.28.channel=28 -unit.1.2.waveform.posn.28.name=DataPort[28] -unit.1.2.waveform.posn.28.type=signal -unit.1.2.waveform.posn.29.channel=29 -unit.1.2.waveform.posn.29.name=DataPort[29] -unit.1.2.waveform.posn.29.type=signal -unit.1.2.waveform.posn.3.channel=3 -unit.1.2.waveform.posn.3.name=DataPort[3] -unit.1.2.waveform.posn.3.type=signal -unit.1.2.waveform.posn.30.channel=30 -unit.1.2.waveform.posn.30.name=DataPort[30] -unit.1.2.waveform.posn.30.type=signal -unit.1.2.waveform.posn.31.channel=31 -unit.1.2.waveform.posn.31.name=DataPort[31] -unit.1.2.waveform.posn.31.type=signal -unit.1.2.waveform.posn.32.channel=32 -unit.1.2.waveform.posn.32.name=DataPort[32] -unit.1.2.waveform.posn.32.type=signal -unit.1.2.waveform.posn.33.channel=33 -unit.1.2.waveform.posn.33.name=DataPort[33] -unit.1.2.waveform.posn.33.type=signal -unit.1.2.waveform.posn.34.channel=34 -unit.1.2.waveform.posn.34.name=DataPort[34] -unit.1.2.waveform.posn.34.type=signal -unit.1.2.waveform.posn.35.channel=35 -unit.1.2.waveform.posn.35.name=DataPort[35] -unit.1.2.waveform.posn.35.type=signal -unit.1.2.waveform.posn.36.channel=36 -unit.1.2.waveform.posn.36.name=DataPort[36] -unit.1.2.waveform.posn.36.type=signal -unit.1.2.waveform.posn.37.channel=37 -unit.1.2.waveform.posn.37.name=DataPort[37] -unit.1.2.waveform.posn.37.type=signal -unit.1.2.waveform.posn.38.channel=38 -unit.1.2.waveform.posn.38.name=DataPort[38] -unit.1.2.waveform.posn.38.type=signal -unit.1.2.waveform.posn.39.channel=39 -unit.1.2.waveform.posn.39.name=DataPort[39] -unit.1.2.waveform.posn.39.type=signal -unit.1.2.waveform.posn.4.channel=4 -unit.1.2.waveform.posn.4.name=DataPort[4] -unit.1.2.waveform.posn.4.type=signal -unit.1.2.waveform.posn.40.channel=40 -unit.1.2.waveform.posn.40.name=DataPort[40] -unit.1.2.waveform.posn.40.type=signal -unit.1.2.waveform.posn.41.channel=41 -unit.1.2.waveform.posn.41.name=DataPort[41] -unit.1.2.waveform.posn.41.type=signal -unit.1.2.waveform.posn.42.channel=42 -unit.1.2.waveform.posn.42.name=DataPort[42] -unit.1.2.waveform.posn.42.type=signal -unit.1.2.waveform.posn.43.channel=43 -unit.1.2.waveform.posn.43.name=DataPort[43] -unit.1.2.waveform.posn.43.type=signal -unit.1.2.waveform.posn.44.channel=44 -unit.1.2.waveform.posn.44.name=DataPort[44] -unit.1.2.waveform.posn.44.type=signal -unit.1.2.waveform.posn.45.channel=45 -unit.1.2.waveform.posn.45.name=DataPort[45] -unit.1.2.waveform.posn.45.type=signal -unit.1.2.waveform.posn.46.channel=46 -unit.1.2.waveform.posn.46.name=DataPort[46] -unit.1.2.waveform.posn.46.type=signal -unit.1.2.waveform.posn.47.channel=47 -unit.1.2.waveform.posn.47.name=DataPort[47] -unit.1.2.waveform.posn.47.type=signal -unit.1.2.waveform.posn.48.channel=48 -unit.1.2.waveform.posn.48.name=DataPort[48] -unit.1.2.waveform.posn.48.type=signal -unit.1.2.waveform.posn.49.channel=49 -unit.1.2.waveform.posn.49.name=DataPort[49] -unit.1.2.waveform.posn.49.type=signal -unit.1.2.waveform.posn.5.channel=5 -unit.1.2.waveform.posn.5.name=DataPort[5] -unit.1.2.waveform.posn.5.type=signal -unit.1.2.waveform.posn.50.channel=50 -unit.1.2.waveform.posn.50.name=DataPort[50] -unit.1.2.waveform.posn.50.type=signal -unit.1.2.waveform.posn.51.channel=51 -unit.1.2.waveform.posn.51.name=DataPort[51] -unit.1.2.waveform.posn.51.type=signal -unit.1.2.waveform.posn.52.channel=52 -unit.1.2.waveform.posn.52.name=DataPort[52] -unit.1.2.waveform.posn.52.type=signal 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-unit.1.2.waveform.posn.75.channel=75 -unit.1.2.waveform.posn.75.name=DataPort[75] -unit.1.2.waveform.posn.75.type=signal -unit.1.2.waveform.posn.76.channel=76 -unit.1.2.waveform.posn.76.name=DataPort[76] -unit.1.2.waveform.posn.76.type=signal -unit.1.2.waveform.posn.77.channel=77 -unit.1.2.waveform.posn.77.name=DataPort[77] -unit.1.2.waveform.posn.77.type=signal -unit.1.2.waveform.posn.78.channel=78 -unit.1.2.waveform.posn.78.name=DataPort[78] -unit.1.2.waveform.posn.78.type=signal -unit.1.2.waveform.posn.79.channel=79 -unit.1.2.waveform.posn.79.name=DataPort[79] -unit.1.2.waveform.posn.79.type=signal -unit.1.2.waveform.posn.8.channel=8 -unit.1.2.waveform.posn.8.name=DataPort[8] -unit.1.2.waveform.posn.8.type=signal -unit.1.2.waveform.posn.80.channel=80 -unit.1.2.waveform.posn.80.name=DataPort[80] -unit.1.2.waveform.posn.80.type=signal -unit.1.2.waveform.posn.81.channel=81 -unit.1.2.waveform.posn.81.name=DataPort[81] -unit.1.2.waveform.posn.81.type=signal -unit.1.2.waveform.posn.82.channel=82 -unit.1.2.waveform.posn.82.name=DataPort[82] -unit.1.2.waveform.posn.82.type=signal -unit.1.2.waveform.posn.83.channel=83 -unit.1.2.waveform.posn.83.name=DataPort[83] -unit.1.2.waveform.posn.83.type=signal -unit.1.2.waveform.posn.84.channel=84 -unit.1.2.waveform.posn.84.name=DataPort[84] -unit.1.2.waveform.posn.84.type=signal -unit.1.2.waveform.posn.85.channel=85 -unit.1.2.waveform.posn.85.name=DataPort[85] -unit.1.2.waveform.posn.85.type=signal -unit.1.2.waveform.posn.86.channel=86 -unit.1.2.waveform.posn.86.name=DataPort[86] -unit.1.2.waveform.posn.86.type=signal -unit.1.2.waveform.posn.87.channel=87 -unit.1.2.waveform.posn.87.name=DataPort[87] -unit.1.2.waveform.posn.87.type=signal -unit.1.2.waveform.posn.88.channel=88 -unit.1.2.waveform.posn.88.name=DataPort[88] -unit.1.2.waveform.posn.88.type=signal -unit.1.2.waveform.posn.89.channel=89 -unit.1.2.waveform.posn.89.name=DataPort[89] -unit.1.2.waveform.posn.89.type=signal -unit.1.2.waveform.posn.9.channel=9 -unit.1.2.waveform.posn.9.name=DataPort[9] -unit.1.2.waveform.posn.9.type=signal -unit.1.2.waveform.posn.90.channel=90 -unit.1.2.waveform.posn.90.name=DataPort[90] -unit.1.2.waveform.posn.90.type=signal -unit.1.2.waveform.posn.91.channel=91 -unit.1.2.waveform.posn.91.name=DataPort[91] -unit.1.2.waveform.posn.91.type=signal -unit.1.2.waveform.posn.92.channel=92 -unit.1.2.waveform.posn.92.name=DataPort[92] -unit.1.2.waveform.posn.92.type=signal -unit.1.2.waveform.posn.93.channel=93 -unit.1.2.waveform.posn.93.name=DataPort[93] -unit.1.2.waveform.posn.93.type=signal -unit.1.2.waveform.posn.94.channel=94 -unit.1.2.waveform.posn.94.name=DataPort[94] -unit.1.2.waveform.posn.94.type=signal -unit.1.2.waveform.posn.95.channel=95 -unit.1.2.waveform.posn.95.name=DataPort[95] -unit.1.2.waveform.posn.95.type=signal -unit.1.2.waveform.posn.96.channel=96 -unit.1.2.waveform.posn.96.name=DataPort[96] -unit.1.2.waveform.posn.96.type=signal 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-unit.1.3.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.83.name=DataPort[83] -unit.1.3.port.-1.s.83.orderindex=-1 -unit.1.3.port.-1.s.83.visible=1 -unit.1.3.port.-1.s.84.alias= -unit.1.3.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.84.name=DataPort[84] -unit.1.3.port.-1.s.84.orderindex=-1 -unit.1.3.port.-1.s.84.visible=1 -unit.1.3.port.-1.s.85.alias= -unit.1.3.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.85.name=DataPort[85] -unit.1.3.port.-1.s.85.orderindex=-1 -unit.1.3.port.-1.s.85.visible=1 -unit.1.3.port.-1.s.86.alias= -unit.1.3.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.86.name=DataPort[86] -unit.1.3.port.-1.s.86.orderindex=-1 -unit.1.3.port.-1.s.86.visible=1 -unit.1.3.port.-1.s.87.alias= -unit.1.3.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.87.name=DataPort[87] -unit.1.3.port.-1.s.87.orderindex=-1 -unit.1.3.port.-1.s.87.visible=1 -unit.1.3.port.-1.s.88.alias= -unit.1.3.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.88.name=DataPort[88] -unit.1.3.port.-1.s.88.orderindex=-1 -unit.1.3.port.-1.s.88.visible=1 -unit.1.3.port.-1.s.89.alias= -unit.1.3.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.89.name=DataPort[89] -unit.1.3.port.-1.s.89.orderindex=-1 -unit.1.3.port.-1.s.89.visible=1 -unit.1.3.port.-1.s.9.alias= -unit.1.3.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.9.name=DataPort[9] -unit.1.3.port.-1.s.9.orderindex=-1 -unit.1.3.port.-1.s.9.visible=0 -unit.1.3.port.-1.s.90.alias= -unit.1.3.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.90.name=DataPort[90] -unit.1.3.port.-1.s.90.orderindex=-1 -unit.1.3.port.-1.s.90.visible=1 -unit.1.3.port.-1.s.91.alias= -unit.1.3.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.91.name=DataPort[91] -unit.1.3.port.-1.s.91.orderindex=-1 -unit.1.3.port.-1.s.91.visible=1 -unit.1.3.port.-1.s.92.alias= -unit.1.3.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.92.name=DataPort[92] -unit.1.3.port.-1.s.92.orderindex=-1 -unit.1.3.port.-1.s.92.visible=1 -unit.1.3.port.-1.s.93.alias= -unit.1.3.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.93.name=DataPort[93] -unit.1.3.port.-1.s.93.orderindex=-1 -unit.1.3.port.-1.s.93.visible=1 -unit.1.3.port.-1.s.94.alias= -unit.1.3.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.94.name=DataPort[94] -unit.1.3.port.-1.s.94.orderindex=-1 -unit.1.3.port.-1.s.94.visible=1 -unit.1.3.port.-1.s.95.alias= -unit.1.3.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.95.name=DataPort[95] -unit.1.3.port.-1.s.95.orderindex=-1 -unit.1.3.port.-1.s.95.visible=1 -unit.1.3.port.-1.s.96.alias= -unit.1.3.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.96.name=DataPort[96] -unit.1.3.port.-1.s.96.orderindex=-1 -unit.1.3.port.-1.s.96.visible=1 -unit.1.3.port.-1.s.97.alias= -unit.1.3.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.97.name=DataPort[97] -unit.1.3.port.-1.s.97.orderindex=-1 -unit.1.3.port.-1.s.97.visible=1 -unit.1.3.port.-1.s.98.alias= -unit.1.3.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.98.name=DataPort[98] -unit.1.3.port.-1.s.98.orderindex=-1 -unit.1.3.port.-1.s.98.visible=1 -unit.1.3.port.-1.s.99.alias= -unit.1.3.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.99.name=DataPort[99] -unit.1.3.port.-1.s.99.orderindex=-1 -unit.1.3.port.-1.s.99.visible=1 -unit.1.3.port.0.b.0.alias= -unit.1.3.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.b.0.name=TriggerPort0 -unit.1.3.port.0.b.0.orderindex=-1 -unit.1.3.port.0.b.0.radix=Hex -unit.1.3.port.0.b.0.signedOffset=0.0 -unit.1.3.port.0.b.0.signedPrecision=0 -unit.1.3.port.0.b.0.signedScaleFactor=1.0 -unit.1.3.port.0.b.0.unsignedOffset=0.0 -unit.1.3.port.0.b.0.unsignedPrecision=0 -unit.1.3.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.0.b.0.visible=1 -unit.1.3.port.0.buscount=1 -unit.1.3.port.0.channelcount=32 -unit.1.3.port.0.s.0.alias= -unit.1.3.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.0.name=TriggerPort0[0] -unit.1.3.port.0.s.0.orderindex=-1 -unit.1.3.port.0.s.0.visible=1 -unit.1.3.port.0.s.1.alias= -unit.1.3.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.1.name=TriggerPort0[1] -unit.1.3.port.0.s.1.orderindex=-1 -unit.1.3.port.0.s.1.visible=1 -unit.1.3.port.0.s.10.alias= -unit.1.3.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.10.name=TriggerPort0[10] -unit.1.3.port.0.s.10.orderindex=-1 -unit.1.3.port.0.s.10.visible=1 -unit.1.3.port.0.s.11.alias= -unit.1.3.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 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-unit.1.3.waveform.posn.117.channel=127 -unit.1.3.waveform.posn.117.name=DataPort[127] -unit.1.3.waveform.posn.117.type=signal -unit.1.3.waveform.posn.118.channel=127 -unit.1.3.waveform.posn.118.name=DataPort[127] -unit.1.3.waveform.posn.118.type=signal -unit.1.3.waveform.posn.119.channel=127 -unit.1.3.waveform.posn.119.name=DataPort[127] -unit.1.3.waveform.posn.119.type=signal -unit.1.3.waveform.posn.12.channel=36 -unit.1.3.waveform.posn.12.name=DataPort[36] -unit.1.3.waveform.posn.12.type=signal -unit.1.3.waveform.posn.120.channel=127 -unit.1.3.waveform.posn.120.name=DataPort[127] -unit.1.3.waveform.posn.120.type=signal -unit.1.3.waveform.posn.121.channel=127 -unit.1.3.waveform.posn.121.name=DataPort[127] -unit.1.3.waveform.posn.121.type=signal -unit.1.3.waveform.posn.122.channel=127 -unit.1.3.waveform.posn.122.name=DataPort[127] -unit.1.3.waveform.posn.122.type=signal -unit.1.3.waveform.posn.123.channel=127 -unit.1.3.waveform.posn.123.name=DataPort[127] -unit.1.3.waveform.posn.123.type=signal -unit.1.3.waveform.posn.124.channel=127 -unit.1.3.waveform.posn.124.name=DataPort[127] -unit.1.3.waveform.posn.124.type=signal -unit.1.3.waveform.posn.125.channel=127 -unit.1.3.waveform.posn.125.name=DataPort[127] -unit.1.3.waveform.posn.125.type=signal -unit.1.3.waveform.posn.126.channel=127 -unit.1.3.waveform.posn.126.name=DataPort[127] -unit.1.3.waveform.posn.126.type=signal -unit.1.3.waveform.posn.127.channel=127 -unit.1.3.waveform.posn.127.name=DataPort[127] -unit.1.3.waveform.posn.127.type=signal -unit.1.3.waveform.posn.13.channel=37 -unit.1.3.waveform.posn.13.name=DataPort[37] -unit.1.3.waveform.posn.13.type=signal -unit.1.3.waveform.posn.14.channel=38 -unit.1.3.waveform.posn.14.name=DataPort[38] -unit.1.3.waveform.posn.14.type=signal -unit.1.3.waveform.posn.15.channel=39 -unit.1.3.waveform.posn.15.name=DataPort[39] -unit.1.3.waveform.posn.15.type=signal -unit.1.3.waveform.posn.16.channel=40 -unit.1.3.waveform.posn.16.name=DataPort[40] -unit.1.3.waveform.posn.16.type=signal -unit.1.3.waveform.posn.17.channel=41 -unit.1.3.waveform.posn.17.name=DataPort[41] -unit.1.3.waveform.posn.17.type=signal -unit.1.3.waveform.posn.18.channel=42 -unit.1.3.waveform.posn.18.name=DataPort[42] -unit.1.3.waveform.posn.18.type=signal -unit.1.3.waveform.posn.19.channel=43 -unit.1.3.waveform.posn.19.name=DataPort[43] -unit.1.3.waveform.posn.19.type=signal -unit.1.3.waveform.posn.2.channel=26 -unit.1.3.waveform.posn.2.name=DataPort[26] -unit.1.3.waveform.posn.2.type=signal -unit.1.3.waveform.posn.20.channel=44 -unit.1.3.waveform.posn.20.name=DataPort[44] -unit.1.3.waveform.posn.20.type=signal -unit.1.3.waveform.posn.21.channel=45 -unit.1.3.waveform.posn.21.name=DataPort[45] -unit.1.3.waveform.posn.21.type=signal -unit.1.3.waveform.posn.22.channel=46 -unit.1.3.waveform.posn.22.name=DataPort[46] -unit.1.3.waveform.posn.22.type=signal -unit.1.3.waveform.posn.23.channel=47 -unit.1.3.waveform.posn.23.name=DataPort[47] -unit.1.3.waveform.posn.23.type=signal -unit.1.3.waveform.posn.24.channel=48 -unit.1.3.waveform.posn.24.name=DataPort[48] -unit.1.3.waveform.posn.24.type=signal -unit.1.3.waveform.posn.25.channel=49 -unit.1.3.waveform.posn.25.name=DataPort[49] -unit.1.3.waveform.posn.25.type=signal -unit.1.3.waveform.posn.26.channel=50 -unit.1.3.waveform.posn.26.name=DataPort[50] -unit.1.3.waveform.posn.26.type=signal -unit.1.3.waveform.posn.27.channel=51 -unit.1.3.waveform.posn.27.name=DataPort[51] -unit.1.3.waveform.posn.27.type=signal -unit.1.3.waveform.posn.28.channel=52 -unit.1.3.waveform.posn.28.name=DataPort[52] -unit.1.3.waveform.posn.28.type=signal -unit.1.3.waveform.posn.29.channel=53 -unit.1.3.waveform.posn.29.name=DataPort[53] -unit.1.3.waveform.posn.29.type=signal -unit.1.3.waveform.posn.3.channel=27 -unit.1.3.waveform.posn.3.name=DataPort[27] -unit.1.3.waveform.posn.3.type=signal -unit.1.3.waveform.posn.30.channel=54 -unit.1.3.waveform.posn.30.name=DataPort[54] -unit.1.3.waveform.posn.30.type=signal -unit.1.3.waveform.posn.31.channel=55 -unit.1.3.waveform.posn.31.name=DataPort[55] -unit.1.3.waveform.posn.31.type=signal -unit.1.3.waveform.posn.32.channel=56 -unit.1.3.waveform.posn.32.name=DataPort[56] -unit.1.3.waveform.posn.32.type=signal -unit.1.3.waveform.posn.33.channel=57 -unit.1.3.waveform.posn.33.name=DataPort[57] -unit.1.3.waveform.posn.33.type=signal -unit.1.3.waveform.posn.34.channel=58 -unit.1.3.waveform.posn.34.name=DataPort[58] -unit.1.3.waveform.posn.34.type=signal -unit.1.3.waveform.posn.35.channel=59 -unit.1.3.waveform.posn.35.name=DataPort[59] -unit.1.3.waveform.posn.35.type=signal -unit.1.3.waveform.posn.36.channel=60 -unit.1.3.waveform.posn.36.name=DataPort[60] -unit.1.3.waveform.posn.36.type=signal -unit.1.3.waveform.posn.37.channel=61 -unit.1.3.waveform.posn.37.name=DataPort[61] -unit.1.3.waveform.posn.37.type=signal -unit.1.3.waveform.posn.38.channel=62 -unit.1.3.waveform.posn.38.name=DataPort[62] -unit.1.3.waveform.posn.38.type=signal -unit.1.3.waveform.posn.39.channel=63 -unit.1.3.waveform.posn.39.name=DataPort[63] -unit.1.3.waveform.posn.39.type=signal -unit.1.3.waveform.posn.4.channel=28 -unit.1.3.waveform.posn.4.name=DataPort[28] -unit.1.3.waveform.posn.4.type=signal -unit.1.3.waveform.posn.40.channel=64 -unit.1.3.waveform.posn.40.name=DataPort[64] -unit.1.3.waveform.posn.40.type=signal -unit.1.3.waveform.posn.41.channel=65 -unit.1.3.waveform.posn.41.name=DataPort[65] -unit.1.3.waveform.posn.41.type=signal -unit.1.3.waveform.posn.42.channel=66 -unit.1.3.waveform.posn.42.name=DataPort[66] -unit.1.3.waveform.posn.42.type=signal -unit.1.3.waveform.posn.43.channel=67 -unit.1.3.waveform.posn.43.name=DataPort[67] -unit.1.3.waveform.posn.43.type=signal -unit.1.3.waveform.posn.44.channel=68 -unit.1.3.waveform.posn.44.name=DataPort[68] -unit.1.3.waveform.posn.44.type=signal -unit.1.3.waveform.posn.45.channel=69 -unit.1.3.waveform.posn.45.name=DataPort[69] -unit.1.3.waveform.posn.45.type=signal -unit.1.3.waveform.posn.46.channel=70 -unit.1.3.waveform.posn.46.name=DataPort[70] -unit.1.3.waveform.posn.46.type=signal -unit.1.3.waveform.posn.47.channel=71 -unit.1.3.waveform.posn.47.name=DataPort[71] -unit.1.3.waveform.posn.47.type=signal -unit.1.3.waveform.posn.48.channel=72 -unit.1.3.waveform.posn.48.name=DataPort[72] -unit.1.3.waveform.posn.48.type=signal -unit.1.3.waveform.posn.49.channel=73 -unit.1.3.waveform.posn.49.name=DataPort[73] -unit.1.3.waveform.posn.49.type=signal -unit.1.3.waveform.posn.5.channel=29 -unit.1.3.waveform.posn.5.name=DataPort[29] -unit.1.3.waveform.posn.5.type=signal -unit.1.3.waveform.posn.50.channel=74 -unit.1.3.waveform.posn.50.name=DataPort[74] -unit.1.3.waveform.posn.50.type=signal -unit.1.3.waveform.posn.51.channel=75 -unit.1.3.waveform.posn.51.name=DataPort[75] -unit.1.3.waveform.posn.51.type=signal -unit.1.3.waveform.posn.52.channel=76 -unit.1.3.waveform.posn.52.name=DataPort[76] -unit.1.3.waveform.posn.52.type=signal -unit.1.3.waveform.posn.53.channel=77 -unit.1.3.waveform.posn.53.name=DataPort[77] -unit.1.3.waveform.posn.53.type=signal -unit.1.3.waveform.posn.54.channel=78 -unit.1.3.waveform.posn.54.name=DataPort[78] -unit.1.3.waveform.posn.54.type=signal -unit.1.3.waveform.posn.55.channel=79 -unit.1.3.waveform.posn.55.name=DataPort[79] -unit.1.3.waveform.posn.55.type=signal -unit.1.3.waveform.posn.56.channel=80 -unit.1.3.waveform.posn.56.name=DataPort[80] -unit.1.3.waveform.posn.56.type=signal -unit.1.3.waveform.posn.57.channel=81 -unit.1.3.waveform.posn.57.name=DataPort[81] -unit.1.3.waveform.posn.57.type=signal -unit.1.3.waveform.posn.58.channel=82 -unit.1.3.waveform.posn.58.name=DataPort[82] -unit.1.3.waveform.posn.58.type=signal -unit.1.3.waveform.posn.59.channel=83 -unit.1.3.waveform.posn.59.name=DataPort[83] -unit.1.3.waveform.posn.59.type=signal -unit.1.3.waveform.posn.6.channel=30 -unit.1.3.waveform.posn.6.name=DataPort[30] -unit.1.3.waveform.posn.6.type=signal -unit.1.3.waveform.posn.60.channel=84 -unit.1.3.waveform.posn.60.name=DataPort[84] -unit.1.3.waveform.posn.60.type=signal -unit.1.3.waveform.posn.61.channel=85 -unit.1.3.waveform.posn.61.name=DataPort[85] -unit.1.3.waveform.posn.61.type=signal -unit.1.3.waveform.posn.62.channel=86 -unit.1.3.waveform.posn.62.name=DataPort[86] -unit.1.3.waveform.posn.62.type=signal -unit.1.3.waveform.posn.63.channel=87 -unit.1.3.waveform.posn.63.name=DataPort[87] -unit.1.3.waveform.posn.63.type=signal -unit.1.3.waveform.posn.64.channel=88 -unit.1.3.waveform.posn.64.name=DataPort[88] -unit.1.3.waveform.posn.64.type=signal -unit.1.3.waveform.posn.65.channel=89 -unit.1.3.waveform.posn.65.name=DataPort[89] -unit.1.3.waveform.posn.65.type=signal -unit.1.3.waveform.posn.66.channel=90 -unit.1.3.waveform.posn.66.name=DataPort[90] -unit.1.3.waveform.posn.66.type=signal -unit.1.3.waveform.posn.67.channel=91 -unit.1.3.waveform.posn.67.name=DataPort[91] -unit.1.3.waveform.posn.67.type=signal -unit.1.3.waveform.posn.68.channel=92 -unit.1.3.waveform.posn.68.name=DataPort[92] -unit.1.3.waveform.posn.68.type=signal -unit.1.3.waveform.posn.69.channel=93 -unit.1.3.waveform.posn.69.name=DataPort[93] -unit.1.3.waveform.posn.69.type=signal -unit.1.3.waveform.posn.7.channel=31 -unit.1.3.waveform.posn.7.name=DataPort[31] -unit.1.3.waveform.posn.7.type=signal -unit.1.3.waveform.posn.70.channel=94 -unit.1.3.waveform.posn.70.name=DataPort[94] -unit.1.3.waveform.posn.70.type=signal -unit.1.3.waveform.posn.71.channel=95 -unit.1.3.waveform.posn.71.name=DataPort[95] -unit.1.3.waveform.posn.71.type=signal -unit.1.3.waveform.posn.72.channel=96 -unit.1.3.waveform.posn.72.name=DataPort[96] -unit.1.3.waveform.posn.72.type=signal -unit.1.3.waveform.posn.73.channel=97 -unit.1.3.waveform.posn.73.name=DataPort[97] -unit.1.3.waveform.posn.73.type=signal -unit.1.3.waveform.posn.74.channel=98 -unit.1.3.waveform.posn.74.name=DataPort[98] -unit.1.3.waveform.posn.74.type=signal -unit.1.3.waveform.posn.75.channel=99 -unit.1.3.waveform.posn.75.name=DataPort[99] -unit.1.3.waveform.posn.75.type=signal -unit.1.3.waveform.posn.76.channel=100 -unit.1.3.waveform.posn.76.name=DataPort[100] -unit.1.3.waveform.posn.76.type=signal -unit.1.3.waveform.posn.77.channel=101 -unit.1.3.waveform.posn.77.name=DataPort[101] -unit.1.3.waveform.posn.77.type=signal -unit.1.3.waveform.posn.78.channel=102 -unit.1.3.waveform.posn.78.name=DataPort[102] -unit.1.3.waveform.posn.78.type=signal -unit.1.3.waveform.posn.79.channel=103 -unit.1.3.waveform.posn.79.name=DataPort[103] -unit.1.3.waveform.posn.79.type=signal -unit.1.3.waveform.posn.8.channel=32 -unit.1.3.waveform.posn.8.name=DataPort[32] -unit.1.3.waveform.posn.8.type=signal -unit.1.3.waveform.posn.80.channel=104 -unit.1.3.waveform.posn.80.name=DataPort[104] -unit.1.3.waveform.posn.80.type=signal -unit.1.3.waveform.posn.81.channel=105 -unit.1.3.waveform.posn.81.name=DataPort[105] -unit.1.3.waveform.posn.81.type=signal -unit.1.3.waveform.posn.82.channel=106 -unit.1.3.waveform.posn.82.name=DataPort[106] -unit.1.3.waveform.posn.82.type=signal -unit.1.3.waveform.posn.83.channel=107 -unit.1.3.waveform.posn.83.name=DataPort[107] -unit.1.3.waveform.posn.83.type=signal -unit.1.3.waveform.posn.84.channel=108 -unit.1.3.waveform.posn.84.name=DataPort[108] -unit.1.3.waveform.posn.84.type=signal -unit.1.3.waveform.posn.85.channel=109 -unit.1.3.waveform.posn.85.name=DataPort[109] -unit.1.3.waveform.posn.85.type=signal -unit.1.3.waveform.posn.86.channel=110 -unit.1.3.waveform.posn.86.name=DataPort[110] -unit.1.3.waveform.posn.86.type=signal -unit.1.3.waveform.posn.87.channel=111 -unit.1.3.waveform.posn.87.name=DataPort[111] -unit.1.3.waveform.posn.87.type=signal -unit.1.3.waveform.posn.88.channel=112 -unit.1.3.waveform.posn.88.name=DataPort[112] -unit.1.3.waveform.posn.88.type=signal -unit.1.3.waveform.posn.89.channel=113 -unit.1.3.waveform.posn.89.name=DataPort[113] -unit.1.3.waveform.posn.89.type=signal -unit.1.3.waveform.posn.9.channel=33 -unit.1.3.waveform.posn.9.name=DataPort[33] -unit.1.3.waveform.posn.9.type=signal -unit.1.3.waveform.posn.90.channel=114 -unit.1.3.waveform.posn.90.name=DataPort[114] -unit.1.3.waveform.posn.90.type=signal -unit.1.3.waveform.posn.91.channel=115 -unit.1.3.waveform.posn.91.name=DataPort[115] -unit.1.3.waveform.posn.91.type=signal -unit.1.3.waveform.posn.92.channel=116 -unit.1.3.waveform.posn.92.name=DataPort[116] -unit.1.3.waveform.posn.92.type=signal -unit.1.3.waveform.posn.93.channel=117 -unit.1.3.waveform.posn.93.name=DataPort[117] -unit.1.3.waveform.posn.93.type=signal -unit.1.3.waveform.posn.94.channel=118 -unit.1.3.waveform.posn.94.name=DataPort[118] -unit.1.3.waveform.posn.94.type=signal -unit.1.3.waveform.posn.95.channel=119 -unit.1.3.waveform.posn.95.name=DataPort[119] -unit.1.3.waveform.posn.95.type=signal -unit.1.3.waveform.posn.96.channel=120 -unit.1.3.waveform.posn.96.name=DataPort[120] -unit.1.3.waveform.posn.96.type=signal -unit.1.3.waveform.posn.97.channel=121 -unit.1.3.waveform.posn.97.name=DataPort[121] -unit.1.3.waveform.posn.97.type=signal -unit.1.3.waveform.posn.98.channel=122 -unit.1.3.waveform.posn.98.name=DataPort[122] -unit.1.3.waveform.posn.98.type=signal -unit.1.3.waveform.posn.99.channel=123 -unit.1.3.waveform.posn.99.name=DataPort[123] -unit.1.3.waveform.posn.99.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/position_calc_core.ucf b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/position_calc_core.ucf deleted file mode 100644 index 138868d7..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/position_calc_core.ucf +++ /dev/null @@ -1,3091 +0,0 @@ - - -# Global period constraint -NET "*position_calc_core/*/clk" TNM_NET = "clk_cc71cef7"; -TIMESPEC "TS_clk_cc71cef7" = PERIOD "clk_cc71cef7" 4.44116091946435 ns HIGH 50 %; - -# ce_1112_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_1112_sg_x32*" TNM_NET = "ce_1112_cc71cef7_group"; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; - -# ce_1390000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_1390000_sg_x3*" TNM_NET = "ce_1390000_cc71cef7_group"; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 6.173213678055446 ms; - -# ce_222400000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_222400000_sg_x7*" TNM_NET = "ce_222400000_cc71cef7_group"; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 987.7141884888714 ms; - -# ce_22240000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_22240000_sg_x25*" TNM_NET = "ce_22240000_cc71cef7_group"; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 98.77141884888714 ms; - -# ce_2224_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2224_sg_x32*" TNM_NET = "ce_2224_cc71cef7_group"; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; - -# ce_2500_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2500_sg_x3*" TNM_NET = "ce_2500_cc71cef7_group"; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; - -# ce_2780000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2780000_sg_x4*" TNM_NET = "ce_2780000_cc71cef7_group"; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 12.346427356110892 ms; - -# ce_2_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_2_sg_x39*" TNM_NET = "ce_2_cc71cef7_group"; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; - -# ce_35_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_35_sg_x22*" TNM_NET = "ce_35_cc71cef7_group"; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; - -# ce_5000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_5000_sg_x10*" TNM_NET = "ce_5000_cc71cef7_group"; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; - -# ce_55600000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_55600000_sg_x4*" TNM_NET = "ce_55600000_cc71cef7_group"; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 246.92854712221785 ms; - -# ce_5560000_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_5560000_sg_x12*" TNM_NET = "ce_5560000_cc71cef7_group"; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 24.692854712221784 ms; - -# ce_556_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_556_sg_x3*" TNM_NET = "ce_556_cc71cef7_group"; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; - -# ce_70_cc71cef7_group and inner group constraint -NET "*position_calc_core/*/ce_70_sg_x31*" TNM_NET = "ce_70_cc71cef7_group"; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_70_cc71cef7_group" 310.8812643625045 ns; - -# Group-to-group constraints -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_2224_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_2500_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_35_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_5000_cc71cef7_group" 35.5292873557148 ns; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_1112_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_1112_cc71cef7_group" TO "ce_70_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_1390000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_1390000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 98.77141884888714 ms; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 246.92854712221785 ms; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 24.692854712221784 ms; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_222400000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_222400000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 98.77141884888714 ms; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 49.38570942444357 ms; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 24.692854712221784 ms; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_22240000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_22240000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_2500_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_35_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_5000_cc71cef7_group" 35.5292873557148 ns; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_2224_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2224_cc71cef7_group" TO "ce_70_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_1112_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2224_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_5000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_556_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_2500_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2500_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_2780000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2780000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_1112_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2224_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2500_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_35_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_5000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_556_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_2_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_2_cc71cef7_group" TO "ce_70_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2224_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2500_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_2_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_556_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_35_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_35_cc71cef7_group" TO "ce_70_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 35.5292873557148 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 35.5292873557148 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_556_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_5000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_5000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 246.92854712221785 ms; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 49.38570942444357 ms; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 24.692854712221784 ms; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_55600000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_55600000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_1112_cc71cef7_group" 4.938570942444358 us; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 6.173213678055446 ms; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 24.692854712221784 ms; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 24.692854712221784 ms; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_2224_cc71cef7_group" 9.877141884888715 us; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_2500_cc71cef7_group" 11.102902298660874 us; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 12.346427356110892 ms; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_35_cc71cef7_group" 22.20580459732175 ns; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_5000_cc71cef7_group" 22.205804597321748 us; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 24.692854712221784 ms; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_556_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_5560000_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_5560000_cc71cef7_group" TO "ce_70_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_1112_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_2224_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_2500_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_35_cc71cef7_group" 4.44116091946435 ns; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_5000_cc71cef7_group" 17.7646436778574 ns; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 2.469285471222179 us; -TIMESPEC "TS_ce_556_cc71cef7_group_to_ce_70_cc71cef7_group" = FROM "ce_556_cc71cef7_group" TO "ce_70_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_1112_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_1112_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_1390000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_1390000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_222400000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_222400000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_22240000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_22240000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2224_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2224_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2500_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2500_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2780000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2780000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_2_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_2_cc71cef7_group" 8.8823218389287 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_35_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_35_cc71cef7_group" 155.44063218125225 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_5000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_5000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_55600000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_55600000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_5560000_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_5560000_cc71cef7_group" 44.4116091946435 ns; -TIMESPEC "TS_ce_70_cc71cef7_group_to_ce_556_cc71cef7_group" = FROM "ce_70_cc71cef7_group" TO "ce_556_cc71cef7_group" 8.8823218389287 ns; - -# Offset in constraints -#NET "del_sig_div_fofb_thres_i(0)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(1)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(2)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(3)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(4)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(5)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(6)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(7)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(8)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(9)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(10)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(11)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(12)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(13)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(14)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(15)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(16)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(17)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(18)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(19)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(20)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(21)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(22)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(23)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(24)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_fofb_thres_i(25)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(0)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(1)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(2)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(3)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(4)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(5)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(6)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(7)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(8)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(9)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(10)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(11)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(12)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(13)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(14)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(15)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(16)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(17)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(18)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(19)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(20)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(21)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(22)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(23)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(24)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_monit_thres_i(25)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(0)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(1)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(2)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(3)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(4)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(5)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(6)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(7)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(8)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(9)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(10)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(11)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(12)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(13)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(14)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(15)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(16)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(17)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(18)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(19)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(20)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(21)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(22)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(23)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(24)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "del_sig_div_tbt_thres_i(25)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(0)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(1)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(2)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(3)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(4)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(5)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(6)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(7)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(8)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(9)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(10)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(11)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(12)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(13)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(14)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(15)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(16)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(17)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(18)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(19)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(20)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(21)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(22)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(23)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ksum_i(24)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(0)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(1)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(2)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(3)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(4)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(5)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(6)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(7)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(8)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(9)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(10)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(11)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(12)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(13)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(14)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(15)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(16)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(17)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(18)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(19)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(20)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(21)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(22)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(23)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "kx_i(24)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(0)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(1)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(2)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(3)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(4)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(5)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(6)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(7)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(8)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(9)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(10)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(11)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(12)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(13)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(14)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(15)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(16)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(17)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(18)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(19)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(20)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(21)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(22)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(23)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -#NET "ky_i(24)" OFFSET = IN : 8.8823218389287 : BEFORE "clk"; -# -## Offset out constraints -#NET "adc_ch0_dbg_data_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(0)" FAST; -#NET "adc_ch0_dbg_data_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(1)" FAST; -#NET "adc_ch0_dbg_data_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(2)" FAST; -#NET "adc_ch0_dbg_data_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(3)" FAST; -#NET "adc_ch0_dbg_data_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(4)" FAST; -#NET "adc_ch0_dbg_data_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(5)" FAST; -#NET "adc_ch0_dbg_data_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(6)" FAST; -#NET "adc_ch0_dbg_data_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(7)" FAST; -#NET "adc_ch0_dbg_data_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(8)" FAST; -#NET "adc_ch0_dbg_data_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(9)" FAST; -#NET "adc_ch0_dbg_data_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(10)" FAST; -#NET "adc_ch0_dbg_data_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(11)" FAST; -#NET "adc_ch0_dbg_data_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(12)" FAST; -#NET "adc_ch0_dbg_data_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(13)" FAST; -#NET "adc_ch0_dbg_data_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(14)" FAST; -#NET "adc_ch0_dbg_data_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch0_dbg_data_o(15)" FAST; -#NET "adc_ch1_dbg_data_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(0)" FAST; -#NET "adc_ch1_dbg_data_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(1)" FAST; -#NET "adc_ch1_dbg_data_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(2)" FAST; -#NET "adc_ch1_dbg_data_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(3)" FAST; -#NET "adc_ch1_dbg_data_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(4)" FAST; -#NET "adc_ch1_dbg_data_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(5)" FAST; -#NET "adc_ch1_dbg_data_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(6)" FAST; -#NET "adc_ch1_dbg_data_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(7)" FAST; -#NET "adc_ch1_dbg_data_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(8)" FAST; -#NET "adc_ch1_dbg_data_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(9)" FAST; -#NET "adc_ch1_dbg_data_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(10)" FAST; -#NET "adc_ch1_dbg_data_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(11)" FAST; -#NET "adc_ch1_dbg_data_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(12)" FAST; -#NET "adc_ch1_dbg_data_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(13)" FAST; -#NET "adc_ch1_dbg_data_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(14)" FAST; -#NET "adc_ch1_dbg_data_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch1_dbg_data_o(15)" FAST; -#NET "adc_ch2_dbg_data_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(0)" FAST; -#NET "adc_ch2_dbg_data_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(1)" FAST; -#NET "adc_ch2_dbg_data_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(2)" FAST; -#NET "adc_ch2_dbg_data_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(3)" FAST; -#NET "adc_ch2_dbg_data_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(4)" FAST; -#NET "adc_ch2_dbg_data_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(5)" FAST; -#NET "adc_ch2_dbg_data_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(6)" FAST; -#NET "adc_ch2_dbg_data_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(7)" FAST; -#NET "adc_ch2_dbg_data_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(8)" FAST; -#NET "adc_ch2_dbg_data_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(9)" FAST; -#NET "adc_ch2_dbg_data_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(10)" FAST; -#NET "adc_ch2_dbg_data_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(11)" FAST; -#NET "adc_ch2_dbg_data_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(12)" FAST; -#NET "adc_ch2_dbg_data_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(13)" FAST; -#NET "adc_ch2_dbg_data_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(14)" FAST; -#NET "adc_ch2_dbg_data_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch2_dbg_data_o(15)" FAST; -#NET "adc_ch3_dbg_data_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(0)" FAST; -#NET "adc_ch3_dbg_data_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(1)" FAST; -#NET "adc_ch3_dbg_data_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(2)" FAST; -#NET "adc_ch3_dbg_data_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(3)" FAST; -#NET "adc_ch3_dbg_data_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(4)" FAST; -#NET "adc_ch3_dbg_data_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(5)" FAST; -#NET "adc_ch3_dbg_data_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(6)" FAST; -#NET "adc_ch3_dbg_data_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(7)" FAST; -#NET "adc_ch3_dbg_data_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(8)" FAST; -#NET "adc_ch3_dbg_data_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(9)" FAST; -#NET "adc_ch3_dbg_data_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(10)" FAST; -#NET "adc_ch3_dbg_data_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(11)" FAST; -#NET "adc_ch3_dbg_data_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(12)" FAST; -#NET "adc_ch3_dbg_data_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(13)" FAST; -#NET "adc_ch3_dbg_data_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(14)" FAST; -#NET "adc_ch3_dbg_data_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "adc_ch3_dbg_data_o(15)" FAST; -#NET "bpf_ch0_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(0)" FAST; -#NET "bpf_ch0_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(1)" FAST; -#NET "bpf_ch0_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(2)" FAST; -#NET "bpf_ch0_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(3)" FAST; -#NET "bpf_ch0_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(4)" FAST; -#NET "bpf_ch0_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(5)" FAST; -#NET "bpf_ch0_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(6)" FAST; -#NET "bpf_ch0_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(7)" FAST; -#NET "bpf_ch0_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(8)" FAST; -#NET "bpf_ch0_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(9)" FAST; -#NET "bpf_ch0_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(10)" FAST; -#NET "bpf_ch0_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(11)" FAST; -#NET "bpf_ch0_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(12)" FAST; -#NET "bpf_ch0_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(13)" FAST; -#NET "bpf_ch0_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(14)" FAST; -#NET "bpf_ch0_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(15)" FAST; -#NET "bpf_ch0_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(16)" FAST; -#NET "bpf_ch0_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(17)" FAST; -#NET "bpf_ch0_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(18)" FAST; -#NET "bpf_ch0_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(19)" FAST; -#NET "bpf_ch0_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(20)" FAST; -#NET "bpf_ch0_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(21)" FAST; -#NET "bpf_ch0_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(22)" FAST; -#NET "bpf_ch0_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch0_o(23)" FAST; -#NET "bpf_ch1_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(0)" FAST; -#NET "bpf_ch1_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(1)" FAST; -#NET "bpf_ch1_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(2)" FAST; -#NET "bpf_ch1_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(3)" FAST; -#NET "bpf_ch1_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(4)" FAST; -#NET "bpf_ch1_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(5)" FAST; -#NET "bpf_ch1_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(6)" FAST; -#NET "bpf_ch1_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(7)" FAST; -#NET "bpf_ch1_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(8)" FAST; -#NET "bpf_ch1_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(9)" FAST; -#NET "bpf_ch1_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(10)" FAST; -#NET "bpf_ch1_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(11)" FAST; -#NET "bpf_ch1_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(12)" FAST; -#NET "bpf_ch1_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(13)" FAST; -#NET "bpf_ch1_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(14)" FAST; -#NET "bpf_ch1_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(15)" FAST; -#NET "bpf_ch1_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(16)" FAST; -#NET "bpf_ch1_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(17)" FAST; -#NET "bpf_ch1_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(18)" FAST; -#NET "bpf_ch1_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(19)" FAST; -#NET "bpf_ch1_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(20)" FAST; -#NET "bpf_ch1_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(21)" FAST; -#NET "bpf_ch1_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(22)" FAST; -#NET "bpf_ch1_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch1_o(23)" FAST; -#NET "bpf_ch2_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(0)" FAST; -#NET "bpf_ch2_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(1)" FAST; -#NET "bpf_ch2_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(2)" FAST; -#NET "bpf_ch2_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(3)" FAST; -#NET "bpf_ch2_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(4)" FAST; -#NET "bpf_ch2_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(5)" FAST; -#NET "bpf_ch2_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(6)" FAST; -#NET "bpf_ch2_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(7)" FAST; -#NET "bpf_ch2_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(8)" FAST; -#NET "bpf_ch2_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(9)" FAST; -#NET "bpf_ch2_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(10)" FAST; -#NET "bpf_ch2_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(11)" FAST; -#NET "bpf_ch2_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(12)" FAST; -#NET "bpf_ch2_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(13)" FAST; -#NET "bpf_ch2_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(14)" FAST; -#NET "bpf_ch2_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(15)" FAST; -#NET "bpf_ch2_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(16)" FAST; -#NET "bpf_ch2_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(17)" FAST; -#NET "bpf_ch2_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(18)" FAST; -#NET "bpf_ch2_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(19)" FAST; -#NET "bpf_ch2_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(20)" FAST; -#NET "bpf_ch2_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(21)" FAST; -#NET "bpf_ch2_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(22)" FAST; -#NET "bpf_ch2_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch2_o(23)" FAST; -#NET "bpf_ch3_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(0)" FAST; -#NET "bpf_ch3_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(1)" FAST; -#NET "bpf_ch3_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(2)" FAST; -#NET "bpf_ch3_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(3)" FAST; -#NET "bpf_ch3_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(4)" FAST; -#NET "bpf_ch3_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(5)" FAST; -#NET "bpf_ch3_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(6)" FAST; -#NET "bpf_ch3_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(7)" FAST; -#NET "bpf_ch3_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(8)" FAST; -#NET "bpf_ch3_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(9)" FAST; -#NET "bpf_ch3_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(10)" FAST; -#NET "bpf_ch3_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(11)" FAST; -#NET "bpf_ch3_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(12)" FAST; -#NET "bpf_ch3_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(13)" FAST; -#NET "bpf_ch3_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(14)" FAST; -#NET "bpf_ch3_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(15)" FAST; -#NET "bpf_ch3_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(16)" FAST; -#NET "bpf_ch3_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(17)" FAST; -#NET "bpf_ch3_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(18)" FAST; -#NET "bpf_ch3_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(19)" FAST; -#NET "bpf_ch3_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(20)" FAST; -#NET "bpf_ch3_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(21)" FAST; -#NET "bpf_ch3_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(22)" FAST; -#NET "bpf_ch3_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "bpf_ch3_o(23)" FAST; -#NET "cic_fofb_q_01_missing_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "cic_fofb_q_01_missing_o" FAST; -#NET "cic_fofb_q_23_missing_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "cic_fofb_q_23_missing_o" FAST; -#NET "fofb_amp_ch0_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(0)" FAST; -#NET "fofb_amp_ch0_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(1)" FAST; -#NET "fofb_amp_ch0_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(2)" FAST; -#NET "fofb_amp_ch0_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(3)" FAST; -#NET "fofb_amp_ch0_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(4)" FAST; -#NET "fofb_amp_ch0_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(5)" FAST; -#NET "fofb_amp_ch0_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(6)" FAST; -#NET "fofb_amp_ch0_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(7)" FAST; -#NET "fofb_amp_ch0_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(8)" FAST; -#NET "fofb_amp_ch0_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(9)" FAST; -#NET "fofb_amp_ch0_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(10)" FAST; -#NET "fofb_amp_ch0_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(11)" FAST; -#NET "fofb_amp_ch0_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(12)" FAST; -#NET "fofb_amp_ch0_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(13)" FAST; -#NET "fofb_amp_ch0_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(14)" FAST; -#NET "fofb_amp_ch0_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(15)" FAST; -#NET "fofb_amp_ch0_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(16)" FAST; -#NET "fofb_amp_ch0_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(17)" FAST; -#NET "fofb_amp_ch0_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(18)" FAST; -#NET "fofb_amp_ch0_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(19)" FAST; -#NET "fofb_amp_ch0_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(20)" FAST; -#NET "fofb_amp_ch0_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(21)" FAST; -#NET "fofb_amp_ch0_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(22)" FAST; -#NET "fofb_amp_ch0_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch0_o(23)" FAST; -#NET "fofb_amp_ch1_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(0)" FAST; -#NET "fofb_amp_ch1_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(1)" FAST; -#NET "fofb_amp_ch1_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(2)" FAST; -#NET "fofb_amp_ch1_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(3)" FAST; -#NET "fofb_amp_ch1_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(4)" FAST; -#NET "fofb_amp_ch1_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(5)" FAST; -#NET "fofb_amp_ch1_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(6)" FAST; -#NET "fofb_amp_ch1_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(7)" FAST; -#NET "fofb_amp_ch1_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(8)" FAST; -#NET "fofb_amp_ch1_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(9)" FAST; -#NET "fofb_amp_ch1_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(10)" FAST; -#NET "fofb_amp_ch1_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(11)" FAST; -#NET "fofb_amp_ch1_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(12)" FAST; -#NET "fofb_amp_ch1_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(13)" FAST; -#NET "fofb_amp_ch1_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(14)" FAST; -#NET "fofb_amp_ch1_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(15)" FAST; -#NET "fofb_amp_ch1_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(16)" FAST; -#NET "fofb_amp_ch1_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(17)" FAST; -#NET "fofb_amp_ch1_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(18)" FAST; -#NET "fofb_amp_ch1_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(19)" FAST; -#NET "fofb_amp_ch1_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(20)" FAST; -#NET "fofb_amp_ch1_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(21)" FAST; -#NET "fofb_amp_ch1_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(22)" FAST; -#NET "fofb_amp_ch1_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch1_o(23)" FAST; -#NET "fofb_amp_ch2_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(0)" FAST; -#NET "fofb_amp_ch2_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(1)" FAST; -#NET "fofb_amp_ch2_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(2)" FAST; -#NET "fofb_amp_ch2_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(3)" FAST; -#NET "fofb_amp_ch2_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(4)" FAST; -#NET "fofb_amp_ch2_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(5)" FAST; -#NET "fofb_amp_ch2_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(6)" FAST; -#NET "fofb_amp_ch2_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(7)" FAST; -#NET "fofb_amp_ch2_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(8)" FAST; -#NET "fofb_amp_ch2_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(9)" FAST; -#NET "fofb_amp_ch2_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(10)" FAST; -#NET "fofb_amp_ch2_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(11)" FAST; -#NET "fofb_amp_ch2_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(12)" FAST; -#NET "fofb_amp_ch2_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(13)" FAST; -#NET "fofb_amp_ch2_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(14)" FAST; -#NET "fofb_amp_ch2_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(15)" FAST; -#NET "fofb_amp_ch2_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(16)" FAST; -#NET "fofb_amp_ch2_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(17)" FAST; -#NET "fofb_amp_ch2_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(18)" FAST; -#NET "fofb_amp_ch2_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(19)" FAST; -#NET "fofb_amp_ch2_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(20)" FAST; -#NET "fofb_amp_ch2_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(21)" FAST; -#NET "fofb_amp_ch2_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(22)" FAST; -#NET "fofb_amp_ch2_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch2_o(23)" FAST; -#NET "fofb_amp_ch3_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(0)" FAST; -#NET "fofb_amp_ch3_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(1)" FAST; -#NET "fofb_amp_ch3_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(2)" FAST; -#NET "fofb_amp_ch3_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(3)" FAST; -#NET "fofb_amp_ch3_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(4)" FAST; -#NET "fofb_amp_ch3_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(5)" FAST; -#NET "fofb_amp_ch3_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(6)" FAST; -#NET "fofb_amp_ch3_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(7)" FAST; -#NET "fofb_amp_ch3_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(8)" FAST; -#NET "fofb_amp_ch3_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(9)" FAST; -#NET "fofb_amp_ch3_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(10)" FAST; -#NET "fofb_amp_ch3_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(11)" FAST; -#NET "fofb_amp_ch3_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(12)" FAST; -#NET "fofb_amp_ch3_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(13)" FAST; -#NET "fofb_amp_ch3_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(14)" FAST; -#NET "fofb_amp_ch3_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(15)" FAST; -#NET "fofb_amp_ch3_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(16)" FAST; -#NET "fofb_amp_ch3_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(17)" FAST; -#NET "fofb_amp_ch3_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(18)" FAST; -#NET "fofb_amp_ch3_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(19)" FAST; -#NET "fofb_amp_ch3_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(20)" FAST; -#NET "fofb_amp_ch3_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(21)" FAST; -#NET "fofb_amp_ch3_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(22)" FAST; -#NET "fofb_amp_ch3_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_amp_ch3_o(23)" FAST; -#NET "fofb_decim_ch0_i_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(0)" FAST; -#NET "fofb_decim_ch0_i_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(1)" FAST; -#NET "fofb_decim_ch0_i_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(2)" FAST; -#NET "fofb_decim_ch0_i_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(3)" FAST; -#NET "fofb_decim_ch0_i_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(4)" FAST; -#NET "fofb_decim_ch0_i_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(5)" FAST; -#NET "fofb_decim_ch0_i_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(6)" FAST; -#NET "fofb_decim_ch0_i_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(7)" FAST; -#NET "fofb_decim_ch0_i_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(8)" FAST; -#NET "fofb_decim_ch0_i_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(9)" FAST; -#NET "fofb_decim_ch0_i_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(10)" FAST; -#NET "fofb_decim_ch0_i_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(11)" FAST; -#NET "fofb_decim_ch0_i_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(12)" FAST; -#NET "fofb_decim_ch0_i_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(13)" FAST; -#NET "fofb_decim_ch0_i_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(14)" FAST; -#NET "fofb_decim_ch0_i_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(15)" FAST; -#NET "fofb_decim_ch0_i_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(16)" FAST; -#NET "fofb_decim_ch0_i_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(17)" FAST; -#NET "fofb_decim_ch0_i_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(18)" FAST; -#NET "fofb_decim_ch0_i_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(19)" FAST; -#NET "fofb_decim_ch0_i_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(20)" FAST; -#NET "fofb_decim_ch0_i_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(21)" FAST; -#NET "fofb_decim_ch0_i_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(22)" FAST; -#NET "fofb_decim_ch0_i_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_i_o(23)" FAST; -#NET "fofb_decim_ch0_q_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(0)" FAST; -#NET "fofb_decim_ch0_q_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(1)" FAST; -#NET "fofb_decim_ch0_q_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(2)" FAST; -#NET "fofb_decim_ch0_q_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(3)" FAST; -#NET "fofb_decim_ch0_q_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(4)" FAST; -#NET "fofb_decim_ch0_q_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(5)" FAST; -#NET "fofb_decim_ch0_q_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(6)" FAST; -#NET "fofb_decim_ch0_q_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(7)" FAST; -#NET "fofb_decim_ch0_q_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(8)" FAST; -#NET "fofb_decim_ch0_q_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(9)" FAST; -#NET "fofb_decim_ch0_q_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(10)" FAST; -#NET "fofb_decim_ch0_q_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(11)" FAST; -#NET "fofb_decim_ch0_q_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(12)" FAST; -#NET "fofb_decim_ch0_q_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(13)" FAST; -#NET "fofb_decim_ch0_q_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(14)" FAST; -#NET "fofb_decim_ch0_q_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(15)" FAST; -#NET "fofb_decim_ch0_q_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(16)" FAST; -#NET "fofb_decim_ch0_q_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(17)" FAST; -#NET "fofb_decim_ch0_q_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(18)" FAST; -#NET "fofb_decim_ch0_q_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(19)" FAST; -#NET "fofb_decim_ch0_q_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(20)" FAST; -#NET "fofb_decim_ch0_q_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(21)" FAST; -#NET "fofb_decim_ch0_q_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(22)" FAST; -#NET "fofb_decim_ch0_q_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch0_q_o(23)" FAST; -#NET "fofb_decim_ch1_i_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(0)" FAST; -#NET "fofb_decim_ch1_i_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(1)" FAST; -#NET "fofb_decim_ch1_i_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(2)" FAST; -#NET "fofb_decim_ch1_i_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(3)" FAST; -#NET "fofb_decim_ch1_i_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(4)" FAST; -#NET "fofb_decim_ch1_i_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(5)" FAST; -#NET "fofb_decim_ch1_i_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(6)" FAST; -#NET "fofb_decim_ch1_i_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(7)" FAST; -#NET "fofb_decim_ch1_i_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(8)" FAST; -#NET "fofb_decim_ch1_i_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(9)" FAST; -#NET "fofb_decim_ch1_i_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(10)" FAST; -#NET "fofb_decim_ch1_i_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(11)" FAST; -#NET "fofb_decim_ch1_i_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(12)" FAST; -#NET "fofb_decim_ch1_i_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(13)" FAST; -#NET "fofb_decim_ch1_i_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(14)" FAST; -#NET "fofb_decim_ch1_i_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(15)" FAST; -#NET "fofb_decim_ch1_i_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(16)" FAST; -#NET "fofb_decim_ch1_i_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(17)" FAST; -#NET "fofb_decim_ch1_i_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(18)" FAST; -#NET "fofb_decim_ch1_i_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(19)" FAST; -#NET "fofb_decim_ch1_i_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(20)" FAST; -#NET "fofb_decim_ch1_i_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(21)" FAST; -#NET "fofb_decim_ch1_i_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(22)" FAST; -#NET "fofb_decim_ch1_i_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_i_o(23)" FAST; -#NET "fofb_decim_ch1_q_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(0)" FAST; -#NET "fofb_decim_ch1_q_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(1)" FAST; -#NET "fofb_decim_ch1_q_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(2)" FAST; -#NET "fofb_decim_ch1_q_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(3)" FAST; -#NET "fofb_decim_ch1_q_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(4)" FAST; -#NET "fofb_decim_ch1_q_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(5)" FAST; -#NET "fofb_decim_ch1_q_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(6)" FAST; -#NET "fofb_decim_ch1_q_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(7)" FAST; -#NET "fofb_decim_ch1_q_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(8)" FAST; -#NET "fofb_decim_ch1_q_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(9)" FAST; -#NET "fofb_decim_ch1_q_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(10)" FAST; -#NET "fofb_decim_ch1_q_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(11)" FAST; -#NET "fofb_decim_ch1_q_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(12)" FAST; -#NET "fofb_decim_ch1_q_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(13)" FAST; -#NET "fofb_decim_ch1_q_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(14)" FAST; -#NET "fofb_decim_ch1_q_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(15)" FAST; -#NET "fofb_decim_ch1_q_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(16)" FAST; -#NET "fofb_decim_ch1_q_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(17)" FAST; -#NET "fofb_decim_ch1_q_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(18)" FAST; -#NET "fofb_decim_ch1_q_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(19)" FAST; -#NET "fofb_decim_ch1_q_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(20)" FAST; -#NET "fofb_decim_ch1_q_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(21)" FAST; -#NET "fofb_decim_ch1_q_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(22)" FAST; -#NET "fofb_decim_ch1_q_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch1_q_o(23)" FAST; -#NET "fofb_decim_ch2_i_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(0)" FAST; -#NET "fofb_decim_ch2_i_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(1)" FAST; -#NET "fofb_decim_ch2_i_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(2)" FAST; -#NET "fofb_decim_ch2_i_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(3)" FAST; -#NET "fofb_decim_ch2_i_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(4)" FAST; -#NET "fofb_decim_ch2_i_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(5)" FAST; -#NET "fofb_decim_ch2_i_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(6)" FAST; -#NET "fofb_decim_ch2_i_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(7)" FAST; -#NET "fofb_decim_ch2_i_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(8)" FAST; -#NET "fofb_decim_ch2_i_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(9)" FAST; -#NET "fofb_decim_ch2_i_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(10)" FAST; -#NET "fofb_decim_ch2_i_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(11)" FAST; -#NET "fofb_decim_ch2_i_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(12)" FAST; -#NET "fofb_decim_ch2_i_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(13)" FAST; -#NET "fofb_decim_ch2_i_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(14)" FAST; -#NET "fofb_decim_ch2_i_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(15)" FAST; -#NET "fofb_decim_ch2_i_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(16)" FAST; -#NET "fofb_decim_ch2_i_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(17)" FAST; -#NET "fofb_decim_ch2_i_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(18)" FAST; -#NET "fofb_decim_ch2_i_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(19)" FAST; -#NET "fofb_decim_ch2_i_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(20)" FAST; -#NET "fofb_decim_ch2_i_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(21)" FAST; -#NET "fofb_decim_ch2_i_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(22)" FAST; -#NET "fofb_decim_ch2_i_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_i_o(23)" FAST; -#NET "fofb_decim_ch2_q_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(0)" FAST; -#NET "fofb_decim_ch2_q_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(1)" FAST; -#NET "fofb_decim_ch2_q_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(2)" FAST; -#NET "fofb_decim_ch2_q_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(3)" FAST; -#NET "fofb_decim_ch2_q_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(4)" FAST; -#NET "fofb_decim_ch2_q_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(5)" FAST; -#NET "fofb_decim_ch2_q_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(6)" FAST; -#NET "fofb_decim_ch2_q_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(7)" FAST; -#NET "fofb_decim_ch2_q_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(8)" FAST; -#NET "fofb_decim_ch2_q_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(9)" FAST; -#NET "fofb_decim_ch2_q_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(10)" FAST; -#NET "fofb_decim_ch2_q_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(11)" FAST; -#NET "fofb_decim_ch2_q_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(12)" FAST; -#NET "fofb_decim_ch2_q_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(13)" FAST; -#NET "fofb_decim_ch2_q_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(14)" FAST; -#NET "fofb_decim_ch2_q_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(15)" FAST; -#NET "fofb_decim_ch2_q_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(16)" FAST; -#NET "fofb_decim_ch2_q_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(17)" FAST; -#NET "fofb_decim_ch2_q_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(18)" FAST; -#NET "fofb_decim_ch2_q_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(19)" FAST; -#NET "fofb_decim_ch2_q_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(20)" FAST; -#NET "fofb_decim_ch2_q_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(21)" FAST; -#NET "fofb_decim_ch2_q_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(22)" FAST; -#NET "fofb_decim_ch2_q_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch2_q_o(23)" FAST; -#NET "fofb_decim_ch3_i_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(0)" FAST; -#NET "fofb_decim_ch3_i_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(1)" FAST; -#NET "fofb_decim_ch3_i_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(2)" FAST; -#NET "fofb_decim_ch3_i_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(3)" FAST; -#NET "fofb_decim_ch3_i_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(4)" FAST; -#NET "fofb_decim_ch3_i_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(5)" FAST; -#NET "fofb_decim_ch3_i_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(6)" FAST; -#NET "fofb_decim_ch3_i_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(7)" FAST; -#NET "fofb_decim_ch3_i_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(8)" FAST; -#NET "fofb_decim_ch3_i_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(9)" FAST; -#NET "fofb_decim_ch3_i_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(10)" FAST; -#NET "fofb_decim_ch3_i_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(11)" FAST; -#NET "fofb_decim_ch3_i_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(12)" FAST; -#NET "fofb_decim_ch3_i_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(13)" FAST; -#NET "fofb_decim_ch3_i_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(14)" FAST; -#NET "fofb_decim_ch3_i_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(15)" FAST; -#NET "fofb_decim_ch3_i_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(16)" FAST; -#NET "fofb_decim_ch3_i_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(17)" FAST; -#NET "fofb_decim_ch3_i_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(18)" FAST; -#NET "fofb_decim_ch3_i_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(19)" FAST; -#NET "fofb_decim_ch3_i_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(20)" FAST; -#NET "fofb_decim_ch3_i_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(21)" FAST; -#NET "fofb_decim_ch3_i_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(22)" FAST; -#NET "fofb_decim_ch3_i_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_i_o(23)" FAST; -#NET "fofb_decim_ch3_q_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(0)" FAST; -#NET "fofb_decim_ch3_q_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(1)" FAST; -#NET "fofb_decim_ch3_q_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(2)" FAST; -#NET "fofb_decim_ch3_q_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(3)" FAST; -#NET "fofb_decim_ch3_q_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(4)" FAST; -#NET "fofb_decim_ch3_q_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(5)" FAST; -#NET "fofb_decim_ch3_q_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(6)" FAST; -#NET "fofb_decim_ch3_q_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(7)" FAST; -#NET "fofb_decim_ch3_q_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(8)" FAST; -#NET "fofb_decim_ch3_q_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(9)" FAST; -#NET "fofb_decim_ch3_q_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(10)" FAST; -#NET "fofb_decim_ch3_q_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(11)" FAST; -#NET "fofb_decim_ch3_q_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(12)" FAST; -#NET "fofb_decim_ch3_q_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(13)" FAST; -#NET "fofb_decim_ch3_q_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(14)" FAST; -#NET "fofb_decim_ch3_q_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(15)" FAST; -#NET "fofb_decim_ch3_q_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(16)" FAST; -#NET "fofb_decim_ch3_q_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(17)" FAST; -#NET "fofb_decim_ch3_q_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(18)" FAST; -#NET "fofb_decim_ch3_q_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(19)" FAST; -#NET "fofb_decim_ch3_q_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(20)" FAST; -#NET "fofb_decim_ch3_q_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(21)" FAST; -#NET "fofb_decim_ch3_q_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(22)" FAST; -#NET "fofb_decim_ch3_q_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_decim_ch3_q_o(23)" FAST; -#NET "fofb_pha_ch0_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(0)" FAST; -#NET "fofb_pha_ch0_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(1)" FAST; -#NET "fofb_pha_ch0_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(2)" FAST; -#NET "fofb_pha_ch0_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(3)" FAST; -#NET "fofb_pha_ch0_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(4)" FAST; -#NET "fofb_pha_ch0_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(5)" FAST; -#NET "fofb_pha_ch0_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(6)" FAST; -#NET "fofb_pha_ch0_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(7)" FAST; -#NET "fofb_pha_ch0_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(8)" FAST; -#NET "fofb_pha_ch0_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(9)" FAST; -#NET "fofb_pha_ch0_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(10)" FAST; -#NET "fofb_pha_ch0_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(11)" FAST; -#NET "fofb_pha_ch0_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(12)" FAST; -#NET "fofb_pha_ch0_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(13)" FAST; -#NET "fofb_pha_ch0_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(14)" FAST; -#NET "fofb_pha_ch0_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(15)" FAST; -#NET "fofb_pha_ch0_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(16)" FAST; -#NET "fofb_pha_ch0_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(17)" FAST; -#NET "fofb_pha_ch0_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(18)" FAST; -#NET "fofb_pha_ch0_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(19)" FAST; -#NET "fofb_pha_ch0_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(20)" FAST; -#NET "fofb_pha_ch0_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(21)" FAST; -#NET "fofb_pha_ch0_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(22)" FAST; -#NET "fofb_pha_ch0_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch0_o(23)" FAST; -#NET "fofb_pha_ch1_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(0)" FAST; -#NET "fofb_pha_ch1_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(1)" FAST; -#NET "fofb_pha_ch1_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(2)" FAST; -#NET "fofb_pha_ch1_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(3)" FAST; -#NET "fofb_pha_ch1_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(4)" FAST; -#NET "fofb_pha_ch1_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(5)" FAST; -#NET "fofb_pha_ch1_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(6)" FAST; -#NET "fofb_pha_ch1_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(7)" FAST; -#NET "fofb_pha_ch1_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(8)" FAST; -#NET "fofb_pha_ch1_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(9)" FAST; -#NET "fofb_pha_ch1_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(10)" FAST; -#NET "fofb_pha_ch1_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(11)" FAST; -#NET "fofb_pha_ch1_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(12)" FAST; -#NET "fofb_pha_ch1_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(13)" FAST; -#NET "fofb_pha_ch1_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(14)" FAST; -#NET "fofb_pha_ch1_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(15)" FAST; -#NET "fofb_pha_ch1_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(16)" FAST; -#NET "fofb_pha_ch1_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(17)" FAST; -#NET "fofb_pha_ch1_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(18)" FAST; -#NET "fofb_pha_ch1_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(19)" FAST; -#NET "fofb_pha_ch1_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(20)" FAST; -#NET "fofb_pha_ch1_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(21)" FAST; -#NET "fofb_pha_ch1_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(22)" FAST; -#NET "fofb_pha_ch1_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch1_o(23)" FAST; -#NET "fofb_pha_ch2_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(0)" FAST; -#NET "fofb_pha_ch2_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(1)" FAST; -#NET "fofb_pha_ch2_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(2)" FAST; -#NET "fofb_pha_ch2_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(3)" FAST; -#NET "fofb_pha_ch2_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(4)" FAST; -#NET "fofb_pha_ch2_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(5)" FAST; -#NET "fofb_pha_ch2_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(6)" FAST; -#NET "fofb_pha_ch2_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(7)" FAST; -#NET "fofb_pha_ch2_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(8)" FAST; -#NET "fofb_pha_ch2_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(9)" FAST; -#NET "fofb_pha_ch2_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(10)" FAST; -#NET "fofb_pha_ch2_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(11)" FAST; -#NET "fofb_pha_ch2_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(12)" FAST; -#NET "fofb_pha_ch2_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(13)" FAST; -#NET "fofb_pha_ch2_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(14)" FAST; -#NET "fofb_pha_ch2_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(15)" FAST; -#NET "fofb_pha_ch2_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(16)" FAST; -#NET "fofb_pha_ch2_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(17)" FAST; -#NET "fofb_pha_ch2_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(18)" FAST; -#NET "fofb_pha_ch2_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(19)" FAST; -#NET "fofb_pha_ch2_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(20)" FAST; -#NET "fofb_pha_ch2_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(21)" FAST; -#NET "fofb_pha_ch2_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(22)" FAST; -#NET "fofb_pha_ch2_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch2_o(23)" FAST; -#NET "fofb_pha_ch3_o(0)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(0)" FAST; -#NET "fofb_pha_ch3_o(1)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(1)" FAST; -#NET "fofb_pha_ch3_o(2)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(2)" FAST; -#NET "fofb_pha_ch3_o(3)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(3)" FAST; -#NET "fofb_pha_ch3_o(4)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(4)" FAST; -#NET "fofb_pha_ch3_o(5)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(5)" FAST; -#NET "fofb_pha_ch3_o(6)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(6)" FAST; -#NET "fofb_pha_ch3_o(7)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(7)" FAST; -#NET "fofb_pha_ch3_o(8)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(8)" FAST; -#NET "fofb_pha_ch3_o(9)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(9)" FAST; -#NET "fofb_pha_ch3_o(10)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(10)" FAST; -#NET "fofb_pha_ch3_o(11)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(11)" FAST; -#NET "fofb_pha_ch3_o(12)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(12)" FAST; -#NET "fofb_pha_ch3_o(13)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(13)" FAST; -#NET "fofb_pha_ch3_o(14)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(14)" FAST; -#NET "fofb_pha_ch3_o(15)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(15)" FAST; -#NET "fofb_pha_ch3_o(16)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(16)" FAST; -#NET "fofb_pha_ch3_o(17)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(17)" FAST; -#NET "fofb_pha_ch3_o(18)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(18)" FAST; -#NET "fofb_pha_ch3_o(19)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(19)" FAST; -#NET "fofb_pha_ch3_o(20)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(20)" FAST; -#NET "fofb_pha_ch3_o(21)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(21)" FAST; -#NET "fofb_pha_ch3_o(22)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(22)" FAST; -#NET "fofb_pha_ch3_o(23)" OFFSET = OUT : 9877.141884888715 : AFTER "clk"; -#NET "fofb_pha_ch3_o(23)" FAST; -#NET "mix_ch0_i_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(0)" FAST; -#NET "mix_ch0_i_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(1)" FAST; -#NET "mix_ch0_i_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(2)" FAST; -#NET "mix_ch0_i_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(3)" FAST; -#NET "mix_ch0_i_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(4)" FAST; -#NET "mix_ch0_i_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(5)" FAST; -#NET "mix_ch0_i_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(6)" FAST; -#NET "mix_ch0_i_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(7)" FAST; -#NET "mix_ch0_i_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(8)" FAST; -#NET "mix_ch0_i_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(9)" FAST; -#NET "mix_ch0_i_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(10)" FAST; -#NET "mix_ch0_i_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(11)" FAST; -#NET "mix_ch0_i_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(12)" FAST; -#NET "mix_ch0_i_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(13)" FAST; -#NET "mix_ch0_i_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(14)" FAST; -#NET "mix_ch0_i_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(15)" FAST; -#NET "mix_ch0_i_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(16)" FAST; -#NET "mix_ch0_i_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(17)" FAST; -#NET "mix_ch0_i_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(18)" FAST; -#NET "mix_ch0_i_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(19)" FAST; -#NET "mix_ch0_i_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(20)" FAST; -#NET "mix_ch0_i_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(21)" FAST; -#NET "mix_ch0_i_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(22)" FAST; -#NET "mix_ch0_i_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_i_o(23)" FAST; -#NET "mix_ch0_q_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(0)" FAST; -#NET "mix_ch0_q_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(1)" FAST; -#NET "mix_ch0_q_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(2)" FAST; -#NET "mix_ch0_q_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(3)" FAST; -#NET "mix_ch0_q_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(4)" FAST; -#NET "mix_ch0_q_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(5)" FAST; -#NET "mix_ch0_q_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(6)" FAST; -#NET "mix_ch0_q_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(7)" FAST; -#NET "mix_ch0_q_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(8)" FAST; -#NET "mix_ch0_q_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(9)" FAST; -#NET "mix_ch0_q_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(10)" FAST; -#NET "mix_ch0_q_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(11)" FAST; -#NET "mix_ch0_q_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(12)" FAST; -#NET "mix_ch0_q_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(13)" FAST; -#NET "mix_ch0_q_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(14)" FAST; -#NET "mix_ch0_q_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(15)" FAST; -#NET "mix_ch0_q_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(16)" FAST; -#NET "mix_ch0_q_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(17)" FAST; -#NET "mix_ch0_q_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(18)" FAST; -#NET "mix_ch0_q_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(19)" FAST; -#NET "mix_ch0_q_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(20)" FAST; -#NET "mix_ch0_q_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(21)" FAST; -#NET "mix_ch0_q_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(22)" FAST; -#NET "mix_ch0_q_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch0_q_o(23)" FAST; -#NET "mix_ch1_i_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(0)" FAST; -#NET "mix_ch1_i_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(1)" FAST; -#NET "mix_ch1_i_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(2)" FAST; -#NET "mix_ch1_i_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(3)" FAST; -#NET "mix_ch1_i_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(4)" FAST; -#NET "mix_ch1_i_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(5)" FAST; -#NET "mix_ch1_i_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(6)" FAST; -#NET "mix_ch1_i_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(7)" FAST; -#NET "mix_ch1_i_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(8)" FAST; -#NET "mix_ch1_i_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(9)" FAST; -#NET "mix_ch1_i_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(10)" FAST; -#NET "mix_ch1_i_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(11)" FAST; -#NET "mix_ch1_i_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(12)" FAST; -#NET "mix_ch1_i_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(13)" FAST; -#NET "mix_ch1_i_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(14)" FAST; -#NET "mix_ch1_i_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(15)" FAST; -#NET "mix_ch1_i_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(16)" FAST; -#NET "mix_ch1_i_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(17)" FAST; -#NET "mix_ch1_i_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(18)" FAST; -#NET "mix_ch1_i_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(19)" FAST; -#NET "mix_ch1_i_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(20)" FAST; -#NET "mix_ch1_i_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(21)" FAST; -#NET "mix_ch1_i_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(22)" FAST; -#NET "mix_ch1_i_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_i_o(23)" FAST; -#NET "mix_ch1_q_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(0)" FAST; -#NET "mix_ch1_q_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(1)" FAST; -#NET "mix_ch1_q_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(2)" FAST; -#NET "mix_ch1_q_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(3)" FAST; -#NET "mix_ch1_q_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(4)" FAST; -#NET "mix_ch1_q_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(5)" FAST; -#NET "mix_ch1_q_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(6)" FAST; -#NET "mix_ch1_q_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(7)" FAST; -#NET "mix_ch1_q_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(8)" FAST; -#NET "mix_ch1_q_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(9)" FAST; -#NET "mix_ch1_q_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(10)" FAST; -#NET "mix_ch1_q_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(11)" FAST; -#NET "mix_ch1_q_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(12)" FAST; -#NET "mix_ch1_q_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(13)" FAST; -#NET "mix_ch1_q_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(14)" FAST; -#NET "mix_ch1_q_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(15)" FAST; -#NET "mix_ch1_q_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(16)" FAST; -#NET "mix_ch1_q_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(17)" FAST; -#NET "mix_ch1_q_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(18)" FAST; -#NET "mix_ch1_q_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(19)" FAST; -#NET "mix_ch1_q_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(20)" FAST; -#NET "mix_ch1_q_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(21)" FAST; -#NET "mix_ch1_q_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(22)" FAST; -#NET "mix_ch1_q_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch1_q_o(23)" FAST; -#NET "mix_ch2_i_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(0)" FAST; -#NET "mix_ch2_i_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(1)" FAST; -#NET "mix_ch2_i_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(2)" FAST; -#NET "mix_ch2_i_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(3)" FAST; -#NET "mix_ch2_i_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(4)" FAST; -#NET "mix_ch2_i_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(5)" FAST; -#NET "mix_ch2_i_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(6)" FAST; -#NET "mix_ch2_i_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(7)" FAST; -#NET "mix_ch2_i_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(8)" FAST; -#NET "mix_ch2_i_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(9)" FAST; -#NET "mix_ch2_i_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(10)" FAST; -#NET "mix_ch2_i_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(11)" FAST; -#NET "mix_ch2_i_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(12)" FAST; -#NET "mix_ch2_i_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(13)" FAST; -#NET "mix_ch2_i_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(14)" FAST; -#NET "mix_ch2_i_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(15)" FAST; -#NET "mix_ch2_i_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(16)" FAST; -#NET "mix_ch2_i_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(17)" FAST; -#NET "mix_ch2_i_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(18)" FAST; -#NET "mix_ch2_i_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(19)" FAST; -#NET "mix_ch2_i_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(20)" FAST; -#NET "mix_ch2_i_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(21)" FAST; -#NET "mix_ch2_i_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(22)" FAST; -#NET "mix_ch2_i_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_i_o(23)" FAST; -#NET "mix_ch2_q_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(0)" FAST; -#NET "mix_ch2_q_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(1)" FAST; -#NET "mix_ch2_q_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(2)" FAST; -#NET "mix_ch2_q_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(3)" FAST; -#NET "mix_ch2_q_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(4)" FAST; -#NET "mix_ch2_q_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(5)" FAST; -#NET "mix_ch2_q_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(6)" FAST; -#NET "mix_ch2_q_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(7)" FAST; -#NET "mix_ch2_q_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(8)" FAST; -#NET "mix_ch2_q_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(9)" FAST; -#NET "mix_ch2_q_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(10)" FAST; -#NET "mix_ch2_q_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(11)" FAST; -#NET "mix_ch2_q_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(12)" FAST; -#NET "mix_ch2_q_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(13)" FAST; -#NET "mix_ch2_q_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(14)" FAST; -#NET "mix_ch2_q_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(15)" FAST; -#NET "mix_ch2_q_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(16)" FAST; -#NET "mix_ch2_q_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(17)" FAST; -#NET "mix_ch2_q_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(18)" FAST; -#NET "mix_ch2_q_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(19)" FAST; -#NET "mix_ch2_q_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(20)" FAST; -#NET "mix_ch2_q_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(21)" FAST; -#NET "mix_ch2_q_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(22)" FAST; -#NET "mix_ch2_q_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch2_q_o(23)" FAST; -#NET "mix_ch3_i_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(0)" FAST; -#NET "mix_ch3_i_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(1)" FAST; -#NET "mix_ch3_i_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(2)" FAST; -#NET "mix_ch3_i_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(3)" FAST; -#NET "mix_ch3_i_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(4)" FAST; -#NET "mix_ch3_i_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(5)" FAST; -#NET "mix_ch3_i_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(6)" FAST; -#NET "mix_ch3_i_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(7)" FAST; -#NET "mix_ch3_i_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(8)" FAST; -#NET "mix_ch3_i_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(9)" FAST; -#NET "mix_ch3_i_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(10)" FAST; -#NET "mix_ch3_i_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(11)" FAST; -#NET "mix_ch3_i_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(12)" FAST; -#NET "mix_ch3_i_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(13)" FAST; -#NET "mix_ch3_i_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(14)" FAST; -#NET "mix_ch3_i_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(15)" FAST; -#NET "mix_ch3_i_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(16)" FAST; -#NET "mix_ch3_i_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(17)" FAST; -#NET "mix_ch3_i_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(18)" FAST; -#NET "mix_ch3_i_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(19)" FAST; -#NET "mix_ch3_i_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(20)" FAST; -#NET "mix_ch3_i_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(21)" FAST; -#NET "mix_ch3_i_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(22)" FAST; -#NET "mix_ch3_i_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_i_o(23)" FAST; -#NET "mix_ch3_q_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(0)" FAST; -#NET "mix_ch3_q_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(1)" FAST; -#NET "mix_ch3_q_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(2)" FAST; -#NET "mix_ch3_q_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(3)" FAST; -#NET "mix_ch3_q_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(4)" FAST; -#NET "mix_ch3_q_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(5)" FAST; -#NET "mix_ch3_q_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(6)" FAST; -#NET "mix_ch3_q_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(7)" FAST; -#NET "mix_ch3_q_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(8)" FAST; -#NET "mix_ch3_q_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(9)" FAST; -#NET "mix_ch3_q_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(10)" FAST; -#NET "mix_ch3_q_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(11)" FAST; -#NET "mix_ch3_q_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(12)" FAST; -#NET "mix_ch3_q_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(13)" FAST; -#NET "mix_ch3_q_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(14)" FAST; -#NET "mix_ch3_q_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(15)" FAST; -#NET "mix_ch3_q_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(16)" FAST; -#NET "mix_ch3_q_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(17)" FAST; -#NET "mix_ch3_q_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(18)" FAST; -#NET "mix_ch3_q_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(19)" FAST; -#NET "mix_ch3_q_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(20)" FAST; -#NET "mix_ch3_q_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(21)" FAST; -#NET "mix_ch3_q_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(22)" FAST; -#NET "mix_ch3_q_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "mix_ch3_q_o(23)" FAST; -#NET "monit_amp_ch0_o(0)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(0)" FAST; -#NET "monit_amp_ch0_o(1)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(1)" FAST; -#NET "monit_amp_ch0_o(2)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(2)" FAST; -#NET "monit_amp_ch0_o(3)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(3)" FAST; -#NET "monit_amp_ch0_o(4)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(4)" FAST; -#NET "monit_amp_ch0_o(5)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(5)" FAST; -#NET "monit_amp_ch0_o(6)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(6)" FAST; -#NET "monit_amp_ch0_o(7)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(7)" FAST; -#NET "monit_amp_ch0_o(8)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(8)" FAST; -#NET "monit_amp_ch0_o(9)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(9)" FAST; -#NET "monit_amp_ch0_o(10)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(10)" FAST; -#NET "monit_amp_ch0_o(11)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(11)" FAST; -#NET "monit_amp_ch0_o(12)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(12)" FAST; -#NET "monit_amp_ch0_o(13)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(13)" FAST; -#NET "monit_amp_ch0_o(14)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(14)" FAST; -#NET "monit_amp_ch0_o(15)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(15)" FAST; -#NET "monit_amp_ch0_o(16)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(16)" FAST; -#NET "monit_amp_ch0_o(17)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(17)" FAST; -#NET "monit_amp_ch0_o(18)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(18)" FAST; -#NET "monit_amp_ch0_o(19)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(19)" FAST; -#NET "monit_amp_ch0_o(20)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(20)" FAST; -#NET "monit_amp_ch0_o(21)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(21)" FAST; -#NET "monit_amp_ch0_o(22)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(22)" FAST; -#NET "monit_amp_ch0_o(23)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch0_o(23)" FAST; -#NET "monit_amp_ch1_o(0)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(0)" FAST; -#NET "monit_amp_ch1_o(1)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(1)" FAST; -#NET "monit_amp_ch1_o(2)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(2)" FAST; -#NET "monit_amp_ch1_o(3)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(3)" FAST; -#NET "monit_amp_ch1_o(4)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(4)" FAST; -#NET "monit_amp_ch1_o(5)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(5)" FAST; -#NET "monit_amp_ch1_o(6)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(6)" FAST; -#NET "monit_amp_ch1_o(7)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(7)" FAST; -#NET "monit_amp_ch1_o(8)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(8)" FAST; -#NET "monit_amp_ch1_o(9)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(9)" FAST; -#NET "monit_amp_ch1_o(10)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(10)" FAST; -#NET "monit_amp_ch1_o(11)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(11)" FAST; -#NET "monit_amp_ch1_o(12)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(12)" FAST; -#NET "monit_amp_ch1_o(13)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(13)" FAST; -#NET "monit_amp_ch1_o(14)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(14)" FAST; -#NET "monit_amp_ch1_o(15)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(15)" FAST; -#NET "monit_amp_ch1_o(16)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(16)" FAST; -#NET "monit_amp_ch1_o(17)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(17)" FAST; -#NET "monit_amp_ch1_o(18)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(18)" FAST; -#NET "monit_amp_ch1_o(19)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(19)" FAST; -#NET "monit_amp_ch1_o(20)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(20)" FAST; -#NET "monit_amp_ch1_o(21)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(21)" FAST; -#NET "monit_amp_ch1_o(22)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(22)" FAST; -#NET "monit_amp_ch1_o(23)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch1_o(23)" FAST; -#NET "monit_amp_ch2_o(0)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(0)" FAST; -#NET "monit_amp_ch2_o(1)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(1)" FAST; -#NET "monit_amp_ch2_o(2)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(2)" FAST; -#NET "monit_amp_ch2_o(3)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(3)" FAST; -#NET "monit_amp_ch2_o(4)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(4)" FAST; -#NET "monit_amp_ch2_o(5)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(5)" FAST; -#NET "monit_amp_ch2_o(6)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(6)" FAST; -#NET "monit_amp_ch2_o(7)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(7)" FAST; -#NET "monit_amp_ch2_o(8)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(8)" FAST; -#NET "monit_amp_ch2_o(9)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(9)" FAST; -#NET "monit_amp_ch2_o(10)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(10)" FAST; -#NET "monit_amp_ch2_o(11)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(11)" FAST; -#NET "monit_amp_ch2_o(12)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(12)" FAST; -#NET "monit_amp_ch2_o(13)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(13)" FAST; -#NET "monit_amp_ch2_o(14)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(14)" FAST; -#NET "monit_amp_ch2_o(15)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(15)" FAST; -#NET "monit_amp_ch2_o(16)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(16)" FAST; -#NET "monit_amp_ch2_o(17)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(17)" FAST; -#NET "monit_amp_ch2_o(18)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(18)" FAST; -#NET "monit_amp_ch2_o(19)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(19)" FAST; -#NET "monit_amp_ch2_o(20)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(20)" FAST; -#NET "monit_amp_ch2_o(21)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(21)" FAST; -#NET "monit_amp_ch2_o(22)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(22)" FAST; -#NET "monit_amp_ch2_o(23)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch2_o(23)" FAST; -#NET "monit_amp_ch3_o(0)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(0)" FAST; -#NET "monit_amp_ch3_o(1)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(1)" FAST; -#NET "monit_amp_ch3_o(2)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(2)" FAST; -#NET "monit_amp_ch3_o(3)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(3)" FAST; -#NET "monit_amp_ch3_o(4)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(4)" FAST; -#NET "monit_amp_ch3_o(5)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(5)" FAST; -#NET "monit_amp_ch3_o(6)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(6)" FAST; -#NET "monit_amp_ch3_o(7)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(7)" FAST; -#NET "monit_amp_ch3_o(8)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(8)" FAST; -#NET "monit_amp_ch3_o(9)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(9)" FAST; -#NET "monit_amp_ch3_o(10)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(10)" FAST; -#NET "monit_amp_ch3_o(11)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(11)" FAST; -#NET "monit_amp_ch3_o(12)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(12)" FAST; -#NET "monit_amp_ch3_o(13)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(13)" FAST; -#NET "monit_amp_ch3_o(14)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(14)" FAST; -#NET "monit_amp_ch3_o(15)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(15)" FAST; -#NET "monit_amp_ch3_o(16)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(16)" FAST; -#NET "monit_amp_ch3_o(17)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(17)" FAST; -#NET "monit_amp_ch3_o(18)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(18)" FAST; -#NET "monit_amp_ch3_o(19)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(19)" FAST; -#NET "monit_amp_ch3_o(20)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(20)" FAST; -#NET "monit_amp_ch3_o(21)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(21)" FAST; -#NET "monit_amp_ch3_o(22)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(22)" FAST; -#NET "monit_amp_ch3_o(23)" OFFSET = OUT : 2097151.0 : AFTER "clk"; -#NET "monit_amp_ch3_o(23)" FAST; -#NET "monit_cfir_incorrect_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "monit_cfir_incorrect_o" FAST; -#NET "monit_cic_unexpected_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "monit_cic_unexpected_o" FAST; -#NET "monit_pfir_incorrect_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "monit_pfir_incorrect_o" FAST; -#NET "q_fofb_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "q_fofb_valid_o" FAST; -#NET "q_monit_1_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "q_monit_1_valid_o" FAST; -#NET "q_monit_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "q_monit_valid_o" FAST; -#NET "q_tbt_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(0)" FAST; -#NET "q_tbt_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(1)" FAST; -#NET "q_tbt_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(2)" FAST; -#NET "q_tbt_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(3)" FAST; -#NET "q_tbt_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(4)" FAST; -#NET "q_tbt_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(5)" FAST; -#NET "q_tbt_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(6)" FAST; -#NET "q_tbt_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(7)" FAST; -#NET "q_tbt_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(8)" FAST; -#NET "q_tbt_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(9)" FAST; -#NET "q_tbt_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(10)" FAST; -#NET "q_tbt_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(11)" FAST; -#NET "q_tbt_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(12)" FAST; -#NET "q_tbt_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(13)" FAST; -#NET "q_tbt_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(14)" FAST; -#NET "q_tbt_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(15)" FAST; -#NET "q_tbt_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(16)" FAST; -#NET "q_tbt_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(17)" FAST; -#NET "q_tbt_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(18)" FAST; -#NET "q_tbt_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(19)" FAST; -#NET "q_tbt_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(20)" FAST; -#NET "q_tbt_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(21)" FAST; -#NET "q_tbt_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(22)" FAST; -#NET "q_tbt_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(23)" FAST; -#NET "q_tbt_o(24)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(24)" FAST; -#NET "q_tbt_o(25)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "q_tbt_o(25)" FAST; -#NET "q_tbt_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "q_tbt_valid_o" FAST; -#NET "sum_fofb_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "sum_fofb_valid_o" FAST; -#NET "sum_monit_1_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "sum_monit_1_valid_o" FAST; -#NET "sum_monit_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "sum_monit_valid_o" FAST; -#NET "sum_tbt_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(0)" FAST; -#NET "sum_tbt_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(1)" FAST; -#NET "sum_tbt_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(2)" FAST; -#NET "sum_tbt_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(3)" FAST; -#NET "sum_tbt_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(4)" FAST; -#NET "sum_tbt_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(5)" FAST; -#NET "sum_tbt_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(6)" FAST; -#NET "sum_tbt_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(7)" FAST; -#NET "sum_tbt_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(8)" FAST; -#NET "sum_tbt_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(9)" FAST; -#NET "sum_tbt_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(10)" FAST; -#NET "sum_tbt_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(11)" FAST; -#NET "sum_tbt_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(12)" FAST; -#NET "sum_tbt_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(13)" FAST; -#NET "sum_tbt_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(14)" FAST; -#NET "sum_tbt_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(15)" FAST; -#NET "sum_tbt_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(16)" FAST; -#NET "sum_tbt_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(17)" FAST; -#NET "sum_tbt_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(18)" FAST; -#NET "sum_tbt_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(19)" FAST; -#NET "sum_tbt_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(20)" FAST; -#NET "sum_tbt_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(21)" FAST; -#NET "sum_tbt_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(22)" FAST; -#NET "sum_tbt_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(23)" FAST; -#NET "sum_tbt_o(24)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(24)" FAST; -#NET "sum_tbt_o(25)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "sum_tbt_o(25)" FAST; -#NET "sum_tbt_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "sum_tbt_valid_o" FAST; -#NET "tbt_amp_ch0_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(0)" FAST; -#NET "tbt_amp_ch0_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(1)" FAST; -#NET "tbt_amp_ch0_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(2)" FAST; -#NET "tbt_amp_ch0_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(3)" FAST; -#NET "tbt_amp_ch0_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(4)" FAST; -#NET "tbt_amp_ch0_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(5)" FAST; -#NET "tbt_amp_ch0_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(6)" FAST; -#NET "tbt_amp_ch0_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(7)" FAST; -#NET "tbt_amp_ch0_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(8)" FAST; -#NET "tbt_amp_ch0_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(9)" FAST; -#NET "tbt_amp_ch0_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(10)" FAST; -#NET "tbt_amp_ch0_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(11)" FAST; -#NET "tbt_amp_ch0_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(12)" FAST; -#NET "tbt_amp_ch0_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(13)" FAST; -#NET "tbt_amp_ch0_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(14)" FAST; -#NET "tbt_amp_ch0_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(15)" FAST; -#NET "tbt_amp_ch0_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(16)" FAST; -#NET "tbt_amp_ch0_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(17)" FAST; -#NET "tbt_amp_ch0_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(18)" FAST; -#NET "tbt_amp_ch0_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(19)" FAST; -#NET "tbt_amp_ch0_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(20)" FAST; -#NET "tbt_amp_ch0_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(21)" FAST; -#NET "tbt_amp_ch0_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(22)" FAST; -#NET "tbt_amp_ch0_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch0_o(23)" FAST; -#NET "tbt_amp_ch1_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(0)" FAST; -#NET "tbt_amp_ch1_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(1)" FAST; -#NET "tbt_amp_ch1_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(2)" FAST; -#NET "tbt_amp_ch1_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(3)" FAST; -#NET "tbt_amp_ch1_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(4)" FAST; -#NET "tbt_amp_ch1_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(5)" FAST; -#NET "tbt_amp_ch1_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(6)" FAST; -#NET "tbt_amp_ch1_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(7)" FAST; -#NET "tbt_amp_ch1_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(8)" FAST; -#NET "tbt_amp_ch1_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(9)" FAST; -#NET "tbt_amp_ch1_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(10)" FAST; -#NET "tbt_amp_ch1_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(11)" FAST; -#NET "tbt_amp_ch1_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(12)" FAST; -#NET "tbt_amp_ch1_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(13)" FAST; -#NET "tbt_amp_ch1_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(14)" FAST; -#NET "tbt_amp_ch1_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(15)" FAST; -#NET "tbt_amp_ch1_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(16)" FAST; -#NET "tbt_amp_ch1_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(17)" FAST; -#NET "tbt_amp_ch1_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(18)" FAST; -#NET "tbt_amp_ch1_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(19)" FAST; -#NET "tbt_amp_ch1_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(20)" FAST; -#NET "tbt_amp_ch1_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(21)" FAST; -#NET "tbt_amp_ch1_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(22)" FAST; -#NET "tbt_amp_ch1_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch1_o(23)" FAST; -#NET "tbt_amp_ch2_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(0)" FAST; -#NET "tbt_amp_ch2_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(1)" FAST; -#NET "tbt_amp_ch2_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(2)" FAST; -#NET "tbt_amp_ch2_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(3)" FAST; -#NET "tbt_amp_ch2_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(4)" FAST; -#NET "tbt_amp_ch2_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(5)" FAST; -#NET "tbt_amp_ch2_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(6)" FAST; -#NET "tbt_amp_ch2_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(7)" FAST; -#NET "tbt_amp_ch2_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(8)" FAST; -#NET "tbt_amp_ch2_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(9)" FAST; -#NET "tbt_amp_ch2_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(10)" FAST; -#NET "tbt_amp_ch2_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(11)" FAST; -#NET "tbt_amp_ch2_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(12)" FAST; -#NET "tbt_amp_ch2_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(13)" FAST; -#NET "tbt_amp_ch2_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(14)" FAST; -#NET "tbt_amp_ch2_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(15)" FAST; -#NET "tbt_amp_ch2_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(16)" FAST; -#NET "tbt_amp_ch2_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(17)" FAST; -#NET "tbt_amp_ch2_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(18)" FAST; -#NET "tbt_amp_ch2_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(19)" FAST; -#NET "tbt_amp_ch2_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(20)" FAST; -#NET "tbt_amp_ch2_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(21)" FAST; -#NET "tbt_amp_ch2_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(22)" FAST; -#NET "tbt_amp_ch2_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch2_o(23)" FAST; -#NET "tbt_amp_ch3_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(0)" FAST; -#NET "tbt_amp_ch3_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(1)" FAST; -#NET "tbt_amp_ch3_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(2)" FAST; -#NET "tbt_amp_ch3_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(3)" FAST; -#NET "tbt_amp_ch3_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(4)" FAST; -#NET "tbt_amp_ch3_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(5)" FAST; -#NET "tbt_amp_ch3_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(6)" FAST; -#NET "tbt_amp_ch3_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(7)" FAST; -#NET "tbt_amp_ch3_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(8)" FAST; -#NET "tbt_amp_ch3_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(9)" FAST; -#NET "tbt_amp_ch3_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(10)" FAST; -#NET "tbt_amp_ch3_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(11)" FAST; -#NET "tbt_amp_ch3_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(12)" FAST; -#NET "tbt_amp_ch3_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(13)" FAST; -#NET "tbt_amp_ch3_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(14)" FAST; -#NET "tbt_amp_ch3_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(15)" FAST; -#NET "tbt_amp_ch3_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(16)" FAST; -#NET "tbt_amp_ch3_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(17)" FAST; -#NET "tbt_amp_ch3_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(18)" FAST; -#NET "tbt_amp_ch3_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(19)" FAST; -#NET "tbt_amp_ch3_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(20)" FAST; -#NET "tbt_amp_ch3_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(21)" FAST; -#NET "tbt_amp_ch3_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(22)" FAST; -#NET "tbt_amp_ch3_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_amp_ch3_o(23)" FAST; -#NET "tbt_decim_ch01_incorrect_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "tbt_decim_ch01_incorrect_o" FAST; -#NET "tbt_decim_ch0_i_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(0)" FAST; -#NET "tbt_decim_ch0_i_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(1)" FAST; -#NET "tbt_decim_ch0_i_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(2)" FAST; -#NET "tbt_decim_ch0_i_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(3)" FAST; -#NET "tbt_decim_ch0_i_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(4)" FAST; -#NET "tbt_decim_ch0_i_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(5)" FAST; -#NET "tbt_decim_ch0_i_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(6)" FAST; -#NET "tbt_decim_ch0_i_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(7)" FAST; -#NET "tbt_decim_ch0_i_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(8)" FAST; -#NET "tbt_decim_ch0_i_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(9)" FAST; -#NET "tbt_decim_ch0_i_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(10)" FAST; -#NET "tbt_decim_ch0_i_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(11)" FAST; -#NET "tbt_decim_ch0_i_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(12)" FAST; -#NET "tbt_decim_ch0_i_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(13)" FAST; -#NET "tbt_decim_ch0_i_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(14)" FAST; -#NET "tbt_decim_ch0_i_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(15)" FAST; -#NET "tbt_decim_ch0_i_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(16)" FAST; -#NET "tbt_decim_ch0_i_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(17)" FAST; -#NET "tbt_decim_ch0_i_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(18)" FAST; -#NET "tbt_decim_ch0_i_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(19)" FAST; -#NET "tbt_decim_ch0_i_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(20)" FAST; -#NET "tbt_decim_ch0_i_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(21)" FAST; -#NET "tbt_decim_ch0_i_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(22)" FAST; -#NET "tbt_decim_ch0_i_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_i_o(23)" FAST; -#NET "tbt_decim_ch0_q_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(0)" FAST; -#NET "tbt_decim_ch0_q_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(1)" FAST; -#NET "tbt_decim_ch0_q_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(2)" FAST; -#NET "tbt_decim_ch0_q_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(3)" FAST; -#NET "tbt_decim_ch0_q_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(4)" FAST; -#NET "tbt_decim_ch0_q_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(5)" FAST; -#NET "tbt_decim_ch0_q_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(6)" FAST; -#NET "tbt_decim_ch0_q_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(7)" FAST; -#NET "tbt_decim_ch0_q_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(8)" FAST; -#NET "tbt_decim_ch0_q_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(9)" FAST; -#NET "tbt_decim_ch0_q_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(10)" FAST; -#NET "tbt_decim_ch0_q_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(11)" FAST; -#NET "tbt_decim_ch0_q_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(12)" FAST; -#NET "tbt_decim_ch0_q_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(13)" FAST; -#NET "tbt_decim_ch0_q_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(14)" FAST; -#NET "tbt_decim_ch0_q_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(15)" FAST; -#NET "tbt_decim_ch0_q_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(16)" FAST; -#NET "tbt_decim_ch0_q_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(17)" FAST; -#NET "tbt_decim_ch0_q_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(18)" FAST; -#NET "tbt_decim_ch0_q_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(19)" FAST; -#NET "tbt_decim_ch0_q_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(20)" FAST; -#NET "tbt_decim_ch0_q_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(21)" FAST; -#NET "tbt_decim_ch0_q_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(22)" FAST; -#NET "tbt_decim_ch0_q_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch0_q_o(23)" FAST; -#NET "tbt_decim_ch1_i_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(0)" FAST; -#NET "tbt_decim_ch1_i_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(1)" FAST; -#NET "tbt_decim_ch1_i_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(2)" FAST; -#NET "tbt_decim_ch1_i_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(3)" FAST; -#NET "tbt_decim_ch1_i_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(4)" FAST; -#NET "tbt_decim_ch1_i_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(5)" FAST; -#NET "tbt_decim_ch1_i_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(6)" FAST; -#NET "tbt_decim_ch1_i_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(7)" FAST; -#NET "tbt_decim_ch1_i_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(8)" FAST; -#NET "tbt_decim_ch1_i_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(9)" FAST; -#NET "tbt_decim_ch1_i_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(10)" FAST; -#NET "tbt_decim_ch1_i_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(11)" FAST; -#NET "tbt_decim_ch1_i_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(12)" FAST; -#NET "tbt_decim_ch1_i_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(13)" FAST; -#NET "tbt_decim_ch1_i_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(14)" FAST; -#NET "tbt_decim_ch1_i_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(15)" FAST; -#NET "tbt_decim_ch1_i_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(16)" FAST; -#NET "tbt_decim_ch1_i_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(17)" FAST; -#NET "tbt_decim_ch1_i_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(18)" FAST; -#NET "tbt_decim_ch1_i_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(19)" FAST; -#NET "tbt_decim_ch1_i_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(20)" FAST; -#NET "tbt_decim_ch1_i_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(21)" FAST; -#NET "tbt_decim_ch1_i_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(22)" FAST; -#NET "tbt_decim_ch1_i_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_i_o(23)" FAST; -#NET "tbt_decim_ch1_q_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(0)" FAST; -#NET "tbt_decim_ch1_q_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(1)" FAST; -#NET "tbt_decim_ch1_q_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(2)" FAST; -#NET "tbt_decim_ch1_q_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(3)" FAST; -#NET "tbt_decim_ch1_q_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(4)" FAST; -#NET "tbt_decim_ch1_q_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(5)" FAST; -#NET "tbt_decim_ch1_q_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(6)" FAST; -#NET "tbt_decim_ch1_q_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(7)" FAST; -#NET "tbt_decim_ch1_q_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(8)" FAST; -#NET "tbt_decim_ch1_q_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(9)" FAST; -#NET "tbt_decim_ch1_q_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(10)" FAST; -#NET "tbt_decim_ch1_q_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(11)" FAST; -#NET "tbt_decim_ch1_q_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(12)" FAST; -#NET "tbt_decim_ch1_q_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(13)" FAST; -#NET "tbt_decim_ch1_q_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(14)" FAST; -#NET "tbt_decim_ch1_q_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(15)" FAST; -#NET "tbt_decim_ch1_q_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(16)" FAST; -#NET "tbt_decim_ch1_q_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(17)" FAST; -#NET "tbt_decim_ch1_q_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(18)" FAST; -#NET "tbt_decim_ch1_q_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(19)" FAST; -#NET "tbt_decim_ch1_q_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(20)" FAST; -#NET "tbt_decim_ch1_q_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(21)" FAST; -#NET "tbt_decim_ch1_q_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(22)" FAST; -#NET "tbt_decim_ch1_q_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch1_q_o(23)" FAST; -#NET "tbt_decim_ch23_incorrect_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "tbt_decim_ch23_incorrect_o" FAST; -#NET "tbt_decim_ch2_i_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(0)" FAST; -#NET "tbt_decim_ch2_i_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(1)" FAST; -#NET "tbt_decim_ch2_i_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(2)" FAST; -#NET "tbt_decim_ch2_i_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(3)" FAST; -#NET "tbt_decim_ch2_i_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(4)" FAST; -#NET "tbt_decim_ch2_i_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(5)" FAST; -#NET "tbt_decim_ch2_i_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(6)" FAST; -#NET "tbt_decim_ch2_i_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(7)" FAST; -#NET "tbt_decim_ch2_i_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(8)" FAST; -#NET "tbt_decim_ch2_i_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(9)" FAST; -#NET "tbt_decim_ch2_i_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(10)" FAST; -#NET "tbt_decim_ch2_i_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(11)" FAST; -#NET "tbt_decim_ch2_i_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(12)" FAST; -#NET "tbt_decim_ch2_i_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(13)" FAST; -#NET "tbt_decim_ch2_i_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(14)" FAST; -#NET "tbt_decim_ch2_i_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(15)" FAST; -#NET "tbt_decim_ch2_i_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(16)" FAST; -#NET "tbt_decim_ch2_i_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(17)" FAST; -#NET "tbt_decim_ch2_i_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(18)" FAST; -#NET "tbt_decim_ch2_i_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(19)" FAST; -#NET "tbt_decim_ch2_i_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(20)" FAST; -#NET "tbt_decim_ch2_i_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(21)" FAST; -#NET "tbt_decim_ch2_i_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(22)" FAST; -#NET "tbt_decim_ch2_i_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_i_o(23)" FAST; -#NET "tbt_decim_ch2_q_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(0)" FAST; -#NET "tbt_decim_ch2_q_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(1)" FAST; -#NET "tbt_decim_ch2_q_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(2)" FAST; -#NET "tbt_decim_ch2_q_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(3)" FAST; -#NET "tbt_decim_ch2_q_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(4)" FAST; -#NET "tbt_decim_ch2_q_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(5)" FAST; -#NET "tbt_decim_ch2_q_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(6)" FAST; -#NET "tbt_decim_ch2_q_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(7)" FAST; -#NET "tbt_decim_ch2_q_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(8)" FAST; -#NET "tbt_decim_ch2_q_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(9)" FAST; -#NET "tbt_decim_ch2_q_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(10)" FAST; -#NET "tbt_decim_ch2_q_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(11)" FAST; -#NET "tbt_decim_ch2_q_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(12)" FAST; -#NET "tbt_decim_ch2_q_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(13)" FAST; -#NET "tbt_decim_ch2_q_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(14)" FAST; -#NET "tbt_decim_ch2_q_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(15)" FAST; -#NET "tbt_decim_ch2_q_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(16)" FAST; -#NET "tbt_decim_ch2_q_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(17)" FAST; -#NET "tbt_decim_ch2_q_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(18)" FAST; -#NET "tbt_decim_ch2_q_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(19)" FAST; -#NET "tbt_decim_ch2_q_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(20)" FAST; -#NET "tbt_decim_ch2_q_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(21)" FAST; -#NET "tbt_decim_ch2_q_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(22)" FAST; -#NET "tbt_decim_ch2_q_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch2_q_o(23)" FAST; -#NET "tbt_decim_ch3_i_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(0)" FAST; -#NET "tbt_decim_ch3_i_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(1)" FAST; -#NET "tbt_decim_ch3_i_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(2)" FAST; -#NET "tbt_decim_ch3_i_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(3)" FAST; -#NET "tbt_decim_ch3_i_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(4)" FAST; -#NET "tbt_decim_ch3_i_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(5)" FAST; -#NET "tbt_decim_ch3_i_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(6)" FAST; -#NET "tbt_decim_ch3_i_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(7)" FAST; -#NET "tbt_decim_ch3_i_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(8)" FAST; -#NET "tbt_decim_ch3_i_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(9)" FAST; -#NET "tbt_decim_ch3_i_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(10)" FAST; -#NET "tbt_decim_ch3_i_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(11)" FAST; -#NET "tbt_decim_ch3_i_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(12)" FAST; -#NET "tbt_decim_ch3_i_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(13)" FAST; -#NET "tbt_decim_ch3_i_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(14)" FAST; -#NET "tbt_decim_ch3_i_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(15)" FAST; -#NET "tbt_decim_ch3_i_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(16)" FAST; -#NET "tbt_decim_ch3_i_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(17)" FAST; -#NET "tbt_decim_ch3_i_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(18)" FAST; -#NET "tbt_decim_ch3_i_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(19)" FAST; -#NET "tbt_decim_ch3_i_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(20)" FAST; -#NET "tbt_decim_ch3_i_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(21)" FAST; -#NET "tbt_decim_ch3_i_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(22)" FAST; -#NET "tbt_decim_ch3_i_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_i_o(23)" FAST; -#NET "tbt_decim_ch3_q_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(0)" FAST; -#NET "tbt_decim_ch3_q_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(1)" FAST; -#NET "tbt_decim_ch3_q_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(2)" FAST; -#NET "tbt_decim_ch3_q_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(3)" FAST; -#NET "tbt_decim_ch3_q_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(4)" FAST; -#NET "tbt_decim_ch3_q_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(5)" FAST; -#NET "tbt_decim_ch3_q_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(6)" FAST; -#NET "tbt_decim_ch3_q_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(7)" FAST; -#NET "tbt_decim_ch3_q_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(8)" FAST; -#NET "tbt_decim_ch3_q_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(9)" FAST; -#NET "tbt_decim_ch3_q_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(10)" FAST; -#NET "tbt_decim_ch3_q_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(11)" FAST; -#NET "tbt_decim_ch3_q_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(12)" FAST; -#NET "tbt_decim_ch3_q_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(13)" FAST; -#NET "tbt_decim_ch3_q_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(14)" FAST; -#NET "tbt_decim_ch3_q_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(15)" FAST; -#NET "tbt_decim_ch3_q_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(16)" FAST; -#NET "tbt_decim_ch3_q_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(17)" FAST; -#NET "tbt_decim_ch3_q_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(18)" FAST; -#NET "tbt_decim_ch3_q_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(19)" FAST; -#NET "tbt_decim_ch3_q_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(20)" FAST; -#NET "tbt_decim_ch3_q_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(21)" FAST; -#NET "tbt_decim_ch3_q_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(22)" FAST; -#NET "tbt_decim_ch3_q_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_decim_ch3_q_o(23)" FAST; -#NET "tbt_pha_ch0_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(0)" FAST; -#NET "tbt_pha_ch0_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(1)" FAST; -#NET "tbt_pha_ch0_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(2)" FAST; -#NET "tbt_pha_ch0_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(3)" FAST; -#NET "tbt_pha_ch0_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(4)" FAST; -#NET "tbt_pha_ch0_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(5)" FAST; -#NET "tbt_pha_ch0_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(6)" FAST; -#NET "tbt_pha_ch0_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(7)" FAST; -#NET "tbt_pha_ch0_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(8)" FAST; -#NET "tbt_pha_ch0_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(9)" FAST; -#NET "tbt_pha_ch0_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(10)" FAST; -#NET "tbt_pha_ch0_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(11)" FAST; -#NET "tbt_pha_ch0_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(12)" FAST; -#NET "tbt_pha_ch0_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(13)" FAST; -#NET "tbt_pha_ch0_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(14)" FAST; -#NET "tbt_pha_ch0_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(15)" FAST; -#NET "tbt_pha_ch0_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(16)" FAST; -#NET "tbt_pha_ch0_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(17)" FAST; -#NET "tbt_pha_ch0_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(18)" FAST; -#NET "tbt_pha_ch0_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(19)" FAST; -#NET "tbt_pha_ch0_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(20)" FAST; -#NET "tbt_pha_ch0_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(21)" FAST; -#NET "tbt_pha_ch0_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(22)" FAST; -#NET "tbt_pha_ch0_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch0_o(23)" FAST; -#NET "tbt_pha_ch1_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(0)" FAST; -#NET "tbt_pha_ch1_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(1)" FAST; -#NET "tbt_pha_ch1_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(2)" FAST; -#NET "tbt_pha_ch1_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(3)" FAST; -#NET "tbt_pha_ch1_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(4)" FAST; -#NET "tbt_pha_ch1_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(5)" FAST; -#NET "tbt_pha_ch1_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(6)" FAST; -#NET "tbt_pha_ch1_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(7)" FAST; -#NET "tbt_pha_ch1_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(8)" FAST; -#NET "tbt_pha_ch1_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(9)" FAST; -#NET "tbt_pha_ch1_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(10)" FAST; -#NET "tbt_pha_ch1_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(11)" FAST; -#NET "tbt_pha_ch1_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(12)" FAST; -#NET "tbt_pha_ch1_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(13)" FAST; -#NET "tbt_pha_ch1_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(14)" FAST; -#NET "tbt_pha_ch1_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(15)" FAST; -#NET "tbt_pha_ch1_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(16)" FAST; -#NET "tbt_pha_ch1_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(17)" FAST; -#NET "tbt_pha_ch1_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(18)" FAST; -#NET "tbt_pha_ch1_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(19)" FAST; -#NET "tbt_pha_ch1_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(20)" FAST; -#NET "tbt_pha_ch1_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(21)" FAST; -#NET "tbt_pha_ch1_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(22)" FAST; -#NET "tbt_pha_ch1_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch1_o(23)" FAST; -#NET "tbt_pha_ch2_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(0)" FAST; -#NET "tbt_pha_ch2_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(1)" FAST; -#NET "tbt_pha_ch2_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(2)" FAST; -#NET "tbt_pha_ch2_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(3)" FAST; -#NET "tbt_pha_ch2_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(4)" FAST; -#NET "tbt_pha_ch2_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(5)" FAST; -#NET "tbt_pha_ch2_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(6)" FAST; -#NET "tbt_pha_ch2_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(7)" FAST; -#NET "tbt_pha_ch2_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(8)" FAST; -#NET "tbt_pha_ch2_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(9)" FAST; -#NET "tbt_pha_ch2_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(10)" FAST; -#NET "tbt_pha_ch2_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(11)" FAST; -#NET "tbt_pha_ch2_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(12)" FAST; -#NET "tbt_pha_ch2_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(13)" FAST; -#NET "tbt_pha_ch2_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(14)" FAST; -#NET "tbt_pha_ch2_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(15)" FAST; -#NET "tbt_pha_ch2_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(16)" FAST; -#NET "tbt_pha_ch2_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(17)" FAST; -#NET "tbt_pha_ch2_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(18)" FAST; -#NET "tbt_pha_ch2_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(19)" FAST; -#NET "tbt_pha_ch2_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(20)" FAST; -#NET "tbt_pha_ch2_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(21)" FAST; -#NET "tbt_pha_ch2_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(22)" FAST; -#NET "tbt_pha_ch2_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch2_o(23)" FAST; -#NET "tbt_pha_ch3_o(0)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(0)" FAST; -#NET "tbt_pha_ch3_o(1)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(1)" FAST; -#NET "tbt_pha_ch3_o(2)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(2)" FAST; -#NET "tbt_pha_ch3_o(3)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(3)" FAST; -#NET "tbt_pha_ch3_o(4)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(4)" FAST; -#NET "tbt_pha_ch3_o(5)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(5)" FAST; -#NET "tbt_pha_ch3_o(6)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(6)" FAST; -#NET "tbt_pha_ch3_o(7)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(7)" FAST; -#NET "tbt_pha_ch3_o(8)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(8)" FAST; -#NET "tbt_pha_ch3_o(9)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(9)" FAST; -#NET "tbt_pha_ch3_o(10)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(10)" FAST; -#NET "tbt_pha_ch3_o(11)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(11)" FAST; -#NET "tbt_pha_ch3_o(12)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(12)" FAST; -#NET "tbt_pha_ch3_o(13)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(13)" FAST; -#NET "tbt_pha_ch3_o(14)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(14)" FAST; -#NET "tbt_pha_ch3_o(15)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(15)" FAST; -#NET "tbt_pha_ch3_o(16)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(16)" FAST; -#NET "tbt_pha_ch3_o(17)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(17)" FAST; -#NET "tbt_pha_ch3_o(18)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(18)" FAST; -#NET "tbt_pha_ch3_o(19)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(19)" FAST; -#NET "tbt_pha_ch3_o(20)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(20)" FAST; -#NET "tbt_pha_ch3_o(21)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(21)" FAST; -#NET "tbt_pha_ch3_o(22)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(22)" FAST; -#NET "tbt_pha_ch3_o(23)" OFFSET = OUT : 310.8812643625045 : AFTER "clk"; -#NET "tbt_pha_ch3_o(23)" FAST; -#NET "x_fofb_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "x_fofb_valid_o" FAST; -#NET "x_monit_1_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "x_monit_1_valid_o" FAST; -#NET "x_monit_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "x_monit_valid_o" FAST; -#NET "x_tbt_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(0)" FAST; -#NET "x_tbt_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(1)" FAST; -#NET "x_tbt_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(2)" FAST; -#NET "x_tbt_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(3)" FAST; -#NET "x_tbt_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(4)" FAST; -#NET "x_tbt_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(5)" FAST; -#NET "x_tbt_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(6)" FAST; -#NET "x_tbt_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(7)" FAST; -#NET "x_tbt_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(8)" FAST; -#NET "x_tbt_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(9)" FAST; -#NET "x_tbt_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(10)" FAST; -#NET "x_tbt_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(11)" FAST; -#NET "x_tbt_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(12)" FAST; -#NET "x_tbt_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(13)" FAST; -#NET "x_tbt_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(14)" FAST; -#NET "x_tbt_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(15)" FAST; -#NET "x_tbt_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(16)" FAST; -#NET "x_tbt_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(17)" FAST; -#NET "x_tbt_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(18)" FAST; -#NET "x_tbt_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(19)" FAST; -#NET "x_tbt_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(20)" FAST; -#NET "x_tbt_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(21)" FAST; -#NET "x_tbt_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(22)" FAST; -#NET "x_tbt_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(23)" FAST; -#NET "x_tbt_o(24)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(24)" FAST; -#NET "x_tbt_o(25)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "x_tbt_o(25)" FAST; -#NET "x_tbt_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "x_tbt_valid_o" FAST; -#NET "y_fofb_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "y_fofb_valid_o" FAST; -#NET "y_monit_1_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "y_monit_1_valid_o" FAST; -#NET "y_monit_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "y_monit_valid_o" FAST; -#NET "y_tbt_o(0)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(0)" FAST; -#NET "y_tbt_o(1)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(1)" FAST; -#NET "y_tbt_o(2)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(2)" FAST; -#NET "y_tbt_o(3)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(3)" FAST; -#NET "y_tbt_o(4)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(4)" FAST; -#NET "y_tbt_o(5)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(5)" FAST; -#NET "y_tbt_o(6)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(6)" FAST; -#NET "y_tbt_o(7)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(7)" FAST; -#NET "y_tbt_o(8)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(8)" FAST; -#NET "y_tbt_o(9)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(9)" FAST; -#NET "y_tbt_o(10)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(10)" FAST; -#NET "y_tbt_o(11)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(11)" FAST; -#NET "y_tbt_o(12)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(12)" FAST; -#NET "y_tbt_o(13)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(13)" FAST; -#NET "y_tbt_o(14)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(14)" FAST; -#NET "y_tbt_o(15)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(15)" FAST; -#NET "y_tbt_o(16)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(16)" FAST; -#NET "y_tbt_o(17)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(17)" FAST; -#NET "y_tbt_o(18)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(18)" FAST; -#NET "y_tbt_o(19)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(19)" FAST; -#NET "y_tbt_o(20)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(20)" FAST; -#NET "y_tbt_o(21)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(21)" FAST; -#NET "y_tbt_o(22)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(22)" FAST; -#NET "y_tbt_o(23)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(23)" FAST; -#NET "y_tbt_o(24)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(24)" FAST; -#NET "y_tbt_o(25)" OFFSET = OUT : 8.8823218389287 : AFTER "clk"; -#NET "y_tbt_o(25)" FAST; -#NET "y_tbt_valid_o" OFFSET = OUT : 4.44116091946435 : AFTER "clk"; -#NET "y_tbt_valid_o" FAST; -# -## Offset inout constraints - diff --git a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_dsp_fmc516/sys_pll.vhd deleted file mode 100644 index 036e6b5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_dsp_fmc516/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/ml_605/dbe_bpm_ebone/Manifest.py b/hdl/top/ml_605/dbe_bpm_ebone/Manifest.py deleted file mode 100644 index 46cdba90..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/Manifest.py +++ /dev/null @@ -1,3 +0,0 @@ -files = [ "dbe_bpm_ebone.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_bpm_ebone.ucf" ]; - -modules = { "local" : ["../../.." ] }; diff --git a/hdl/top/ml_605/dbe_bpm_ebone/chipscope.cpj b/hdl/top/ml_605/dbe_bpm_ebone/chipscope.cpj deleted file mode 100644 index 9123ed67..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/chipscope.cpj +++ /dev/null @@ -1,6536 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Fri Mar 01 09:45:59 BRT 2013 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109364250093 -mdiAreaHeight=0.7049723756906078 -mdiAreaHeightLast=0.6773480662983425 -mdiCount=6 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice2=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiType0=1 -mdiType1=0 -mdiType2=5 -mdiType3=0 -mdiType4=1 -mdiType5=2 -mdiUnit0=0 -mdiUnit1=0 -mdiUnit2=0 -mdiUnit3=3 -mdiUnit4=3 -mdiUnit5=3 -navigatorHeight=0.1734806629834254 -navigatorHeightLast=0.1734806629834254 -navigatorWidth=0.13545568039950062 -navigatorWidthLast=0.13545568039950062 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.36220473 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=0.7126185 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5480315 -unit.1.0.1.WIDTH1=0.7126185 -unit.1.0.1.X1=0.0043763677 -unit.1.0.1.Y1=0.4488189 -unit.1.0.5.HEIGHT5=0.9496063 -unit.1.0.5.WIDTH5=0.92997813 -unit.1.0.5.X5=0.07002188 -unit.1.0.5.Y5=0.0 -unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsB0=00000000000000000000000000000000 -unit.1.0.MFBitsB1=00000000000000000000000000000000 -unit.1.0.MFBitsB2=00000000000000000000000000000000 -unit.1.0.MFBitsB3=00000000000000000000000000000000 -unit.1.0.MFCompareA0=0 -unit.1.0.MFCompareA1=0 -unit.1.0.MFCompareA2=0 -unit.1.0.MFCompareA3=0 -unit.1.0.MFCompareB0=999 -unit.1.0.MFCompareB1=999 -unit.1.0.MFCompareB2=999 -unit.1.0.MFCompareB3=999 -unit.1.0.MFCount=4 -unit.1.0.MFDisplay0=0 -unit.1.0.MFDisplay1=0 -unit.1.0.MFDisplay2=0 -unit.1.0.MFDisplay3=0 -unit.1.0.MFEventType0=3 -unit.1.0.MFEventType1=3 -unit.1.0.MFEventType2=3 -unit.1.0.MFEventType3=3 -unit.1.0.RunMode=REPETITIVE RUN -unit.1.0.SQCondition=All Data -unit.1.0.SQContiguous0=0 -unit.1.0.SequencerOn=0 -unit.1.0.TCActive=0 -unit.1.0.TCAdvanced0=0 -unit.1.0.TCCondition0_0=M0 -unit.1.0.TCCondition0_1= -unit.1.0.TCConditionType0=0 -unit.1.0.TCCount=1 -unit.1.0.TCEventCount0=1 -unit.1.0.TCEventType0=3 -unit.1.0.TCName0=TriggerCondition0 -unit.1.0.TCOutputEnable0=0 -unit.1.0.TCOutputHigh0=1 -unit.1.0.TCOutputMode0=0 -unit.1.0.browser_tree_state=1 -unit.1.0.browser_tree_state=0 -unit.1.0.coretype=ILA -unit.1.0.eventCount0=1 -unit.1.0.eventCount1=1 -unit.1.0.eventCount2=1 -unit.1.0.eventCount3=1 -unit.1.0.plotBusColor0=-16777092 -unit.1.0.plotBusColor1=-16777092 -unit.1.0.plotBusColor2=-16777092 -unit.1.0.plotBusColor3=-16777092 -unit.1.0.plotBusCount=4 -unit.1.0.plotBusName0=adc_ch0 -unit.1.0.plotBusName1=adc_ch1 -unit.1.0.plotBusName2=adc_ch2 -unit.1.0.plotBusName3=adc_ch3 -unit.1.0.plotBusX=adc_ch0 -unit.1.0.plotBusY=adc_ch1 -unit.1.0.plotDataTimeMode=1 -unit.1.0.plotDisplayMode=line -unit.1.0.plotMaxX=0.0 -unit.1.0.plotMaxY=0.0 -unit.1.0.plotMinX=0.0 -unit.1.0.plotMinY=0.0 -unit.1.0.plotSelectedBus=8 -unit.1.0.port.-1.b.0.alias=adc_ch0 -unit.1.0.port.-1.b.0.channellist=32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 -unit.1.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.0.name=DataPort -unit.1.0.port.-1.b.0.orderindex=-1 -unit.1.0.port.-1.b.0.radix=Signed -unit.1.0.port.-1.b.0.signedOffset=0.0 -unit.1.0.port.-1.b.0.signedPrecision=0 -unit.1.0.port.-1.b.0.signedScaleFactor=1.0 -unit.1.0.port.-1.b.0.tokencount=0 -unit.1.0.port.-1.b.0.unsignedOffset=0.0 -unit.1.0.port.-1.b.0.unsignedPrecision=0 -unit.1.0.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.0.visible=1 -unit.1.0.port.-1.b.1.alias=adc_ch1 -unit.1.0.port.-1.b.1.channellist=48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.1.name=DataPort -unit.1.0.port.-1.b.1.orderindex=-1 -unit.1.0.port.-1.b.1.radix=Signed -unit.1.0.port.-1.b.1.signedOffset=0.0 -unit.1.0.port.-1.b.1.signedPrecision=0 -unit.1.0.port.-1.b.1.signedScaleFactor=1.0 -unit.1.0.port.-1.b.1.tokencount=0 -unit.1.0.port.-1.b.1.unsignedOffset=0.0 -unit.1.0.port.-1.b.1.unsignedPrecision=0 -unit.1.0.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.1.visible=1 -unit.1.0.port.-1.b.2.alias=adc_ch2 -unit.1.0.port.-1.b.2.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.1.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.2.name=DataPort -unit.1.0.port.-1.b.2.orderindex=-1 -unit.1.0.port.-1.b.2.radix=Signed -unit.1.0.port.-1.b.2.signedOffset=0.0 -unit.1.0.port.-1.b.2.signedPrecision=0 -unit.1.0.port.-1.b.2.signedScaleFactor=1.0 -unit.1.0.port.-1.b.2.tokencount=0 -unit.1.0.port.-1.b.2.unsignedOffset=0.0 -unit.1.0.port.-1.b.2.unsignedPrecision=0 -unit.1.0.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.2.visible=1 -unit.1.0.port.-1.b.3.alias=adc_ch3 -unit.1.0.port.-1.b.3.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.3.name=DataPort -unit.1.0.port.-1.b.3.orderindex=-1 -unit.1.0.port.-1.b.3.radix=Signed -unit.1.0.port.-1.b.3.signedOffset=0.0 -unit.1.0.port.-1.b.3.signedPrecision=0 -unit.1.0.port.-1.b.3.signedScaleFactor=1.0 -unit.1.0.port.-1.b.3.tokencount=0 -unit.1.0.port.-1.b.3.unsignedOffset=0.0 -unit.1.0.port.-1.b.3.unsignedPrecision=0 -unit.1.0.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.3.visible=1 -unit.1.0.port.-1.buscount=4 -unit.1.0.port.-1.channelcount=128 -unit.1.0.port.-1.s.0.alias= -unit.1.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.0.name=DataPort[0] -unit.1.0.port.-1.s.0.orderindex=-1 -unit.1.0.port.-1.s.0.visible=0 -unit.1.0.port.-1.s.1.alias= -unit.1.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.1.name=DataPort[1] -unit.1.0.port.-1.s.1.orderindex=-1 -unit.1.0.port.-1.s.1.visible=0 -unit.1.0.port.-1.s.10.alias= -unit.1.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.10.name=DataPort[10] -unit.1.0.port.-1.s.10.orderindex=-1 -unit.1.0.port.-1.s.10.visible=0 -unit.1.0.port.-1.s.100.alias= -unit.1.0.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.100.name=DataPort[100] -unit.1.0.port.-1.s.100.orderindex=-1 -unit.1.0.port.-1.s.100.visible=1 -unit.1.0.port.-1.s.101.alias= -unit.1.0.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.101.name=DataPort[101] -unit.1.0.port.-1.s.101.orderindex=-1 -unit.1.0.port.-1.s.101.visible=1 -unit.1.0.port.-1.s.102.alias= -unit.1.0.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.102.name=DataPort[102] -unit.1.0.port.-1.s.102.orderindex=-1 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-unit.1.0.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.124.name=DataPort[124] -unit.1.0.port.-1.s.124.orderindex=-1 -unit.1.0.port.-1.s.124.visible=1 -unit.1.0.port.-1.s.125.alias= -unit.1.0.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.125.name=DataPort[125] -unit.1.0.port.-1.s.125.orderindex=-1 -unit.1.0.port.-1.s.125.visible=1 -unit.1.0.port.-1.s.126.alias= -unit.1.0.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.126.name=DataPort[126] -unit.1.0.port.-1.s.126.orderindex=-1 -unit.1.0.port.-1.s.126.visible=1 -unit.1.0.port.-1.s.127.alias= -unit.1.0.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.127.name=DataPort[127] -unit.1.0.port.-1.s.127.orderindex=-1 -unit.1.0.port.-1.s.127.visible=1 -unit.1.0.port.-1.s.13.alias= -unit.1.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.13.name=DataPort[13] -unit.1.0.port.-1.s.13.orderindex=-1 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-unit.1.0.port.-1.s.88.name=DataPort[88] -unit.1.0.port.-1.s.88.orderindex=-1 -unit.1.0.port.-1.s.88.visible=1 -unit.1.0.port.-1.s.89.alias= -unit.1.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.89.name=DataPort[89] -unit.1.0.port.-1.s.89.orderindex=-1 -unit.1.0.port.-1.s.89.visible=1 -unit.1.0.port.-1.s.9.alias= -unit.1.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.9.name=DataPort[9] -unit.1.0.port.-1.s.9.orderindex=-1 -unit.1.0.port.-1.s.9.visible=0 -unit.1.0.port.-1.s.90.alias= -unit.1.0.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.90.name=DataPort[90] -unit.1.0.port.-1.s.90.orderindex=-1 -unit.1.0.port.-1.s.90.visible=1 -unit.1.0.port.-1.s.91.alias= -unit.1.0.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.91.name=DataPort[91] -unit.1.0.port.-1.s.91.orderindex=-1 -unit.1.0.port.-1.s.91.visible=1 -unit.1.0.port.-1.s.92.alias= -unit.1.0.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.92.name=DataPort[92] -unit.1.0.port.-1.s.92.orderindex=-1 -unit.1.0.port.-1.s.92.visible=1 -unit.1.0.port.-1.s.93.alias= -unit.1.0.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.93.name=DataPort[93] -unit.1.0.port.-1.s.93.orderindex=-1 -unit.1.0.port.-1.s.93.visible=1 -unit.1.0.port.-1.s.94.alias= -unit.1.0.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.94.name=DataPort[94] -unit.1.0.port.-1.s.94.orderindex=-1 -unit.1.0.port.-1.s.94.visible=1 -unit.1.0.port.-1.s.95.alias= -unit.1.0.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.95.name=DataPort[95] -unit.1.0.port.-1.s.95.orderindex=-1 -unit.1.0.port.-1.s.95.visible=1 -unit.1.0.port.-1.s.96.alias= -unit.1.0.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.96.name=DataPort[96] -unit.1.0.port.-1.s.96.orderindex=-1 -unit.1.0.port.-1.s.96.visible=1 -unit.1.0.port.-1.s.97.alias= -unit.1.0.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.97.name=DataPort[97] -unit.1.0.port.-1.s.97.orderindex=-1 -unit.1.0.port.-1.s.97.visible=1 -unit.1.0.port.-1.s.98.alias= -unit.1.0.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.98.name=DataPort[98] -unit.1.0.port.-1.s.98.orderindex=-1 -unit.1.0.port.-1.s.98.visible=1 -unit.1.0.port.-1.s.99.alias= -unit.1.0.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.99.name=DataPort[99] -unit.1.0.port.-1.s.99.orderindex=-1 -unit.1.0.port.-1.s.99.visible=1 -unit.1.0.port.0.b.0.alias= -unit.1.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.b.0.name=TriggerPort0 -unit.1.0.port.0.b.0.orderindex=-1 -unit.1.0.port.0.b.0.radix=Hex -unit.1.0.port.0.b.0.signedOffset=0.0 -unit.1.0.port.0.b.0.signedPrecision=0 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-unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias= -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= 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-unit.1.1.port.-1.s.57.name=DataPort[57] -unit.1.1.port.-1.s.57.orderindex=-1 -unit.1.1.port.-1.s.57.visible=1 -unit.1.1.port.-1.s.58.alias= -unit.1.1.port.-1.s.58.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.58.name=DataPort[58] -unit.1.1.port.-1.s.58.orderindex=-1 -unit.1.1.port.-1.s.58.visible=1 -unit.1.1.port.-1.s.59.alias= -unit.1.1.port.-1.s.59.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.59.name=DataPort[59] -unit.1.1.port.-1.s.59.orderindex=-1 -unit.1.1.port.-1.s.59.visible=1 -unit.1.1.port.-1.s.6.alias= -unit.1.1.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.6.name=DataPort[6] -unit.1.1.port.-1.s.6.orderindex=-1 -unit.1.1.port.-1.s.6.visible=1 -unit.1.1.port.-1.s.60.alias= -unit.1.1.port.-1.s.60.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.60.name=DataPort[60] -unit.1.1.port.-1.s.60.orderindex=-1 -unit.1.1.port.-1.s.60.visible=1 -unit.1.1.port.-1.s.61.alias= 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-unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=32 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 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-unit.1.2.port.-1.s.71.alias= -unit.1.2.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.71.name=DataPort[71] -unit.1.2.port.-1.s.71.orderindex=-1 -unit.1.2.port.-1.s.71.visible=1 -unit.1.2.port.-1.s.72.alias= -unit.1.2.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.72.name=DataPort[72] -unit.1.2.port.-1.s.72.orderindex=-1 -unit.1.2.port.-1.s.72.visible=1 -unit.1.2.port.-1.s.73.alias= -unit.1.2.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.73.name=DataPort[73] -unit.1.2.port.-1.s.73.orderindex=-1 -unit.1.2.port.-1.s.73.visible=1 -unit.1.2.port.-1.s.74.alias= -unit.1.2.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.74.name=DataPort[74] -unit.1.2.port.-1.s.74.orderindex=-1 -unit.1.2.port.-1.s.74.visible=1 -unit.1.2.port.-1.s.75.alias= -unit.1.2.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.75.name=DataPort[75] -unit.1.2.port.-1.s.75.orderindex=-1 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-unit.1.2.port.-1.s.8.orderindex=-1 -unit.1.2.port.-1.s.8.visible=1 -unit.1.2.port.-1.s.80.alias= -unit.1.2.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.80.name=DataPort[80] -unit.1.2.port.-1.s.80.orderindex=-1 -unit.1.2.port.-1.s.80.visible=1 -unit.1.2.port.-1.s.81.alias= -unit.1.2.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.81.name=DataPort[81] -unit.1.2.port.-1.s.81.orderindex=-1 -unit.1.2.port.-1.s.81.visible=1 -unit.1.2.port.-1.s.82.alias= -unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=1 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=1 -unit.1.2.port.-1.s.84.alias= -unit.1.2.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.2.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.89.name=DataPort[89] -unit.1.2.port.-1.s.89.orderindex=-1 -unit.1.2.port.-1.s.89.visible=1 -unit.1.2.port.-1.s.9.alias= -unit.1.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.9.name=DataPort[9] -unit.1.2.port.-1.s.9.orderindex=-1 -unit.1.2.port.-1.s.9.visible=1 -unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=1 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=1 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 -unit.1.2.port.-1.s.92.visible=1 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-unit.1.2.port.0.b.0.visible=1 -unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=32 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex -unit.1.2.port.3.b.0.signedOffset=0.0 -unit.1.2.port.3.b.0.signedPrecision=0 -unit.1.2.port.3.b.0.signedScaleFactor=1.0 -unit.1.2.port.3.b.0.unsignedOffset=0.0 -unit.1.2.port.3.b.0.unsignedPrecision=0 -unit.1.2.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.3.b.0.visible=1 -unit.1.2.port.3.buscount=1 -unit.1.2.port.3.channelcount=32 -unit.1.2.port.3.s.0.alias= -unit.1.2.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.0.name=TriggerPort3[0] -unit.1.2.port.3.s.0.orderindex=-1 -unit.1.2.port.3.s.0.visible=1 -unit.1.2.port.3.s.1.alias= -unit.1.2.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.1.name=TriggerPort3[1] -unit.1.2.port.3.s.1.orderindex=-1 -unit.1.2.port.3.s.1.visible=1 -unit.1.2.port.3.s.10.alias= -unit.1.2.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.10.name=TriggerPort3[10] -unit.1.2.port.3.s.10.orderindex=-1 -unit.1.2.port.3.s.10.visible=1 -unit.1.2.port.3.s.11.alias= -unit.1.2.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.11.name=TriggerPort3[11] -unit.1.2.port.3.s.11.orderindex=-1 -unit.1.2.port.3.s.11.visible=1 -unit.1.2.port.3.s.12.alias= -unit.1.2.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.12.name=TriggerPort3[12] -unit.1.2.port.3.s.12.orderindex=-1 -unit.1.2.port.3.s.12.visible=1 -unit.1.2.port.3.s.13.alias= -unit.1.2.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.13.name=TriggerPort3[13] -unit.1.2.port.3.s.13.orderindex=-1 -unit.1.2.port.3.s.13.visible=1 -unit.1.2.port.3.s.14.alias= -unit.1.2.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.14.name=TriggerPort3[14] -unit.1.2.port.3.s.14.orderindex=-1 -unit.1.2.port.3.s.14.visible=1 -unit.1.2.port.3.s.15.alias= -unit.1.2.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.15.name=TriggerPort3[15] -unit.1.2.port.3.s.15.orderindex=-1 -unit.1.2.port.3.s.15.visible=1 -unit.1.2.port.3.s.16.alias= -unit.1.2.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.16.name=TriggerPort3[16] -unit.1.2.port.3.s.16.orderindex=-1 -unit.1.2.port.3.s.16.visible=1 -unit.1.2.port.3.s.17.alias= -unit.1.2.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.17.name=TriggerPort3[17] -unit.1.2.port.3.s.17.orderindex=-1 -unit.1.2.port.3.s.17.visible=1 -unit.1.2.port.3.s.18.alias= -unit.1.2.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.18.name=TriggerPort3[18] -unit.1.2.port.3.s.18.orderindex=-1 -unit.1.2.port.3.s.18.visible=1 -unit.1.2.port.3.s.19.alias= -unit.1.2.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.19.name=TriggerPort3[19] -unit.1.2.port.3.s.19.orderindex=-1 -unit.1.2.port.3.s.19.visible=1 -unit.1.2.port.3.s.2.alias= -unit.1.2.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.2.name=TriggerPort3[2] -unit.1.2.port.3.s.2.orderindex=-1 -unit.1.2.port.3.s.2.visible=1 -unit.1.2.port.3.s.20.alias= -unit.1.2.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.20.name=TriggerPort3[20] -unit.1.2.port.3.s.20.orderindex=-1 -unit.1.2.port.3.s.20.visible=1 -unit.1.2.port.3.s.21.alias= -unit.1.2.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.21.name=TriggerPort3[21] -unit.1.2.port.3.s.21.orderindex=-1 -unit.1.2.port.3.s.21.visible=1 -unit.1.2.port.3.s.22.alias= -unit.1.2.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.22.name=TriggerPort3[22] -unit.1.2.port.3.s.22.orderindex=-1 -unit.1.2.port.3.s.22.visible=1 -unit.1.2.port.3.s.23.alias= -unit.1.2.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.23.name=TriggerPort3[23] -unit.1.2.port.3.s.23.orderindex=-1 -unit.1.2.port.3.s.23.visible=1 -unit.1.2.port.3.s.24.alias= -unit.1.2.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.24.name=TriggerPort3[24] -unit.1.2.port.3.s.24.orderindex=-1 -unit.1.2.port.3.s.24.visible=1 -unit.1.2.port.3.s.25.alias= -unit.1.2.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.25.name=TriggerPort3[25] -unit.1.2.port.3.s.25.orderindex=-1 -unit.1.2.port.3.s.25.visible=1 -unit.1.2.port.3.s.26.alias= -unit.1.2.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.26.name=TriggerPort3[26] -unit.1.2.port.3.s.26.orderindex=-1 -unit.1.2.port.3.s.26.visible=1 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-unit.1.3.port.-1.s.79.name=DataPort[79] -unit.1.3.port.-1.s.79.orderindex=-1 -unit.1.3.port.-1.s.79.visible=1 -unit.1.3.port.-1.s.8.alias= -unit.1.3.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.8.name=DataPort[8] -unit.1.3.port.-1.s.8.orderindex=-1 -unit.1.3.port.-1.s.8.visible=1 -unit.1.3.port.-1.s.80.alias= -unit.1.3.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.80.name=DataPort[80] -unit.1.3.port.-1.s.80.orderindex=-1 -unit.1.3.port.-1.s.80.visible=1 -unit.1.3.port.-1.s.81.alias= -unit.1.3.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.81.name=DataPort[81] -unit.1.3.port.-1.s.81.orderindex=-1 -unit.1.3.port.-1.s.81.visible=1 -unit.1.3.port.-1.s.82.alias= -unit.1.3.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.82.name=DataPort[82] -unit.1.3.port.-1.s.82.orderindex=-1 -unit.1.3.port.-1.s.82.visible=1 -unit.1.3.port.-1.s.83.alias= -unit.1.3.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.83.name=DataPort[83] -unit.1.3.port.-1.s.83.orderindex=-1 -unit.1.3.port.-1.s.83.visible=1 -unit.1.3.port.-1.s.84.alias= -unit.1.3.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.84.name=DataPort[84] -unit.1.3.port.-1.s.84.orderindex=-1 -unit.1.3.port.-1.s.84.visible=1 -unit.1.3.port.-1.s.85.alias= -unit.1.3.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.85.name=DataPort[85] -unit.1.3.port.-1.s.85.orderindex=-1 -unit.1.3.port.-1.s.85.visible=1 -unit.1.3.port.-1.s.86.alias= -unit.1.3.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.86.name=DataPort[86] -unit.1.3.port.-1.s.86.orderindex=-1 -unit.1.3.port.-1.s.86.visible=1 -unit.1.3.port.-1.s.87.alias= -unit.1.3.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.87.name=DataPort[87] -unit.1.3.port.-1.s.87.orderindex=-1 -unit.1.3.port.-1.s.87.visible=1 -unit.1.3.port.-1.s.88.alias= -unit.1.3.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.88.name=DataPort[88] -unit.1.3.port.-1.s.88.orderindex=-1 -unit.1.3.port.-1.s.88.visible=1 -unit.1.3.port.-1.s.89.alias= -unit.1.3.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.89.name=DataPort[89] -unit.1.3.port.-1.s.89.orderindex=-1 -unit.1.3.port.-1.s.89.visible=1 -unit.1.3.port.-1.s.9.alias= -unit.1.3.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.9.name=DataPort[9] -unit.1.3.port.-1.s.9.orderindex=-1 -unit.1.3.port.-1.s.9.visible=1 -unit.1.3.port.-1.s.90.alias= -unit.1.3.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.90.name=DataPort[90] -unit.1.3.port.-1.s.90.orderindex=-1 -unit.1.3.port.-1.s.90.visible=1 -unit.1.3.port.-1.s.91.alias= -unit.1.3.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.91.name=DataPort[91] -unit.1.3.port.-1.s.91.orderindex=-1 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-unit.1.3.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 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-unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.portcount=4 -unit.1.3.rep_trigger.clobber=1 -unit.1.3.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone -unit.1.3.rep_trigger.filename=waveform -unit.1.3.rep_trigger.format=ASCII -unit.1.3.rep_trigger.loggingEnabled=0 -unit.1.3.rep_trigger.signals=All Signals/Buses -unit.1.3.samplesPerTrigger=1 -unit.1.3.triggerCapture=1 -unit.1.3.triggerNSamplesTS=0 -unit.1.3.triggerPosition=0 -unit.1.3.triggerWindowCount=1 -unit.1.3.triggerWindowDepth=4096 -unit.1.3.triggerWindowTS=0 -unit.1.3.username=MyILA3 -unit.1.3.waveform.count=128 -unit.1.3.waveform.posn.0.channel=0 -unit.1.3.waveform.posn.0.name=DataPort[0] -unit.1.3.waveform.posn.0.type=signal -unit.1.3.waveform.posn.1.channel=1 -unit.1.3.waveform.posn.1.name=DataPort[1] -unit.1.3.waveform.posn.1.type=signal -unit.1.3.waveform.posn.10.channel=10 -unit.1.3.waveform.posn.10.name=DataPort[10] -unit.1.3.waveform.posn.10.type=signal -unit.1.3.waveform.posn.100.channel=100 -unit.1.3.waveform.posn.100.name=DataPort[100] -unit.1.3.waveform.posn.100.type=signal -unit.1.3.waveform.posn.101.channel=101 -unit.1.3.waveform.posn.101.name=DataPort[101] -unit.1.3.waveform.posn.101.type=signal -unit.1.3.waveform.posn.102.channel=102 -unit.1.3.waveform.posn.102.name=DataPort[102] -unit.1.3.waveform.posn.102.type=signal -unit.1.3.waveform.posn.103.channel=103 -unit.1.3.waveform.posn.103.name=DataPort[103] -unit.1.3.waveform.posn.103.type=signal -unit.1.3.waveform.posn.104.channel=104 -unit.1.3.waveform.posn.104.name=DataPort[104] -unit.1.3.waveform.posn.104.type=signal -unit.1.3.waveform.posn.105.channel=105 -unit.1.3.waveform.posn.105.name=DataPort[105] -unit.1.3.waveform.posn.105.type=signal -unit.1.3.waveform.posn.106.channel=106 -unit.1.3.waveform.posn.106.name=DataPort[106] -unit.1.3.waveform.posn.106.type=signal -unit.1.3.waveform.posn.107.channel=107 -unit.1.3.waveform.posn.107.name=DataPort[107] -unit.1.3.waveform.posn.107.type=signal -unit.1.3.waveform.posn.108.channel=108 -unit.1.3.waveform.posn.108.name=DataPort[108] -unit.1.3.waveform.posn.108.type=signal -unit.1.3.waveform.posn.109.channel=109 -unit.1.3.waveform.posn.109.name=DataPort[109] -unit.1.3.waveform.posn.109.type=signal -unit.1.3.waveform.posn.11.channel=11 -unit.1.3.waveform.posn.11.name=DataPort[11] -unit.1.3.waveform.posn.11.type=signal -unit.1.3.waveform.posn.110.channel=110 -unit.1.3.waveform.posn.110.name=DataPort[110] -unit.1.3.waveform.posn.110.type=signal -unit.1.3.waveform.posn.111.channel=111 -unit.1.3.waveform.posn.111.name=DataPort[111] -unit.1.3.waveform.posn.111.type=signal -unit.1.3.waveform.posn.112.channel=112 -unit.1.3.waveform.posn.112.name=DataPort[112] -unit.1.3.waveform.posn.112.type=signal -unit.1.3.waveform.posn.113.channel=113 -unit.1.3.waveform.posn.113.name=DataPort[113] -unit.1.3.waveform.posn.113.type=signal -unit.1.3.waveform.posn.114.channel=114 -unit.1.3.waveform.posn.114.name=DataPort[114] -unit.1.3.waveform.posn.114.type=signal -unit.1.3.waveform.posn.115.channel=115 -unit.1.3.waveform.posn.115.name=DataPort[115] -unit.1.3.waveform.posn.115.type=signal -unit.1.3.waveform.posn.116.channel=116 -unit.1.3.waveform.posn.116.name=DataPort[116] -unit.1.3.waveform.posn.116.type=signal -unit.1.3.waveform.posn.117.channel=117 -unit.1.3.waveform.posn.117.name=DataPort[117] -unit.1.3.waveform.posn.117.type=signal -unit.1.3.waveform.posn.118.channel=118 -unit.1.3.waveform.posn.118.name=DataPort[118] -unit.1.3.waveform.posn.118.type=signal -unit.1.3.waveform.posn.119.channel=119 -unit.1.3.waveform.posn.119.name=DataPort[119] -unit.1.3.waveform.posn.119.type=signal -unit.1.3.waveform.posn.12.channel=12 -unit.1.3.waveform.posn.12.name=DataPort[12] -unit.1.3.waveform.posn.12.type=signal -unit.1.3.waveform.posn.120.channel=120 -unit.1.3.waveform.posn.120.name=DataPort[120] -unit.1.3.waveform.posn.120.type=signal -unit.1.3.waveform.posn.121.channel=121 -unit.1.3.waveform.posn.121.name=DataPort[121] -unit.1.3.waveform.posn.121.type=signal -unit.1.3.waveform.posn.122.channel=122 -unit.1.3.waveform.posn.122.name=DataPort[122] -unit.1.3.waveform.posn.122.type=signal -unit.1.3.waveform.posn.123.channel=123 -unit.1.3.waveform.posn.123.name=DataPort[123] -unit.1.3.waveform.posn.123.type=signal -unit.1.3.waveform.posn.124.channel=124 -unit.1.3.waveform.posn.124.name=DataPort[124] -unit.1.3.waveform.posn.124.type=signal -unit.1.3.waveform.posn.125.channel=125 -unit.1.3.waveform.posn.125.name=DataPort[125] -unit.1.3.waveform.posn.125.type=signal -unit.1.3.waveform.posn.126.channel=126 -unit.1.3.waveform.posn.126.name=DataPort[126] -unit.1.3.waveform.posn.126.type=signal -unit.1.3.waveform.posn.127.channel=127 -unit.1.3.waveform.posn.127.name=DataPort[127] -unit.1.3.waveform.posn.127.type=signal -unit.1.3.waveform.posn.13.channel=13 -unit.1.3.waveform.posn.13.name=DataPort[13] -unit.1.3.waveform.posn.13.type=signal -unit.1.3.waveform.posn.14.channel=14 -unit.1.3.waveform.posn.14.name=DataPort[14] -unit.1.3.waveform.posn.14.type=signal -unit.1.3.waveform.posn.15.channel=15 -unit.1.3.waveform.posn.15.name=DataPort[15] -unit.1.3.waveform.posn.15.type=signal -unit.1.3.waveform.posn.16.channel=16 -unit.1.3.waveform.posn.16.name=DataPort[16] -unit.1.3.waveform.posn.16.type=signal -unit.1.3.waveform.posn.17.channel=17 -unit.1.3.waveform.posn.17.name=DataPort[17] -unit.1.3.waveform.posn.17.type=signal -unit.1.3.waveform.posn.18.channel=18 -unit.1.3.waveform.posn.18.name=DataPort[18] -unit.1.3.waveform.posn.18.type=signal -unit.1.3.waveform.posn.19.channel=19 -unit.1.3.waveform.posn.19.name=DataPort[19] -unit.1.3.waveform.posn.19.type=signal -unit.1.3.waveform.posn.2.channel=2 -unit.1.3.waveform.posn.2.name=DataPort[2] -unit.1.3.waveform.posn.2.type=signal -unit.1.3.waveform.posn.20.channel=20 -unit.1.3.waveform.posn.20.name=DataPort[20] -unit.1.3.waveform.posn.20.type=signal -unit.1.3.waveform.posn.21.channel=21 -unit.1.3.waveform.posn.21.name=DataPort[21] -unit.1.3.waveform.posn.21.type=signal -unit.1.3.waveform.posn.22.channel=22 -unit.1.3.waveform.posn.22.name=DataPort[22] -unit.1.3.waveform.posn.22.type=signal -unit.1.3.waveform.posn.23.channel=23 -unit.1.3.waveform.posn.23.name=DataPort[23] -unit.1.3.waveform.posn.23.type=signal -unit.1.3.waveform.posn.24.channel=24 -unit.1.3.waveform.posn.24.name=DataPort[24] -unit.1.3.waveform.posn.24.type=signal -unit.1.3.waveform.posn.25.channel=25 -unit.1.3.waveform.posn.25.name=DataPort[25] -unit.1.3.waveform.posn.25.type=signal -unit.1.3.waveform.posn.26.channel=26 -unit.1.3.waveform.posn.26.name=DataPort[26] -unit.1.3.waveform.posn.26.type=signal -unit.1.3.waveform.posn.27.channel=27 -unit.1.3.waveform.posn.27.name=DataPort[27] -unit.1.3.waveform.posn.27.type=signal -unit.1.3.waveform.posn.28.channel=28 -unit.1.3.waveform.posn.28.name=DataPort[28] -unit.1.3.waveform.posn.28.type=signal -unit.1.3.waveform.posn.29.channel=29 -unit.1.3.waveform.posn.29.name=DataPort[29] -unit.1.3.waveform.posn.29.type=signal -unit.1.3.waveform.posn.3.channel=3 -unit.1.3.waveform.posn.3.name=DataPort[3] -unit.1.3.waveform.posn.3.type=signal -unit.1.3.waveform.posn.30.channel=30 -unit.1.3.waveform.posn.30.name=DataPort[30] -unit.1.3.waveform.posn.30.type=signal -unit.1.3.waveform.posn.31.channel=31 -unit.1.3.waveform.posn.31.name=DataPort[31] -unit.1.3.waveform.posn.31.type=signal -unit.1.3.waveform.posn.32.channel=32 -unit.1.3.waveform.posn.32.name=DataPort[32] -unit.1.3.waveform.posn.32.type=signal -unit.1.3.waveform.posn.33.channel=33 -unit.1.3.waveform.posn.33.name=DataPort[33] -unit.1.3.waveform.posn.33.type=signal -unit.1.3.waveform.posn.34.channel=34 -unit.1.3.waveform.posn.34.name=DataPort[34] -unit.1.3.waveform.posn.34.type=signal -unit.1.3.waveform.posn.35.channel=35 -unit.1.3.waveform.posn.35.name=DataPort[35] -unit.1.3.waveform.posn.35.type=signal -unit.1.3.waveform.posn.36.channel=36 -unit.1.3.waveform.posn.36.name=DataPort[36] -unit.1.3.waveform.posn.36.type=signal -unit.1.3.waveform.posn.37.channel=37 -unit.1.3.waveform.posn.37.name=DataPort[37] -unit.1.3.waveform.posn.37.type=signal -unit.1.3.waveform.posn.38.channel=38 -unit.1.3.waveform.posn.38.name=DataPort[38] -unit.1.3.waveform.posn.38.type=signal -unit.1.3.waveform.posn.39.channel=39 -unit.1.3.waveform.posn.39.name=DataPort[39] -unit.1.3.waveform.posn.39.type=signal -unit.1.3.waveform.posn.4.channel=4 -unit.1.3.waveform.posn.4.name=DataPort[4] -unit.1.3.waveform.posn.4.type=signal -unit.1.3.waveform.posn.40.channel=40 -unit.1.3.waveform.posn.40.name=DataPort[40] -unit.1.3.waveform.posn.40.type=signal -unit.1.3.waveform.posn.41.channel=41 -unit.1.3.waveform.posn.41.name=DataPort[41] -unit.1.3.waveform.posn.41.type=signal -unit.1.3.waveform.posn.42.channel=42 -unit.1.3.waveform.posn.42.name=DataPort[42] -unit.1.3.waveform.posn.42.type=signal -unit.1.3.waveform.posn.43.channel=43 -unit.1.3.waveform.posn.43.name=DataPort[43] -unit.1.3.waveform.posn.43.type=signal -unit.1.3.waveform.posn.44.channel=44 -unit.1.3.waveform.posn.44.name=DataPort[44] -unit.1.3.waveform.posn.44.type=signal -unit.1.3.waveform.posn.45.channel=45 -unit.1.3.waveform.posn.45.name=DataPort[45] -unit.1.3.waveform.posn.45.type=signal -unit.1.3.waveform.posn.46.channel=46 -unit.1.3.waveform.posn.46.name=DataPort[46] -unit.1.3.waveform.posn.46.type=signal -unit.1.3.waveform.posn.47.channel=47 -unit.1.3.waveform.posn.47.name=DataPort[47] -unit.1.3.waveform.posn.47.type=signal -unit.1.3.waveform.posn.48.channel=48 -unit.1.3.waveform.posn.48.name=DataPort[48] -unit.1.3.waveform.posn.48.type=signal -unit.1.3.waveform.posn.49.channel=49 -unit.1.3.waveform.posn.49.name=DataPort[49] -unit.1.3.waveform.posn.49.type=signal -unit.1.3.waveform.posn.5.channel=5 -unit.1.3.waveform.posn.5.name=DataPort[5] -unit.1.3.waveform.posn.5.type=signal -unit.1.3.waveform.posn.50.channel=50 -unit.1.3.waveform.posn.50.name=DataPort[50] -unit.1.3.waveform.posn.50.type=signal -unit.1.3.waveform.posn.51.channel=51 -unit.1.3.waveform.posn.51.name=DataPort[51] -unit.1.3.waveform.posn.51.type=signal -unit.1.3.waveform.posn.52.channel=52 -unit.1.3.waveform.posn.52.name=DataPort[52] -unit.1.3.waveform.posn.52.type=signal -unit.1.3.waveform.posn.53.channel=53 -unit.1.3.waveform.posn.53.name=DataPort[53] -unit.1.3.waveform.posn.53.type=signal -unit.1.3.waveform.posn.54.channel=54 -unit.1.3.waveform.posn.54.name=DataPort[54] -unit.1.3.waveform.posn.54.type=signal -unit.1.3.waveform.posn.55.channel=55 -unit.1.3.waveform.posn.55.name=DataPort[55] -unit.1.3.waveform.posn.55.type=signal -unit.1.3.waveform.posn.56.channel=56 -unit.1.3.waveform.posn.56.name=DataPort[56] -unit.1.3.waveform.posn.56.type=signal -unit.1.3.waveform.posn.57.channel=57 -unit.1.3.waveform.posn.57.name=DataPort[57] -unit.1.3.waveform.posn.57.type=signal -unit.1.3.waveform.posn.58.channel=58 -unit.1.3.waveform.posn.58.name=DataPort[58] -unit.1.3.waveform.posn.58.type=signal -unit.1.3.waveform.posn.59.channel=59 -unit.1.3.waveform.posn.59.name=DataPort[59] -unit.1.3.waveform.posn.59.type=signal -unit.1.3.waveform.posn.6.channel=6 -unit.1.3.waveform.posn.6.name=DataPort[6] -unit.1.3.waveform.posn.6.type=signal -unit.1.3.waveform.posn.60.channel=60 -unit.1.3.waveform.posn.60.name=DataPort[60] -unit.1.3.waveform.posn.60.type=signal -unit.1.3.waveform.posn.61.channel=61 -unit.1.3.waveform.posn.61.name=DataPort[61] -unit.1.3.waveform.posn.61.type=signal -unit.1.3.waveform.posn.62.channel=62 -unit.1.3.waveform.posn.62.name=DataPort[62] -unit.1.3.waveform.posn.62.type=signal -unit.1.3.waveform.posn.63.channel=63 -unit.1.3.waveform.posn.63.name=DataPort[63] -unit.1.3.waveform.posn.63.type=signal -unit.1.3.waveform.posn.64.channel=64 -unit.1.3.waveform.posn.64.name=DataPort[64] -unit.1.3.waveform.posn.64.type=signal -unit.1.3.waveform.posn.65.channel=65 -unit.1.3.waveform.posn.65.name=DataPort[65] -unit.1.3.waveform.posn.65.type=signal -unit.1.3.waveform.posn.66.channel=66 -unit.1.3.waveform.posn.66.name=DataPort[66] -unit.1.3.waveform.posn.66.type=signal -unit.1.3.waveform.posn.67.channel=67 -unit.1.3.waveform.posn.67.name=DataPort[67] -unit.1.3.waveform.posn.67.type=signal -unit.1.3.waveform.posn.68.channel=68 -unit.1.3.waveform.posn.68.name=DataPort[68] -unit.1.3.waveform.posn.68.type=signal -unit.1.3.waveform.posn.69.channel=69 -unit.1.3.waveform.posn.69.name=DataPort[69] -unit.1.3.waveform.posn.69.type=signal -unit.1.3.waveform.posn.7.channel=7 -unit.1.3.waveform.posn.7.name=DataPort[7] -unit.1.3.waveform.posn.7.type=signal -unit.1.3.waveform.posn.70.channel=70 -unit.1.3.waveform.posn.70.name=DataPort[70] -unit.1.3.waveform.posn.70.type=signal -unit.1.3.waveform.posn.71.channel=71 -unit.1.3.waveform.posn.71.name=DataPort[71] -unit.1.3.waveform.posn.71.type=signal -unit.1.3.waveform.posn.72.channel=72 -unit.1.3.waveform.posn.72.name=DataPort[72] -unit.1.3.waveform.posn.72.type=signal -unit.1.3.waveform.posn.73.channel=73 -unit.1.3.waveform.posn.73.name=DataPort[73] -unit.1.3.waveform.posn.73.type=signal -unit.1.3.waveform.posn.74.channel=74 -unit.1.3.waveform.posn.74.name=DataPort[74] -unit.1.3.waveform.posn.74.type=signal -unit.1.3.waveform.posn.75.channel=75 -unit.1.3.waveform.posn.75.name=DataPort[75] -unit.1.3.waveform.posn.75.type=signal -unit.1.3.waveform.posn.76.channel=76 -unit.1.3.waveform.posn.76.name=DataPort[76] -unit.1.3.waveform.posn.76.type=signal -unit.1.3.waveform.posn.77.channel=77 -unit.1.3.waveform.posn.77.name=DataPort[77] -unit.1.3.waveform.posn.77.type=signal -unit.1.3.waveform.posn.78.channel=78 -unit.1.3.waveform.posn.78.name=DataPort[78] -unit.1.3.waveform.posn.78.type=signal -unit.1.3.waveform.posn.79.channel=79 -unit.1.3.waveform.posn.79.name=DataPort[79] -unit.1.3.waveform.posn.79.type=signal -unit.1.3.waveform.posn.8.channel=8 -unit.1.3.waveform.posn.8.name=DataPort[8] -unit.1.3.waveform.posn.8.type=signal -unit.1.3.waveform.posn.80.channel=80 -unit.1.3.waveform.posn.80.name=DataPort[80] -unit.1.3.waveform.posn.80.type=signal -unit.1.3.waveform.posn.81.channel=81 -unit.1.3.waveform.posn.81.name=DataPort[81] -unit.1.3.waveform.posn.81.type=signal -unit.1.3.waveform.posn.82.channel=82 -unit.1.3.waveform.posn.82.name=DataPort[82] -unit.1.3.waveform.posn.82.type=signal -unit.1.3.waveform.posn.83.channel=83 -unit.1.3.waveform.posn.83.name=DataPort[83] -unit.1.3.waveform.posn.83.type=signal -unit.1.3.waveform.posn.84.channel=84 -unit.1.3.waveform.posn.84.name=DataPort[84] -unit.1.3.waveform.posn.84.type=signal -unit.1.3.waveform.posn.85.channel=85 -unit.1.3.waveform.posn.85.name=DataPort[85] -unit.1.3.waveform.posn.85.type=signal -unit.1.3.waveform.posn.86.channel=86 -unit.1.3.waveform.posn.86.name=DataPort[86] -unit.1.3.waveform.posn.86.type=signal -unit.1.3.waveform.posn.87.channel=87 -unit.1.3.waveform.posn.87.name=DataPort[87] -unit.1.3.waveform.posn.87.type=signal -unit.1.3.waveform.posn.88.channel=88 -unit.1.3.waveform.posn.88.name=DataPort[88] -unit.1.3.waveform.posn.88.type=signal -unit.1.3.waveform.posn.89.channel=89 -unit.1.3.waveform.posn.89.name=DataPort[89] -unit.1.3.waveform.posn.89.type=signal -unit.1.3.waveform.posn.9.channel=9 -unit.1.3.waveform.posn.9.name=DataPort[9] -unit.1.3.waveform.posn.9.type=signal -unit.1.3.waveform.posn.90.channel=90 -unit.1.3.waveform.posn.90.name=DataPort[90] -unit.1.3.waveform.posn.90.type=signal -unit.1.3.waveform.posn.91.channel=91 -unit.1.3.waveform.posn.91.name=DataPort[91] -unit.1.3.waveform.posn.91.type=signal -unit.1.3.waveform.posn.92.channel=92 -unit.1.3.waveform.posn.92.name=DataPort[92] -unit.1.3.waveform.posn.92.type=signal -unit.1.3.waveform.posn.93.channel=93 -unit.1.3.waveform.posn.93.name=DataPort[93] -unit.1.3.waveform.posn.93.type=signal -unit.1.3.waveform.posn.94.channel=94 -unit.1.3.waveform.posn.94.name=DataPort[94] -unit.1.3.waveform.posn.94.type=signal -unit.1.3.waveform.posn.95.channel=95 -unit.1.3.waveform.posn.95.name=DataPort[95] -unit.1.3.waveform.posn.95.type=signal -unit.1.3.waveform.posn.96.channel=96 -unit.1.3.waveform.posn.96.name=DataPort[96] -unit.1.3.waveform.posn.96.type=signal -unit.1.3.waveform.posn.97.channel=97 -unit.1.3.waveform.posn.97.name=DataPort[97] -unit.1.3.waveform.posn.97.type=signal -unit.1.3.waveform.posn.98.channel=98 -unit.1.3.waveform.posn.98.name=DataPort[98] -unit.1.3.waveform.posn.98.type=signal -unit.1.3.waveform.posn.99.channel=99 -unit.1.3.waveform.posn.99.name=DataPort[99] -unit.1.3.waveform.posn.99.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd deleted file mode 100644 index 21542e5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd +++ /dev/null @@ -1,47 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf b/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf deleted file mode 100644 index 57a42952..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf +++ /dev/null @@ -1,96 +0,0 @@ -NET "buttons_i[0]" LOC = D22; -NET "buttons_i[1]" LOC = C22; -NET "buttons_i[2]" LOC = L21; -NET "buttons_i[3]" LOC = L20; -NET "buttons_i[4]" LOC = C18; -NET "buttons_i[5]" LOC = B18; -NET "buttons_i[6]" LOC = K22; -NET "buttons_i[7]" LOC = K21; -NET "leds_o[0]" LOC = AC22; -NET "leds_o[1]" LOC = AC24; -NET "leds_o[2]" LOC = AE22; -NET "leds_o[3]" LOC = AE23; -NET "leds_o[4]" LOC = AB23; -NET "leds_o[5]" LOC = AG23; -NET "leds_o[6]" LOC = AE24; -NET "leds_o[7]" LOC = AD24; -NET "uart_rxd_i" LOC = J24; -NET "uart_txd_o" LOC = J25; -NET "buttons_i[7]" IOSTANDARD = LVCMOS25; -NET "buttons_i[6]" IOSTANDARD = LVCMOS25; -NET "buttons_i[5]" IOSTANDARD = LVCMOS25; -NET "buttons_i[4]" IOSTANDARD = LVCMOS25; -NET "buttons_i[3]" IOSTANDARD = LVCMOS25; -NET "buttons_i[2]" IOSTANDARD = LVCMOS25; -NET "buttons_i[1]" IOSTANDARD = LVCMOS25; -NET "buttons_i[0]" IOSTANDARD = LVCMOS25; -NET "leds_o[7]" IOSTANDARD = LVCMOS25; -NET "leds_o[7]" DRIVE = 12; -NET "leds_o[7]" SLEW = SLOW; -NET "leds_o[6]" IOSTANDARD = LVCMOS25; -NET "leds_o[6]" DRIVE = 12; -NET "leds_o[6]" SLEW = SLOW; -NET "leds_o[5]" IOSTANDARD = LVCMOS25; -NET "leds_o[5]" DRIVE = 12; -NET "leds_o[5]" SLEW = SLOW; -NET "leds_o[4]" IOSTANDARD = LVCMOS25; -NET "leds_o[4]" DRIVE = 12; -NET "leds_o[4]" SLEW = SLOW; -NET "leds_o[3]" IOSTANDARD = LVCMOS25; -NET "leds_o[3]" DRIVE = 12; -NET "leds_o[3]" SLEW = SLOW; -NET "leds_o[2]" IOSTANDARD = LVCMOS25; -NET "leds_o[2]" DRIVE = 12; -NET "leds_o[2]" SLEW = SLOW; -NET "leds_o[1]" IOSTANDARD = LVCMOS25; -NET "leds_o[1]" DRIVE = 12; -NET "leds_o[1]" SLEW = SLOW; -NET "leds_o[0]" IOSTANDARD = LVCMOS25; -NET "leds_o[0]" DRIVE = 12; -NET "leds_o[0]" SLEW = SLOW; -NET "uart_rxd_i" IOSTANDARD = LVCMOS25; -NET "uart_txd_o" IOSTANDARD = LVCMOS25; - -NET "sys_clk_p_i" IOSTANDARD = LVDS_25; -NET "sys_clk_n_i" IOSTANDARD = LVDS_25; -NET "sys_rst_button_i" IOSTANDARD = "SSTL15" | TIG; - -NET "sys_rst_button_i" LOC = H10; - -# PlanAhead Generated physical constraints - -NET "sys_clk_n_i" LOC = H9; -NET "sys_clk_p_i" LOC = J9; - -# Ethernet LOC Contraints. MII 10/100 Mode - -NET "mrstn_o" LOC = AH13; -NET "mcoll_pad_i" LOC = AK13; ## 114 on U80 -NET "mcrs_pad_i" LOC = AL13; ## 115 on U80 -# NET "PHY_INT" LOC = AH14; ## 32 on U80 -NET "mdc_pad_o" LOC = AP14; ## 35 on U80 -NET "md_pad_b" LOC = AN14; ## 33 on U80 -# NET "PHY_RESET" LOC = AH13; ## 36 on U80 -NET "mrx_clk_pad_i" LOC = AP11; ## 7 on U80 -NET "mrxdv_pad_i" LOC = AM13; ## 4 on U80 -NET "mrxd_pad_i[0]" LOC = AN13; ## 3 on U80 -NET "mrxd_pad_i[1]" LOC = AF14; ## 128 on U80 -NET "mrxd_pad_i[2]" LOC = AE14; ## 126 on U80 -NET "mrxd_pad_i[3]" LOC = AN12; ## 125 on U80 -# NET "PHY_RXD4" LOC = AM12; ## 124 on U80 -# NET "PHY_RXD5" LOC = AD11; ## 123 on U80 -# NET "PHY_RXD6" LOC = AC12; ## 121 on U80 -# NET "PHY_RXD7" LOC = AC13; ## 120 on U80 -NET "mrxerr_pad_i" LOC = AG12; ## 9 on U80 -NET "mtx_clk_pad_i" LOC = AD12; ## 10 on U80 -NET "mtxen_pad_o" LOC = AJ10; ## 16 on U80 -# NET "PHY_TXC_GTXCLK" LOC = AH12; ## 14 on U80 -NET "mtxd_pad_o[0]" LOC = AM11; ## 18 on U80 -NET "mtxd_pad_o[1]" LOC = AL11; ## 19 on U80 -NET "mtxd_pad_o[2]" LOC = AG10; ## 20 on U80 -NET "mtxd_pad_o[3]" LOC = AG11; ## 24 on U80 -# NET "PHY_TXD4" LOC = AL10; ## 25 on U80 -# NET "PHY_TXD5" LOC = AM10; ## 26 on U80 -# NET "PHY_TXD6" LOC = AE11; ## 28 on U80 -# NET "PHY_TXD7" LOC = AF11; ## 29 on U80 -NET "mtxerr_pad_o" LOC = AH10; ## 13 on U80 diff --git a/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd b/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd deleted file mode 100755 index c1f0897a..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd +++ /dev/null @@ -1,833 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top Etherbone test design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2012-11-12 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top dsign for testing the integration of Etherbone and --- MAC cores -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2012-11-12 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_generic_pkg.all; --- Ethernet MAC Modules and SDB structure -use work.ethmac_pkg.all; --- Wishbone Fabric interface -use work.wr_fabric_pkg.all; --- Etherbone slave core -use work.etherbone_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_ebone is -port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - uart_txd_o : out std_logic; - uart_rxd_i : in std_logic; - - ----------------------------------------- - -- PHY pins - ----------------------------------------- - - -- Clock and resets to PHY (GMII). Not used in MII mode (10/100) - mgtx_clk_o : out std_logic; - mrstn_o : out std_logic; - - -- PHY TX - mtx_clk_pad_i : in std_logic; - mtxd_pad_o : out std_logic_vector(3 downto 0); - mtxen_pad_o : out std_logic; - mtxerr_pad_o : out std_logic; - - -- PHY RX - mrx_clk_pad_i : in std_logic; - mrxd_pad_i : in std_logic_vector(3 downto 0); - mrxdv_pad_i : in std_logic; - mrxerr_pad_i : in std_logic; - mcoll_pad_i : in std_logic; - mcrs_pad_i : in std_logic; - - -- MII - mdc_pad_o : out std_logic; - md_pad_b : inout std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - leds_o : out std_logic_vector(7 downto 0) -); -end dbe_bpm_ebone; - -architecture rtl of dbe_bpm_ebone is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 10; -- LED, Button, - -- General Dual-port memory, Buffer Single-por memory, UART, DMA control port, MAC, - --Etherbone - -- Number of masters - constant c_masters : natural := 8; -- LM32 master, Data + Instruction, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone - - constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB) - --constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB) - constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB) - - -- GPIO num pinscalc - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - constant c_xwb_etherbone_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"0000000000000651", -- GSI - device_id => x"68202b22", - version => x"00000001", - date => x"20120912", - name => "GSI_ETHERBONE_CFG "))); - - constant c_xwb_ethmac_adapter_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"1000000000001215", -- LNLS - device_id => x"2ff9a28e", - version => x"00000001", - date => x"20130701", - name => "ETHMAC_ADAPTER "))); - - -- WB SDB (Self describing bus) layout - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory - 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - x"20000000"), -- 64KB RAM - --3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30014000"), -- DMA control port - --4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30015000"), -- Ethernet MAC control port - --5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30016000"), -- Ethernet Adapter control port - --6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30017000"), -- Etherbone control port - --7 => f_sdb_embed_device(c_xwb_uart_sdb, x"30018000"), -- UART control port - --8 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"30019000"), -- GPIO LED - --9 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"3001A000") -- GPIO Button - 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"60000000"), -- DMA control port - 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"70000000"), -- Ethernet MAC control port - 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"80000000"), -- Ethernet Adapter control port - 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"90000000"), -- Etherbone control port - 7 => f_sdb_embed_device(c_xwb_uart_sdb, x"A0000000"), -- UART control port - 8 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"B0000000"), -- GPIO LED - 9 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"C0000000") -- GPIO Button - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well - constant c_sdb_address : t_wishbone_address := x"30000000"; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - -- Only one clock domain - signal reset_clks : std_logic_vector(0 downto 0); - signal reset_rstn : std_logic_vector(0 downto 0); - - -- 200 Mhz clocck for iodelay_ctrl - signal clk_200mhz : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - - -- Ethernet MAC signals - signal ethmac_int : std_logic; - signal ethmac_md_in : std_logic; - signal ethmac_md_out : std_logic; - signal ethmac_md_oe : std_logic; - - signal mtxd_pad_int : std_logic_vector(3 downto 0); - signal mtxen_pad_int : std_logic; - signal mtxerr_pad_int : std_logic; - signal mdc_pad_int : std_logic; - - - -- Ethrnet MAC adapter signals - signal irq_rx_done : std_logic; - signal irq_tx_done : std_logic; - - -- Etherbone signals - signal wb_ebone_out : t_wishbone_master_out; - signal wb_ebone_in : t_wishbone_master_in; - - signal eb_src_i : t_wrf_source_in; - signal eb_src_o : t_wrf_source_out; - signal eb_snk_i : t_wrf_sink_in; - signal eb_snk_o : t_wrf_sink_out; - - -- DMA signals - signal dma_int : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - -- Counter signal - signal s_counter : unsigned(c_counter_width-1 downto 0); - -- 100MHz period or 1 second - constant s_counter_full : integer := 100000000; - - -- Chipscope control signals - signal CONTROL0 : std_logic_vector(35 downto 0); - signal CONTROL1 : std_logic_vector(35 downto 0); - signal CONTROL2 : std_logic_vector(35 downto 0); - signal CONTROL3 : std_logic_vector(35 downto 0); - - -- Chipscope ILA 0 signals - signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 1 signals - signal TRIG_ILA1_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 2 signals - signal TRIG_ILA2_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 3 signals - signal TRIG_ILA3_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_3 : std_logic_vector(31 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic - ); - end component; - - -- Xilinx Megafunction - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Controller 2 port - --component chipscope_icon_2_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0) - --); - --end component; - - component chipscope_icon_4_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0); - CONTROL2 : inout std_logic_vector(35 downto 0); - CONTROL3 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; - -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - clk_i => sys_clk_gen, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => 1 -- CLK_SYS - ) - port map( - free_clk_i => sys_clk_gen, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(0) <= clk_sys; - clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n; - clk_sys_rst <= not clk_sys_rstn; - mrstn_o <= clk_sys_rstn; - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => false, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - lm32_rstn <= clk_sys_rstn; - - cmp_lm32 : xwb_lm32 - generic map( - g_profile => "medium_icache_debug" - ) -- Including JTAG and I-cache (no divide) - port map( - clk_sys_i => clk_sys, - rst_n_i => lm32_rstn, - irq_i => lm32_interrupt, - dwb_o => cbar_slave_i(0), -- Data bus - dwb_i => cbar_slave_o(0), - iwb_o => cbar_slave_i(1), -- Instruction bus - iwb_i => cbar_slave_o(1) - ); - - -- Interrupt '0' is Ethmac. - -- Interrupt '1' is DMA completion. - -- Interrupt '2' is Button(0). - -- Interrupt '3' is Ethernet Adapter RX completion. - -- Interrupt '4' is Ethernet Adapter TX completion. - -- Interrupts 31 downto 5 are disabled - - lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done, - 4 => irq_tx_done, others => '0'); - - -- A DMA controller is master 2+3, slave 3, and interrupt 1 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(3), - slave_o => cbar_master_i(3), - r_master_i => cbar_slave_o(2), - r_master_o => cbar_slave_i(2), - w_master_i => cbar_slave_o(3), - w_master_o => cbar_slave_i(3), - interrupt_o => dma_int - ); - - -- Slave 0+1 is the RAM. Load a input file containing the embedded software - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - g_init_file => "../../../embedded-sw/dbe.ram", - --"../../top/ml_605/dbe_bpm_simple/sw/main.ram", - g_must_have_init_file => true, - g_slave1_interface_mode => PIPELINED, - g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE, - g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - ); - - -- Slave 2 is the RAM Buffer for Ethernet MAC. - cmp_ethmac_buf_ram : xwb_dpram - generic map( - g_size => c_dpram_ethbuf_size, - g_init_file => "", - g_must_have_init_file => false, - g_slave1_interface_mode => CLASSIC, - --g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE - --g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(2), - slave1_o => cbar_master_i(2), - -- Second port connected to the crossbar - slave2_i => cc_dummy_slave_in, -- CYC always low - slave2_o => open - ); - - -- The Ethernet MAC is master 4, slave 4 - cmp_xwb_ethmac : xwb_ethmac - generic map ( - --g_ma_interface_mode => PIPELINED, - g_ma_interface_mode => CLASSIC, -- NOT used for now - --g_ma_address_granularity => WORD, - g_ma_address_granularity => BYTE, -- NOT used for now - g_sl_interface_mode => PIPELINED, - --g_sl_interface_mode => CLASSIC, - --g_sl_address_granularity => WORD - g_sl_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - - -- WISHBONE slave - wb_slave_in => cbar_master_o(4), - wb_slave_out => cbar_master_i(4), - - -- WISHBONE master - wb_master_in => cbar_slave_o(4), - wb_master_out => cbar_slave_i(4), - - -- PHY TX - mtx_clk_pad_i => mtx_clk_pad_i, - --mtxd_pad_o => mtxd_pad_o, - mtxd_pad_o => mtxd_pad_int, - --mtxen_pad_o => mtxen_pad_o, - mtxen_pad_o => mtxen_pad_int, - --mtxerr_pad_o => mtxerr_pad_o, - mtxerr_pad_o => mtxerr_pad_int, - - -- PHY RX - mrx_clk_pad_i => mrx_clk_pad_i, - mrxd_pad_i => mrxd_pad_i, - mrxdv_pad_i => mrxdv_pad_i, - mrxerr_pad_i => mrxerr_pad_i, - mcoll_pad_i => mcoll_pad_i, - mcrs_pad_i => mcrs_pad_i, - - -- MII - --mdc_pad_o => mdc_pad_o, - mdc_pad_o => mdc_pad_int, - md_pad_i => ethmac_md_in, - md_pad_o => ethmac_md_out, - md_padoe_o => ethmac_md_oe, - - -- Interrupt - int_o => ethmac_int - ); - - -- Tri-state buffer for MII config - md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z'; - ethmac_md_in <= md_pad_b; - - mtxd_pad_o <= mtxd_pad_int; - mtxen_pad_o <= mtxen_pad_int; - mtxerr_pad_o <= mtxerr_pad_int; - mdc_pad_o <= mdc_pad_int; - - -- The Ethernet MAC Adapter is master 5+6, slave 5 - cmp_xwb_ethmac_adapter : xwb_ethmac_adapter - port map( - clk_i => clk_sys, - rstn_i => clk_sys_rstn, - - wb_slave_o => cbar_master_i(5), - wb_slave_i => cbar_master_o(5), - - tx_ram_o => cbar_slave_i(5), - tx_ram_i => cbar_slave_o(5), - - rx_ram_o => cbar_slave_i(6), - rx_ram_i => cbar_slave_o(6), - - rx_eb_o => eb_snk_i, - rx_eb_i => eb_snk_o, - - tx_eb_o => eb_src_i, - tx_eb_i => eb_src_o, - - irq_tx_done_o => irq_tx_done, - irq_rx_done_o => irq_rx_done - ); - - -- The Etherbone is slave 6 - cmp_eb_slave_core : eb_slave_core - generic map( - g_sdb_address => x"00000000" & c_sdb_address - ) - port map - ( - clk_i => clk_sys, - nRst_i => clk_sys_rstn, - - -- EB streaming sink - snk_i => eb_snk_i, - snk_o => eb_snk_o, - - -- EB streaming source - src_i => eb_src_i, - src_o => eb_src_o, - - -- WB slave - Cfg IF - cfg_slave_o => cbar_master_i(6), - cfg_slave_i => cbar_master_o(6), - - -- WB master - Bus IF - master_o => wb_ebone_out, - master_i => wb_ebone_in - ); - - cbar_slave_i(7) <= wb_ebone_out; - wb_ebone_in <= cbar_slave_o(7); - - -- Slave 7 is the UART - cmp_uart : xwb_simple_uart - generic map ( - g_interface_mode => PIPELINED, - g_address_granularity => BYTE - ) - port map ( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(7), - slave_o => cbar_master_i(7), - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o - ); - - -- Slave 8 is the LED driver - cmp_leds : xwb_gpio_port - generic map( - g_interface_mode => CLASSIC, - g_address_granularity => BYTE, - g_num_pins => c_leds_num_pins, - g_with_builtin_tristates => false - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- Wishbone - slave_i => cbar_master_o(8), - slave_o => cbar_master_i(8), - desc_o => open, -- Not implemented - - --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0); - - gpio_out_o => gpio_leds_int, - gpio_in_i => gpio_leds_int, - gpio_oen_o => open - ); - - leds_o <= gpio_leds_int; - - -- Slave 9 is the Button driver - cmp_buttons : xwb_gpio_port - generic map( - g_interface_mode => CLASSIC, - g_address_granularity => BYTE, - g_num_pins => c_buttons_num_pins, - g_with_builtin_tristates => false - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- Wishbone - slave_i => cbar_master_o(9), - slave_o => cbar_master_i(9), - desc_o => open, -- Not implemented - - --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0); - - gpio_out_o => open, - gpio_in_i => buttons_i, - gpio_oen_o => open - ); - - ---- Xilinx Chipscope - cmp_chipscope_icon_0 : chipscope_icon_4_port - port map ( - CONTROL0 => CONTROL0, - CONTROL1 => CONTROL1, - CONTROL2 => CONTROL2, - CONTROL3 => CONTROL3 - ); - - cmp_chipscope_ila_0_ethmac : chipscope_ila - port map ( - CONTROL => CONTROL0, - CLK => clk_sys, - TRIG0 => TRIG_ILA0_0, - TRIG1 => TRIG_ILA0_1, - TRIG2 => TRIG_ILA0_2, - TRIG3 => TRIG_ILA0_3 - ); - - -- ETHMAC master output (slave input) control data - TRIG_ILA0_0 <= cbar_slave_o(4).dat; - -- ETHMAC master input (slave output) control data - TRIG_ILA0_1 <= cbar_slave_i(4).dat; - - -- ETHMAC master control input (slave output) control signals - TRIG_ILA0_2(4 downto 0) <= cbar_slave_o(4).ack & - cbar_slave_o(4).err & - cbar_slave_o(4).rty & - cbar_slave_o(4).stall & - cbar_slave_o(4).int; - TRIG_ILA0_2(31 downto 5) <= (others => '0'); - - -- ETHMAC master control output (slave input) control signals - -- Partial decoding. Thus, only the LSB part of address matters to - -- a specific slave core - TRIG_ILA0_3(18 downto 0) <= cbar_slave_i(4).cyc & - cbar_slave_i(4).stb & - cbar_slave_i(4).adr(11 downto 0) & - cbar_slave_i(4).sel & - cbar_slave_i(4).we; - TRIG_ILA0_3(31 downto 19) <= (others => '0'); - - -- Etherbone debuging signals - --cmp_chipscope_ila_1_etherbone : chipscope_ila - --port map ( - -- CONTROL => CONTROL1, - -- CLK => clk_sys, - -- TRIG0 => TRIG_ILA1_0, - -- TRIG1 => TRIG_ILA1_1, - -- TRIG2 => TRIG_ILA1_2, - -- TRIG3 => TRIG_ILA1_3 - --); - - --TRIG_ILA1_0 <= wb_ebone_out.dat; - --TRIG_ILA1_1 <= wb_ebone_in.dat; - --TRIG_ILA1_2 <= wb_ebone_out.adr; - --TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc & - -- wb_ebone_out.stb & - -- wb_ebone_out.sel & - -- wb_ebone_out.we; - --TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack & - -- wb_ebone_in.err & - -- wb_ebone_in.rty & - -- wb_ebone_in.stall & - -- wb_ebone_in.int; - --TRIG_ILA1_3(31 downto 12) <= (others => '0'); - - cmp_chipscope_ila_1_ethmac_rx : chipscope_ila - port map ( - CONTROL => CONTROL1, - CLK => mrx_clk_pad_i, - TRIG0 => TRIG_ILA1_0, - TRIG1 => TRIG_ILA1_1, - TRIG2 => TRIG_ILA1_2, - TRIG3 => TRIG_ILA1_3 - ); - - TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i & - mrxdv_pad_i & - mrxerr_pad_i & - mcoll_pad_i & - mcrs_pad_i; - - TRIG_ILA1_0(31 downto 8) <= (others => '0'); - TRIG_ILA1_1 <= (others => '0'); - TRIG_ILA1_2 <= (others => '0'); - TRIG_ILA1_3 <= (others => '0'); - - cmp_chipscope_ila_1_ethmac_tx : chipscope_ila - port map ( - CONTROL => CONTROL2, - CLK => mtx_clk_pad_i, - TRIG0 => TRIG_ILA2_0, - TRIG1 => TRIG_ILA2_1, - TRIG2 => TRIG_ILA2_2, - TRIG3 => TRIG_ILA2_3 - ); - - TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int & - mtxen_pad_int & - mtxerr_pad_int; - - TRIG_ILA2_0(31 downto 6) <= (others => '0'); - TRIG_ILA2_1 <= (others => '0'); - TRIG_ILA2_2 <= (others => '0'); - TRIG_ILA2_3 <= (others => '0'); - - cmp_chipscope_ila_1_ethmac_miim : chipscope_ila - port map ( - CONTROL => CONTROL3, - CLK => clk_sys, - TRIG0 => TRIG_ILA3_0, - TRIG1 => TRIG_ILA3_1, - TRIG2 => TRIG_ILA3_2, - TRIG3 => TRIG_ILA3_3 - ); - - TRIG_ILA3_0(4 downto 0) <= mdc_pad_int & - ethmac_md_in & - ethmac_md_out & - ethmac_md_oe & - ethmac_int; - - TRIG_ILA3_0(31 downto 6) <= (others => '0'); - TRIG_ILA3_1 <= (others => '0'); - TRIG_ILA3_2 <= (others => '0'); - TRIG_ILA3_3 <= (others => '0'); - -end rtl; diff --git a/hdl/top/ml_605/dbe_bpm_ebone/make_output b/hdl/top/ml_605/dbe_bpm_ebone/make_output deleted file mode 100644 index 4a310889..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/make_output +++ /dev/null @@ -1,3 +0,0 @@ -echo "project open None" > run.tcl -echo "process run {Generate Programming File} -force rerun_all" >> run.tcl -xtclsh run.tcl diff --git a/hdl/top/ml_605/dbe_bpm_ebone/run.tcl b/hdl/top/ml_605/dbe_bpm_ebone/run.tcl deleted file mode 100644 index 0c259581..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/run.tcl +++ /dev/null @@ -1,2 +0,0 @@ -project open None -process run {Generate Programming File} -force rerun_all diff --git a/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd deleted file mode 100644 index 036e6b5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/Manifest.py b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/Manifest.py deleted file mode 100644 index 36a306e2..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/Manifest.py +++ /dev/null @@ -1,3 +0,0 @@ -files = [ "dbe_bpm_fmc130m_4ch.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_bpm_fmc130m_4ch.ucf" ]; - -modules = { "local" : ["../../.." ] }; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/clk_gen.vhd deleted file mode 100644 index 21542e5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/clk_gen.vhd +++ /dev/null @@ -1,47 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.ucf b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.ucf deleted file mode 100644 index f2b0a77d..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.ucf +++ /dev/null @@ -1,297 +0,0 @@ -#-------------------------------- -# Virtex6 Board ML605 -#-------------------------------- - -NET "sys_clk_n_i" LOC = H9 | IOSTANDARD = LVDS_25; # 5 on U11, 5 on U89 (DNP) -NET "sys_clk_p_i" LOC = J9 | IOSTANDARD = LVDS_25; # 4 on U11, 4 on U89 (DNP) - -NET "rs232_rxd_i" LOC = J24 | IOSTANDARD = LVCMOS25; # 25 on U34 -NET "rs232_txd_o" LOC = J25 | IOSTANDARD = LVCMOS25; # 24 on U34 - -NET "sys_rst_button_i" LOC = H10 | IOSTANDARD = "SSTL15" | TIG; - -# MMCM Status -NET "fmc_mmcm_lock_led_o" LOC = "AP24" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_C, DS16 - -# LMK clock distribution Status -NET "fmc_pll_status_led_o" LOC = "AD21" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_W, DS17 - -#NET "led_south_o" LOC = "AH28" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_S, DS18 -#NET "led_east_o" LOC = "AE21" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_E, DS19 -#NET "led_north_o" LOC = "AH27" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_N, DS20 - -#NET "board_led1_o" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 0 -#NET "board_led2_o" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 1 -#NET "board_led3_o" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 2 - -#-------------------------------- -# Button/LEDs Contraints -#-------------------------------- - -NET "buttons_i[0]" LOC = D22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[1]" LOC = C22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[2]" LOC = L21 | IOSTANDARD = LVCMOS25; -NET "buttons_i[3]" LOC = L20 | IOSTANDARD = LVCMOS25; -NET "buttons_i[4]" LOC = C18 | IOSTANDARD = LVCMOS25; -NET "buttons_i[5]" LOC = B18 | IOSTANDARD = LVCMOS25; -NET "buttons_i[6]" LOC = K22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[7]" LOC = K21 | IOSTANDARD = LVCMOS25; -NET "leds_o[0]" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[1]" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[2]" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[3]" LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[4]" LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[5]" LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[6]" LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[7]" LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; - -#-------------------------------- -# FMC Connector HPC -#-------------------------------- - -NET "fmc_prsnt_i" LOC = AP25 | IOSTANDARD = "LVCMOS25"; -NET "fmc_pg_m2c_i" LOC = AK29 | IOSTANDARD = "LVCMOS25"; // LA31_N - -// Trigger -NET "fmc_trig_dir_o" LOC = AK27 | IOSTANDARD = "LVCMOS25"; // LA28_P -NET "fmc_trig_term_o" LOC = AL25 | IOSTANDARD = "LVCMOS25"; // LA26_N -NET "fmc_trig_val_p_b" LOC = AG25 | IOSTANDARD = "BLVDS_25"; // LA32_P -NET "fmc_trig_val_n_b" LOC = AG26 | IOSTANDARD = "BLVDS_25"; // LA32_N - -// Si571 clock gen -NET "si571_scl_pad_b" LOC = AE32 | IOSTANDARD = "LVCMOS25"; // HA12_N -NET "si571_sda_pad_b" LOC = AE31 | IOSTANDARD = "LVCMOS25"; // HA13_P -NET "fmc_si571_oe_o" LOC = AD32 | IOSTANDARD = "LVCMOS25"; // HA12_P - -// AD9510 clock distribution PLL -NET "spi_ad9510_cs_o" LOC = AN18 | IOSTANDARD = "LVCMOS25"; // LA13_N -NET "spi_ad9510_sclk_o" LOC = AP19 | IOSTANDARD = "LVCMOS25"; // LA13_P -NET "spi_ad9510_mosi_o" LOC = AL18 | IOSTANDARD = "LVCMOS25"; // LA09_N -NET "spi_ad9510_miso_i" LOC = AN19 | IOSTANDARD = "LVCMOS25"; // LA14_P -NET "fmc_pll_function_o" LOC = AN20 | IOSTANDARD = "LVCMOS25"; // LA14_N -NET "fmc_pll_status_i" LOC = AM18 | IOSTANDARD = "LVCMOS25"; // LA09_P - -#NET "fmc_fpga_clk_p_i" LOC = K24 | IOSTANDARD = "LVDS_25"; // CLK0_M2C_P -#NET "fmc_fpga_clk_n_i" LOC = K23 | IOSTANDARD = "LVDS_25"; // CLK0_M2C_N - -// Clock reference selection (TS3USB221) -NET "fmc_clk_sel_o" LOC = AL29 | IOSTANDARD = "LVCMOS25"; // LA31_P - -// EEPROM (multiplexer PCA9548) -NET "eeprom_scl_pad_b" LOC = AK9 | IOSTANDARD ="LVCMOS25"; # SCL C30 -NET "eeprom_sda_pad_b" LOC = AE9 | IOSTANDARD ="LVCMOS25"; # SDA C31 - -// LM75 temperature monitor (can be used without multiplexer on KC705 board) -NET "lm75_scl_pad_b" LOC = AP30 | IOSTANDARD = "LVCMOS25"; // LA27_P -NET "lm75_sda_pad_b" LOC = AP31 | IOSTANDARD = "LVCMOS25"; // LA27_N -NET "fmc_lm75_temp_alarm_i" LOC = AJ27 | IOSTANDARD = "LVCMOS25"; // LA28_N - -// LTC ADC control pins -NET "fmc_adc_pga_o" LOC = AG20 | IOSTANDARD = "LVCMOS25"; // LA06_P -NET "fmc_adc_shdn_o" LOC = AL20 | IOSTANDARD = "LVCMOS25"; // LA10_N -NET "fmc_adc_dith_o" LOC = AM20 | IOSTANDARD = "LVCMOS25"; // LA10_P -NET "fmc_adc_rand_o" LOC = AG21 | IOSTANDARD = "LVCMOS25"; // LA06_N - -// LEDs -NET "fmc_led1_o" LOC = AN23 | IOSTANDARD = "LVCMOS25"; // LA16_N -NET "fmc_led2_o" LOC = AP22 | IOSTANDARD = "LVCMOS25"; // LA16_P -NET "fmc_led3_o" LOC = AM25 | IOSTANDARD = "LVCMOS25"; // LA26_P - -#-------------------------------- -# FMC Connector HPC -# LTC ADC lines -#-------------------------------- - -// ADC0 -NET "fmc_adc0_clk_i" LOC = AN27 | IOSTANDARD = "LVCMOS25"; // LA17_CC_P - -NET "fmc_adc0_data_i[0]" LOC = AN30 | IOSTANDARD = "LVCMOS25"; // LA24_P -NET "fmc_adc0_data_i[1]" LOC = AM30 | IOSTANDARD = "LVCMOS25"; // LA24_N -NET "fmc_adc0_data_i[2]" LOC = AN28 | IOSTANDARD = "LVCMOS25"; // LA25_P -NET "fmc_adc0_data_i[3]" LOC = AM28 | IOSTANDARD = "LVCMOS25"; // LA25_N -NET "fmc_adc0_data_i[4]" LOC = AN29 | IOSTANDARD = "LVCMOS25"; // LA21_P -NET "fmc_adc0_data_i[5]" LOC = AP29 | IOSTANDARD = "LVCMOS25"; // LA21_N -NET "fmc_adc0_data_i[6]" LOC = AP27 | IOSTANDARD = "LVCMOS25"; // LA22_P -NET "fmc_adc0_data_i[7]" LOC = AP26 | IOSTANDARD = "LVCMOS25"; // LA22_N -NET "fmc_adc0_data_i[8]" LOC = AM26 | IOSTANDARD = "LVCMOS25"; // LA23_N -NET "fmc_adc0_data_i[9]" LOC = AN24 | IOSTANDARD = "LVCMOS25"; // LA19_N -NET "fmc_adc0_data_i[10]" LOC = AJ25 | IOSTANDARD = "LVCMOS25"; // LA18_CC_N -NET "fmc_adc0_data_i[11]" LOC = AL26 | IOSTANDARD = "LVCMOS25"; // LA23_P -NET "fmc_adc0_data_i[12]" LOC = AL24 | IOSTANDARD = "LVCMOS25"; // LA20_N -NET "fmc_adc0_data_i[13]" LOC = AN25 | IOSTANDARD = "LVCMOS25"; // LA19_P -NET "fmc_adc0_data_i[14]" LOC = AH25 | IOSTANDARD = "LVCMOS25"; // LA18_CC_P -NET "fmc_adc0_data_i[15]" LOC = AK23 | IOSTANDARD = "LVCMOS25"; // LA20_P -NET "fmc_adc0_of_i" LOC = AL28 | IOSTANDARD = "LVCMOS25"; // LA29_P - -// ADC1 -NET "fmc_adc1_clk_i" LOC = V30 | IOSTANDARD = "LVCMOS25"; // HA17_CC_P - -NET "fmc_adc1_data_i[15]" LOC = AD34 | IOSTANDARD = "LVCMOS25"; // HA10_P -NET "fmc_adc1_data_i[14]" LOC = AG33 | IOSTANDARD = "LVCMOS25"; // HA11_P -NET "fmc_adc1_data_i[13]" LOC = AC34 | IOSTANDARD = "LVCMOS25"; // HA10_N -NET "fmc_adc1_data_i[12]" LOC = AG32 | IOSTANDARD = "LVCMOS25"; // HA11_N -NET "fmc_adc1_data_i[11]" LOC = AB32 | IOSTANDARD = "LVCMOS25"; // HA15_P -NET "fmc_adc1_data_i[10]" LOC = AA30 | IOSTANDARD = "LVCMOS25"; // HA14_P -NET "fmc_adc1_data_i[9]" LOC = AC32 | IOSTANDARD = "LVCMOS25"; // HA15_N -NET "fmc_adc1_data_i[8]" LOC = AA31 | IOSTANDARD = "LVCMOS25"; // HA14_N -NET "fmc_adc1_data_i[7]" LOC = T34 | IOSTANDARD = "LVCMOS25"; // HA18_N -NET "fmc_adc1_data_i[6]" LOC = T33 | IOSTANDARD = "LVCMOS25"; // HA18_P -NET "fmc_adc1_data_i[5]" LOC = U32 | IOSTANDARD = "LVCMOS25"; // HA19_N -NET "fmc_adc1_data_i[4]" LOC = U31 | IOSTANDARD = "LVCMOS25"; // HA21_P -NET "fmc_adc1_data_i[3]" LOC = U28 | IOSTANDARD = "LVCMOS25"; // HA22_P -NET "fmc_adc1_data_i[2]" LOC = U30 | IOSTANDARD = "LVCMOS25"; // HA21_N -NET "fmc_adc1_data_i[1]" LOC = U26 | IOSTANDARD = "LVCMOS25"; // HA23_P -NET "fmc_adc1_data_i[0]" LOC = V29 | IOSTANDARD = "LVCMOS25"; // HA22_N -NET "fmc_adc1_of_i" LOC = U27 | IOSTANDARD = "LVCMOS25"; // HA23_N - -// ADC2 -NET "fmc_adc2_clk_i" LOC = AF20 | IOSTANDARD = "LVCMOS25"; // LA00_CC_P - -NET "fmc_adc2_data_i[15]" LOC = AK19 | IOSTANDARD = "LVCMOS25"; // LA01_CC_P -NET "fmc_adc2_data_i[14]" LOC = AC20 | IOSTANDARD = "LVCMOS25"; // LA02_P -NET "fmc_adc2_data_i[13]" LOC = AL19 | IOSTANDARD = "LVCMOS25"; // LA01_CC_N -NET "fmc_adc2_data_i[12]" LOC = AD20 | IOSTANDARD = "LVCMOS25"; // LA02_N -NET "fmc_adc2_data_i[11]" LOC = AD19 | IOSTANDARD = "LVCMOS25"; // LA03_N -NET "fmc_adc2_data_i[10]" LOC = AC19 | IOSTANDARD = "LVCMOS25"; // LA03_P -NET "fmc_adc2_data_i[9]" LOC = AE19 | IOSTANDARD = "LVCMOS25"; // LA04_N -NET "fmc_adc2_data_i[8]" LOC = AF19 | IOSTANDARD = "LVCMOS25"; // LA04_P -NET "fmc_adc2_data_i[7]" LOC = AH22 | IOSTANDARD = "LVCMOS25"; // LA05_N -NET "fmc_adc2_data_i[6]" LOC = AG22 | IOSTANDARD = "LVCMOS25"; // LA05_P -NET "fmc_adc2_data_i[5]" LOC = AJ22 | IOSTANDARD = "LVCMOS25"; // LA08_N -NET "fmc_adc2_data_i[4]" LOC = AK22 | IOSTANDARD = "LVCMOS25"; // LA08_P -NET "fmc_adc2_data_i[3]" LOC = AJ21 | IOSTANDARD = "LVCMOS25"; // LA07_N -NET "fmc_adc2_data_i[2]" LOC = AK21 | IOSTANDARD = "LVCMOS25"; // LA07_P -NET "fmc_adc2_data_i[1]" LOC = AL21 | IOSTANDARD = "LVCMOS25"; // LA12_N -NET "fmc_adc2_data_i[0]" LOC = AM21 | IOSTANDARD = "LVCMOS25"; // LA12_P -NET "fmc_adc2_of_i" LOC = AM22 | IOSTANDARD = "LVCMOS25"; // LA11_P - -// ADC3 -NET "fmc_adc3_clk_i" LOC = AD29 | IOSTANDARD = "LVCMOS25"; // HA01_CC_P - -NET "fmc_adc3_data_i[15]" LOC = AF33 | IOSTANDARD = "LVCMOS25"; // HA00_CC_N -NET "fmc_adc3_data_i[14]" LOC = AE33 | IOSTANDARD = "LVCMOS25"; // HA00_CC_P -NET "fmc_adc3_data_i[13]" LOC = AC27 | IOSTANDARD = "LVCMOS25"; // HA05_N -NET "fmc_adc3_data_i[12]" LOC = AB27 | IOSTANDARD = "LVCMOS25"; // HA05_P -NET "fmc_adc3_data_i[11]" LOC = AC28 | IOSTANDARD = "LVCMOS25"; // HA04_N -NET "fmc_adc3_data_i[10]" LOC = AB28 | IOSTANDARD = "LVCMOS25"; // HA04_P -NET "fmc_adc3_data_i[9]" LOC = AB31 | IOSTANDARD = "LVCMOS25"; // HA09_N -NET "fmc_adc3_data_i[8]" LOC = AB30 | IOSTANDARD = "LVCMOS25"; // HA09_P -NET "fmc_adc3_data_i[7]" LOC = Y26 | IOSTANDARD = "LVCMOS25"; // HA03_N -NET "fmc_adc3_data_i[6]" LOC = AA25 | IOSTANDARD = "LVCMOS25"; // HA03_P -NET "fmc_adc3_data_i[5]" LOC = AG31 | IOSTANDARD = "LVCMOS25"; // HA08_P -NET "fmc_adc3_data_i[4]" LOC = AB25 | IOSTANDARD = "LVCMOS25"; // HA02_P -NET "fmc_adc3_data_i[3]" LOC = AA26 | IOSTANDARD = "LVCMOS25"; // HA07_P -NET "fmc_adc3_data_i[2]" LOC = AC25 | IOSTANDARD = "LVCMOS25"; // HA02_N -NET "fmc_adc3_data_i[1]" LOC = AA28 | IOSTANDARD = "LVCMOS25"; // HA06_P -NET "fmc_adc3_data_i[0]" LOC = AB26 | IOSTANDARD = "LVCMOS25"; // HA07_N -NET "fmc_adc3_of_i" LOC = AA29 | IOSTANDARD = "LVCMOS25"; // HA06_N - -#-------------------------------- -# Ethernet Contraints. -# MII 10/100 Mode -#-------------------------------- - -NET "mrstn_o" LOC = AH13; -NET "mcoll_pad_i" LOC = AK13; ## 114 on U80 -NET "mcrs_pad_i" LOC = AL13; ## 115 on U80 -# NET "PHY_INT" LOC = AH14; ## 32 on U80 -NET "mdc_pad_o" LOC = AP14; ## 35 on U80 -NET "md_pad_b" LOC = AN14; ## 33 on U80 -# NET "PHY_RESET" LOC = AH13; ## 36 on U80 -NET "mrx_clk_pad_i" LOC = AP11; ## 7 on U80 -NET "mrxdv_pad_i" LOC = AM13; ## 4 on U80 -NET "mrxd_pad_i[0]" LOC = AN13; ## 3 on U80 -NET "mrxd_pad_i[1]" LOC = AF14; ## 128 on U80 -NET "mrxd_pad_i[2]" LOC = AE14; ## 126 on U80 -NET "mrxd_pad_i[3]" LOC = AN12; ## 125 on U80 -# NET "PHY_RXD4" LOC = AM12; ## 124 on U80 -# NET "PHY_RXD5" LOC = AD11; ## 123 on U80 -# NET "PHY_RXD6" LOC = AC12; ## 121 on U80 -# NET "PHY_RXD7" LOC = AC13; ## 120 on U80 -NET "mrxerr_pad_i" LOC = AG12; ## 9 on U80 -NET "mtx_clk_pad_i" LOC = AD12; ## 10 on U80 -NET "mtxen_pad_o" LOC = AJ10; ## 16 on U80 -# NET "PHY_TXC_GTXCLK" LOC = AH12; ## 14 on U80 -NET "mtxd_pad_o[0]" LOC = AM11; ## 18 on U80 -NET "mtxd_pad_o[1]" LOC = AL11; ## 19 on U80 -NET "mtxd_pad_o[2]" LOC = AG10; ## 20 on U80 -NET "mtxd_pad_o[3]" LOC = AG11; ## 24 on U80 -# NET "PHY_TXD4" LOC = AL10; ## 25 on U80 -# NET "PHY_TXD5" LOC = AM10; ## 26 on U80 -# NET "PHY_TXD6" LOC = AE11; ## 28 on U80 -# NET "PHY_TXD7" LOC = AF11; ## 29 on U80 -NET "mtxerr_pad_o" LOC = AH10; ## 13 on U80 - -#-------------------------------- -# Pinout and Related I/O Constraints -#-------------------------------- - -# On ML605 kit, all clock pins are assigned to MRCC pins. However, two of them -# (fmc_adc1_clk and fmc_adc3_clk) are located in the outer left/right column -# I/Os. These locations cannot connect to BUFG primitives, only inner (center) -# left/right column I/Os on the same half top/bottom can! -# -# For 7-series FPGAs there is no such impediment, apparently. - -#-------------------------------- -# DIFF TERM -#-------------------------------- -NET "sys_clk_p_i" DIFF_TERM = TRUE; -NET "sys_clk_n_i" DIFF_TERM = TRUE; - -NET "fmc_trig_val_p_b" DIFF_TERM = TRUE; -NET "fmc_trig_val_n_b" DIFF_TERM = TRUE; - -#NET "fmc_fpga_clk_p_i" DIFF_TERM = TRUE; -#NET "fmc_fpga_clk_n_i" DIFF_TERM = TRUE; - -#-------------------------------- -# Timing constraints -#-------------------------------- -#-------------------------------- -# Clocks -#-------------------------------- -NET "sys_clk_p_i" TNM_NET = sys_clk_p_i; -TIMESPEC TS_sys_clk_p_i = PERIOD "sys_clk_p_i" 200 MHz HIGH 50% INPUT_JITTER 50 ps; - -// real jitter is about 22ps peak-to-peak -NET "fmc_adc0_clk_i" TNM_NET = fmc_adc0_clk_i; -// TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc1_clk_i" TNM_NET = fmc_adc1_clk_i; -// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc2_clk_i" TNM_NET = fmc_adc2_clk_i; -// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc3_clk_i" TNM_NET = fmc_adc3_clk_i; -// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps; - -//NET "fmc_fpga_clk_p" TNM_NET = fmc_fpga_clk_p; -//TIMESPEC TS_fmc_fpga_clk_p = PERIOD "fmc_fpga_clk_p" 130 MHz HIGH 50% INPUT_JITTER 40 ps; - -#-------------------------------- -# Data -#-------------------------------- -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc0_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc1_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y2; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc2_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y0; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc3_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; // same as ADC1 - -// including 50ps jitter, for 130MHz clock -// since design uses copy of input ADC clock -// there is additional delay for clock/ data (tC) - -INST "fmc_adc0_data_i<*>" TNM = fmc_adc0_data_i; -INST "fmc_adc1_data_i<*>" TNM = fmc_adc1_data_i; -INST "fmc_adc2_data_i<*>" TNM = fmc_adc2_data_i; -INST "fmc_adc3_data_i<*>" TNM = fmc_adc3_data_i; - -TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc0_clk_i"; -TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc1_clk_i"; -TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc2_clk_i"; -TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc3_clk_i"; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd deleted file mode 100755 index b010cc72..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd +++ /dev/null @@ -1,1243 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top FMC516 design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2013-02-25 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control of the FMC516 -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2013-02-25 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_generic_pkg.all; --- Ethernet MAC Modules and SDB structure -use work.ethmac_pkg.all; --- Wishbone Fabric interface -use work.wr_fabric_pkg.all; --- Etherbone slave core -use work.etherbone_pkg.all; --- FMC516 definitions -use work.fmc_adc_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_fmc130m_4ch is -port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - rs232_txd_o : out std_logic; - rs232_rxd_i : in std_logic; - - ----------------------------------------- - -- PHY pins - ----------------------------------------- - - -- Clock and resets to PHY (GMII). Not used in MII mode (10/100) - mgtx_clk_o : out std_logic; - mrstn_o : out std_logic; - - -- PHY TX - mtx_clk_pad_i : in std_logic; - mtxd_pad_o : out std_logic_vector(3 downto 0); - mtxen_pad_o : out std_logic; - mtxerr_pad_o : out std_logic; - - -- PHY RX - mrx_clk_pad_i : in std_logic; - mrxd_pad_i : in std_logic_vector(3 downto 0); - mrxdv_pad_i : in std_logic; - mrxerr_pad_i : in std_logic; - mcoll_pad_i : in std_logic; - mcrs_pad_i : in std_logic; - - -- MII - mdc_pad_o : out std_logic; - md_pad_b : inout std_logic; - - ----------------------------- - -- FMC130m_4ch ports - ----------------------------- - - -- ADC LTC2208 interface - fmc_adc_pga_o : out std_logic; - fmc_adc_shdn_o : out std_logic; - fmc_adc_dith_o : out std_logic; - fmc_adc_rand_o : out std_logic; - - -- ADC0 LTC2208 - fmc_adc0_clk_i : in std_logic; - fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc0_of_i : in std_logic; -- Unused - - -- ADC1 LTC2208 - fmc_adc1_clk_i : in std_logic; - fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc1_of_i : in std_logic; -- Unused - - -- ADC2 LTC2208 - fmc_adc2_clk_i : in std_logic; - fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc2_of_i : in std_logic; -- Unused - - -- ADC3 LTC2208 - fmc_adc3_clk_i : in std_logic; - fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc3_of_i : in std_logic; -- Unused - - -- FMC General Status - fmc_prsnt_i : in std_logic; - fmc_pg_m2c_i : in std_logic; - --fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board - - -- Trigger - fmc_trig_dir_o : out std_logic; - fmc_trig_term_o : out std_logic; - fmc_trig_val_p_b : inout std_logic; - fmc_trig_val_n_b : inout std_logic; - - -- Si571 clock gen - si571_scl_pad_b : inout std_logic; - si571_sda_pad_b : inout std_logic; - fmc_si571_oe_o : out std_logic; - - -- AD9510 clock distribution PLL - spi_ad9510_cs_o : out std_logic; - spi_ad9510_sclk_o : out std_logic; - spi_ad9510_mosi_o : out std_logic; - spi_ad9510_miso_i : in std_logic; - - fmc_pll_function_o : out std_logic; - fmc_pll_status_i : in std_logic; - - -- AD9510 clock copy - fmc_fpga_clk_p_i : in std_logic; - fmc_fpga_clk_n_i : in std_logic; - - -- Clock reference selection (TS3USB221) - fmc_clk_sel_o : out std_logic; - - -- EEPROM - eeprom_scl_pad_b : inout std_logic; - eeprom_sda_pad_b : inout std_logic; - - -- Temperature monitor - -- LM75AIMM - lm75_scl_pad_b : inout std_logic; - lm75_sda_pad_b : inout std_logic; - - fmc_lm75_temp_alarm_i : in std_logic; - - -- FMC LEDs - fmc_led1_o : out std_logic; - fmc_led2_o : out std_logic; - fmc_led3_o : out std_logic; - - ----------------------------------------- - -- General board status - ----------------------------------------- - fmc_mmcm_lock_led_o : out std_logic; - fmc_pll_status_led_o : out std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - - -- Directional leds - --led_south_o : out std_logic; - --led_east_o : out std_logic; - --led_north_o : out std_logic; - - -- GPIO leds - leds_o : out std_logic_vector(7 downto 0) -); -end dbe_bpm_fmc130m_4ch; - -architecture rtl of dbe_bpm_fmc130m_4ch is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 9; - -- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC, - --Etherbone, FMC516, Peripherals - -- Number of masters - --constant c_masters : natural := 9; -- LM32 master, Data + Instruction, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon - constant c_masters : natural := 7; -- RS232-Syscon, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone - - constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB) - --constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB) - constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB) - - -- GPIO num pinscalc - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- TICs counter period. 100MHz clock -> msec granularity - constant c_tics_cntr_period : natural := 100000; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - -- number of the ADC reference clock used for all downstream - -- FPGA logic - constant c_adc_ref_clk : natural := 1; - - constant c_xwb_etherbone_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"0000000000000651", -- GSI - device_id => x"68202b22", - version => x"00000001", - date => x"20120912", - name => "GSI_ETHERBONE_CFG "))); - - constant c_xwb_ethmac_adapter_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"1000000000001215", -- LNLS - device_id => x"2ff9a28e", - version => x"00000001", - date => x"20130701", - name => "ETHMAC_ADAPTER "))); - - -- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure - -- no address overlaps will occur - --constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - -- FMC130m_4ch - constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - - -- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter - constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400"); - - -- WB SDB (Self describing bus) layout - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory - 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - x"20000000"), -- 64KB RAM - 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port - 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port - 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port - 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port - 7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port - 8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well - constant c_sdb_address : t_wishbone_address := x"30000000"; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - signal rs232_rstn : std_logic; - - -- Only one clock domain - signal reset_clks : std_logic_vector(0 downto 0); - signal reset_rstn : std_logic_vector(0 downto 0); - - -- 200 Mhz clocck for iodelay_ctrl - signal clk_200mhz : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - - -- Ethernet MAC signals - signal ethmac_int : std_logic; - signal ethmac_md_in : std_logic; - signal ethmac_md_out : std_logic; - signal ethmac_md_oe : std_logic; - - signal mtxd_pad_int : std_logic_vector(3 downto 0); - signal mtxen_pad_int : std_logic; - signal mtxerr_pad_int : std_logic; - signal mdc_pad_int : std_logic; - - -- Ethrnet MAC adapter signals - signal irq_rx_done : std_logic; - signal irq_tx_done : std_logic; - - -- Etherbone signals - signal wb_ebone_out : t_wishbone_master_out; - signal wb_ebone_in : t_wishbone_master_in; - - signal eb_src_i : t_wrf_source_in; - signal eb_src_o : t_wrf_source_out; - signal eb_snk_i : t_wrf_sink_in; - signal eb_snk_o : t_wrf_sink_out; - - -- DMA signals - signal dma_int : std_logic; - - -- FMC130m_4ch Signals - signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0); - signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0); - - signal fmc_mmcm_lock_int : std_logic; - signal fmc_pll_status_int : std_logic; - - signal fmc_led1_int : std_logic; - signal fmc_led2_int : std_logic; - signal fmc_led3_int : std_logic; - - signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0); - signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal fmc_debug : std_logic; - signal reset_adc_counter : unsigned(6 downto 0) := (others => '0'); - signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0); - - -- fmc130m_4ch Debug - signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0); - - signal sys_spi_clk_int : std_logic; - --signal sys_spi_data_int : std_logic; - signal sys_spi_dout_int : std_logic; - signal sys_spi_din_int : std_logic; - signal sys_spi_miosio_oe_n_int : std_logic; - signal sys_spi_cs_adc0_n_int : std_logic; - signal sys_spi_cs_adc1_n_int : std_logic; - signal sys_spi_cs_adc2_n_int : std_logic; - signal sys_spi_cs_adc3_n_int : std_logic; - - signal lmk_lock_int : std_logic; - signal lmk_sync_int : std_logic; - signal lmk_uwire_latch_en_int : std_logic; - signal lmk_uwire_data_int : std_logic; - signal lmk_uwire_clock_int : std_logic; - - signal fmc_reset_adcs_n_int : std_logic; - signal fmc_reset_adcs_n_out : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - -- Counter signal - --signal s_counter : unsigned(c_counter_width-1 downto 0); - -- 100MHz period or 1 second - --constant s_counter_full : integer := 100000000; - - -- Chipscope control signals - signal CONTROL0 : std_logic_vector(35 downto 0); - signal CONTROL1 : std_logic_vector(35 downto 0); - signal CONTROL2 : std_logic_vector(35 downto 0); - signal CONTROL3 : std_logic_vector(35 downto 0); - - -- Chipscope ILA 0 signals - signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 1 signals - signal TRIG_ILA1_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 2 signals - signal TRIG_ILA2_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 3 signals - signal TRIG_ILA3_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_3 : std_logic_vector(31 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic - ); - end component; - - -- Xilinx Megafunction - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Controller 2 port - --component chipscope_icon_2_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0) - --); - --end component; - - component chipscope_icon_4_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0); - CONTROL2 : inout std_logic_vector(35 downto 0); - CONTROL3 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; - -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - clk_i => sys_clk_gen, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => 1 -- CLK_SYS - ) - port map( - free_clk_i => sys_clk_gen, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(0) <= clk_sys; - --clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n; - clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n and rs232_rstn; - clk_sys_rst <= not clk_sys_rstn; - mrstn_o <= clk_sys_rstn; - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => true, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - lm32_rstn <= clk_sys_rstn; - - --cmp_lm32 : xwb_lm32 - --generic map( - -- g_profile => "medium_icache_debug" - --) -- Including JTAG and I-cache (no divide) - --port map( - -- clk_sys_i => clk_sys, - -- rst_n_i => lm32_rstn, - -- irq_i => lm32_interrupt, - -- dwb_o => cbar_slave_i(0), -- Data bus - -- dwb_i => cbar_slave_o(0), - -- iwb_o => cbar_slave_i(1), -- Instruction bus - -- iwb_i => cbar_slave_o(1) - --); - - -- Interrupt '0' is Ethmac. - -- Interrupt '1' is DMA completion. - -- Interrupt '2' is Button(0). - -- Interrupt '3' is Ethernet Adapter RX completion. - -- Interrupt '4' is Ethernet Adapter TX completion. - -- Interrupts 31 downto 5 are disabled - - lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done, - 4 => irq_tx_done, others => '0'); - - cmp_xwb_rs232_syscon : xwb_rs232_syscon - generic map ( - g_ma_interface_mode => PIPELINED, - g_ma_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rstn_i => '1', -- No need for resetting the controller - - -- External ports - rs232_rxd_i => rs232_rxd_i, - rs232_txd_o => rs232_txd_o, - - -- Reset to FPGA logic - rstn_o => rs232_rstn, - - -- WISHBONE master - wb_master_i => cbar_slave_o(0), - wb_master_o => cbar_slave_i(0) - ); - - -- A DMA controller is master 2+3, slave 3, and interrupt 1 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(3), - slave_o => cbar_master_i(3), - r_master_i => cbar_slave_o(1), - r_master_o => cbar_slave_i(1), - w_master_i => cbar_slave_o(2), - w_master_o => cbar_slave_i(2), - interrupt_o => dma_int - ); - - -- Slave 0+1 is the RAM. Load a input file containing the embedded software - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - --g_init_file => "../../../embedded-sw/dbe.ram", - --"../../top/ml_605/dbe_bpm_simple/sw/main.ram", - --g_must_have_init_file => true, - g_must_have_init_file => false, - g_slave1_interface_mode => PIPELINED, - g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE, - g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - ); - - -- Slave 2 is the RAM Buffer for Ethernet MAC. - cmp_ethmac_buf_ram : xwb_dpram - generic map( - g_size => c_dpram_ethbuf_size, - g_init_file => "", - g_must_have_init_file => false, - g_slave1_interface_mode => CLASSIC, - --g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE - --g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(2), - slave1_o => cbar_master_i(2), - -- Second port connected to the crossbar - slave2_i => cc_dummy_slave_in, -- CYC always low - slave2_o => open - ); - - -- The Ethernet MAC is master 4, slave 4 - cmp_xwb_ethmac : xwb_ethmac - generic map ( - --g_ma_interface_mode => PIPELINED, - g_ma_interface_mode => CLASSIC, -- NOT used for now - --g_ma_address_granularity => WORD, - g_ma_address_granularity => BYTE, -- NOT used for now - g_sl_interface_mode => PIPELINED, - --g_sl_interface_mode => CLASSIC, - --g_sl_address_granularity => WORD - g_sl_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - - -- WISHBONE slave - wb_slave_in => cbar_master_o(4), - wb_slave_out => cbar_master_i(4), - - -- WISHBONE master - wb_master_in => cbar_slave_o(3), - wb_master_out => cbar_slave_i(3), - - -- PHY TX - mtx_clk_pad_i => mtx_clk_pad_i, - --mtxd_pad_o => mtxd_pad_o, - mtxd_pad_o => mtxd_pad_int, - --mtxen_pad_o => mtxen_pad_o, - mtxen_pad_o => mtxen_pad_int, - --mtxerr_pad_o => mtxerr_pad_o, - mtxerr_pad_o => mtxerr_pad_int, - - -- PHY RX - mrx_clk_pad_i => mrx_clk_pad_i, - mrxd_pad_i => mrxd_pad_i, - mrxdv_pad_i => mrxdv_pad_i, - mrxerr_pad_i => mrxerr_pad_i, - mcoll_pad_i => mcoll_pad_i, - mcrs_pad_i => mcrs_pad_i, - - -- MII - --mdc_pad_o => mdc_pad_o, - mdc_pad_o => mdc_pad_int, - md_pad_i => ethmac_md_in, - md_pad_o => ethmac_md_out, - md_padoe_o => ethmac_md_oe, - - -- Interrupt - int_o => ethmac_int - ); - - -- Tri-state buffer for MII config - md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z'; - ethmac_md_in <= md_pad_b; - - mtxd_pad_o <= mtxd_pad_int; - mtxen_pad_o <= mtxen_pad_int; - mtxerr_pad_o <= mtxerr_pad_int; - mdc_pad_o <= mdc_pad_int; - - -- The Ethernet MAC Adapter is master 5+6, slave 5 - cmp_xwb_ethmac_adapter : xwb_ethmac_adapter - port map( - clk_i => clk_sys, - rstn_i => clk_sys_rstn, - - wb_slave_o => cbar_master_i(5), - wb_slave_i => cbar_master_o(5), - - tx_ram_o => cbar_slave_i(4), - tx_ram_i => cbar_slave_o(4), - - rx_ram_o => cbar_slave_i(5), - rx_ram_i => cbar_slave_o(5), - - rx_eb_o => eb_snk_i, - rx_eb_i => eb_snk_o, - - tx_eb_o => eb_src_i, - tx_eb_i => eb_src_o, - - irq_tx_done_o => irq_tx_done, - irq_rx_done_o => irq_rx_done - ); - - -- The Etherbone is slave 6 - cmp_eb_slave_core : eb_slave_core - generic map( - g_sdb_address => x"00000000" & c_sdb_address - ) - port map - ( - clk_i => clk_sys, - nRst_i => clk_sys_rstn, - - -- EB streaming sink - snk_i => eb_snk_i, - snk_o => eb_snk_o, - - -- EB streaming source - src_i => eb_src_i, - src_o => eb_src_o, - - -- WB slave - Cfg IF - cfg_slave_o => cbar_master_i(6), - cfg_slave_i => cbar_master_o(6), - - -- WB master - Bus IF - master_o => wb_ebone_out, - master_i => wb_ebone_in - ); - - cbar_slave_i(6) <= wb_ebone_out; - wb_ebone_in <= cbar_slave_o(6); - - -- The FMC130M_4CH is slave 7 - cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch - generic map( - g_fpga_device => "VIRTEX6", - g_interface_mode => PIPELINED, - --g_address_granularity => WORD, - g_address_granularity => BYTE, - --g_adc_clk_period_values => default_adc_clk_period_values, - g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88), - --g_use_clk_chains => default_clk_use_chain, - -- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair) - -- using clock0 from fmc130m_4ch. - -- BUFIO can drive half-bank only, not the full IO bank - g_use_clk_chains => "1111", - g_with_bufio_clk_chains => "0000", - g_with_bufr_clk_chains => "1111", - g_use_data_chains => "1111", - --g_map_clk_data_chains => (-1,-1,-1,-1), - -- Clock 1 is the adc reference clock - g_ref_clk => c_adc_ref_clk, - g_packet_size => 32, - g_sim => 0 - ) - port map( - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - sys_clk_200Mhz_i => clk_200mhz, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(7), - wb_slv_o => cbar_master_i(7), - - ----------------------------- - -- External ports - ----------------------------- - - -- ADC LTC2208 interface - fmc_adc_pga_o => fmc_adc_pga_o, - fmc_adc_shdn_o => fmc_adc_shdn_o, - fmc_adc_dith_o => fmc_adc_dith_o, - fmc_adc_rand_o => fmc_adc_rand_o, - - -- ADC0 LTC2208 - fmc_adc0_clk_i => fmc_adc0_clk_i, - fmc_adc0_data_i => fmc_adc0_data_i, - fmc_adc0_of_i => fmc_adc0_of_i, - - -- ADC1 LTC2208 - fmc_adc1_clk_i => fmc_adc1_clk_i, - fmc_adc1_data_i => fmc_adc1_data_i, - fmc_adc1_of_i => fmc_adc1_of_i, - - -- ADC2 LTC2208 - fmc_adc2_clk_i => fmc_adc2_clk_i, - fmc_adc2_data_i => fmc_adc2_data_i, - fmc_adc2_of_i => fmc_adc2_of_i, - - -- ADC3 LTC2208 - fmc_adc3_clk_i => fmc_adc3_clk_i, - fmc_adc3_data_i => fmc_adc3_data_i, - fmc_adc3_of_i => fmc_adc3_of_i, - - -- FMC General Status - fmc_prsnt_i => fmc_prsnt_i, - fmc_pg_m2c_i => fmc_pg_m2c_i, - - -- Trigger - fmc_trig_dir_o => fmc_trig_dir_o, - fmc_trig_term_o => fmc_trig_term_o, - fmc_trig_val_p_b => fmc_trig_val_p_b, - fmc_trig_val_n_b => fmc_trig_val_n_b, - - -- Si571 clock gen - si571_scl_pad_b => si571_scl_pad_b, - si571_sda_pad_b => si571_sda_pad_b, - fmc_si571_oe_o => fmc_si571_oe_o, - - -- AD9510 clock distribution PLL - spi_ad9510_cs_o => spi_ad9510_cs_o, - spi_ad9510_sclk_o => spi_ad9510_sclk_o, - spi_ad9510_mosi_o => spi_ad9510_mosi_o, - spi_ad9510_miso_i => spi_ad9510_miso_i, - - fmc_pll_function_o => fmc_pll_function_o, - fmc_pll_status_i => fmc_pll_status_i, - - -- AD9510 clock copy - fmc_fpga_clk_p_i => fmc_fpga_clk_p_i, - fmc_fpga_clk_n_i => fmc_fpga_clk_n_i, - - -- Clock reference selection (TS3USB221) - fmc_clk_sel_o => fmc_clk_sel_o, - - -- EEPROM - eeprom_scl_pad_b => eeprom_scl_pad_b, - eeprom_sda_pad_b => eeprom_sda_pad_b, - - -- Temperature monitor - -- LM75AIMM - lm75_scl_pad_b => lm75_scl_pad_b, - lm75_sda_pad_b => lm75_sda_pad_b, - - fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i, - - -- FMC LEDs - fmc_led1_o => fmc_led1_int, - fmc_led2_o => fmc_led2_int, - fmc_led3_o => fmc_led3_int, - - ----------------------------- - -- Optional external reference clock ports - ----------------------------- - fmc_ext_ref_clk_i => '0', -- Unused - fmc_ext_ref_clk2x_i => '0', -- Unused - fmc_ext_ref_mmcm_locked_i => '0', -- Unused - - ----------------------------- - -- ADC output signals. Continuous flow - ----------------------------- - adc_clk_o => fmc_130m_4ch_clk, - adc_clk2x_o => fmc_130m_4ch_clk2x, - adc_rst_n_o => fmc_130m_4ch_rst_n, - adc_data_o => fmc_130m_4ch_data, - adc_data_valid_o => fmc_130m_4ch_data_valid, - - ----------------------------- - -- General ADC output signals and status - ----------------------------- - -- Trigger to other FPGA logic - trig_hw_o => open, - trig_hw_i => '0', - - -- General board status - fmc_mmcm_lock_o => fmc_mmcm_lock_int, - fmc_pll_status_o => fmc_pll_status_int, - - ----------------------------- - -- Wishbone Streaming Interface Source - ----------------------------- - wbs_source_i => wbs_fmc130m_4ch_in_array, - wbs_source_o => wbs_fmc130m_4ch_out_array, - - adc_dly_debug_o => adc_dly_debug_int, - - fifo_debug_valid_o => fmc130m_4ch_debug_valid_int, - fifo_debug_full_o => fmc130m_4ch_debug_full_int, - fifo_debug_empty_o => fmc130m_4ch_debug_empty_int - ); - - gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate - wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in; - end generate; - - fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int; - fmc_pll_status_led_o <= fmc_pll_status_int; - - fmc_led1_o <= fmc_led1_int; - fmc_led2_o <= fmc_led2_int; - fmc_led3_o <= fmc_led3_int; - - --led_south_o <= fmc_led1_int; - --led_east_o <= fmc_led2_int; - --led_north_o <= fmc_led3_int; - - -- The board peripherals components is slave 8 - cmp_xwb_dbe_periph : xwb_dbe_periph - generic map( - -- NOT used! - --g_interface_mode : t_wishbone_interface_mode := CLASSIC; - -- NOT used! - --g_address_granularity : t_wishbone_address_granularity := WORD; - g_cntr_period => c_tics_cntr_period, - g_num_leds => c_leds_num_pins, - g_num_buttons => c_buttons_num_pins - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- UART - uart_rxd_i => '0', - uart_txd_o => open, - - -- LEDs - led_out_o => gpio_leds_int, - led_in_i => gpio_leds_int, - led_oen_o => open, - - -- Buttons - button_out_o => open, - button_in_i => buttons_i, - button_oen_o => open, - - -- Wishbone - slave_i => cbar_master_o(8), - slave_o => cbar_master_i(8) - ); - - leds_o <= gpio_leds_int; - - ---- Xilinx Chipscope - cmp_chipscope_icon_0 : chipscope_icon_4_port - port map ( - CONTROL0 => CONTROL0, - CONTROL1 => CONTROL1, - CONTROL2 => CONTROL2, - CONTROL3 => CONTROL3 - ); - - cmp_chipscope_ila_0_fmc130m_4ch_clk0 : chipscope_ila - port map ( - CONTROL => CONTROL0, - --CLK => clk_sys, - CLK => fmc_130m_4ch_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA0_0, - TRIG1 => TRIG_ILA0_1, - TRIG2 => TRIG_ILA0_2, - TRIG3 => TRIG_ILA0_3 - ); - - -- fmc130m_4ch WBS master output data - --TRIG_ILA0_0 <= wbs_fmc130m_4ch_out_array(3).dat & - -- wbs_fmc130m_4ch_out_array(2).dat; - TRIG_ILA0_0 <= fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(47 downto 32); - - -- fmc130m_4ch WBS master output data - --TRIG_ILA0_1 <= wbs_fmc130m_4ch_out_array(1).dat & - -- wbs_fmc130m_4ch_out_array(0).dat; - --TRIG_ILA0_1 <= fmc130m_4ch_adc_data(15 downto 0) & - -- fmc130m_4ch_adc_data(47 downto 32); - TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse & - adc_dly_debug_int(1).data_chain.idelay.pulse & - adc_dly_debug_int(1).clk_chain.idelay.val & - adc_dly_debug_int(1).data_chain.idelay.val; - TRIG_ILA0_1(31 downto 12) <= (others => '0'); - - -- fmc130m_4ch WBS master output control signals - TRIG_ILA0_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc & - wbs_fmc130m_4ch_out_array(1).stb & - wbs_fmc130m_4ch_out_array(1).adr & - wbs_fmc130m_4ch_out_array(1).sel & - wbs_fmc130m_4ch_out_array(1).we & - wbs_fmc130m_4ch_out_array(2).cyc & - wbs_fmc130m_4ch_out_array(2).stb & - wbs_fmc130m_4ch_out_array(2).adr & - wbs_fmc130m_4ch_out_array(2).sel & - wbs_fmc130m_4ch_out_array(2).we; - TRIG_ILA0_2(18) <= '0'; - TRIG_ILA0_2(22 downto 19) <= fmc_130m_4ch_data_valid; - TRIG_ILA0_2(23) <= fmc_mmcm_lock_int; - TRIG_ILA0_2(24) <= fmc_pll_status_int; - TRIG_ILA0_2(25) <= fmc130m_4ch_debug_valid_int(1); - TRIG_ILA0_2(26) <= fmc130m_4ch_debug_full_int(1); - TRIG_ILA0_2(27) <= fmc130m_4ch_debug_empty_int(1); - TRIG_ILA0_2(31 downto 28) <= (others => '0'); - - -- fmc130m_4ch WBS master output control signals - --TRIG_ILA0_3(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc & - -- wbs_fmc130m_4ch_out_array(1).stb & - -- wbs_fmc130m_4ch_out_array(1).adr & - -- wbs_fmc130m_4ch_out_array(1).sel & - -- wbs_fmc130m_4ch_out_array(1).we & - -- wbs_fmc130m_4ch_out_array(0).cyc & - -- wbs_fmc130m_4ch_out_array(0).stb & - -- wbs_fmc130m_4ch_out_array(0).adr & - -- wbs_fmc130m_4ch_out_array(0).sel & - -- wbs_fmc130m_4ch_out_array(0).we; - --TRIG_ILA0_3(18) <= fmc_reset_adcs_n_out; - --TRIG_ILA0_3(22 downto 19) <= fmc130m_4ch_adc_valid; - --TRIG_ILA0_3(23) <= fmc130m_4ch_mmcm_lock_int; - --TRIG_ILA0_3(24) <= fmc130m_4ch_lmk_lock_int; - --TRIG_ILA0_3(25) <= fmc130m_4ch_debug_valid_int(1); - --TRIG_ILA0_3(26) <= fmc130m_4ch_debug_full_int(1); - --TRIG_ILA0_3(27) <= fmc130m_4ch_debug_empty_int(1); - --TRIG_ILA0_3(31 downto 28) <= (others => '0'); - TRIG_ILA0_3 <= (others => '0'); - - -- Etherbone debuging signals - --cmp_chipscope_ila_1_etherbone : chipscope_ila - --port map ( - -- CONTROL => CONTROL1, - -- CLK => clk_sys, - -- TRIG0 => TRIG_ILA1_0, - -- TRIG1 => TRIG_ILA1_1, - -- TRIG2 => TRIG_ILA1_2, - -- TRIG3 => TRIG_ILA1_3 - --); - - --TRIG_ILA1_0 <= wb_ebone_out.dat; - --TRIG_ILA1_1 <= wb_ebone_in.dat; - --TRIG_ILA1_2 <= wb_ebone_out.adr; - --TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc & - -- wb_ebone_out.stb & - -- wb_ebone_out.sel & - -- wb_ebone_out.we; - --TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack & - -- wb_ebone_in.err & - -- wb_ebone_in.rty & - -- wb_ebone_in.stall & - -- wb_ebone_in.int; - --TRIG_ILA1_3(31 downto 12) <= (others => '0'); - - --cmp_chipscope_ila_1_ethmac_rx : chipscope_ila - --port map ( - -- CONTROL => CONTROL1, - -- CLK => mrx_clk_pad_i, - -- TRIG0 => TRIG_ILA1_0, - -- TRIG1 => TRIG_ILA1_1, - -- TRIG2 => TRIG_ILA1_2, - -- TRIG3 => TRIG_ILA1_3 - --); - -- - --TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i & - -- mrxdv_pad_i & - -- mrxerr_pad_i & - -- mcoll_pad_i & - -- mcrs_pad_i; - -- - --TRIG_ILA1_0(31 downto 8) <= (others => '0'); - --TRIG_ILA1_1 <= (others => '0'); - --TRIG_ILA1_2 <= (others => '0'); - --TRIG_ILA1_3 <= (others => '0'); - - cmp_chipscope_ila_1_fmc130m_4ch_clk1 : chipscope_ila - port map ( - CONTROL => CONTROL1, - --CLK => fmc_130m_4ch_clk(1), - CLK => fmc_130m_4ch_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA1_0, - TRIG1 => TRIG_ILA1_1, - TRIG2 => TRIG_ILA1_2, - TRIG3 => TRIG_ILA1_3 - ); - - -- fmc130m_4ch WBS master output data - TRIG_ILA1_0 <= fmc_130m_4ch_data(15 downto 0) & - fmc_130m_4ch_data(63 downto 48); - - -- fmc130m_4ch WBS master output data - TRIG_ILA1_1 <= (others => '0'); - - -- fmc130m_4ch WBS master output control signals - TRIG_ILA1_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(0).cyc & - wbs_fmc130m_4ch_out_array(0).stb & - wbs_fmc130m_4ch_out_array(0).adr & - wbs_fmc130m_4ch_out_array(0).sel & - wbs_fmc130m_4ch_out_array(0).we & - wbs_fmc130m_4ch_out_array(3).cyc & - wbs_fmc130m_4ch_out_array(3).stb & - wbs_fmc130m_4ch_out_array(3).adr & - wbs_fmc130m_4ch_out_array(3).sel & - wbs_fmc130m_4ch_out_array(3).we; - TRIG_ILA1_2(18) <= '0'; - TRIG_ILA1_2(22 downto 19) <= fmc_130m_4ch_data_valid; - TRIG_ILA1_2(23) <= fmc_mmcm_lock_int; - TRIG_ILA1_2(24) <= fmc_pll_status_int; - TRIG_ILA1_2(25) <= fmc130m_4ch_debug_valid_int(0); - TRIG_ILA1_2(26) <= fmc130m_4ch_debug_full_int(0); - TRIG_ILA1_2(27) <= fmc130m_4ch_debug_empty_int(0); - TRIG_ILA1_2(31 downto 28) <= (others => '0'); - - TRIG_ILA1_3 <= (others => '0'); - - - cmp_chipscope_ila_2_ethmac_tx : chipscope_ila - port map ( - CONTROL => CONTROL2, - CLK => mtx_clk_pad_i, - TRIG0 => TRIG_ILA2_0, - TRIG1 => TRIG_ILA2_1, - TRIG2 => TRIG_ILA2_2, - TRIG3 => TRIG_ILA2_3 - ); - - TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int & - mtxen_pad_int & - mtxerr_pad_int; - - TRIG_ILA2_0(31 downto 6) <= (others => '0'); - TRIG_ILA2_1 <= (others => '0'); - TRIG_ILA2_2 <= (others => '0'); - TRIG_ILA2_3 <= (others => '0'); - - --cmp_chipscope_ila_3_ethmac_miim : chipscope_ila - --port map ( - -- CONTROL => CONTROL3, - -- CLK => clk_sys, - -- TRIG0 => TRIG_ILA3_0, - -- TRIG1 => TRIG_ILA3_1, - -- TRIG2 => TRIG_ILA3_2, - -- TRIG3 => TRIG_ILA3_3 - --); - -- - --TRIG_ILA3_0(4 downto 0) <= mdc_pad_int & - -- ethmac_md_in & - -- ethmac_md_out & - -- ethmac_md_oe & - -- ethmac_int; - -- - --TRIG_ILA3_0(31 downto 6) <= (others => '0'); - --TRIG_ILA3_1 <= (others => '0'); - --TRIG_ILA3_2 <= (others => '0'); - --TRIG_ILA3_3 <= (others => '0'); - - -- The clocks to/from peripherals are derived from the bus clock. - -- Therefore we don't have to worry about synchronization here, just - -- keep in mind that the data/ss lines will appear longer than normal - cmp_chipscope_ila_3_fmc130m_4ch_periph : chipscope_ila - port map ( - CONTROL => CONTROL3, - CLK => clk_sys, - TRIG0 => TRIG_ILA3_0, - TRIG1 => TRIG_ILA3_1, - TRIG2 => TRIG_ILA3_2, - TRIG3 => TRIG_ILA3_3 - ); - - TRIG_ILA3_0(7 downto 0) <= (others => '0'); - - TRIG_ILA3_0(31 downto 8) <= (others => '0'); - - TRIG_ILA3_1(4 downto 0) <= (others => '0'); - - TRIG_ILA3_1(31 downto 5) <= (others => '0'); - TRIG_ILA3_2 <= (others => '0'); - TRIG_ILA3_3 <= (others => '0'); - -end rtl; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/sys_pll.vhd deleted file mode 100644 index 036e6b5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/Manifest.py b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/Manifest.py deleted file mode 100644 index 195e7a84..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/Manifest.py +++ /dev/null @@ -1,4 +0,0 @@ -files = [ "dbe_bpm_fmc130m_4ch_pcie.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_bpm_fmc130m_4ch_pcie.ucf", - "dbe_bpm_fmc130m_4ch_pcie.xcf" ]; - -modules = { "local" : ["../../.."] }; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/chipscope.cpj b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/chipscope.cpj deleted file mode 100644 index 3cd3eafd..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/chipscope.cpj +++ /dev/null @@ -1,7044 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-unit.1.0.port.-1.b.2.signedPrecision=0 -unit.1.0.port.-1.b.2.signedScaleFactor=1.0 -unit.1.0.port.-1.b.2.tokencount=0 -unit.1.0.port.-1.b.2.unsignedOffset=0.0 -unit.1.0.port.-1.b.2.unsignedPrecision=0 -unit.1.0.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.2.visible=1 -unit.1.0.port.-1.b.3.alias=fmc516_ch1_clk_load -unit.1.0.port.-1.b.3.channellist=43 -unit.1.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.3.name=fmc516_ch -unit.1.0.port.-1.b.3.orderindex=-1 -unit.1.0.port.-1.b.3.radix=Hex -unit.1.0.port.-1.b.3.signedOffset=0.0 -unit.1.0.port.-1.b.3.signedPrecision=0 -unit.1.0.port.-1.b.3.signedScaleFactor=1.0 -unit.1.0.port.-1.b.3.tokencount=0 -unit.1.0.port.-1.b.3.unsignedOffset=0.0 -unit.1.0.port.-1.b.3.unsignedPrecision=0 -unit.1.0.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.3.visible=1 -unit.1.0.port.-1.b.4.alias=fmc516_ch1_data_dly -unit.1.0.port.-1.b.4.channellist=32 33 34 35 36 -unit.1.0.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.4.name=DataPort -unit.1.0.port.-1.b.4.orderindex=-1 -unit.1.0.port.-1.b.4.radix=Unsigned -unit.1.0.port.-1.b.4.signedOffset=0.0 -unit.1.0.port.-1.b.4.signedPrecision=0 -unit.1.0.port.-1.b.4.signedScaleFactor=1.0 -unit.1.0.port.-1.b.4.tokencount=0 -unit.1.0.port.-1.b.4.unsignedOffset=0.0 -unit.1.0.port.-1.b.4.unsignedPrecision=0 -unit.1.0.port.-1.b.4.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.4.visible=1 -unit.1.0.port.-1.b.5.alias=fmc516_ch1_data_load -unit.1.0.port.-1.b.5.channellist=42 -unit.1.0.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.5.name=DataPort -unit.1.0.port.-1.b.5.orderindex=-1 -unit.1.0.port.-1.b.5.radix=Hex -unit.1.0.port.-1.b.5.signedOffset=0.0 -unit.1.0.port.-1.b.5.signedPrecision=0 -unit.1.0.port.-1.b.5.signedScaleFactor=1.0 -unit.1.0.port.-1.b.5.tokencount=0 -unit.1.0.port.-1.b.5.unsignedOffset=0.0 -unit.1.0.port.-1.b.5.unsignedPrecision=0 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-unit.1.0.port.-1.b.7.signedScaleFactor=1.0 -unit.1.0.port.-1.b.7.tokencount=0 -unit.1.0.port.-1.b.7.unsignedOffset=0.0 -unit.1.0.port.-1.b.7.unsignedPrecision=0 -unit.1.0.port.-1.b.7.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.7.visible=1 -unit.1.0.port.-1.b.8.alias=fmc516_debug_valid -unit.1.0.port.-1.b.8.channellist=89 -unit.1.0.port.-1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.8.name=DataPort -unit.1.0.port.-1.b.8.orderindex=-1 -unit.1.0.port.-1.b.8.radix=Hex -unit.1.0.port.-1.b.8.signedOffset=0.0 -unit.1.0.port.-1.b.8.signedPrecision=0 -unit.1.0.port.-1.b.8.signedScaleFactor=1.0 -unit.1.0.port.-1.b.8.tokencount=0 -unit.1.0.port.-1.b.8.unsignedOffset=0.0 -unit.1.0.port.-1.b.8.unsignedPrecision=0 -unit.1.0.port.-1.b.8.unsignedScaleFactor=1.0 -unit.1.0.port.-1.b.8.visible=1 -unit.1.0.port.-1.b.9.alias=fmc_adc_valid -unit.1.0.port.-1.b.9.channellist=83 84 85 86 -unit.1.0.port.-1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.b.9.name=DataPort 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-unit.1.0.port.-1.s.10.orderindex=-1 -unit.1.0.port.-1.s.10.visible=0 -unit.1.0.port.-1.s.100.alias= -unit.1.0.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.100.name=DataPort[100] -unit.1.0.port.-1.s.100.orderindex=-1 -unit.1.0.port.-1.s.100.visible=1 -unit.1.0.port.-1.s.101.alias= -unit.1.0.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.101.name=DataPort[101] -unit.1.0.port.-1.s.101.orderindex=-1 -unit.1.0.port.-1.s.101.visible=1 -unit.1.0.port.-1.s.102.alias= -unit.1.0.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.102.name=DataPort[102] -unit.1.0.port.-1.s.102.orderindex=-1 -unit.1.0.port.-1.s.102.visible=1 -unit.1.0.port.-1.s.103.alias= -unit.1.0.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.103.name=DataPort[103] -unit.1.0.port.-1.s.103.orderindex=-1 -unit.1.0.port.-1.s.103.visible=1 -unit.1.0.port.-1.s.104.alias= -unit.1.0.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.104.name=DataPort[104] -unit.1.0.port.-1.s.104.orderindex=-1 -unit.1.0.port.-1.s.104.visible=1 -unit.1.0.port.-1.s.105.alias= -unit.1.0.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.105.name=DataPort[105] -unit.1.0.port.-1.s.105.orderindex=-1 -unit.1.0.port.-1.s.105.visible=1 -unit.1.0.port.-1.s.106.alias= -unit.1.0.port.-1.s.106.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.106.name=DataPort[106] -unit.1.0.port.-1.s.106.orderindex=-1 -unit.1.0.port.-1.s.106.visible=1 -unit.1.0.port.-1.s.107.alias= -unit.1.0.port.-1.s.107.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.107.name=DataPort[107] -unit.1.0.port.-1.s.107.orderindex=-1 -unit.1.0.port.-1.s.107.visible=1 -unit.1.0.port.-1.s.108.alias= -unit.1.0.port.-1.s.108.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.108.name=DataPort[108] -unit.1.0.port.-1.s.108.orderindex=-1 -unit.1.0.port.-1.s.108.visible=1 -unit.1.0.port.-1.s.109.alias= -unit.1.0.port.-1.s.109.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.109.name=DataPort[109] -unit.1.0.port.-1.s.109.orderindex=-1 -unit.1.0.port.-1.s.109.visible=1 -unit.1.0.port.-1.s.11.alias= -unit.1.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.11.name=DataPort[11] -unit.1.0.port.-1.s.11.orderindex=-1 -unit.1.0.port.-1.s.11.visible=0 -unit.1.0.port.-1.s.110.alias= -unit.1.0.port.-1.s.110.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.110.name=DataPort[110] -unit.1.0.port.-1.s.110.orderindex=-1 -unit.1.0.port.-1.s.110.visible=1 -unit.1.0.port.-1.s.111.alias= -unit.1.0.port.-1.s.111.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.111.name=DataPort[111] -unit.1.0.port.-1.s.111.orderindex=-1 -unit.1.0.port.-1.s.111.visible=1 -unit.1.0.port.-1.s.112.alias= -unit.1.0.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.112.name=DataPort[112] -unit.1.0.port.-1.s.112.orderindex=-1 -unit.1.0.port.-1.s.112.visible=1 -unit.1.0.port.-1.s.113.alias= -unit.1.0.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.113.name=DataPort[113] -unit.1.0.port.-1.s.113.orderindex=-1 -unit.1.0.port.-1.s.113.visible=1 -unit.1.0.port.-1.s.114.alias= -unit.1.0.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.114.name=DataPort[114] -unit.1.0.port.-1.s.114.orderindex=-1 -unit.1.0.port.-1.s.114.visible=1 -unit.1.0.port.-1.s.115.alias= -unit.1.0.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.115.name=DataPort[115] -unit.1.0.port.-1.s.115.orderindex=-1 -unit.1.0.port.-1.s.115.visible=1 -unit.1.0.port.-1.s.116.alias= -unit.1.0.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.116.name=DataPort[116] -unit.1.0.port.-1.s.116.orderindex=-1 -unit.1.0.port.-1.s.116.visible=1 -unit.1.0.port.-1.s.117.alias= -unit.1.0.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.117.name=DataPort[117] -unit.1.0.port.-1.s.117.orderindex=-1 -unit.1.0.port.-1.s.117.visible=1 -unit.1.0.port.-1.s.118.alias= -unit.1.0.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.118.name=DataPort[118] -unit.1.0.port.-1.s.118.orderindex=-1 -unit.1.0.port.-1.s.118.visible=1 -unit.1.0.port.-1.s.119.alias= -unit.1.0.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.119.name=DataPort[119] -unit.1.0.port.-1.s.119.orderindex=-1 -unit.1.0.port.-1.s.119.visible=1 -unit.1.0.port.-1.s.12.alias= -unit.1.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.12.name=DataPort[12] -unit.1.0.port.-1.s.12.orderindex=-1 -unit.1.0.port.-1.s.12.visible=0 -unit.1.0.port.-1.s.120.alias= -unit.1.0.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.120.name=DataPort[120] -unit.1.0.port.-1.s.120.orderindex=-1 -unit.1.0.port.-1.s.120.visible=1 -unit.1.0.port.-1.s.121.alias= -unit.1.0.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.121.name=DataPort[121] -unit.1.0.port.-1.s.121.orderindex=-1 -unit.1.0.port.-1.s.121.visible=1 -unit.1.0.port.-1.s.122.alias= -unit.1.0.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.122.name=DataPort[122] -unit.1.0.port.-1.s.122.orderindex=-1 -unit.1.0.port.-1.s.122.visible=1 -unit.1.0.port.-1.s.123.alias= -unit.1.0.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.123.name=DataPort[123] -unit.1.0.port.-1.s.123.orderindex=-1 -unit.1.0.port.-1.s.123.visible=1 -unit.1.0.port.-1.s.124.alias= -unit.1.0.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.124.name=DataPort[124] -unit.1.0.port.-1.s.124.orderindex=-1 -unit.1.0.port.-1.s.124.visible=1 -unit.1.0.port.-1.s.125.alias= -unit.1.0.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.125.name=DataPort[125] -unit.1.0.port.-1.s.125.orderindex=-1 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-unit.1.0.port.-1.s.72.alias= -unit.1.0.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.72.name=DataPort[72] -unit.1.0.port.-1.s.72.orderindex=-1 -unit.1.0.port.-1.s.72.visible=1 -unit.1.0.port.-1.s.73.alias= -unit.1.0.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.73.name=DataPort[73] -unit.1.0.port.-1.s.73.orderindex=-1 -unit.1.0.port.-1.s.73.visible=1 -unit.1.0.port.-1.s.74.alias= -unit.1.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.74.name=DataPort[74] -unit.1.0.port.-1.s.74.orderindex=-1 -unit.1.0.port.-1.s.74.visible=1 -unit.1.0.port.-1.s.75.alias= -unit.1.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.75.name=DataPort[75] -unit.1.0.port.-1.s.75.orderindex=-1 -unit.1.0.port.-1.s.75.visible=1 -unit.1.0.port.-1.s.76.alias= -unit.1.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.76.name=DataPort[76] -unit.1.0.port.-1.s.76.orderindex=-1 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-unit.1.0.port.-1.s.80.orderindex=-1 -unit.1.0.port.-1.s.80.visible=1 -unit.1.0.port.-1.s.81.alias= -unit.1.0.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.81.name=DataPort[81] -unit.1.0.port.-1.s.81.orderindex=-1 -unit.1.0.port.-1.s.81.visible=1 -unit.1.0.port.-1.s.82.alias= -unit.1.0.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.82.name=DataPort[82] -unit.1.0.port.-1.s.82.orderindex=-1 -unit.1.0.port.-1.s.82.visible=0 -unit.1.0.port.-1.s.83.alias= -unit.1.0.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.83.name=DataPort[83] -unit.1.0.port.-1.s.83.orderindex=-1 -unit.1.0.port.-1.s.83.visible=0 -unit.1.0.port.-1.s.84.alias= -unit.1.0.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.84.name=DataPort[84] -unit.1.0.port.-1.s.84.orderindex=-1 -unit.1.0.port.-1.s.84.visible=0 -unit.1.0.port.-1.s.85.alias= -unit.1.0.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.85.name=DataPort[85] -unit.1.0.port.-1.s.85.orderindex=-1 -unit.1.0.port.-1.s.85.visible=0 -unit.1.0.port.-1.s.86.alias= -unit.1.0.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.86.name=DataPort[86] -unit.1.0.port.-1.s.86.orderindex=-1 -unit.1.0.port.-1.s.86.visible=0 -unit.1.0.port.-1.s.87.alias= -unit.1.0.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.87.name=DataPort[87] -unit.1.0.port.-1.s.87.orderindex=-1 -unit.1.0.port.-1.s.87.visible=0 -unit.1.0.port.-1.s.88.alias= -unit.1.0.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.88.name=DataPort[88] -unit.1.0.port.-1.s.88.orderindex=-1 -unit.1.0.port.-1.s.88.visible=0 -unit.1.0.port.-1.s.89.alias= -unit.1.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.89.name=DataPort[89] -unit.1.0.port.-1.s.89.orderindex=-1 -unit.1.0.port.-1.s.89.visible=0 -unit.1.0.port.-1.s.9.alias= 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-unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= -unit.1.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.10.name=TriggerPort0[10] -unit.1.0.port.0.s.10.orderindex=-1 -unit.1.0.port.0.s.10.visible=1 -unit.1.0.port.0.s.11.alias= -unit.1.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.11.name=TriggerPort0[11] -unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 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19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= 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-unit.1.0.port.3.s.28.name=TriggerPort3[28] -unit.1.0.port.3.s.28.orderindex=-1 -unit.1.0.port.3.s.28.visible=1 -unit.1.0.port.3.s.29.alias= -unit.1.0.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.29.name=TriggerPort3[29] -unit.1.0.port.3.s.29.orderindex=-1 -unit.1.0.port.3.s.29.visible=1 -unit.1.0.port.3.s.3.alias= -unit.1.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.3.name=TriggerPort3[3] -unit.1.0.port.3.s.3.orderindex=-1 -unit.1.0.port.3.s.3.visible=1 -unit.1.0.port.3.s.30.alias= -unit.1.0.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=MyILA0 -unit.1.0.waveform.count=12 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=fmc516_ch1_data_load -unit.1.0.waveform.posn.0.radix=1 -unit.1.0.waveform.posn.0.type=bus -unit.1.0.waveform.posn.1.channel=2147483646 -unit.1.0.waveform.posn.1.name=fmc516_ch1_clk_dly -unit.1.0.waveform.posn.1.radix=4 -unit.1.0.waveform.posn.1.type=bus -unit.1.0.waveform.posn.10.channel=2147483646 -unit.1.0.waveform.posn.10.name=fmc_mmcm_lock -unit.1.0.waveform.posn.10.radix=1 -unit.1.0.waveform.posn.10.type=bus -unit.1.0.waveform.posn.100.channel=127 -unit.1.0.waveform.posn.100.name=DataPort[127] -unit.1.0.waveform.posn.100.type=signal -unit.1.0.waveform.posn.101.channel=127 -unit.1.0.waveform.posn.101.name=DataPort[127] -unit.1.0.waveform.posn.101.type=signal -unit.1.0.waveform.posn.102.channel=127 -unit.1.0.waveform.posn.102.name=DataPort[127] -unit.1.0.waveform.posn.102.type=signal -unit.1.0.waveform.posn.103.channel=127 -unit.1.0.waveform.posn.103.name=DataPort[127] -unit.1.0.waveform.posn.103.type=signal -unit.1.0.waveform.posn.104.channel=127 -unit.1.0.waveform.posn.104.name=DataPort[127] -unit.1.0.waveform.posn.104.type=signal -unit.1.0.waveform.posn.105.channel=127 -unit.1.0.waveform.posn.105.name=DataPort[127] -unit.1.0.waveform.posn.105.type=signal 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-unit.1.0.waveform.posn.112.name=DataPort[127] -unit.1.0.waveform.posn.112.type=signal -unit.1.0.waveform.posn.113.channel=127 -unit.1.0.waveform.posn.113.name=DataPort[127] -unit.1.0.waveform.posn.113.type=signal -unit.1.0.waveform.posn.114.channel=127 -unit.1.0.waveform.posn.114.name=DataPort[127] -unit.1.0.waveform.posn.114.type=signal -unit.1.0.waveform.posn.115.channel=127 -unit.1.0.waveform.posn.115.name=DataPort[127] -unit.1.0.waveform.posn.115.type=signal -unit.1.0.waveform.posn.116.channel=127 -unit.1.0.waveform.posn.116.name=DataPort[127] -unit.1.0.waveform.posn.116.type=signal -unit.1.0.waveform.posn.117.channel=127 -unit.1.0.waveform.posn.117.name=DataPort[127] -unit.1.0.waveform.posn.117.type=signal -unit.1.0.waveform.posn.118.channel=127 -unit.1.0.waveform.posn.118.name=DataPort[127] -unit.1.0.waveform.posn.118.type=signal -unit.1.0.waveform.posn.119.channel=127 -unit.1.0.waveform.posn.119.name=DataPort[127] -unit.1.0.waveform.posn.119.type=signal -unit.1.0.waveform.posn.12.channel=2147483646 -unit.1.0.waveform.posn.12.name=fmc_rst_adcs_n -unit.1.0.waveform.posn.12.radix=1 -unit.1.0.waveform.posn.12.type=bus -unit.1.0.waveform.posn.120.channel=127 -unit.1.0.waveform.posn.120.name=DataPort[127] -unit.1.0.waveform.posn.120.type=signal -unit.1.0.waveform.posn.121.channel=127 -unit.1.0.waveform.posn.121.name=DataPort[127] -unit.1.0.waveform.posn.121.type=signal -unit.1.0.waveform.posn.122.channel=127 -unit.1.0.waveform.posn.122.name=DataPort[127] -unit.1.0.waveform.posn.122.type=signal -unit.1.0.waveform.posn.123.channel=127 -unit.1.0.waveform.posn.123.name=DataP -unit.1.0.waveform.posn.2.channel=2147483646 -unit.1.0.waveform.posn.2.name=fmc516_ch1_data_dly -unit.1.0.waveform.posn.2.radix=4 -unit.1.0.waveform.posn.2.type=bus -unit.1.0.waveform.posn.3.channel=2147483646 -unit.1.0.waveform.posn.3.name=fmc516_adc_ch1 -unit.1.0.waveform.posn.3.radix=3 -unit.1.0.waveform.posn.3.type=bus -unit.1.0.waveform.posn.4.channel=2147483646 -unit.1.0.waveform.posn.4.name=fmc516_adc_ch2 -unit.1.0.waveform.posn.4.radix=3 -unit.1.0.waveform.posn.4.type=bus -unit.1.0.waveform.posn.5.channel=2147483646 -unit.1.0.waveform.posn.5.name=fmc516_debug_empty -unit.1.0.waveform.posn.5.radix=1 -unit.1.0.waveform.posn.5.type=bus -unit.1.0.waveform.posn.6.channel=2147483646 -unit.1.0.waveform.posn.6.name=fmc516_debug_dull -unit.1.0.waveform.posn.6.radix=1 -unit.1.0.waveform.posn.6.type=bus -unit.1.0.waveform.posn.7.channel=2147483646 -unit.1.0.waveform.posn.7.name=fmc516_debug_valid -unit.1.0.waveform.posn.7.radix=1 -unit.1.0.waveform.posn.7.type=bus -unit.1.0.waveform.posn.8.channel=2147483646 -unit.1.0.waveform.posn.8.name=fmc_adc_valid -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_lmk_lock -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.3764321 -unit.1.1.0.TriggerRow0=1 -unit.1.1.0.TriggerRow1=1 -unit.1.1.0.TriggerRow2=1 -unit.1.1.0.WIDTH0=0.94846153 -unit.1.1.0.X0=0.04923077 -unit.1.1.0.Y0=0.0 -unit.1.1.1.HEIGHT1=0.80851066 -unit.1.1.1.WIDTH1=0.8992308 -unit.1.1.1.X1=0.09846154 -unit.1.1.1.Y1=0.57937807 -unit.1.1.5.HEIGHT5=0.80851066 -unit.1.1.5.WIDTH5=0.8746154 -unit.1.1.5.X5=0.033076923 -unit.1.1.5.Y5=0.058919802 -unit.1.1.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.1.MFBitsB0=00000000000000000000000000000000 -unit.1.1.MFBitsB1=00000000000000000000000000000000 -unit.1.1.MFBitsB2=00000000000000000000000000000000 -unit.1.1.MFBitsB3=00000000000000000000000000000000 -unit.1.1.MFCompareA0=0 -unit.1.1.MFCompareA1=0 -unit.1.1.MFCompareA2=0 -unit.1.1.MFCompareA3=0 -unit.1.1.MFCompareB0=999 -unit.1.1.MFCompareB1=999 -unit.1.1.MFCompareB2=999 -unit.1.1.MFCompareB3=999 -unit.1.1.MFCount=4 -unit.1.1.MFDisplay0=0 -unit.1.1.MFDisplay1=0 -unit.1.1.MFDisplay2=0 -unit.1.1.MFDisplay3=0 -unit.1.1.MFEventType0=3 -unit.1.1.MFEventType1=3 -unit.1.1.MFEventType2=3 -unit.1.1.MFEventType3=3 -unit.1.1.RunMode=SINGLE RUN -unit.1.1.SQCondition=All Data -unit.1.1.SQContiguous0=0 -unit.1.1.SequencerOn=0 -unit.1.1.TCActive=0 -unit.1.1.TCAdvanced0=0 -unit.1.1.TCCondition0_0=M0 -unit.1.1.TCCondition0_1= -unit.1.1.TCConditionType0=0 -unit.1.1.TCCount=1 -unit.1.1.TCEventCount0=1 -unit.1.1.TCEventType0=3 -unit.1.1.TCName0=TriggerCondition0 -unit.1.1.TCOutputEnable0=0 -unit.1.1.TCOutputHigh0=1 -unit.1.1.TCOutputMode0=0 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=0 -unit.1.1.browser_tree_state=0 -unit.1.1.coretype=ILA -unit.1.1.eventCount0=1 -unit.1.1.eventCount1=1 -unit.1.1.eventCount2=1 -unit.1.1.eventCount3=1 -unit.1.1.plotBusColor0=-16777092 -unit.1.1.plotBusColor1=-3407821 -unit.1.1.plotBusCount=2 -unit.1.1.plotBusName0=fmc_adc_data_ch0 -unit.1.1.plotBusName1=fmc_adc_data_ch3 -unit.1.1.plotBusX=fmc_adc_data_ch3 -unit.1.1.plotBusY=fmc_adc_data_ch3 -unit.1.1.plotDataTimeMode=1 -unit.1.1.plotDisplayMode=line -unit.1.1.plotMaxX=0.0 -unit.1.1.plotMaxY=0.0 -unit.1.1.plotMinX=0.0 -unit.1.1.plotMinY=0.0 -unit.1.1.plotSelectedBus=3 -unit.1.1.port.-1.b.0.alias=fmc_adc_data_ch0 -unit.1.1.port.-1.b.0.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.b.0.name=DataPort -unit.1.1.port.-1.b.0.orderindex=-1 -unit.1.1.port.-1.b.0.radix=Signed -unit.1.1.port.-1.b.0.signedOffset=0.0 -unit.1.1.port.-1.b.0.signedPrecision=0 -unit.1.1.port.-1.b.0.signedScaleFactor=1.0 -unit.1.1.port.-1.b.0.tokencount=0 -unit.1.1.port.-1.b.0.unsignedOffset=0.0 -unit.1.1.port.-1.b.0.unsignedPrecision=0 -unit.1.1.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.0.visible=1 -unit.1.1.port.-1.b.1.alias=fmc_adc_data_ch3 -unit.1.1.port.-1.b.1.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.1.1.port.-1.b.1.color=java.awt.Color[r\=204,g\=0,b\=51] -unit.1.1.port.-1.b.1.name=DataPort -unit.1.1.port.-1.b.1.orderindex=-1 -unit.1.1.port.-1.b.1.radix=Signed -unit.1.1.port.-1.b.1.signedOffset=0.0 -unit.1.1.port.-1.b.1.signedPrecision=0 -unit.1.1.port.-1.b.1.signedScaleFactor=1.0 -unit.1.1.port.-1.b.1.tokencount=0 -unit.1.1.port.-1.b.1.unsignedOffset=0.0 -unit.1.1.port.-1.b.1.unsignedPrecision=0 -unit.1.1.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.1.port.-1.b.1.visible=1 -unit.1.1.port.-1.buscount=2 -unit.1.1.port.-1.channelcount=128 -unit.1.1.port.-1.s.0.alias= -unit.1.1.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.0.name=DataPort[0] -unit.1.1.port.-1.s.0.orderindex=-1 -unit.1.1.port.-1.s.0.visible=0 -unit.1.1.port.-1.s.1.alias= -unit.1.1.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.1.name=DataPort[1] -unit.1.1.port.-1.s.1.orderindex=-1 -unit.1.1.port.-1.s.1.visible=0 -unit.1.1.port.-1.s.10.alias= -unit.1.1.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.10.name=DataPort[10] -unit.1.1.port.-1.s.10.orderindex=-1 -unit.1.1.port.-1.s.10.visible=0 -unit.1.1.port.-1.s.100.alias= -unit.1.1.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.100.name=DataPort[100] -unit.1.1.port.-1.s.100.orderindex=-1 -unit.1.1.port.-1.s.100.visible=1 -unit.1.1.port.-1.s.101.alias= -unit.1.1.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.101.name=DataPort[101] -unit.1.1.port.-1.s.101.orderindex=-1 -unit.1.1.port.-1.s.101.visible=1 -unit.1.1.port.-1.s.102.alias= -unit.1.1.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.102.name=DataPort[102] -unit.1.1.port.-1.s.102.orderindex=-1 -unit.1.1.port.-1.s.102.visible=1 -unit.1.1.port.-1.s.103.alias= -unit.1.1.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.103.name=DataPort[103] -unit.1.1.port.-1.s.103.orderindex=-1 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-unit.1.1.port.-1.s.112.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.112.name=DataPort[112] -unit.1.1.port.-1.s.112.orderindex=-1 -unit.1.1.port.-1.s.112.visible=1 -unit.1.1.port.-1.s.113.alias= -unit.1.1.port.-1.s.113.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.113.name=DataPort[113] -unit.1.1.port.-1.s.113.orderindex=-1 -unit.1.1.port.-1.s.113.visible=1 -unit.1.1.port.-1.s.114.alias= -unit.1.1.port.-1.s.114.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.114.name=DataPort[114] -unit.1.1.port.-1.s.114.orderindex=-1 -unit.1.1.port.-1.s.114.visible=1 -unit.1.1.port.-1.s.115.alias= -unit.1.1.port.-1.s.115.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.115.name=DataPort[115] -unit.1.1.port.-1.s.115.orderindex=-1 -unit.1.1.port.-1.s.115.visible=1 -unit.1.1.port.-1.s.116.alias= -unit.1.1.port.-1.s.116.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.116.name=DataPort[116] -unit.1.1.port.-1.s.116.orderindex=-1 -unit.1.1.port.-1.s.116.visible=1 -unit.1.1.port.-1.s.117.alias= -unit.1.1.port.-1.s.117.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.117.name=DataPort[117] -unit.1.1.port.-1.s.117.orderindex=-1 -unit.1.1.port.-1.s.117.visible=1 -unit.1.1.port.-1.s.118.alias= -unit.1.1.port.-1.s.118.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.118.name=DataPort[118] -unit.1.1.port.-1.s.118.orderindex=-1 -unit.1.1.port.-1.s.118.visible=1 -unit.1.1.port.-1.s.119.alias= -unit.1.1.port.-1.s.119.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.119.name=DataPort[119] -unit.1.1.port.-1.s.119.orderindex=-1 -unit.1.1.port.-1.s.119.visible=1 -unit.1.1.port.-1.s.12.alias= -unit.1.1.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.12.name=DataPort[12] -unit.1.1.port.-1.s.12.orderindex=-1 -unit.1.1.port.-1.s.12.visible=0 -unit.1.1.port.-1.s.120.alias= -unit.1.1.port.-1.s.120.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.120.name=DataPort[120] -unit.1.1.port.-1.s.120.orderindex=-1 -unit.1.1.port.-1.s.120.visible=1 -unit.1.1.port.-1.s.121.alias= -unit.1.1.port.-1.s.121.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.121.name=DataPort[121] -unit.1.1.port.-1.s.121.orderindex=-1 -unit.1.1.port.-1.s.121.visible=1 -unit.1.1.port.-1.s.122.alias= -unit.1.1.port.-1.s.122.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.122.name=DataPort[122] -unit.1.1.port.-1.s.122.orderindex=-1 -unit.1.1.port.-1.s.122.visible=1 -unit.1.1.port.-1.s.123.alias= -unit.1.1.port.-1.s.123.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.123.name=DataPort[123] -unit.1.1.port.-1.s.123.orderindex=-1 -unit.1.1.port.-1.s.123.visible=1 -unit.1.1.port.-1.s.124.alias= -unit.1.1.port.-1.s.124.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.124.name=DataPort[124] -unit.1.1.port.-1.s.124.orderindex=-1 -unit.1.1.port.-1.s.124.visible=1 -unit.1.1.port.-1.s.125.alias= -unit.1.1.port.-1.s.125.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.125.name=DataPort[125] -unit.1.1.port.-1.s.125.orderindex=-1 -unit.1.1.port.-1.s.125.visible=1 -unit.1.1.port.-1.s.126.alias= -unit.1.1.port.-1.s.126.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.126.name=DataPort[126] -unit.1.1.port.-1.s.126.orderindex=-1 -unit.1.1.port.-1.s.126.visible=1 -unit.1.1.port.-1.s.127.alias= -unit.1.1.port.-1.s.127.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.127.name=DataPort[127] -unit.1.1.port.-1.s.127.orderindex=-1 -unit.1.1.port.-1.s.127.visible=1 -unit.1.1.port.-1.s.13.alias= -unit.1.1.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.13.name=DataPort[13] -unit.1.1.port.-1.s.13.orderindex=-1 -unit.1.1.port.-1.s.13.visible=0 -unit.1.1.port.-1.s.14.alias= -unit.1.1.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.14.name=DataPort[14] -unit.1.1.port.-1.s.14.orderindex=-1 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-unit.1.1.port.-1.s.62.orderindex=-1 -unit.1.1.port.-1.s.62.visible=1 -unit.1.1.port.-1.s.63.alias= -unit.1.1.port.-1.s.63.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.63.name=DataPort[63] -unit.1.1.port.-1.s.63.orderindex=-1 -unit.1.1.port.-1.s.63.visible=1 -unit.1.1.port.-1.s.64.alias= -unit.1.1.port.-1.s.64.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.64.name=DataPort[64] -unit.1.1.port.-1.s.64.orderindex=-1 -unit.1.1.port.-1.s.64.visible=1 -unit.1.1.port.-1.s.65.alias= -unit.1.1.port.-1.s.65.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.65.name=DataPort[65] -unit.1.1.port.-1.s.65.orderindex=-1 -unit.1.1.port.-1.s.65.visible=1 -unit.1.1.port.-1.s.66.alias= -unit.1.1.port.-1.s.66.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.66.name=DataPort[66] -unit.1.1.port.-1.s.66.orderindex=-1 -unit.1.1.port.-1.s.66.visible=1 -unit.1.1.port.-1.s.67.alias= -unit.1.1.port.-1.s.67.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.67.name=DataPort[67] -unit.1.1.port.-1.s.67.orderindex=-1 -unit.1.1.port.-1.s.67.visible=1 -unit.1.1.port.-1.s.68.alias= -unit.1.1.port.-1.s.68.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.68.name=DataPort[68] -unit.1.1.port.-1.s.68.orderindex=-1 -unit.1.1.port.-1.s.68.visible=1 -unit.1.1.port.-1.s.69.alias= -unit.1.1.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.69.name=DataPort[69] -unit.1.1.port.-1.s.69.orderindex=-1 -unit.1.1.port.-1.s.69.visible=1 -unit.1.1.port.-1.s.7.alias= -unit.1.1.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.7.name=DataPort[7] -unit.1.1.port.-1.s.7.orderindex=-1 -unit.1.1.port.-1.s.7.visible=0 -unit.1.1.port.-1.s.70.alias= -unit.1.1.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.70.name=DataPort[70] -unit.1.1.port.-1.s.70.orderindex=-1 -unit.1.1.port.-1.s.70.visible=1 -unit.1.1.port.-1.s.71.alias= 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-unit.1.1.port.-1.s.89.name=DataPort[89] -unit.1.1.port.-1.s.89.orderindex=-1 -unit.1.1.port.-1.s.89.visible=1 -unit.1.1.port.-1.s.9.alias= -unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=1 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=1 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=1 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=1 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=1 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=1 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 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-unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] 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-unit.1.1.waveform.posn.77.name=DataPort[107] -unit.1.1.waveform.posn.77.type=signal -unit.1.1.waveform.posn.78.channel=108 -unit.1.1.waveform.posn.78.name=DataPort[108] -unit.1.1.waveform.posn.78.type=signal -unit.1.1.waveform.posn.79.channel=109 -unit.1.1.waveform.posn.79.name=DataPort[109] -unit.1.1.waveform.posn.79.type=signal -unit.1.1.waveform.posn.8.channel=38 -unit.1.1.waveform.posn.8.name=DataPort[38] -unit.1.1.waveform.posn.8.type=signal -unit.1.1.waveform.posn.80.channel=110 -unit.1.1.waveform.posn.80.name=DataPort[110] -unit.1.1.waveform.posn.80.type=signal -unit.1.1.waveform.posn.81.channel=111 -unit.1.1.waveform.posn.81.name=DataPort[111] -unit.1.1.waveform.posn.81.type=signal -unit.1.1.waveform.posn.82.channel=112 -unit.1.1.waveform.posn.82.name=DataPort[112] -unit.1.1.waveform.posn.82.type=signal -unit.1.1.waveform.posn.83.channel=113 -unit.1.1.waveform.posn.83.name=DataPort[113] -unit.1.1.waveform.posn.83.type=signal -unit.1.1.waveform.posn.84.channel=114 -unit.1.1.waveform.posn.84.name=DataPort[114] -unit.1.1.waveform.posn.84.type=signal -unit.1.1.waveform.posn.85.channel=115 -unit.1.1.waveform.posn.85.name=DataPort[115] -unit.1.1.waveform.posn.85.type=signal -unit.1.1.waveform.posn.86.channel=116 -unit.1.1.waveform.posn.86.name=DataPort[116] -unit.1.1.waveform.posn.86.type=signal -unit.1.1.waveform.posn.87.channel=117 -unit.1.1.waveform.posn.87.name=DataPort[117] -unit.1.1.waveform.posn.87.type=signal -unit.1.1.waveform.posn.88.channel=118 -unit.1.1.waveform.posn.88.name=DataPort[118] -unit.1.1.waveform.posn.88.type=signal -unit.1.1.waveform.posn.89.channel=119 -unit.1.1.waveform.posn.89.name=DataPort[119] -unit.1.1.waveform.posn.89.type=signal -unit.1.1.waveform.posn.9.channel=39 -unit.1.1.waveform.posn.9.name=DataPort[39] -unit.1.1.waveform.posn.9.type=signal -unit.1.1.waveform.posn.90.channel=120 -unit.1.1.waveform.posn.90.name=DataPort[120] -unit.1.1.waveform.posn.90.type=signal -unit.1.1.waveform.posn.91.channel=121 -unit.1.1.waveform.posn.91.name=DataPort[121] -unit.1.1.waveform.posn.91.type=signal -unit.1.1.waveform.posn.92.channel=122 -unit.1.1.waveform.posn.92.name=DataPort[122] -unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=123 -unit.1.1.waveform.posn.93.name=DataPort[123] -unit.1.1.waveform.posn.93.type=signal -unit.1.1.waveform.posn.94.channel=124 -unit.1.1.waveform.posn.94.name=DataPort[124] -unit.1.1.waveform.posn.94.type=signal -unit.1.1.waveform.posn.95.channel=125 -unit.1.1.waveform.posn.95.name=DataPort[125] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=126 -unit.1.1.waveform.posn.96.name=DataPort[126] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal -unit.1.2.0.HEIGHT0=0.3764321 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 -unit.1.2.0.TriggerRow2=1 -unit.1.2.0.WIDTH0=0.9238461 -unit.1.2.0.X0=0.073846154 -unit.1.2.0.Y0=0.0 -unit.1.2.5.HEIGHT5=0.84889644 -unit.1.2.5.WIDTH5=0.8520801 -unit.1.2.5.X5=-0.062403698 -unit.1.2.5.Y5=0.22410867 -unit.1.2.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsB0=00000000000000000000000000000000 -unit.1.2.MFBitsB1=00000000000000000000000000000000 -unit.1.2.MFBitsB2=00000000000000000000000000000000 -unit.1.2.MFBitsB3=00000000000000000000000000000000 -unit.1.2.MFCompareA0=0 -unit.1.2.MFCompareA1=0 -unit.1.2.MFCompareA2=0 -unit.1.2.MFCompareA3=0 -unit.1.2.MFCompareB0=999 -unit.1.2.MFCompareB1=999 -unit.1.2.MFCompareB2=999 -unit.1.2.MFCompareB3=999 -unit.1.2.MFCount=4 -unit.1.2.MFDisplay0=0 -unit.1.2.MFDisplay1=0 -unit.1.2.MFDisplay2=0 -unit.1.2.MFDisplay3=0 -unit.1.2.MFEventType0=3 -unit.1.2.MFEventType1=3 -unit.1.2.MFEventType2=3 -unit.1.2.MFEventType3=3 -unit.1.2.RunMode=SINGLE RUN -unit.1.2.SQCondition=All Data -unit.1.2.SQContiguous0=0 -unit.1.2.SequencerOn=0 -unit.1.2.TCActive=0 -unit.1.2.TCAdvanced0=0 -unit.1.2.TCCondition0_0=M0 -unit.1.2.TCCondition0_1= -unit.1.2.TCConditionType0=0 -unit.1.2.TCCount=1 -unit.1.2.TCEventCount0=1 -unit.1.2.TCEventType0=3 -unit.1.2.TCName0=TriggerCondition0 -unit.1.2.TCOutputEnable0=0 -unit.1.2.TCOutputHigh0=1 -unit.1.2.TCOutputMode0=0 -unit.1.2.coretype=ILA -unit.1.2.eventCount0=1 -unit.1.2.eventCount1=1 -unit.1.2.eventCount2=1 -unit.1.2.eventCount3=1 -unit.1.2.plotBusCount=0 -unit.1.2.plotBusX= -unit.1.2.plotBusY= -unit.1.2.plotDataTimeMode=1 -unit.1.2.plotDisplayMode=line -unit.1.2.plotMaxX=0.0 -unit.1.2.plotMaxY=0.0 -unit.1.2.plotMinX=0.0 -unit.1.2.plotMinY=0.0 -unit.1.2.plotSelectedBus=0 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-unit.1.2.port.-1.s.101.name=DataPort[101] -unit.1.2.port.-1.s.101.orderindex=-1 -unit.1.2.port.-1.s.101.visible=1 -unit.1.2.port.-1.s.102.alias= -unit.1.2.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.102.name=DataPort[102] -unit.1.2.port.-1.s.102.orderindex=-1 -unit.1.2.port.-1.s.102.visible=1 -unit.1.2.port.-1.s.103.alias= -unit.1.2.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.103.name=DataPort[103] -unit.1.2.port.-1.s.103.orderindex=-1 -unit.1.2.port.-1.s.103.visible=1 -unit.1.2.port.-1.s.104.alias= -unit.1.2.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.104.name=DataPort[104] -unit.1.2.port.-1.s.104.orderindex=-1 -unit.1.2.port.-1.s.104.visible=1 -unit.1.2.port.-1.s.105.alias= -unit.1.2.port.-1.s.105.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.105.name=DataPort[105] -unit.1.2.port.-1.s.105.orderindex=-1 -unit.1.2.port.-1.s.105.visible=1 -unit.1.2.port.-1.s.106.alias= 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-unit.1.2.port.-1.s.73.orderindex=-1 -unit.1.2.port.-1.s.73.visible=1 -unit.1.2.port.-1.s.74.alias= -unit.1.2.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.74.name=DataPort[74] -unit.1.2.port.-1.s.74.orderindex=-1 -unit.1.2.port.-1.s.74.visible=1 -unit.1.2.port.-1.s.75.alias= -unit.1.2.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.75.name=DataPort[75] -unit.1.2.port.-1.s.75.orderindex=-1 -unit.1.2.port.-1.s.75.visible=1 -unit.1.2.port.-1.s.76.alias= -unit.1.2.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.76.name=DataPort[76] -unit.1.2.port.-1.s.76.orderindex=-1 -unit.1.2.port.-1.s.76.visible=1 -unit.1.2.port.-1.s.77.alias= -unit.1.2.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.77.name=DataPort[77] -unit.1.2.port.-1.s.77.orderindex=-1 -unit.1.2.port.-1.s.77.visible=1 -unit.1.2.port.-1.s.78.alias= -unit.1.2.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.78.name=DataPort[78] -unit.1.2.port.-1.s.78.orderindex=-1 -unit.1.2.port.-1.s.78.visible=1 -unit.1.2.port.-1.s.79.alias= -unit.1.2.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.79.name=DataPort[79] -unit.1.2.port.-1.s.79.orderindex=-1 -unit.1.2.port.-1.s.79.visible=1 -unit.1.2.port.-1.s.8.alias= -unit.1.2.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.8.name=DataPort[8] -unit.1.2.port.-1.s.8.orderindex=-1 -unit.1.2.port.-1.s.8.visible=1 -unit.1.2.port.-1.s.80.alias= -unit.1.2.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.80.name=DataPort[80] -unit.1.2.port.-1.s.80.orderindex=-1 -unit.1.2.port.-1.s.80.visible=1 -unit.1.2.port.-1.s.81.alias= -unit.1.2.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.81.name=DataPort[81] -unit.1.2.port.-1.s.81.orderindex=-1 -unit.1.2.port.-1.s.81.visible=1 -unit.1.2.port.-1.s.82.alias= -unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=1 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=1 -unit.1.2.port.-1.s.84.alias= -unit.1.2.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.84.name=DataPort[84] -unit.1.2.port.-1.s.84.orderindex=-1 -unit.1.2.port.-1.s.84.visible=1 -unit.1.2.port.-1.s.85.alias= -unit.1.2.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.85.name=DataPort[85] -unit.1.2.port.-1.s.85.orderindex=-1 -unit.1.2.port.-1.s.85.visible=1 -unit.1.2.port.-1.s.86.alias= -unit.1.2.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.86.name=DataPort[86] -unit.1.2.port.-1.s.86.orderindex=-1 -unit.1.2.port.-1.s.86.visible=1 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-unit.1.2.port.-1.s.95.orderindex=-1 -unit.1.2.port.-1.s.95.visible=1 -unit.1.2.port.-1.s.96.alias= -unit.1.2.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.96.name=DataPort[96] -unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=1 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex -unit.1.2.port.0.b.0.signedOffset=0.0 -unit.1.2.port.0.b.0.signedPrecision=0 -unit.1.2.port.0.b.0.signedScaleFactor=1.0 -unit.1.2.port.0.b.0.unsignedOffset=0.0 -unit.1.2.port.0.b.0.unsignedPrecision=0 -unit.1.2.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.0.b.0.visible=1 -unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=32 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 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-unit.1.2.port.3.s.5.name=TriggerPort3[5] -unit.1.2.port.3.s.5.orderindex=-1 -unit.1.2.port.3.s.5.visible=1 -unit.1.2.port.3.s.6.alias= -unit.1.2.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.6.name=TriggerPort3[6] -unit.1.2.port.3.s.6.orderindex=-1 -unit.1.2.port.3.s.6.visible=1 -unit.1.2.port.3.s.7.alias= -unit.1.2.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.7.name=TriggerPort3[7] -unit.1.2.port.3.s.7.orderindex=-1 -unit.1.2.port.3.s.7.visible=1 -unit.1.2.port.3.s.8.alias= -unit.1.2.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.8.name=TriggerPort3[8] -unit.1.2.port.3.s.8.orderindex=-1 -unit.1.2.port.3.s.8.visible=1 -unit.1.2.port.3.s.9.alias= -unit.1.2.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.s.9.name=TriggerPort3[9] -unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.portcount=4 -unit.1.2.rep_trigger.clobber=1 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-unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.portcount=4 -unit.1.3.rep_trigger.clobber=1 -unit.1.3.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.3.rep_trigger.filename=waveform -unit.1.3.rep_trigger.format=ASCII -unit.1.3.rep_trigger.loggingEnabled=0 -unit.1.3.rep_trigger.signals=All Signals/Buses -unit.1.3.samplesPerTrigger=1 -unit.1.3.triggerCapture=1 -unit.1.3.triggerNSamplesTS=0 -unit.1.3.triggerPosition=0 -unit.1.3.triggerWindowCount=1 -unit.1.3.triggerWindowDepth=4096 -unit.1.3.triggerWindowTS=0 -unit.1.3.username=MyILA3 -unit.1.3.waveform.count=35 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-unit.1.3.waveform.posn.67.channel=127 -unit.1.3.waveform.posn.67.name=DataPort[127] -unit.1.3.waveform.posn.67.type=signal -unit.1.3.waveform.posn.68.channel=127 -unit.1.3.waveform.posn.68.name=DataPort[127] -unit.1.3.waveform.posn.68.type=signal -unit.1.3.waveform.posn.69.channel=127 -unit.1.3.waveform.posn.69.name=DataPort[127] -unit.1.3.waveform.posn.69.type=signal -unit.1.3.waveform.posn.7.channel=2147483646 -unit.1.3.waveform.posn.7.name=wb_ma_pcie_addr_out -unit.1.3.waveform.posn.7.radix=1 -unit.1.3.waveform.posn.7.type=bus -unit.1.3.waveform.posn.70.channel=127 -unit.1.3.waveform.posn.70.name=DataPort[127] -unit.1.3.waveform.posn.70.type=signal -unit.1.3.waveform.posn.71.channel=127 -unit.1.3.waveform.posn.71.name=DataPort[127] -unit.1.3.waveform.posn.71.type=signal -unit.1.3.waveform.posn.72.channel=127 -unit.1.3.waveform.posn.72.name=DataPort[127] -unit.1.3.waveform.posn.72.type=signal -unit.1.3.waveform.posn.73.channel=127 -unit.1.3.waveform.posn.73.name=DataPort[127] -unit.1.3.waveform.posn.73.type=signal -unit.1.3.waveform.posn.74.channel=127 -unit.1.3.waveform.posn.74.name=DataPort[127] -unit.1.3.waveform.posn.74.type=signal -unit.1.3.waveform.posn.75.channel=127 -unit.1.3.waveform.posn.75.name=DataPort[127] -unit.1.3.waveform.posn.75.type=signal -unit.1.3.waveform.posn.76.channel=127 -unit.1.3.waveform.posn.76.name=DataPort[127] -unit.1.3.waveform.posn.76.type=signal -unit.1.3.waveform.posn.77.channel=127 -unit.1.3.waveform.posn.77.name=DataPort[127] -unit.1.3.waveform.posn.77.type=signal -unit.1.3.waveform.posn.78.channel=127 -unit.1.3.waveform.posn.78.name=DataPort[127] -unit.1.3.waveform.posn.78.type=signal -unit.1.3.waveform.posn.79.channel=127 -unit.1.3.waveform.posn.79.name=DataPort[127] -unit.1.3.waveform.posn.79.type=signal -unit.1.3.waveform.posn.8.channel=93 -unit.1.3.waveform.posn.8.name=DataPort[93] -unit.1.3.waveform.posn.8.radix=1 -unit.1.3.waveform.posn.8.type=signal -unit.1.3.waveform.posn.80.channel=127 -unit.1.3.waveform.posn.80.name=DataPort[127] -unit.1.3.waveform.posn.80.type=signal -unit.1.3.waveform.posn.81.channel=127 -unit.1.3.waveform.posn.81.name=DataPort[127] -unit.1.3.waveform.posn.81.type=signal -unit.1.3.waveform.posn.82.channel=127 -unit.1.3.waveform.posn.82.name=DataPort[127] -unit.1.3.waveform.posn.82.type=signal -unit.1.3.waveform.posn.83.channel=127 -unit.1.3.waveform.posn.83.name=DataPort[127] -unit.1.3.waveform.posn.83.type=signal -unit.1.3.waveform.posn.84.channel=127 -unit.1.3.waveform.posn.84.name=DataPort[127] -unit.1.3.waveform.posn.84.type=signal -unit.1.3.waveform.posn.85.channel=127 -unit.1.3.waveform.posn.85.name=DataPort[127] -unit.1.3.waveform.posn.85.type=signal -unit.1.3.waveform.posn.86.channel=127 -unit.1.3.waveform.posn.86.name=DataPort[127] -unit.1.3.waveform.posn.86.type=signal -unit.1.3.waveform.posn.87.channel=127 -unit.1.3.waveform.posn.87.name=DataPort[127] -unit.1.3.waveform.posn.87.type=signal -unit.1.3.waveform.posn.88.channel=127 -unit.1.3.waveform.posn.88.name=DataPort[127] -unit.1.3.waveform.posn.88.type=signal -unit.1.3.waveform.posn.89.channel=127 -unit.1.3.waveform.posn.89.name=DataPort[127] -unit.1.3.waveform.posn.89.type=signal -unit.1.3.waveform.posn.9.channel=94 -unit.1.3.waveform.posn.9.name=DataPort[94] -unit.1.3.waveform.posn.9.radix=1 -unit.1.3.waveform.posn.9.type=signal -unit.1.3.waveform.posn.90.channel=127 -unit.1.3.waveform.posn.90.name=DataPort[127] -unit.1.3.waveform.posn.90.type=signal -unit.1.3.waveform.posn.91.channel=127 -unit.1.3.waveform.posn.91.name=DataPort[127] -unit.1.3.waveform.posn.91.type=signal -unit.1.3.waveform.posn.92.channel=127 -unit.1.3.waveform.posn.92.name=DataPort[127] -unit.1.3.waveform.posn.92.type=signal -unit.1.3.waveform.posn.93.channel=127 -unit.1.3.waveform.posn.93.name=DataPort[127] -unit.1.3.waveform.posn.93.type=signal -unit.1.3.waveform.posn.94.channel=127 -unit.1.3.waveform.posn.94.name=DataPort[127] -unit.1.3.waveform.posn.94.type=signal -unit.1.3.waveform.posn.95.channel=127 -unit.1.3.waveform.posn.95.name=DataPort[127] -unit.1.3.waveform.posn.95.type=signal -unit.1.3.waveform.posn.96.channel=127 -unit.1.3.waveform.posn.96.name=DataPort[127] -unit.1.3.waveform.posn.96.type=signal -unit.1.3.waveform.posn.97.channel=127 -unit.1.3.waveform.posn.97.name=DataPort[127] -unit.1.3.waveform.posn.97.type=signal -unit.1.3.waveform.posn.98.channel=127 -unit.1.3.waveform.posn.98.name=DataPort[127] -unit.1.3.waveform.posn.98.type=signal -unit.1.3.waveform.posn.99.channel=127 -unit.1.3.waveform.posn.99.name=DataPort[127] -unit.1.3.waveform.posn.99.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd deleted file mode 100644 index 7f0be7ca..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic; - sys_clk_bufg_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => TRUE, -- Differential Termination - IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - sys_clk_o <= s_sys_clk; - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.ucf b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.ucf deleted file mode 100644 index 3f23da77..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.ucf +++ /dev/null @@ -1,673 +0,0 @@ -#-------------------------------- -# Virtex6 Board ML605 -#-------------------------------- - -NET "sys_clk_n_i" LOC = H9 | IOSTANDARD = LVDS_25; # 5 on U11, 5 on U89 (DNP) -NET "sys_clk_p_i" LOC = J9 | IOSTANDARD = LVDS_25; # 4 on U11, 4 on U89 (DNP) - -NET "rs232_rxd_i" LOC = J24 | IOSTANDARD = LVCMOS25; # 25 on U34 -NET "rs232_txd_o" LOC = J25 | IOSTANDARD = LVCMOS25; # 24 on U34 - -NET "sys_rst_button_i" LOC = H10 | IOSTANDARD = "SSTL15" | TIG; - -# MMCM Status -NET "fmc_mmcm_lock_led_o" LOC = "AP24" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_C, DS16 - -# LMK clock distribution Status -NET "fmc_pll_status_led_o" LOC = "AD21" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_W, DS17 - -#NET "led_south_o" LOC = "AH28" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_S, DS18 -#NET "led_east_o" LOC = "AE21" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_E, DS19 -#NET "led_north_o" LOC = "AH27" | IOSTANDARD = "LVCMOS25"; # GPIO_LED_N, DS20 - -#NET "board_led1_o" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 0 -#NET "board_led2_o" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 1 -#NET "board_led3_o" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 2 - -#-------------------------------- -# Button/LEDs Contraints -#-------------------------------- - -#NET "buttons_i[0]" LOC = D22 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[1]" LOC = C22 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[2]" LOC = L21 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[3]" LOC = L20 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[4]" LOC = C18 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[5]" LOC = B18 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[6]" LOC = K22 | IOSTANDARD = LVCMOS25; -#NET "buttons_i[7]" LOC = K21 | IOSTANDARD = LVCMOS25; -NET "leds_o[0]" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[1]" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[2]" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[3]" LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[4]" LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[5]" LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[6]" LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[7]" LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; - -#-------------------------------- -# FMC Connector HPC -#-------------------------------- - -NET "fmc_prsnt_i" LOC = AP25 | IOSTANDARD = "LVCMOS25"; -NET "fmc_pg_m2c_i" LOC = AK29 | IOSTANDARD = "LVCMOS25"; // LA31_N - -// Trigger -NET "fmc_trig_dir_o" LOC = AK27 | IOSTANDARD = "LVCMOS25"; // LA28_P -NET "fmc_trig_term_o" LOC = AL25 | IOSTANDARD = "LVCMOS25"; // LA26_N -NET "fmc_trig_val_p_b" LOC = AG25 | IOSTANDARD = "BLVDS_25"; // LA32_P -NET "fmc_trig_val_n_b" LOC = AG26 | IOSTANDARD = "BLVDS_25"; // LA32_N - -// Si571 clock gen -NET "si571_scl_pad_b" LOC = AE32 | IOSTANDARD = "LVCMOS25"; // HA12_N -NET "si571_sda_pad_b" LOC = AE31 | IOSTANDARD = "LVCMOS25"; // HA13_P -NET "fmc_si571_oe_o" LOC = AD32 | IOSTANDARD = "LVCMOS25"; // HA12_P - -// AD9510 clock distribution PLL -NET "spi_ad9510_cs_o" LOC = AN18 | IOSTANDARD = "LVCMOS25"; // LA13_N -NET "spi_ad9510_sclk_o" LOC = AP19 | IOSTANDARD = "LVCMOS25"; // LA13_P -NET "spi_ad9510_mosi_o" LOC = AL18 | IOSTANDARD = "LVCMOS25"; // LA09_N -NET "spi_ad9510_miso_i" LOC = AN19 | IOSTANDARD = "LVCMOS25"; // LA14_P -NET "fmc_pll_function_o" LOC = AN20 | IOSTANDARD = "LVCMOS25"; // LA14_N -NET "fmc_pll_status_i" LOC = AM18 | IOSTANDARD = "LVCMOS25"; // LA09_P - -#NET "fmc_fpga_clk_p_i" LOC = K24 | IOSTANDARD = "LVDS_25"; // CLK0_M2C_P -#NET "fmc_fpga_clk_n_i" LOC = K23 | IOSTANDARD = "LVDS_25"; // CLK0_M2C_N - -// Clock reference selection (TS3USB221) -NET "fmc_clk_sel_o" LOC = AL29 | IOSTANDARD = "LVCMOS25"; // LA31_P - -// EEPROM (multiplexer PCA9548) -NET "eeprom_scl_pad_b" LOC = AK9 | IOSTANDARD ="LVCMOS25"; # SCL C30 -NET "eeprom_sda_pad_b" LOC = AE9 | IOSTANDARD ="LVCMOS25"; # SDA C31 - -// LM75 temperature monitor (can be used without multiplexer on KC705 board) -NET "lm75_scl_pad_b" LOC = AP30 | IOSTANDARD = "LVCMOS25"; // LA27_P -NET "lm75_sda_pad_b" LOC = AP31 | IOSTANDARD = "LVCMOS25"; // LA27_N -NET "fmc_lm75_temp_alarm_i" LOC = AJ27 | IOSTANDARD = "LVCMOS25"; // LA28_N - -// LTC ADC control pins -NET "fmc_adc_pga_o" LOC = AG20 | IOSTANDARD = "LVCMOS25"; // LA06_P -NET "fmc_adc_shdn_o" LOC = AL20 | IOSTANDARD = "LVCMOS25"; // LA10_N -NET "fmc_adc_dith_o" LOC = AM20 | IOSTANDARD = "LVCMOS25"; // LA10_P -NET "fmc_adc_rand_o" LOC = AG21 | IOSTANDARD = "LVCMOS25"; // LA06_N - -// LEDs -NET "fmc_led1_o" LOC = AN23 | IOSTANDARD = "LVCMOS25"; // LA16_N -NET "fmc_led2_o" LOC = AP22 | IOSTANDARD = "LVCMOS25"; // LA16_P -NET "fmc_led3_o" LOC = AM25 | IOSTANDARD = "LVCMOS25"; // LA26_P - -#-------------------------------- -# FMC Connector HPC -# LTC ADC lines -#-------------------------------- - -// ADC0 -NET "fmc_adc0_clk_i" LOC = AN27 | IOSTANDARD = "LVCMOS25"; // LA17_CC_P - -NET "fmc_adc0_data_i[0]" LOC = AN30 | IOSTANDARD = "LVCMOS25"; // LA24_P -NET "fmc_adc0_data_i[1]" LOC = AM30 | IOSTANDARD = "LVCMOS25"; // LA24_N -NET "fmc_adc0_data_i[2]" LOC = AN28 | IOSTANDARD = "LVCMOS25"; // LA25_P -NET "fmc_adc0_data_i[3]" LOC = AM28 | IOSTANDARD = "LVCMOS25"; // LA25_N -NET "fmc_adc0_data_i[4]" LOC = AN29 | IOSTANDARD = "LVCMOS25"; // LA21_P -NET "fmc_adc0_data_i[5]" LOC = AP29 | IOSTANDARD = "LVCMOS25"; // LA21_N -NET "fmc_adc0_data_i[6]" LOC = AP27 | IOSTANDARD = "LVCMOS25"; // LA22_P -NET "fmc_adc0_data_i[7]" LOC = AP26 | IOSTANDARD = "LVCMOS25"; // LA22_N -NET "fmc_adc0_data_i[8]" LOC = AM26 | IOSTANDARD = "LVCMOS25"; // LA23_N -NET "fmc_adc0_data_i[9]" LOC = AN24 | IOSTANDARD = "LVCMOS25"; // LA19_N -NET "fmc_adc0_data_i[10]" LOC = AJ25 | IOSTANDARD = "LVCMOS25"; // LA18_CC_N -NET "fmc_adc0_data_i[11]" LOC = AL26 | IOSTANDARD = "LVCMOS25"; // LA23_P -NET "fmc_adc0_data_i[12]" LOC = AL24 | IOSTANDARD = "LVCMOS25"; // LA20_N -NET "fmc_adc0_data_i[13]" LOC = AN25 | IOSTANDARD = "LVCMOS25"; // LA19_P -NET "fmc_adc0_data_i[14]" LOC = AH25 | IOSTANDARD = "LVCMOS25"; // LA18_CC_P -NET "fmc_adc0_data_i[15]" LOC = AK23 | IOSTANDARD = "LVCMOS25"; // LA20_P -NET "fmc_adc0_of_i" LOC = AL28 | IOSTANDARD = "LVCMOS25"; // LA29_P - -// ADC1 -NET "fmc_adc1_clk_i" LOC = V30 | IOSTANDARD = "LVCMOS25"; // HA17_CC_P - -NET "fmc_adc1_data_i[15]" LOC = AD34 | IOSTANDARD = "LVCMOS25"; // HA10_P -NET "fmc_adc1_data_i[14]" LOC = AG33 | IOSTANDARD = "LVCMOS25"; // HA11_P -NET "fmc_adc1_data_i[13]" LOC = AC34 | IOSTANDARD = "LVCMOS25"; // HA10_N -NET "fmc_adc1_data_i[12]" LOC = AG32 | IOSTANDARD = "LVCMOS25"; // HA11_N -NET "fmc_adc1_data_i[11]" LOC = AB32 | IOSTANDARD = "LVCMOS25"; // HA15_P -NET "fmc_adc1_data_i[10]" LOC = AA30 | IOSTANDARD = "LVCMOS25"; // HA14_P -NET "fmc_adc1_data_i[9]" LOC = AC32 | IOSTANDARD = "LVCMOS25"; // HA15_N -NET "fmc_adc1_data_i[8]" LOC = AA31 | IOSTANDARD = "LVCMOS25"; // HA14_N -NET "fmc_adc1_data_i[7]" LOC = T34 | IOSTANDARD = "LVCMOS25"; // HA18_N -NET "fmc_adc1_data_i[6]" LOC = T33 | IOSTANDARD = "LVCMOS25"; // HA18_P -NET "fmc_adc1_data_i[5]" LOC = U32 | IOSTANDARD = "LVCMOS25"; // HA19_N -NET "fmc_adc1_data_i[4]" LOC = U31 | IOSTANDARD = "LVCMOS25"; // HA21_P -NET "fmc_adc1_data_i[3]" LOC = U28 | IOSTANDARD = "LVCMOS25"; // HA22_P -NET "fmc_adc1_data_i[2]" LOC = U30 | IOSTANDARD = "LVCMOS25"; // HA21_N -NET "fmc_adc1_data_i[1]" LOC = U26 | IOSTANDARD = "LVCMOS25"; // HA23_P -NET "fmc_adc1_data_i[0]" LOC = V29 | IOSTANDARD = "LVCMOS25"; // HA22_N -NET "fmc_adc1_of_i" LOC = U27 | IOSTANDARD = "LVCMOS25"; // HA23_N - -// ADC2 -NET "fmc_adc2_clk_i" LOC = AF20 | IOSTANDARD = "LVCMOS25"; // LA00_CC_P - -NET "fmc_adc2_data_i[15]" LOC = AK19 | IOSTANDARD = "LVCMOS25"; // LA01_CC_P -NET "fmc_adc2_data_i[14]" LOC = AC20 | IOSTANDARD = "LVCMOS25"; // LA02_P -NET "fmc_adc2_data_i[13]" LOC = AL19 | IOSTANDARD = "LVCMOS25"; // LA01_CC_N -NET "fmc_adc2_data_i[12]" LOC = AD20 | IOSTANDARD = "LVCMOS25"; // LA02_N -NET "fmc_adc2_data_i[11]" LOC = AD19 | IOSTANDARD = "LVCMOS25"; // LA03_N -NET "fmc_adc2_data_i[10]" LOC = AC19 | IOSTANDARD = "LVCMOS25"; // LA03_P -NET "fmc_adc2_data_i[9]" LOC = AE19 | IOSTANDARD = "LVCMOS25"; // LA04_N -NET "fmc_adc2_data_i[8]" LOC = AF19 | IOSTANDARD = "LVCMOS25"; // LA04_P -NET "fmc_adc2_data_i[7]" LOC = AH22 | IOSTANDARD = "LVCMOS25"; // LA05_N -NET "fmc_adc2_data_i[6]" LOC = AG22 | IOSTANDARD = "LVCMOS25"; // LA05_P -NET "fmc_adc2_data_i[5]" LOC = AJ22 | IOSTANDARD = "LVCMOS25"; // LA08_N -NET "fmc_adc2_data_i[4]" LOC = AK22 | IOSTANDARD = "LVCMOS25"; // LA08_P -NET "fmc_adc2_data_i[3]" LOC = AJ21 | IOSTANDARD = "LVCMOS25"; // LA07_N -NET "fmc_adc2_data_i[2]" LOC = AK21 | IOSTANDARD = "LVCMOS25"; // LA07_P -NET "fmc_adc2_data_i[1]" LOC = AL21 | IOSTANDARD = "LVCMOS25"; // LA12_N -NET "fmc_adc2_data_i[0]" LOC = AM21 | IOSTANDARD = "LVCMOS25"; // LA12_P -NET "fmc_adc2_of_i" LOC = AM22 | IOSTANDARD = "LVCMOS25"; // LA11_P - -// ADC3 -NET "fmc_adc3_clk_i" LOC = AD29 | IOSTANDARD = "LVCMOS25"; // HA01_CC_P - -NET "fmc_adc3_data_i[15]" LOC = AF33 | IOSTANDARD = "LVCMOS25"; // HA00_CC_N -NET "fmc_adc3_data_i[14]" LOC = AE33 | IOSTANDARD = "LVCMOS25"; // HA00_CC_P -NET "fmc_adc3_data_i[13]" LOC = AC27 | IOSTANDARD = "LVCMOS25"; // HA05_N -NET "fmc_adc3_data_i[12]" LOC = AB27 | IOSTANDARD = "LVCMOS25"; // HA05_P -NET "fmc_adc3_data_i[11]" LOC = AC28 | IOSTANDARD = "LVCMOS25"; // HA04_N -NET "fmc_adc3_data_i[10]" LOC = AB28 | IOSTANDARD = "LVCMOS25"; // HA04_P -NET "fmc_adc3_data_i[9]" LOC = AB31 | IOSTANDARD = "LVCMOS25"; // HA09_N -NET "fmc_adc3_data_i[8]" LOC = AB30 | IOSTANDARD = "LVCMOS25"; // HA09_P -NET "fmc_adc3_data_i[7]" LOC = Y26 | IOSTANDARD = "LVCMOS25"; // HA03_N -NET "fmc_adc3_data_i[6]" LOC = AA25 | IOSTANDARD = "LVCMOS25"; // HA03_P -NET "fmc_adc3_data_i[5]" LOC = AG31 | IOSTANDARD = "LVCMOS25"; // HA08_P -NET "fmc_adc3_data_i[4]" LOC = AB25 | IOSTANDARD = "LVCMOS25"; // HA02_P -NET "fmc_adc3_data_i[3]" LOC = AA26 | IOSTANDARD = "LVCMOS25"; // HA07_P -NET "fmc_adc3_data_i[2]" LOC = AC25 | IOSTANDARD = "LVCMOS25"; // HA02_N -NET "fmc_adc3_data_i[1]" LOC = AA28 | IOSTANDARD = "LVCMOS25"; // HA06_P -NET "fmc_adc3_data_i[0]" LOC = AB26 | IOSTANDARD = "LVCMOS25"; // HA07_N -NET "fmc_adc3_of_i" LOC = AA29 | IOSTANDARD = "LVCMOS25"; // HA06_N - -#-------------------------------- -# Ethernet Contraints. -# MII 10/100 Mode -#-------------------------------- - -NET "mrstn_o" LOC = AH13; -NET "mcoll_pad_i" LOC = AK13; ## 114 on U80 -NET "mcrs_pad_i" LOC = AL13; ## 115 on U80 -# NET "PHY_INT" LOC = AH14; ## 32 on U80 -NET "mdc_pad_o" LOC = AP14; ## 35 on U80 -NET "md_pad_b" LOC = AN14; ## 33 on U80 -# NET "PHY_RESET" LOC = AH13; ## 36 on U80 -NET "mrx_clk_pad_i" LOC = AP11; ## 7 on U80 -NET "mrxdv_pad_i" LOC = AM13; ## 4 on U80 -NET "mrxd_pad_i[0]" LOC = AN13; ## 3 on U80 -NET "mrxd_pad_i[1]" LOC = AF14; ## 128 on U80 -NET "mrxd_pad_i[2]" LOC = AE14; ## 126 on U80 -NET "mrxd_pad_i[3]" LOC = AN12; ## 125 on U80 -# NET "PHY_RXD4" LOC = AM12; ## 124 on U80 -# NET "PHY_RXD5" LOC = AD11; ## 123 on U80 -# NET "PHY_RXD6" LOC = AC12; ## 121 on U80 -# NET "PHY_RXD7" LOC = AC13; ## 120 on U80 -NET "mrxerr_pad_i" LOC = AG12; ## 9 on U80 -NET "mtx_clk_pad_i" LOC = AD12; ## 10 on U80 -NET "mtxen_pad_o" LOC = AJ10; ## 16 on U80 -# NET "PHY_TXC_GTXCLK" LOC = AH12; ## 14 on U80 -NET "mtxd_pad_o[0]" LOC = AM11; ## 18 on U80 -NET "mtxd_pad_o[1]" LOC = AL11; ## 19 on U80 -NET "mtxd_pad_o[2]" LOC = AG10; ## 20 on U80 -NET "mtxd_pad_o[3]" LOC = AG11; ## 24 on U80 -# NET "PHY_TXD4" LOC = AL10; ## 25 on U80 -# NET "PHY_TXD5" LOC = AM10; ## 26 on U80 -# NET "PHY_TXD6" LOC = AE11; ## 28 on U80 -# NET "PHY_TXD7" LOC = AF11; ## 29 on U80 -NET "mtxerr_pad_o" LOC = AH10; ## 13 on U80 - -#-------------------------------- -# Pinout and Related I/O Constraints -#-------------------------------- - -# On ML605 kit, all clock pins are assigned to MRCC pins. However, two of them -# (fmc_adc1_clk and fmc_adc3_clk) are located in the outer left/right column -# I/Os. These locations cannot connect to BUFG primitives, only inner (center) -# left/right column I/Os on the same half top/bottom can! -# -# For 7-series FPGAs there is no such impediment, apparently. - -#-------------------------------- -# DIFF TERM -#-------------------------------- - -NET "sys_clk_p_i" DIFF_TERM = TRUE; -NET "sys_clk_n_i" DIFF_TERM = TRUE; - -NET "fmc_trig_val_p_b" DIFF_TERM = TRUE; -NET "fmc_trig_val_n_b" DIFF_TERM = TRUE; - -#NET "fmc_fpga_clk_p_i" DIFF_TERM = TRUE; -#NET "fmc_fpga_clk_n_i" DIFF_TERM = TRUE; - -#-------------------------------- -# Timing constraints -#-------------------------------- -#-------------------------------- -# Clocks -#-------------------------------- - -# 200 MHz onboard input clock -NET "sys_clk_p_i" TNM_NET = "sys_clk_group"; -TIMESPEC "TS_sys_clk_group" = PERIOD "sys_clk_group" 5 ns HIGH 50%; - -# 100 MHz wihsbone clock -NET "clk_sys" TNM_NET = "clk_sys_group"; -TIMESPEC "TS_clk_sys_group" = PERIOD "clk_sys_group" 10 ns HIGH 50%; - -# 200 MHz DDR3 and IDELAY CONTROL clock -NET "clk_200mhz" TNM_NET = TNM_200mhz_sys_clk; -TIMESPEC "TS_200mhz_sys_clk" = PERIOD "TNM_200mhz_sys_clk" 5 ns HIGH 50%; - -# 200 MHz DDR3 UI Clock -NET "*/u_infrastructure/clk_pll" TNM_NET = "TNM_ddr_sys_clk"; -TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns HIGH 50%; -NET "clk_sys" TNM_NET = "TNM_clk_sys_group_ffs"; -TIMESPEC TS_clk_sys_to_ddr3_ui_clk = FROM "TNM_clk_sys_group_ffs" TO "TNM_ddr_sys_clk" 10 ns DATAPATHONLY; - -// real jitter is about 22ps peak-to-peak -NET "fmc_adc0_clk_i" TNM_NET = fmc_adc0_clk_i; -// TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -//TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc1_clk_i" TNM_NET = fmc_adc1_clk_i; -// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc2_clk_i" TNM_NET = fmc_adc2_clk_i; -// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -NET "fmc_adc3_clk_i" TNM_NET = fmc_adc3_clk_i; -// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps; -// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps; -TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps; - -//NET "fmc_fpga_clk_p" TNM_NET = fmc_fpga_clk_p; -//TIMESPEC TS_fmc_fpga_clk_p = PERIOD "fmc_fpga_clk_p" 130 MHz HIGH 50% INPUT_JITTER 40 ps; - -#-------------------------------- -# Data -#-------------------------------- - -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc0_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc1_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y2; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc2_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y0; -#INST "fmc_adc_130m_4ch_i/ltcInterface_adc3_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; // same as ADC1 - -// including 50ps jitter, for 130MHz clock -// since design uses copy of input ADC clock -// there is additional delay for clock/ data (tC) - -INST "fmc_adc0_data_i<*>" TNM = fmc_adc0_data_i; -INST "fmc_adc1_data_i<*>" TNM = fmc_adc1_data_i; -INST "fmc_adc2_data_i<*>" TNM = fmc_adc2_data_i; -INST "fmc_adc3_data_i<*>" TNM = fmc_adc3_data_i; - -TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc0_clk_i"; -TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc1_clk_i"; -TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc2_clk_i"; -TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc3_clk_i"; - -#-------------------------------- -# PCIe constraints -#-------------------------------- -# -CONFIG PART = xc6vlx240t-ff1156-1; - -#-------------------------------- -# User Constraints -#-------------------------------- -#-------------------------------- -# User Time Names / User Time Groups / Time Specs -#-------------------------------- -#-------------------------------- -# User Physical Constraints -#-------------------------------- - -#PCIe reset -NET "pcie_rst_n_i" IOSTANDARD = "LVCMOS25" | PULLUP | NODELAY; -NET "pcie_rst_n_i" TIG; -# Bank 16 VCCO - VADJ_FPGA - IO_25_16 -NET "pcie_rst_n_i" LOC = AE13; -#PCIe reset -#PCIe clock -NET "pcie_clk_n_i" LOC = P5; -# Bank 115 - MGTREFCLK1N_115 -NET "pcie_clk_p_i" LOC = P6; - -#-------------------------------- -# DDR controller -#-------------------------------- -NET "ddr3_dq_b[0]" LOC = "J11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[1]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[2]" LOC = "F13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[3]" LOC = "K11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[4]" LOC = "L11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[5]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[6]" LOC = "K12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[7]" LOC = "D11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[8]" LOC = "M13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[9]" LOC = "J14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[10]" LOC = "B13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[11]" LOC = "B12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[12]" LOC = "G10" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[13]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[14]" LOC = "C12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[15]" LOC = "A11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[16]" LOC = "G11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[17]" LOC = "F11" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[18]" LOC = "D14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[19]" LOC = "C14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[20]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[21]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[23]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[24]" LOC = "C19" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[25]" LOC = "G20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[26]" LOC = "E19" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[27]" LOC = "F20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[28]" LOC = "A20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[29]" LOC = "A21" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[30]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[31]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[32]" LOC = "G21" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[33]" LOC = "B21" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[34]" LOC = "A23" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[35]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[36]" LOC = "C20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[37]" LOC = "D20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[38]" LOC = "J20" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[39]" LOC = "G22" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[40]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[41]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[42]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[43]" LOC = "E26" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[44]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[45]" LOC = "D25" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[46]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[47]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[48]" LOC = "C27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[49]" LOC = "B28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[50]" LOC = "D29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[51]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[52]" LOC = "G27" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[53]" LOC = "A28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[54]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[55]" LOC = "G25" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[56]" LOC = "F28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[57]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[58]" LOC = "H29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[59]" LOC = "H28" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[60]" LOC = "B30" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[61]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[62]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_dq_b[63]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI ; -NET "ddr3_addr_o[13]" LOC = "J15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[12]" LOC = "H15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[11]" LOC = "M15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[10]" LOC = "M16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[9]" LOC = "F15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[8]" LOC = "G15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[7]" LOC = "B15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[6]" LOC = "A15" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[5]" LOC = "J17" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[4]" LOC = "D16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[3]" LOC = "E16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[2]" LOC = "B16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[1]" LOC = "A16" | IOSTANDARD = SSTL15 ; -NET "ddr3_addr_o[0]" LOC = "L14" | IOSTANDARD = SSTL15 ; -NET "ddr3_ba_o[2]" LOC = "L15" | IOSTANDARD = SSTL15 ; -NET "ddr3_ba_o[1]" LOC = "J19" | IOSTANDARD = SSTL15 ; -NET "ddr3_ba_o[0]" LOC = "K19" | IOSTANDARD = SSTL15 ; -NET "ddr3_ras_n_o" LOC = "L19" | IOSTANDARD = SSTL15 ; -NET "ddr3_cas_n_o" LOC = "C17" | IOSTANDARD = SSTL15 ; -NET "ddr3_we_n_o" LOC = "B17" | IOSTANDARD = SSTL15 ; -NET "ddr3_reset_n_o" LOC = "E18" | IOSTANDARD = LVCMOS15 ; -NET "ddr3_cke_o[0]" LOC = "M18" | IOSTANDARD = SSTL15 ; -NET "ddr3_odt_o[0]" LOC = "F18" | IOSTANDARD = SSTL15 ; -NET "ddr3_cs_n_o[0]" LOC = "K18" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[0]" LOC = "E11" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[1]" LOC = "B11" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[2]" LOC = "E14" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[3]" LOC = "D19" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[4]" LOC = "B22" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[5]" LOC = "A26" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[6]" LOC = "A29" | IOSTANDARD = SSTL15 ; -NET "ddr3_dm_o[7]" LOC = "A31" | IOSTANDARD = SSTL15 ; -NET "ddr3_dqs_p_b[0]" LOC = "D12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[0]" LOC = "E12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[1]" LOC = "H12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[2]" LOC = "A13" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[2]" LOC = "A14" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[3]" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[3]" LOC = "H20" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[4]" LOC = "B23" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[4]" LOC = "C23" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[5]" LOC = "B25" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[5]" LOC = "A25" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[6]" LOC = "H27" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[6]" LOC = "G28" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_p_b[7]" LOC = "C30" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_dqs_n_b[7]" LOC = "D30" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -NET "ddr3_ck_p_o[0]" LOC = "G18" | IOSTANDARD = DIFF_SSTL15 ; -NET "ddr3_ck_n_o[0]" LOC = "H18" | IOSTANDARD = DIFF_SSTL15 ; -#NET "ddr_sys_clk_p_i" LOC = "J9" | IOSTANDARD = LVDS_25; -#NET "ddr_sys_clk_n_i" LOC = "H9" | IOSTANDARD = LVDS_25; - -#-------------------------------- -# Pinout and Related I/O Constraints -#-------------------------------- - -# -# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n -# signals are the PCI Express reference clock. Virtex-6 GT -# Transceiver architecture requires the use of a dedicated clock -# resources (FPGA input pins) associated with each GT Transceiver. -# To use these pins an IBUFDS primitive (refclk_ibuf) is -# instantiated in user's design. -# Please refer to the Virtex-6 GT Transceiver User Guide -# (UG) for guidelines regarding clock resource selection. -# - -INST "*/pcieclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6; - -# -# Transceiver instance placement. This constraint selects the -# transceivers to be used, which also dictates the pinout for the -# transmit and receive differential pairs. Please refer to the -# Virtex-6 GT Transceiver User Guide (UG) for more information. -# -# PCIe Lane 0 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX" LOC = GTXE1_X0Y15; -# PCIe Lane 1 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX" LOC = GTXE1_X0Y14; -# PCIe Lane 2 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX" LOC = GTXE1_X0Y13; -# PCIe Lane 3 -INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX" LOC = GTXE1_X0Y12; - -# -# PCI Express Block placement. This constraint selects the PCI Express -# Block to be used. -# -INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1; - - -# -# DDR controller component placement -# Check it after changing memory controller paramenters - -#-------------------------------- -#DCI_CASCADING -#Syntax : CONFIG DCI_CASCADE = " .."; -#-------------------------------- - -CONFIG DCI_CASCADE = "26 25";# -CONFIG DCI_CASCADE = "36 35";# - -#-------------------------------- -## The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must -## be a clock pin capable of spanning to all of the banks containing data bytes in the particular -## column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be -## used for other functions and should not be connected externally. If a different pin is chosen, -## he corresponding LOC constraint must also be changed. -#-------------------------------- -CONFIG PROHIBIT = C29,M12; - -#-------------------------------- -## The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock -## capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for -## this pin. This pin cannot be used for other functions and should not be connected externally. -## If a different pin is chosen, the corresponding LOC constraint must also be changed. -#-------------------------------- -CONFIG PROHIBIT = B20,C13,C28,D24,F21,F25,K14,L13; - -#-------------------------------- -#Place RSYNC OSERDES and IODELAYy -#-------------------------------- - -##Site: C29 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" - LOC = "OLOGIC_X1Y139"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" - LOC = "IODELAY_X1Y139"; - -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" - LOC = "BUFR_X1Y6"; - -##Site: M12 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" - LOC = "OLOGIC_X2Y139"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" - LOC = "IODELAY_X2Y139"; - -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" - LOC = "BUFR_X2Y6"; - -#-------------------------------- -# Place CPT OSERDES and IODELAY: -#-------------------------------- - -##Site: C13 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" - LOC = "OLOGIC_X2Y137"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" - LOC = "IODELAY_X2Y137"; - -##Site: L13 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" - LOC = "OLOGIC_X2Y141"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" - LOC = "IODELAY_X2Y141"; - -##Site: K14 -- Bank 35 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" - LOC = "OLOGIC_X2Y143"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" - LOC = "IODELAY_X2Y143"; - -##Site: F21 -- Bank 26 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" - LOC = "OLOGIC_X1Y179"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" - LOC = "IODELAY_X1Y179"; - -##Site: B20 -- Bank 26 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" - LOC = "OLOGIC_X1Y181"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" - LOC = "IODELAY_X1Y181"; - -##Site: F25 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" - LOC = "OLOGIC_X1Y137"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" - LOC = "IODELAY_X1Y137"; - -##Site: C28 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" - LOC = "OLOGIC_X1Y141"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" - LOC = "IODELAY_X1Y141"; - -##Site: D24 -- Bank 25 -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" - LOC = "OLOGIC_X1Y143"; -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" - LOC = "IODELAY_X1Y143"; - -INST "*/u_infrastructure/u_mmcm_adv" LOC = "MMCM_ADV_X0Y8"; #Banks 16, 26, 36 - -#-------------------------------- -# Timing Constraints -#-------------------------------- - -NET "*/sys_clk_c" TNM_NET = "SYSCLK" ; -NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; -NET "*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG"; - -TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ; -TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1 ; -TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ; - - -PIN "*/trn_reset_n_int_i.CLR" TIG ; -PIN "*/trn_reset_n_i.CLR" TIG ; -PIN "*/pcie_clocking_i/mmcm_adv_i.RST" TIG ; - -INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7; - -#-------------------------------- -# DDR -#-------------------------------- - -# Constrain BUFR clocks used to synchronize data from IOB to fabric logic -# Note that ISE cannot infer this from other PERIOD constraints because -# of the use of OSERDES blocks in the BUFR clock generation path -NET "*/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync[?]" TNM_NET = TNM_clk_rsync; -TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5 ns; - -# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling -# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for -# that particular flop. Mark this path as being a full-cycle, rather than -# a half cycle path for timing purposes. NOTE: This constraint forces full- -# cycle timing to be applied globally for all rising->falling edge paths -# in all resynchronizaton clock domains. If the user had modified the logic -# in the resync clock domain such that other rising->falling edge paths -# exist, then constraint below should be modified to utilize pattern -# matching to specific affect only the DQ/DQS ISERDES.Q outputs -TIMEGRP "TG_clk_rsync_rise" = RISING "TNM_clk_rsync"; -TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync"; -TIMESPEC "TS_clk_rsync_rise_to_fall" = - FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" "TS_ddr_sys_clk" * 4; - -# Signal to select between controller and physical layer signals. Four divided by two clock -# cycles (4 memory clock cycles) are provided by design for the signal to settle down. -# Used only by the phy modules. -INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL"; -TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_ddr_sys_clk"*8; - -#-------------------------------- -# Physical Constraints -#-------------------------------- - -## Constrain the PCIe core elements placement, so that it won't fail -## timing analysis. -## Comment out because we use nonstandard GTP location -#INST "*/pcie_core_i" AREA_GROUP = "GRP_PCIE_CORE"; -#AREA_GROUP "GRP_PCIE_CORE" RANGE = CLOCKREGION_X0Y4; -# -## Place the DMA design not far from PCIe core, otherwise it also breaks timing -#INST "*/theTlpControl" AREA_GROUP = "GRP_tlpControl"; -#AREA_GROUP "GRP_tlpControl" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y4; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd deleted file mode 100755 index 41df99c5..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd +++ /dev/null @@ -1,1725 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top FMC516 design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2013-09-26 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control between pcie and --- the crossbar -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2013-09-26 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_generic_pkg.all; --- Ethernet MAC Modules and SDB structure -use work.ethmac_pkg.all; --- Wishbone Fabric interface -use work.wr_fabric_pkg.all; --- Etherbone slave core -use work.etherbone_pkg.all; --- FMC516 definitions -use work.fmc_adc_pkg.all; --- Data Acquisition core -use work.acq_core_pkg.all; --- PCIe Core -use work.bpm_pcie_ml605_pkg.all; -use work.bpm_pcie_ml605_priv_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_fmc130m_4ch_pcie is -generic( - -- PCIe Lanes - g_pcieLanes : integer := 4; - -- PCIE Constants. TEMPORARY! - constant pcieLanes : integer := 4; - constant DDR_DQ_WIDTH : integer := 64; - constant DDR_PAYLOAD_WIDTH : integer := 256; - constant DDR_DQS_WIDTH : integer := 8; - constant DDR_DM_WIDTH : integer := 8; - constant DDR_ROW_WIDTH : integer := 14; - constant DDR_BANK_WIDTH : integer := 3; - constant DDR_CK_WIDTH : integer := 1; - constant DDR_CKE_WIDTH : integer := 1; - constant DDR_ODT_WIDTH : integer := 1 -); -port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - rs232_txd_o : out std_logic; - rs232_rxd_i : in std_logic; - - ----------------------------------------- - -- PHY pins - ----------------------------------------- - - -- Clock and resets to PHY (GMII). Not used in MII mode (10/100) - mgtx_clk_o : out std_logic; - mrstn_o : out std_logic; - - -- PHY TX - mtx_clk_pad_i : in std_logic; - mtxd_pad_o : out std_logic_vector(3 downto 0); - mtxen_pad_o : out std_logic; - mtxerr_pad_o : out std_logic; - - -- PHY RX - mrx_clk_pad_i : in std_logic; - mrxd_pad_i : in std_logic_vector(3 downto 0); - mrxdv_pad_i : in std_logic; - mrxerr_pad_i : in std_logic; - mcoll_pad_i : in std_logic; - mcrs_pad_i : in std_logic; - - -- MII - mdc_pad_o : out std_logic; - md_pad_b : inout std_logic; - - ----------------------------- - -- FMC130m_4ch ports - ----------------------------- - - -- ADC LTC2208 interface - fmc_adc_pga_o : out std_logic; - fmc_adc_shdn_o : out std_logic; - fmc_adc_dith_o : out std_logic; - fmc_adc_rand_o : out std_logic; - - -- ADC0 LTC2208 - fmc_adc0_clk_i : in std_logic; - fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc0_of_i : in std_logic; -- Unused - - -- ADC1 LTC2208 - fmc_adc1_clk_i : in std_logic; - fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc1_of_i : in std_logic; -- Unused - - -- ADC2 LTC2208 - fmc_adc2_clk_i : in std_logic; - fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc2_of_i : in std_logic; -- Unused - - -- ADC3 LTC2208 - fmc_adc3_clk_i : in std_logic; - fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0); - fmc_adc3_of_i : in std_logic; -- Unused - - -- FMC General Status - fmc_prsnt_i : in std_logic; - fmc_pg_m2c_i : in std_logic; - --fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board - - -- Trigger - fmc_trig_dir_o : out std_logic; - fmc_trig_term_o : out std_logic; - fmc_trig_val_p_b : inout std_logic; - fmc_trig_val_n_b : inout std_logic; - - -- Si571 clock gen - si571_scl_pad_b : inout std_logic; - si571_sda_pad_b : inout std_logic; - fmc_si571_oe_o : out std_logic; - - -- AD9510 clock distribution PLL - spi_ad9510_cs_o : out std_logic; - spi_ad9510_sclk_o : out std_logic; - spi_ad9510_mosi_o : out std_logic; - spi_ad9510_miso_i : in std_logic; - - fmc_pll_function_o : out std_logic; - fmc_pll_status_i : in std_logic; - - -- AD9510 clock copy - fmc_fpga_clk_p_i : in std_logic; - fmc_fpga_clk_n_i : in std_logic; - - -- Clock reference selection (TS3USB221) - fmc_clk_sel_o : out std_logic; - - -- EEPROM - eeprom_scl_pad_b : inout std_logic; - eeprom_sda_pad_b : inout std_logic; - - -- Temperature monitor - -- LM75AIMM - lm75_scl_pad_b : inout std_logic; - lm75_sda_pad_b : inout std_logic; - - fmc_lm75_temp_alarm_i : in std_logic; - - -- FMC LEDs - fmc_led1_o : out std_logic; - fmc_led2_o : out std_logic; - fmc_led3_o : out std_logic; - - ----------------------------------------- - -- General board status - ----------------------------------------- - fmc_mmcm_lock_led_o : out std_logic; - fmc_pll_status_led_o : out std_logic; - - ----------------------------------------- - -- PCIe pins - ----------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p_b : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n_b : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); - ddr3_addr_o : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0); - ddr3_ba_o : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0); - ddr3_cs_n_o : out std_logic_vector(0 downto 0); - ddr3_ras_n_o : out std_logic; - ddr3_cas_n_o : out std_logic; - ddr3_we_n_o : out std_logic; - ddr3_reset_n_o : out std_logic; - ddr3_ck_p_o : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n_o : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); - ddr3_cke_o : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0); - ddr3_dm_o : out std_logic_vector(DDR_DM_WIDTH-1 downto 0); - ddr3_odt_o : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0); - - -- PCIe transceivers - pci_exp_rxp_i : in std_logic_vector(g_pcieLanes - 1 downto 0); - pci_exp_rxn_i : in std_logic_vector(g_pcieLanes - 1 downto 0); - pci_exp_txp_o : out std_logic_vector(g_pcieLanes - 1 downto 0); - pci_exp_txn_o : out std_logic_vector(g_pcieLanes - 1 downto 0); - - -- PCI clock and reset signals - pcie_rst_n_i : in std_logic; - pcie_clk_p_i : in std_logic; - pcie_clk_n_i : in std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - --buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - - -- Directional leds - --led_south_o : out std_logic; - --led_east_o : out std_logic; - --led_north_o : out std_logic; - - -- GPIO leds - leds_o : out std_logic_vector(7 downto 0) -); -end dbe_bpm_fmc130m_4ch_pcie; - -architecture rtl of dbe_bpm_fmc130m_4ch_pcie is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 10; - -- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC, - --Etherbone, FMC516, Peripherals - -- Number of masters - --constant c_masters : natural := 9; -- LM32 master, Data + Instruction, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon - constant c_masters : natural := 8; -- RS232-Syscon, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, PCIe - - --constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB) - constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB) - --constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB) - constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB) - - constant c_acq_fifo_size : natural := 256; - - -- TEMPORARY! DON'T TOUCH! - --constant c_acq_data_width : natural := 64; - constant c_acq_addr_width : natural := 28; - constant c_acq_ddr_payload_width : natural := DDR_PAYLOAD_WIDTH; -- DDR3 UI (256 bits) - constant c_acq_ddr_addr_width : natural := 28; - constant c_acq_ddr_addr_res_width : natural := 32; - constant c_acq_ddr_addr_diff : natural := c_acq_ddr_addr_res_width-c_acq_ddr_addr_width; - constant c_acq_adc_id : natural := 0; - constant c_acq_tbt_id : natural := 1; - constant c_acq_fofb_id : natural := 2; - constant c_acq_monit_id : natural := 3; - constant c_acq_monit_1_id : natural := 4; - constant c_acq_num_channels : natural := 5; -- ADC + TBT + FOFB + MONIT + MONIT_1 - constant c_acq_channels : t_acq_chan_param_array(c_acq_num_channels-1 downto 0) := - ( c_acq_adc_id => (width => to_unsigned(64, c_acq_chan_max_w_log2)), - c_acq_tbt_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_fofb_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_monit_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)), - c_acq_monit_1_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)) - ); - - -- DDR3 constants - constant c_ddr_dq_width : natural := 64; - - -- GPIO num pinscalc - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- TICs counter period. 100MHz clock -> msec granularity - constant c_tics_cntr_period : natural := 100000; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - -- number of the ADC reference clock used for all downstream - -- FPGA logic - constant c_adc_ref_clk : natural := 1; - - -- Number of top level clocks - constant c_num_tlvl_clks : natural := 2; -- CLK_SYS and CLK_200 MHz - constant c_clk_sys_id : natural := 0; -- CLK_SYS and CLK_200 MHz - constant c_clk_200mhz_id : natural := 1; -- CLK_SYS and CLK_200 MHz - - constant c_xwb_etherbone_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"0000000000000651", -- GSI - device_id => x"68202b22", - version => x"00000001", - date => x"20120912", - name => "GSI_ETHERBONE_CFG "))); - - constant c_xwb_ethmac_adapter_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"1000000000001215", -- LNLS - device_id => x"2ff9a28e", - version => x"00000001", - date => x"20130701", - name => "ETHMAC_ADAPTER "))); - - -- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure - -- no address overlaps will occur - --constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - -- FMC130m_4ch - constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - - -- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter - constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400"); - - -- WB SDB (Self describing bus) layout - --constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - -- ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM - -- 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory - -- 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - -- x"20000000"), -- 64KB RAM - -- 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port - -- 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port - -- 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port - -- 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port - -- 7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port - -- 8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000"), -- General peripherals control port - -- 9 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"30030000") -- Data Acquisition control port - -- ); - -- Changed due to the limitation in PCIe addressing. Only up to 29 bits - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00100000"), -- Second port to the same memory - 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - x"00200000"), -- 64KB RAM - 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"00304000"), -- DMA control port - 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"00305000"), -- Ethernet MAC control port - 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"00306000"), -- Ethernet Adapter control port - 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"00307000"), -- Etherbone control port - 7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"00310000"), -- FMC130m_4ch control port - 8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"00320000"), -- General peripherals control port - 9 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"00330000") -- Data Acquisition control port - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well - constant c_sdb_address : t_wishbone_address := x"00300000"; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- PCIe signals - signal wb_ma_pcie_ack_in : std_logic; - signal wb_ma_pcie_dat_in : std_logic_vector(63 downto 0); - signal wb_ma_pcie_addr_out : std_logic_vector(28 downto 0); - signal wb_ma_pcie_dat_out : std_logic_vector(63 downto 0); - signal wb_ma_pcie_we_out : std_logic; - signal wb_ma_pcie_stb_out : std_logic; - signal wb_ma_pcie_sel_out : std_logic; - signal wb_ma_pcie_cyc_out : std_logic; - - signal wb_ma_pcie_rst : std_logic; - signal wb_ma_pcie_rstn : std_logic; - - signal wb_ma_sladp_pcie_ack_in : std_logic; - signal wb_ma_sladp_pcie_dat_in : std_logic_vector(31 downto 0); - signal wb_ma_sladp_pcie_addr_out : std_logic_vector(31 downto 0); - signal wb_ma_sladp_pcie_dat_out : std_logic_vector(31 downto 0); - signal wb_ma_sladp_pcie_we_out : std_logic; - signal wb_ma_sladp_pcie_stb_out : std_logic; - signal wb_ma_sladp_pcie_sel_out : std_logic_vector(3 downto 0); - signal wb_ma_sladp_pcie_cyc_out : std_logic; - - -- PCIe Debug signals - - signal dbg_app_addr : std_logic_vector(31 downto 0); - signal dbg_app_cmd : std_logic_vector(2 downto 0); - signal dbg_app_en : std_logic; - signal dbg_app_wdf_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); - signal dbg_app_wdf_end : std_logic; - signal dbg_app_wdf_wren : std_logic; - signal dbg_app_wdf_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0); - signal dbg_app_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); - signal dbg_app_rd_data_end : std_logic; - signal dbg_app_rd_data_valid : std_logic; - signal dbg_app_rdy : std_logic; - signal dbg_app_wdf_rdy : std_logic; - signal dbg_ddr_ui_clk : std_logic; - signal dbg_ddr_ui_reset : std_logic; - - signal dbg_arb_req : std_logic_vector(1 downto 0); - signal dbg_arb_gnt : std_logic_vector(1 downto 0); - - -- To/From Acquisition Core - signal acq_chan_array : t_acq_chan_array(c_acq_num_channels-1 downto 0); - - signal bpm_acq_dpram_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0); - signal bpm_acq_dpram_valid : std_logic; - - signal bpm_acq_ext_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0); - signal bpm_acq_ext_valid : std_logic; - signal bpm_acq_ext_addr : std_logic_vector(c_acq_addr_width-1 downto 0); - signal bpm_acq_ext_sof : std_logic; - signal bpm_acq_ext_eof : std_logic; - signal bpm_acq_ext_dreq : std_logic; - signal bpm_acq_ext_stall : std_logic; - - signal memc_ui_clk : std_logic; - signal memc_ui_rst : std_logic; - signal memc_ui_rstn : std_logic; - signal memc_cmd_rdy : std_logic; - signal memc_cmd_en : std_logic; - signal memc_cmd_instr : std_logic_vector(2 downto 0); - signal memc_cmd_addr_resized : std_logic_vector(c_acq_ddr_addr_res_width-1 downto 0); - signal memc_cmd_addr : std_logic_vector(c_acq_ddr_addr_width-1 downto 0); - signal memc_wr_en : std_logic; - signal memc_wr_end : std_logic; - signal memc_wr_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0); - signal memc_wr_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); - signal memc_wr_rdy : std_logic; - signal memc_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); - signal memc_rd_valid : std_logic; - - signal dbg_ddr_rb_data : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0); - signal dbg_ddr_rb_addr : std_logic_vector(c_acq_addr_width-1 downto 0); - signal dbg_ddr_rb_valid : std_logic; - - -- memory arbiter interface - signal memarb_acc_req : std_logic; - signal memarb_acc_gnt : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - signal clk_200mhz_rst : std_logic; - signal clk_200mhz_rstn : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - signal rs232_rstn : std_logic; - - -- Only one clock domain - signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0); - signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0); - - -- 200 Mhz clocck for iodelay_ctrl - signal clk_200mhz : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - signal sys_clk_gen_bufg : std_logic; - - -- Ethernet MAC signals - signal ethmac_int : std_logic; - signal ethmac_md_in : std_logic; - signal ethmac_md_out : std_logic; - signal ethmac_md_oe : std_logic; - - signal mtxd_pad_int : std_logic_vector(3 downto 0); - signal mtxen_pad_int : std_logic; - signal mtxerr_pad_int : std_logic; - signal mdc_pad_int : std_logic; - - -- Ethrnet MAC adapter signals - signal irq_rx_done : std_logic; - signal irq_tx_done : std_logic; - - -- Etherbone signals - signal wb_ebone_out : t_wishbone_master_out; - signal wb_ebone_in : t_wishbone_master_in; - - signal eb_src_i : t_wrf_source_in; - signal eb_src_o : t_wrf_source_out; - signal eb_snk_i : t_wrf_sink_in; - signal eb_snk_o : t_wrf_sink_out; - - -- DMA signals - signal dma_int : std_logic; - - -- FMC130m_4ch Signals - signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0); - signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0); - - signal fmc_mmcm_lock_int : std_logic; - signal fmc_pll_status_int : std_logic; - - signal fmc_led1_int : std_logic; - signal fmc_led2_int : std_logic; - signal fmc_led3_int : std_logic; - - signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0); - signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal fmc_debug : std_logic; - signal reset_adc_counter : unsigned(6 downto 0) := (others => '0'); - signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0); - - -- fmc130m_4ch Debug - signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0); - - signal sys_spi_clk_int : std_logic; - --signal sys_spi_data_int : std_logic; - signal sys_spi_dout_int : std_logic; - signal sys_spi_din_int : std_logic; - signal sys_spi_miosio_oe_n_int : std_logic; - signal sys_spi_cs_adc0_n_int : std_logic; - signal sys_spi_cs_adc1_n_int : std_logic; - signal sys_spi_cs_adc2_n_int : std_logic; - signal sys_spi_cs_adc3_n_int : std_logic; - - signal lmk_lock_int : std_logic; - signal lmk_sync_int : std_logic; - signal lmk_uwire_latch_en_int : std_logic; - signal lmk_uwire_data_int : std_logic; - signal lmk_uwire_clock_int : std_logic; - - signal fmc_reset_adcs_n_int : std_logic; - signal fmc_reset_adcs_n_out : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - signal buttons_dummy : std_logic_vector(7 downto 0); - - -- Counter signal - --signal s_counter : unsigned(c_counter_width-1 downto 0); - -- 100MHz period or 1 second - --constant s_counter_full : integer := 100000000; - - -- Chipscope control signals - signal CONTROL0 : std_logic_vector(35 downto 0); - signal CONTROL1 : std_logic_vector(35 downto 0); - signal CONTROL2 : std_logic_vector(35 downto 0); - signal CONTROL3 : std_logic_vector(35 downto 0); - signal CONTROL4 : std_logic_vector(35 downto 0); - signal CONTROL5 : std_logic_vector(35 downto 0); - - -- Chipscope ILA 0 signals - signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 1 signals - signal TRIG_ILA1_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 2 signals - signal TRIG_ILA2_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 3 signals - signal TRIG_ILA3_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 4 signals - signal TRIG_ILA4_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA4_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA4_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA4_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 5 signals - signal TRIG_ILA5_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA5_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA5_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA5_3 : std_logic_vector(31 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic; - sys_clk_bufg_o : out std_logic - ); - end component; - - -- Xilinx Megafunction - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Controller 2 port - --component chipscope_icon_2_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0) - --); - --end component; - - --component chipscope_icon_4_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0); - -- CONTROL2 : inout std_logic_vector(35 downto 0); - -- CONTROL3 : inout std_logic_vector(35 downto 0) - --); - --end component; - - component chipscope_icon_6_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0); - CONTROL2 : inout std_logic_vector(35 downto 0); - CONTROL3 : inout std_logic_vector(35 downto 0); - CONTROL4 : inout std_logic_vector(35 downto 0); - CONTROL5 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; - -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen, - sys_clk_bufg_o => sys_clk_gen_bufg - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - --clk_i => sys_clk_gen, - clk_i => sys_clk_gen_bufg, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200 - ) - port map( - --free_clk_i => sys_clk_gen, - free_clk_i => sys_clk_gen_bufg, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(c_clk_sys_id) <= clk_sys; - reset_clks(c_clk_200mhz_id) <= clk_200mhz; - clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and - rs232_rstn and wb_ma_pcie_rstn; - clk_sys_rst <= not clk_sys_rstn; - mrstn_o <= clk_sys_rstn; - clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id); - clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id)); - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => true, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - --lm32_rstn <= clk_sys_rstn; - - --cmp_lm32 : xwb_lm32 - --generic map( - -- g_profile => "medium_icache_debug" - --) -- Including JTAG and I-cache (no divide) - --port map( - -- clk_sys_i => clk_sys, - -- rst_n_i => lm32_rstn, - -- irq_i => lm32_interrupt, - -- dwb_o => cbar_slave_i(0), -- Data bus - -- dwb_i => cbar_slave_o(0), - -- iwb_o => cbar_slave_i(1), -- Instruction bus - -- iwb_i => cbar_slave_o(1) - --); - - -- Interrupt '0' is Ethmac. - -- Interrupt '1' is DMA completion. - -- Interrupt '2' is Button(0). - -- Interrupt '3' is Ethernet Adapter RX completion. - -- Interrupt '4' is Ethernet Adapter TX completion. - -- Interrupts 31 downto 5 are disabled - - --lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done, - -- 4 => irq_tx_done, others => '0'); - - ---------------------------------- - -- PCIe Core -- - ---------------------------------- - cmp_bpm_pcie_ml605 : bpm_pcie_ml605 - generic map ( - SIM_BYPASS_INIT_CAL => "OFF" -- Full calibration sequence - ) - port map ( - --DDR3 memory pins - ddr3_dq => ddr3_dq_b, - ddr3_dqs_p => ddr3_dqs_p_b, - ddr3_dqs_n => ddr3_dqs_n_b, - ddr3_addr => ddr3_addr_o, - ddr3_ba => ddr3_ba_o, - ddr3_cs_n => ddr3_cs_n_o, - ddr3_ras_n => ddr3_ras_n_o, - ddr3_cas_n => ddr3_cas_n_o, - ddr3_we_n => ddr3_we_n_o, - ddr3_reset_n => ddr3_reset_n_o, - ddr3_ck_p => ddr3_ck_p_o, - ddr3_ck_n => ddr3_ck_n_o, - ddr3_cke => ddr3_cke_o, - ddr3_dm => ddr3_dm_o, - ddr3_odt => ddr3_odt_o, - -- PCIe transceivers - pci_exp_rxp => pci_exp_rxp_i, - pci_exp_rxn => pci_exp_rxn_i, - pci_exp_txp => pci_exp_txp_o, - pci_exp_txn => pci_exp_txn_o, - -- Necessity signals - ddr_sys_clk_p => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL) - --ddr_sys_clk_p => sys_clk_gen_bufg, --200 MHz DDR core clock (connect through BUFG or PLL) - sys_clk_p => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin) - sys_clk_n => pcie_clk_n_i, --100 MHz PCIe Clock - sys_rst_n => pcie_rst_n_i, -- PCIe core reset - - -- DDR memory controller interface -- - ddr_core_rst => wb_ma_pcie_rst, - memc_ui_clk => memc_ui_clk, - memc_ui_rst => memc_ui_rst, - memc_cmd_rdy => memc_cmd_rdy, - memc_cmd_en => memc_cmd_en, - memc_cmd_instr => memc_cmd_instr, - --memc_cmd_addr => memc_cmd_addr, - memc_cmd_addr => memc_cmd_addr_resized, - memc_wr_en => memc_wr_en, - memc_wr_end => memc_wr_end, - memc_wr_mask => memc_wr_mask, - memc_wr_data => memc_wr_data, - memc_wr_rdy => memc_wr_rdy, - memc_rd_data => memc_rd_data, - memc_rd_valid => memc_rd_valid, - -- memory arbiter interface - memarb_acc_req => memarb_acc_req, - memarb_acc_gnt => memarb_acc_gnt, - --/ DDR memory controller interface - - -- Wishbone interface -- - -- uncomment when instantiating in another project - clk_i => clk_sys, - rst_i => clk_sys_rst, - ack_i => wb_ma_pcie_ack_in, - dat_i => wb_ma_pcie_dat_in, - addr_o => wb_ma_pcie_addr_out, - dat_o => wb_ma_pcie_dat_out, - we_o => wb_ma_pcie_we_out, - stb_o => wb_ma_pcie_stb_out, - sel_o => wb_ma_pcie_sel_out, - cyc_o => wb_ma_pcie_cyc_out, - --/ Wishbone interface - -- Additional exported signals for instantiation - ext_rst_o => wb_ma_pcie_rst, - - -- Debug signals - dbg_app_addr_o => dbg_app_addr, - dbg_app_cmd_o => dbg_app_cmd, - dbg_app_en_o => dbg_app_en, - dbg_app_wdf_data_o => dbg_app_wdf_data, - dbg_app_wdf_end_o => dbg_app_wdf_end, - dbg_app_wdf_wren_o => dbg_app_wdf_wren, - dbg_app_wdf_mask_o => dbg_app_wdf_mask, - dbg_app_rd_data_o => dbg_app_rd_data, - dbg_app_rd_data_end_o => dbg_app_rd_data_end, - dbg_app_rd_data_valid_o => dbg_app_rd_data_valid, - dbg_app_rdy_o => dbg_app_rdy, - dbg_app_wdf_rdy_o => dbg_app_wdf_rdy, - dbg_ddr_ui_clk_o => dbg_ddr_ui_clk, - dbg_ddr_ui_reset_o => dbg_ddr_ui_reset, - - dbg_arb_req_o => dbg_arb_req, - dbg_arb_gnt_o => dbg_arb_gnt - ); - - wb_ma_pcie_rstn <= not(wb_ma_pcie_rst); - - cmp_pcie_ma_iface_slave_adapter : wb_slave_adapter - generic map ( - g_master_use_struct => true, - g_master_mode => PIPELINED, - g_master_granularity => WORD, - g_slave_use_struct => false, - g_slave_mode => CLASSIC, - g_slave_granularity => WORD - ) - port map ( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - sl_adr_i => wb_ma_sladp_pcie_addr_out, - sl_dat_i => wb_ma_sladp_pcie_dat_out, - sl_sel_i => wb_ma_sladp_pcie_sel_out, - sl_cyc_i => wb_ma_sladp_pcie_cyc_out, - sl_stb_i => wb_ma_sladp_pcie_stb_out, - sl_we_i => wb_ma_sladp_pcie_we_out, - sl_dat_o => wb_ma_sladp_pcie_dat_in, - sl_ack_o => wb_ma_sladp_pcie_ack_in, - sl_stall_o => open, - sl_int_o => open, - sl_rty_o => open, - sl_err_o => open, - - master_i => cbar_slave_o(0), - master_o => cbar_slave_i(0) - ); - - -- Connect PCIe to the Wishbone Crossbar - wb_ma_sladp_pcie_addr_out(wb_ma_sladp_pcie_addr_out'left downto wb_ma_pcie_addr_out'left+1) - <= (others => '0'); - wb_ma_sladp_pcie_addr_out(wb_ma_pcie_addr_out'left downto 0) - <= wb_ma_pcie_addr_out; - wb_ma_sladp_pcie_dat_out <= wb_ma_pcie_dat_out(wb_ma_sladp_pcie_dat_out'left downto 0); - wb_ma_sladp_pcie_sel_out <= wb_ma_pcie_sel_out & wb_ma_pcie_sel_out & - wb_ma_pcie_sel_out & wb_ma_pcie_sel_out; - wb_ma_sladp_pcie_cyc_out <= wb_ma_pcie_cyc_out; - wb_ma_sladp_pcie_stb_out <= wb_ma_pcie_stb_out; - wb_ma_sladp_pcie_we_out <= wb_ma_pcie_we_out; - wb_ma_pcie_dat_in(wb_ma_pcie_dat_in'left downto wb_ma_sladp_pcie_dat_in'left+1) - <= (others => '0'); - wb_ma_pcie_dat_in(wb_ma_sladp_pcie_dat_in'left downto 0) - <= wb_ma_sladp_pcie_dat_in; - - wb_ma_pcie_ack_in <= wb_ma_sladp_pcie_ack_in; - - cmp_xwb_rs232_syscon : xwb_rs232_syscon - generic map ( - g_ma_interface_mode => PIPELINED, - g_ma_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rstn_i => '1', -- No need for resetting the controller - - -- External ports - rs232_rxd_i => rs232_rxd_i, - rs232_txd_o => rs232_txd_o, - - -- Reset to FPGA logic - rstn_o => rs232_rstn, - - -- WISHBONE master - wb_master_i => cbar_slave_o(1), - wb_master_o => cbar_slave_i(1) - ); - - -- A DMA controller is master 2+3, slave 3, and interrupt 1 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(3), - slave_o => cbar_master_i(3), - r_master_i => cbar_slave_o(2), - r_master_o => cbar_slave_i(2), - w_master_i => cbar_slave_o(3), - w_master_o => cbar_slave_i(3), - interrupt_o => dma_int - ); - - -- Slave 0+1 is the RAM. Load a input file containing the embedded software - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - --g_init_file => "../../../../embedded-sw/rampdata.ram", -- Ramp Data for testing PCIe - g_init_file => "", - --g_must_have_init_file => true, - g_must_have_init_file => false, - --g_slave1_interface_mode => PIPELINED, - --g_slave2_interface_mode => PIPELINED, - --g_slave1_granularity => BYTE, - --g_slave2_granularity => BYTE - g_slave1_interface_mode => CLASSIC, - g_slave2_interface_mode => CLASSIC, - g_slave1_granularity => WORD, - g_slave2_granularity => WORD - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - ); - - -- Slave 2 is the RAM Buffer for Ethernet MAC. - cmp_ethmac_buf_ram : xwb_dpram - generic map( - g_size => c_dpram_ethbuf_size, - g_init_file => "", - g_must_have_init_file => false, - g_slave1_interface_mode => CLASSIC, - --g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE - --g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(2), - slave1_o => cbar_master_i(2), - -- Second port connected to the crossbar - slave2_i => cc_dummy_slave_in, -- CYC always low - slave2_o => open - ); - - -- The Ethernet MAC is master 4, slave 4 - cmp_xwb_ethmac : xwb_ethmac - generic map ( - --g_ma_interface_mode => PIPELINED, - g_ma_interface_mode => CLASSIC, -- NOT used for now - --g_ma_address_granularity => WORD, - g_ma_address_granularity => BYTE, -- NOT used for now - g_sl_interface_mode => PIPELINED, - --g_sl_interface_mode => CLASSIC, - --g_sl_address_granularity => WORD - g_sl_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - - -- WISHBONE slave - wb_slave_in => cbar_master_o(4), - wb_slave_out => cbar_master_i(4), - - -- WISHBONE master - wb_master_in => cbar_slave_o(4), - wb_master_out => cbar_slave_i(4), - - -- PHY TX - mtx_clk_pad_i => mtx_clk_pad_i, - --mtxd_pad_o => mtxd_pad_o, - mtxd_pad_o => mtxd_pad_int, - --mtxen_pad_o => mtxen_pad_o, - mtxen_pad_o => mtxen_pad_int, - --mtxerr_pad_o => mtxerr_pad_o, - mtxerr_pad_o => mtxerr_pad_int, - - -- PHY RX - mrx_clk_pad_i => mrx_clk_pad_i, - mrxd_pad_i => mrxd_pad_i, - mrxdv_pad_i => mrxdv_pad_i, - mrxerr_pad_i => mrxerr_pad_i, - mcoll_pad_i => mcoll_pad_i, - mcrs_pad_i => mcrs_pad_i, - - -- MII - --mdc_pad_o => mdc_pad_o, - mdc_pad_o => mdc_pad_int, - md_pad_i => ethmac_md_in, - md_pad_o => ethmac_md_out, - md_padoe_o => ethmac_md_oe, - - -- Interrupt - int_o => ethmac_int - ); - - -- Tri-state buffer for MII config - md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z'; - ethmac_md_in <= md_pad_b; - - mtxd_pad_o <= mtxd_pad_int; - mtxen_pad_o <= mtxen_pad_int; - mtxerr_pad_o <= mtxerr_pad_int; - mdc_pad_o <= mdc_pad_int; - - -- The Ethernet MAC Adapter is master 5+6, slave 5 - cmp_xwb_ethmac_adapter : xwb_ethmac_adapter - port map( - clk_i => clk_sys, - rstn_i => clk_sys_rstn, - - wb_slave_o => cbar_master_i(5), - wb_slave_i => cbar_master_o(5), - - tx_ram_o => cbar_slave_i(5), - tx_ram_i => cbar_slave_o(5), - - rx_ram_o => cbar_slave_i(6), - rx_ram_i => cbar_slave_o(6), - - rx_eb_o => eb_snk_i, - rx_eb_i => eb_snk_o, - - tx_eb_o => eb_src_i, - tx_eb_i => eb_src_o, - - irq_tx_done_o => irq_tx_done, - irq_rx_done_o => irq_rx_done - ); - - -- The Etherbone is slave 6 - cmp_eb_slave_core : eb_slave_core - generic map( - g_sdb_address => x"00000000" & c_sdb_address - ) - port map - ( - clk_i => clk_sys, - nRst_i => clk_sys_rstn, - - -- EB streaming sink - snk_i => eb_snk_i, - snk_o => eb_snk_o, - - -- EB streaming source - src_i => eb_src_i, - src_o => eb_src_o, - - -- WB slave - Cfg IF - cfg_slave_o => cbar_master_i(6), - cfg_slave_i => cbar_master_o(6), - - -- WB master - Bus IF - master_o => wb_ebone_out, - master_i => wb_ebone_in - ); - - cbar_slave_i(7) <= wb_ebone_out; - wb_ebone_in <= cbar_slave_o(7); - - -- The FMC130M_4CH is slave 7 - cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch - generic map( - g_fpga_device => "VIRTEX6", - g_interface_mode => PIPELINED, - --g_address_granularity => WORD, - g_address_granularity => BYTE, - --g_adc_clk_period_values => default_adc_clk_period_values, - g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88), - --g_use_clk_chains => default_clk_use_chain, - -- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair) - -- using clock0 from fmc130m_4ch. - -- BUFIO can drive half-bank only, not the full IO bank - g_use_clk_chains => "1111", - g_with_bufio_clk_chains => "0000", - g_with_bufr_clk_chains => "1111", - g_use_data_chains => "1111", - --g_map_clk_data_chains => (-1,-1,-1,-1), - -- Clock 1 is the adc reference clock - g_ref_clk => c_adc_ref_clk, - g_packet_size => 32, - g_sim => 0 - ) - port map( - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - sys_clk_200Mhz_i => clk_200mhz, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(7), - wb_slv_o => cbar_master_i(7), - - ----------------------------- - -- External ports - ----------------------------- - - -- ADC LTC2208 interface - fmc_adc_pga_o => fmc_adc_pga_o, - fmc_adc_shdn_o => fmc_adc_shdn_o, - fmc_adc_dith_o => fmc_adc_dith_o, - fmc_adc_rand_o => fmc_adc_rand_o, - - -- ADC0 LTC2208 - fmc_adc0_clk_i => fmc_adc0_clk_i, - fmc_adc0_data_i => fmc_adc0_data_i, - fmc_adc0_of_i => fmc_adc0_of_i, - - -- ADC1 LTC2208 - fmc_adc1_clk_i => fmc_adc1_clk_i, - fmc_adc1_data_i => fmc_adc1_data_i, - fmc_adc1_of_i => fmc_adc1_of_i, - - -- ADC2 LTC2208 - fmc_adc2_clk_i => fmc_adc2_clk_i, - fmc_adc2_data_i => fmc_adc2_data_i, - fmc_adc2_of_i => fmc_adc2_of_i, - - -- ADC3 LTC2208 - fmc_adc3_clk_i => fmc_adc3_clk_i, - fmc_adc3_data_i => fmc_adc3_data_i, - fmc_adc3_of_i => fmc_adc3_of_i, - - -- FMC General Status - fmc_prsnt_i => fmc_prsnt_i, - fmc_pg_m2c_i => fmc_pg_m2c_i, - - -- Trigger - fmc_trig_dir_o => fmc_trig_dir_o, - fmc_trig_term_o => fmc_trig_term_o, - fmc_trig_val_p_b => fmc_trig_val_p_b, - fmc_trig_val_n_b => fmc_trig_val_n_b, - - -- Si571 clock gen - si571_scl_pad_b => si571_scl_pad_b, - si571_sda_pad_b => si571_sda_pad_b, - fmc_si571_oe_o => fmc_si571_oe_o, - - -- AD9510 clock distribution PLL - spi_ad9510_cs_o => spi_ad9510_cs_o, - spi_ad9510_sclk_o => spi_ad9510_sclk_o, - spi_ad9510_mosi_o => spi_ad9510_mosi_o, - spi_ad9510_miso_i => spi_ad9510_miso_i, - - fmc_pll_function_o => fmc_pll_function_o, - fmc_pll_status_i => fmc_pll_status_i, - - -- AD9510 clock copy - fmc_fpga_clk_p_i => fmc_fpga_clk_p_i, - fmc_fpga_clk_n_i => fmc_fpga_clk_n_i, - - -- Clock reference selection (TS3USB221) - fmc_clk_sel_o => fmc_clk_sel_o, - - -- EEPROM - eeprom_scl_pad_b => eeprom_scl_pad_b, - eeprom_sda_pad_b => eeprom_sda_pad_b, - - -- Temperature monitor - -- LM75AIMM - lm75_scl_pad_b => lm75_scl_pad_b, - lm75_sda_pad_b => lm75_sda_pad_b, - - fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i, - - -- FMC LEDs - fmc_led1_o => fmc_led1_int, - fmc_led2_o => fmc_led2_int, - fmc_led3_o => fmc_led3_int, - - ----------------------------- - -- Optional external reference clock ports - ----------------------------- - fmc_ext_ref_clk_i => '0', -- Unused - fmc_ext_ref_clk2x_i => '0', -- Unused - fmc_ext_ref_mmcm_locked_i => '0', -- Unused - - ----------------------------- - -- ADC output signals. Continuous flow - ----------------------------- - adc_clk_o => fmc_130m_4ch_clk, - adc_clk2x_o => fmc_130m_4ch_clk2x, - adc_rst_n_o => fmc_130m_4ch_rst_n, - adc_data_o => fmc_130m_4ch_data, - adc_data_valid_o => fmc_130m_4ch_data_valid, - - ----------------------------- - -- General ADC output signals and status - ----------------------------- - -- Trigger to other FPGA logic - trig_hw_o => open, - trig_hw_i => '0', - - -- General board status - fmc_mmcm_lock_o => fmc_mmcm_lock_int, - fmc_pll_status_o => fmc_pll_status_int, - - ----------------------------- - -- Wishbone Streaming Interface Source - ----------------------------- - wbs_source_i => wbs_fmc130m_4ch_in_array, - wbs_source_o => wbs_fmc130m_4ch_out_array, - - adc_dly_debug_o => adc_dly_debug_int, - - fifo_debug_valid_o => fmc130m_4ch_debug_valid_int, - fifo_debug_full_o => fmc130m_4ch_debug_full_int, - fifo_debug_empty_o => fmc130m_4ch_debug_empty_int - ); - - gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate - wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in; - end generate; - - fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int; - fmc_pll_status_led_o <= fmc_pll_status_int; - - fmc_led1_o <= fmc_led1_int; - fmc_led2_o <= fmc_led2_int; - fmc_led3_o <= fmc_led3_int; - - --led_south_o <= fmc_led1_int; - --led_east_o <= fmc_led2_int; - --led_north_o <= fmc_led3_int; - - -- The board peripherals components is slave 8 - cmp_xwb_dbe_periph : xwb_dbe_periph - generic map( - -- NOT used! - --g_interface_mode : t_wishbone_interface_mode := CLASSIC; - -- NOT used! - --g_address_granularity : t_wishbone_address_granularity := WORD; - g_cntr_period => c_tics_cntr_period, - g_num_leds => c_leds_num_pins, - g_num_buttons => c_buttons_num_pins - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- UART - uart_rxd_i => '0', - uart_txd_o => open, - - -- LEDs - led_out_o => gpio_leds_int, - led_in_i => gpio_leds_int, - led_oen_o => open, - - -- Buttons - button_out_o => open, - --button_in_i => buttons_i, - button_in_i => buttons_dummy, - button_oen_o => open, - - -- Wishbone - slave_i => cbar_master_o(8), - slave_o => cbar_master_i(8) - ); - - leds_o <= gpio_leds_int; - - acq_chan_array(c_acq_adc_id).val_low <= fmc_130m_4ch_data(63 downto 48) & - fmc_130m_4ch_data(47 downto 32) & - fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(15 downto 0); - acq_chan_array(c_acq_adc_id).val_high <= (others => '0'); - acq_chan_array(c_acq_adc_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk); - acq_chan_array(c_acq_adc_id).trig <= '0'; - - acq_chan_array(c_acq_tbt_id).val_low <= fmc_130m_4ch_data(63 downto 48) & - fmc_130m_4ch_data(47 downto 32) & - fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(15 downto 0); - acq_chan_array(c_acq_tbt_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 100) & - std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 100) & - std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 100) & - std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 100); - acq_chan_array(c_acq_tbt_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk); - acq_chan_array(c_acq_tbt_id).trig <= '0'; - - acq_chan_array(c_acq_fofb_id).val_low <= fmc_130m_4ch_data(63 downto 48) & - fmc_130m_4ch_data(47 downto 32) & - fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(15 downto 0); - acq_chan_array(c_acq_fofb_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 200) & - std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 200) & - std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 200) & - std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 200) ; - acq_chan_array(c_acq_fofb_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk); - acq_chan_array(c_acq_fofb_id).trig <= '0'; - - acq_chan_array(c_acq_monit_id).val_low <= fmc_130m_4ch_data(63 downto 48) & - fmc_130m_4ch_data(47 downto 32) & - fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(15 downto 0); - acq_chan_array(c_acq_monit_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 300) & - std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 300) & - std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 300) & - std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 300) ; - acq_chan_array(c_acq_monit_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk); - acq_chan_array(c_acq_monit_id).trig <= '0'; - - acq_chan_array(c_acq_monit_1_id).val_low <= fmc_130m_4ch_data(63 downto 48) & - fmc_130m_4ch_data(47 downto 32) & - fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(15 downto 0); - acq_chan_array(c_acq_monit_1_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 400) & - std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 400) & - std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 400) & - std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 400) ; - acq_chan_array(c_acq_monit_1_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk); - acq_chan_array(c_acq_monit_1_id).trig <= '0'; - - -- The xwb_acq_core is slave 9 - cmp_xwb_acq_core : xwb_acq_core - generic map - ( - g_interface_mode => PIPELINED, - g_address_granularity => WORD, - g_acq_addr_width => c_acq_addr_width, - g_acq_num_channels => c_acq_num_channels, - g_acq_channels => c_acq_channels, - g_ddr_payload_width => c_acq_ddr_payload_width, - g_ddr_dq_width => c_ddr_dq_width, - g_ddr_addr_width => c_acq_ddr_addr_width, - --g_multishot_ram_size => 2048, - g_fifo_fc_size => c_acq_fifo_size -- avoid fifo overflow - --g_sim_readback => false - ) - port map - ( - -- assign to a better and shorter name - fs_clk_i => fmc_130m_4ch_clk(c_adc_ref_clk), - fs_ce_i => '1', - -- assign to a better and shorter name - fs_rst_n_i => fmc_130m_4ch_rst_n(c_adc_ref_clk), - - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - - -- From DDR3 Controller - ext_clk_i => memc_ui_clk, - ext_rst_n_i => memc_ui_rstn, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(9), - wb_slv_o => cbar_master_i(9), - - ----------------------------- - -- External Interface - ----------------------------- - --data_i => fmc_130m_4ch_data, -- ch4 ch3 ch2 ch1 - --dvalid_i => fmc_130m_4ch_data_valid(c_adc_ref_clk), -- Change this!! - --ext_trig_i => '0', - acq_chan_array_i => acq_chan_array, - - ----------------------------- - -- DRRAM Interface - ----------------------------- - dpram_dout_o => bpm_acq_dpram_dout , -- to chipscope - dpram_valid_o => bpm_acq_dpram_valid, -- to chipscope - - ----------------------------- - -- External Interface (w/ FLow Control) - ----------------------------- - ext_dout_o => bpm_acq_ext_dout, -- to chipscope - ext_valid_o => bpm_acq_ext_valid, -- to chipscope - ext_addr_o => bpm_acq_ext_addr, -- to chipscope - ext_sof_o => bpm_acq_ext_sof, -- to chipscope - ext_eof_o => bpm_acq_ext_eof, -- to chipscope - ext_dreq_o => bpm_acq_ext_dreq, -- to chipscope - ext_stall_o => bpm_acq_ext_stall, -- to chipscope - - ----------------------------- - -- DDR3 SDRAM Interface - ----------------------------- - ui_app_addr_o => memc_cmd_addr, - ui_app_cmd_o => memc_cmd_instr, - ui_app_en_o => memc_cmd_en, - ui_app_rdy_i => memc_cmd_rdy, - - ui_app_wdf_data_o => memc_wr_data, - ui_app_wdf_end_o => memc_wr_end, - ui_app_wdf_mask_o => memc_wr_mask, - ui_app_wdf_wren_o => memc_wr_en, - ui_app_wdf_rdy_i => memc_wr_rdy, - - ui_app_rd_data_i => memc_rd_data, -- not used! - ui_app_rd_data_end_i => '0', -- not used! - ui_app_rd_data_valid_i => memc_rd_valid, -- not used! - - -- DDR3 arbitrer for multiple accesses - ui_app_req_o => memarb_acc_req, - ui_app_gnt_i => memarb_acc_gnt, - - ----------------------------- - -- Debug Interface - ----------------------------- - dbg_ddr_rb_data_o => dbg_ddr_rb_data, - dbg_ddr_rb_addr_o => dbg_ddr_rb_addr, - dbg_ddr_rb_valid_o => dbg_ddr_rb_valid - ); - - memc_ui_rstn <= not(memc_ui_rst); - - memc_cmd_addr_resized <= f_gen_std_logic_vector(c_acq_ddr_addr_diff, '0') & - memc_cmd_addr; - - -- Xilinx Chipscope - cmp_chipscope_icon_0 : chipscope_icon_6_port - port map ( - CONTROL0 => CONTROL0, - CONTROL1 => CONTROL1, - CONTROL2 => CONTROL2, - CONTROL3 => CONTROL3, - CONTROL4 => CONTROL4, - CONTROL5 => CONTROL5 - ); - - cmp_chipscope_ila_0_fmc130m_4ch_clk0 : chipscope_ila - port map ( - CONTROL => CONTROL0, - CLK => fmc_130m_4ch_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA0_0, - TRIG1 => TRIG_ILA0_1, - TRIG2 => TRIG_ILA0_2, - TRIG3 => TRIG_ILA0_3 - ); - - -- fmc130m_4ch WBS master output data - --TRIG_ILA0_0 <= wbs_fmc130m_4ch_out_array(3).dat & - -- wbs_fmc130m_4ch_out_array(2).dat; - TRIG_ILA0_0 <= fmc_130m_4ch_data(31 downto 16) & - fmc_130m_4ch_data(47 downto 32); - - -- fmc130m_4ch WBS master output data - TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse & - adc_dly_debug_int(1).data_chain.idelay.pulse & - adc_dly_debug_int(1).clk_chain.idelay.val & - adc_dly_debug_int(1).data_chain.idelay.val; - TRIG_ILA0_1(31 downto 12) <= (others => '0'); - - -- fmc130m_4ch WBS master output control signals - TRIG_ILA0_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc & - wbs_fmc130m_4ch_out_array(1).stb & - wbs_fmc130m_4ch_out_array(1).adr & - wbs_fmc130m_4ch_out_array(1).sel & - wbs_fmc130m_4ch_out_array(1).we & - wbs_fmc130m_4ch_out_array(2).cyc & - wbs_fmc130m_4ch_out_array(2).stb & - wbs_fmc130m_4ch_out_array(2).adr & - wbs_fmc130m_4ch_out_array(2).sel & - wbs_fmc130m_4ch_out_array(2).we; - TRIG_ILA0_2(18) <= '0'; - TRIG_ILA0_2(22 downto 19) <= fmc_130m_4ch_data_valid; - TRIG_ILA0_2(23) <= fmc_mmcm_lock_int; - TRIG_ILA0_2(24) <= fmc_pll_status_int; - TRIG_ILA0_2(25) <= fmc130m_4ch_debug_valid_int(1); - TRIG_ILA0_2(26) <= fmc130m_4ch_debug_full_int(1); - TRIG_ILA0_2(27) <= fmc130m_4ch_debug_empty_int(1); - TRIG_ILA0_2(31 downto 28) <= (others => '0'); - - TRIG_ILA0_3 <= (others => '0'); - - cmp_chipscope_ila_1_fmc130m_4ch_clk1 : chipscope_ila - port map ( - CONTROL => CONTROL1, - --CLK => fmc_130m_4ch_clk(1), - CLK => fmc_130m_4ch_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA1_0, - TRIG1 => TRIG_ILA1_1, - TRIG2 => TRIG_ILA1_2, - TRIG3 => TRIG_ILA1_3 - ); - - -- fmc130m_4ch WBS master output data - TRIG_ILA1_0 <= fmc_130m_4ch_data(15 downto 0) & - fmc_130m_4ch_data(63 downto 48); - - -- fmc130m_4ch WBS master output data - TRIG_ILA1_1 <= (others => '0'); - - -- fmc130m_4ch WBS master output control signals - TRIG_ILA1_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(0).cyc & - wbs_fmc130m_4ch_out_array(0).stb & - wbs_fmc130m_4ch_out_array(0).adr & - wbs_fmc130m_4ch_out_array(0).sel & - wbs_fmc130m_4ch_out_array(0).we & - wbs_fmc130m_4ch_out_array(3).cyc & - wbs_fmc130m_4ch_out_array(3).stb & - wbs_fmc130m_4ch_out_array(3).adr & - wbs_fmc130m_4ch_out_array(3).sel & - wbs_fmc130m_4ch_out_array(3).we; - TRIG_ILA1_2(18) <= '0'; - TRIG_ILA1_2(22 downto 19) <= fmc_130m_4ch_data_valid; - TRIG_ILA1_2(23) <= fmc_mmcm_lock_int; - TRIG_ILA1_2(24) <= fmc_pll_status_int; - TRIG_ILA1_2(25) <= fmc130m_4ch_debug_valid_int(0); - TRIG_ILA1_2(26) <= fmc130m_4ch_debug_full_int(0); - TRIG_ILA1_2(27) <= fmc130m_4ch_debug_empty_int(0); - TRIG_ILA1_2(31 downto 28) <= (others => '0'); - - TRIG_ILA1_3 <= (others => '0'); - - - cmp_chipscope_ila_2_ethmac_tx : chipscope_ila - port map ( - CONTROL => CONTROL2, - CLK => mtx_clk_pad_i, - TRIG0 => TRIG_ILA2_0, - TRIG1 => TRIG_ILA2_1, - TRIG2 => TRIG_ILA2_2, - TRIG3 => TRIG_ILA2_3 - ); - - TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int & - mtxen_pad_int & - mtxerr_pad_int; - - TRIG_ILA2_0(31 downto 6) <= (others => '0'); - TRIG_ILA2_1 <= (others => '0'); - TRIG_ILA2_2 <= (others => '0'); - TRIG_ILA2_3 <= (others => '0'); - - -- The clocks to/from peripherals are derived from the bus clock. - -- Therefore we don't have to worry about synchronization here, just - -- keep in mind that the data/ss lines will appear longer than normal - cmp_chipscope_ila_3_fmc130m_4ch_periph : chipscope_ila - port map ( - CONTROL => CONTROL3, - CLK => clk_sys, -- Wishbone clock - TRIG0 => TRIG_ILA3_0, - TRIG1 => TRIG_ILA3_1, - TRIG2 => TRIG_ILA3_2, - TRIG3 => TRIG_ILA3_3 - ); - - TRIG_ILA3_0 <= wb_ma_pcie_dat_in(31 downto 0); - TRIG_ILA3_1 <= wb_ma_pcie_dat_out(31 downto 0); - TRIG_ILA3_2(31 downto wb_ma_pcie_addr_out'left + 1) <= (others => '0'); - TRIG_ILA3_2(wb_ma_pcie_addr_out'left downto 0) - <= wb_ma_pcie_addr_out(wb_ma_pcie_addr_out'left downto 0); - TRIG_ILA3_3(31 downto 5) <= (others => '0'); - TRIG_ILA3_3(4 downto 0) <= wb_ma_pcie_ack_in & - wb_ma_pcie_we_out & - wb_ma_pcie_stb_out & - wb_ma_pcie_sel_out & - wb_ma_pcie_cyc_out; - - cmp_chipscope_ila_4_bpm_acq : chipscope_ila - port map ( - CONTROL => CONTROL4, - CLK => memc_ui_clk, -- DDR3 controller clk - TRIG0 => TRIG_ILA4_0, - TRIG1 => TRIG_ILA4_1, - TRIG2 => TRIG_ILA4_2, - TRIG3 => TRIG_ILA4_3 - ); - - TRIG_ILA4_0 <= dbg_app_rd_data(207 downto 192) & - dbg_app_rd_data(143 downto 128); - TRIG_ILA4_1 <= dbg_app_rd_data(79 downto 64) & - dbg_app_rd_data(15 downto 0); - - TRIG_ILA4_2 <= dbg_app_addr; - - TRIG_ILA4_3(31 downto 11) <= (others => '0'); - TRIG_ILA4_3(10 downto 0) <= dbg_app_rd_data_end & - dbg_app_rd_data_valid & - dbg_app_cmd & -- std_logic_vector(2 downto 0); - dbg_app_en & - dbg_app_rdy & - dbg_arb_req & - dbg_arb_gnt; - - cmp_chipscope_ila_5_bpm_acq : chipscope_ila - port map ( - CONTROL => CONTROL5, - CLK => memc_ui_clk, -- DDR3 controller clk - TRIG0 => TRIG_ILA5_0, - TRIG1 => TRIG_ILA5_1, - TRIG2 => TRIG_ILA5_2, - TRIG3 => TRIG_ILA5_3 - ); - - TRIG_ILA5_0 <= dbg_app_wdf_data(207 downto 192) & - dbg_app_wdf_data(143 downto 128); - TRIG_ILA5_1 <= dbg_app_wdf_data(79 downto 64) & - dbg_app_wdf_data(15 downto 0); - - TRIG_ILA5_2 <= dbg_app_addr; - TRIG_ILA5_3(31 downto 30) <= (others => '0'); - TRIG_ILA5_3(29 downto 0) <= memc_ui_rst & - clk_200mhz_rstn & - dbg_app_cmd & -- std_logic_vector(2 downto 0); - dbg_app_en & - dbg_app_rdy & - dbg_app_wdf_end & - dbg_app_wdf_mask(15 downto 0) & -- std_logic_vector(31 downto 0); - dbg_app_wdf_wren & - dbg_app_wdf_rdy & - dbg_arb_req & - dbg_arb_gnt; -end rtl; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xcf b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xcf deleted file mode 100644 index 622cfd43..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.xcf +++ /dev/null @@ -1,28 +0,0 @@ - -NET "*/sys_clk_c" TNM_NET = "SYSCLK" ; -NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; - -TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 %; -TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25; - -MODEL ui_rd_data max_fanout = 20; - -BEGIN MODEL ui_wr_data -NET app_wdf_rdy_r max_fanout=20; -END; - -BEGIN MODEL ui_cmd -NET app_rdy_r max_fanout=20; -END; - -BEGIN MODEL phy_rdclk_gen -NET rst_oserdes max_fanout=10; -END; - -BEGIN MODEL phy_data_io -NET rst_r max_fanout=1; -END; - -BEGIN MODEL phy_control_io -NET rst_r max_fanout=1; -END; diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/pcie.ucf b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/pcie.ucf deleted file mode 100644 index 9393086a..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/pcie.ucf +++ /dev/null @@ -1,367 +0,0 @@ -###----------------------------------------------------------------------------- -###----------------------------------------------------------------------------- -### Project : Series-7 Integrated Block for PCI Express -### Version : 1.6 -## -################################################################################ -## Define Device, Package And Speed Grade -################################################################################ -# -#CONFIG PART = xc6vlx240t-ff1156-1; -# -########################################################################################################################## -## User Constraints -########################################################################################################################## -# -################################################################################ -## User Time Names / User Time Groups / Time Specs -################################################################################ -# -################################################################################ -## User Physical Constraints -################################################################################ -############ PCIE ######################### -##PCIe reset -#NET "pcie_rst_n_i" IOSTANDARD = LVCMOS25 | PULLUP | NODELAY; -#NET "pcie_rst_n_i" TIG; -## Bank 16 VCCO - VADJ_FPGA - IO_25_16 -#NET "pcie_rst_n_i" LOC = AE13; -##PCIe reset -##PCIe clock -#NET "pcie_clk_n_i" LOC = P5; -## Bank 115 - MGTREFCLK1N_115 -#NET "pcie_clk_p_i" LOC = P6; -# -############ DDR controller ############## -#NET "ddr3_dq_b[0]" LOC = "J11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[1]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[2]" LOC = "F13" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[3]" LOC = "K11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[4]" LOC = "L11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[5]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[6]" LOC = "K12" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[7]" LOC = "D11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[8]" LOC = "M13" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[9]" LOC = "J14" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[10]" LOC = "B13" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[11]" LOC = "B12" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[12]" LOC = "G10" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[13]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[14]" LOC = "C12" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[15]" LOC = "A11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[16]" LOC = "G11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[17]" LOC = "F11" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[18]" LOC = "D14" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[19]" LOC = "C14" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[20]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[21]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[23]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[24]" LOC = "C19" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[25]" LOC = "G20" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[26]" LOC = "E19" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[27]" LOC = "F20" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[28]" LOC = "A20" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[29]" LOC = "A21" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[30]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[31]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[32]" LOC = "G21" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[33]" LOC = "B21" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[34]" LOC = "A23" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[35]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[36]" LOC = "C20" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[37]" LOC = "D20" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[38]" LOC = "J20" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[39]" LOC = "G22" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[40]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[41]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[42]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[43]" LOC = "E26" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[44]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[45]" LOC = "D25" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[46]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[47]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[48]" LOC = "C27" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[49]" LOC = "B28" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[50]" LOC = "D29" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[51]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[52]" LOC = "G27" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[53]" LOC = "A28" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[54]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[55]" LOC = "G25" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[56]" LOC = "F28" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[57]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[58]" LOC = "H29" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[59]" LOC = "H28" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[60]" LOC = "B30" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[61]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[62]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_dq_b[63]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI ; -#NET "ddr3_addr_o[13]" LOC = "J15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[12]" LOC = "H15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[11]" LOC = "M15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[10]" LOC = "M16" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[9]" LOC = "F15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[8]" LOC = "G15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[7]" LOC = "B15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[6]" LOC = "A15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[5]" LOC = "J17" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[4]" LOC = "D16" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[3]" LOC = "E16" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[2]" LOC = "B16" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[1]" LOC = "A16" | IOSTANDARD = SSTL15 ; -#NET "ddr3_addr_o[0]" LOC = "L14" | IOSTANDARD = SSTL15 ; -#NET "ddr3_ba_o[2]" LOC = "L15" | IOSTANDARD = SSTL15 ; -#NET "ddr3_ba_o[1]" LOC = "J19" | IOSTANDARD = SSTL15 ; -#NET "ddr3_ba_o[0]" LOC = "K19" | IOSTANDARD = SSTL15 ; -#NET "ddr3_ras_n_o" LOC = "L19" | IOSTANDARD = SSTL15 ; -#NET "ddr3_cas_n_o" LOC = "C17" | IOSTANDARD = SSTL15 ; -#NET "ddr3_we_n_o" LOC = "B17" | IOSTANDARD = SSTL15 ; -#NET "ddr3_reset_n_o" LOC = "E18" | IOSTANDARD = LVCMOS15 ; -#NET "ddr3_cke_o[0]" LOC = "M18" | IOSTANDARD = SSTL15 ; -#NET "ddr3_odt_o[0]" LOC = "F18" | IOSTANDARD = SSTL15 ; -#NET "ddr3_cs_n_o[0]" LOC = "K18" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[0]" LOC = "E11" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[1]" LOC = "B11" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[2]" LOC = "E14" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[3]" LOC = "D19" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[4]" LOC = "B22" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[5]" LOC = "A26" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[6]" LOC = "A29" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dm_o[7]" LOC = "A31" | IOSTANDARD = SSTL15 ; -#NET "ddr3_dqs_p_b[0]" LOC = "D12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[0]" LOC = "E12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[1]" LOC = "H12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[2]" LOC = "A13" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[2]" LOC = "A14" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[3]" LOC = "H19" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[3]" LOC = "H20" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[4]" LOC = "B23" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[4]" LOC = "C23" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[5]" LOC = "B25" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[5]" LOC = "A25" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[6]" LOC = "H27" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[6]" LOC = "G28" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_p_b[7]" LOC = "C30" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_dqs_n_b[7]" LOC = "D30" | IOSTANDARD = DIFF_SSTL15_T_DCI ; -#NET "ddr3_ck_p_o[0]" LOC = "G18" | IOSTANDARD = DIFF_SSTL15 ; -#NET "ddr3_ck_n_o[0]" LOC = "H18" | IOSTANDARD = DIFF_SSTL15 ; -##NET "ddr_sys_clk_p_i" LOC = "J9" | IOSTANDARD = LVDS_25; -##NET "ddr_sys_clk_n_i" LOC = "H9" | IOSTANDARD = LVDS_25; -# -########################################################################################################################## -## End User Constraints -########################################################################################################################## -# -################################################################################ -## Pinout and Related I/O Constraints -################################################################################ -# -# -## -## SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n -## signals are the PCI Express reference clock. Virtex-6 GT -## Transceiver architecture requires the use of a dedicated clock -## resources (FPGA input pins) associated with each GT Transceiver. -## To use these pins an IBUFDS primitive (refclk_ibuf) is -## instantiated in user's design. -## Please refer to the Virtex-6 GT Transceiver User Guide -## (UG) for guidelines regarding clock resource selection. -## -# -#INST "cmp_bpm_pcie_ml605/pcieclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6; -# -## -## Transceiver instance placement. This constraint selects the -## transceivers to be used, which also dictates the pinout for the -## transmit and receive differential pairs. Please refer to the -## Virtex-6 GT Transceiver User Guide (UG) for more information. -## -## PCIe Lane 0 -#INST "cmp_bpm_pcie_ml605/*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX" LOC = GTXE1_X0Y15; -## PCIe Lane 1 -#INST "cmp_bpm_pcie_ml605/*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX" LOC = GTXE1_X0Y14; -## PCIe Lane 2 -#INST "cmp_bpm_pcie_ml605/*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX" LOC = GTXE1_X0Y13; -## PCIe Lane 3 -#INST "cmp_bpm_pcie_ml605/*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX" LOC = GTXE1_X0Y12; -# -## -## PCI Express Block placement. This constraint selects the PCI Express -## Block to be used. -## -#INST "cmp_bpm_pcie_ml605/*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1; -# -# -## -## DDR controller component placement -## Check it after changing memory controller paramenters -################################################################################ -##DCI_CASCADING -##Syntax : CONFIG DCI_CASCADE = " .."; -################################################################################ -#CONFIG DCI_CASCADE = "26 25";# -#CONFIG DCI_CASCADE = "36 35";# -# -################################################################################################### -###The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must ## -###be a clock pin capable of spanning to all of the banks containing data bytes in the particular## -###column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be ## -###used for other functions and should not be connected externally. If a different pin is chosen,## -###he corresponding LOC constraint must also be changed. ## -################################################################################################### -#CONFIG PROHIBIT = C29,M12; -# -################################################################################################### -###The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock ## -###capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for ## -###this pin. This pin cannot be used for other functions and should not be connected externally. ## -###If a different pin is chosen, the corresponding LOC constraint must also be changed. ## -################################################################################################### -#CONFIG PROHIBIT = B20,C13,C28,D24,F21,F25,K14,L13; -# -####################################################################################### -###Place RSYNC OSERDES and IODELAY: ## -####################################################################################### -# -###Site: C29 -- Bank 25 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" -# LOC = "OLOGIC_X1Y139"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" -# LOC = "IODELAY_X1Y139"; -# -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" -# LOC = "BUFR_X1Y6"; -# -###Site: M12 -- Bank 35 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" -# LOC = "OLOGIC_X2Y139"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" -# LOC = "IODELAY_X2Y139"; -# -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" -# LOC = "BUFR_X2Y6"; -####################################################################################### -###Place CPT OSERDES and IODELAY: ## -####################################################################################### -# -###Site: C13 -- Bank 35 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" -# LOC = "OLOGIC_X2Y137"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" -# LOC = "IODELAY_X2Y137"; -# -###Site: L13 -- Bank 35 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" -# LOC = "OLOGIC_X2Y141"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" -# LOC = "IODELAY_X2Y141"; -# -###Site: K14 -- Bank 35 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" -# LOC = "OLOGIC_X2Y143"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" -# LOC = "IODELAY_X2Y143"; -# -###Site: F21 -- Bank 26 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" -# LOC = "OLOGIC_X1Y179"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" -# LOC = "IODELAY_X1Y179"; -# -###Site: B20 -- Bank 26 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" -# LOC = "OLOGIC_X1Y181"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" -# LOC = "IODELAY_X1Y181"; -# -###Site: F25 -- Bank 25 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" -# LOC = "OLOGIC_X1Y137"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" -# LOC = "IODELAY_X1Y137"; -# -###Site: C28 -- Bank 25 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" -# LOC = "OLOGIC_X1Y141"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" -# LOC = "IODELAY_X1Y141"; -# -###Site: D24 -- Bank 25 -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" -# LOC = "OLOGIC_X1Y143"; -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" -# LOC = "IODELAY_X1Y143"; -# -#INST "cmp_bpm_pcie_ml605/*/u_infrastructure/u_mmcm_adv" LOC = "MMCM_ADV_X0Y8"; #Banks 16, 26, 36 -# -################################################################################ -## Timing Constraints -################################################################################ -# -#NET "cmp_bpm_pcie_ml605/sys_clk_c" TNM_NET = "SYSCLK" ; -#NET "cmp_bpm_pcie_ml605/*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ; -#NET "cmp_bpm_pcie_ml605/*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG"; -# -#TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ; -#TIMESPEC "TS_CLK_125" = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1 ; -#TIMESPEC "TS_TXOUTCLKBUFG" = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ; -# -# -#PIN "cmp_bpm_pcie_ml605/*/trn_reset_n_int_i.CLR" TIG ; -#PIN "cmp_bpm_pcie_ml605/*/trn_reset_n_i.CLR" TIG ; -#PIN "cmp_bpm_pcie_ml605/*/pcie_clocking_i/mmcm_adv_i.RST" TIG ; -# -#INST "cmp_bpm_pcie_ml605/*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7; -# -# -######## DDR ########### -## Temporary place for this constraint as it should belong to the -## top ucf file, not here. -# -##NET "cmp_bpm_pcie_ml605/ddr_sys_clk_p" TNM_NET = TNM_ddr_sys_clk; -##TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns; -# -#NET "clk_200mhz" TNM_NET = TNM_ddr_sys_clk; -#TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns; -# -## Constrain BUFR clocks used to synchronize data from IOB to fabric logic -## Note that ISE cannot infer this from other PERIOD constraints because -## of the use of OSERDES blocks in the BUFR clock generation path -#NET "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync[?]" TNM_NET = TNM_clk_rsync; -#TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5 ns; -# -## Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling -## edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for -## that particular flop. Mark this path as being a full-cycle, rather than -## a half cycle path for timing purposes. NOTE: This constraint forces full- -## cycle timing to be applied globally for all rising->falling edge paths -## in all resynchronizaton clock domains. If the user had modified the logic -## in the resync clock domain such that other rising->falling edge paths -## exist, then constraint below should be modified to utilize pattern -## matching to specific affect only the DQ/DQS ISERDES.Q outputs -#TIMEGRP "TG_clk_rsync_rise" = RISING "TNM_clk_rsync"; -#TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync"; -#TIMESPEC "TS_clk_rsync_rise_to_fall" = -# FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" "TS_ddr_sys_clk" * 4; -# -## Signal to select between controller and physical layer signals. Four divided by two clock -## cycles (4 memory clock cycles) are provided by design for the signal to settle down. -## Used only by the phy modules. -#INST "cmp_bpm_pcie_ml605/*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL"; -#TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_ddr_sys_clk"*8; -# -################################################################################ -## Physical Constraints -################################################################################ -## Constrain the PCIe core elements placement, so that it won't fail -## timing analysis. -## Comment out because we use nonstandard GTP location -##INST "pcie_core_i" AREA_GROUP = "GRP_PCIE_CORE"; -##AREA_GROUP "GRP_PCIE_CORE" RANGE = CLOCKREGION_X0Y4; -##Place the DMA design not far from PCIe core, otherwise it also breaks timing -##INST "theTlpControl" AREA_GROUP = "GRP_tlpControl"; -##AREA_GROUP "GRP_tlpControl" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y4; -# -## PlanAhead Generated physical constraints diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/pcie_test.cpj b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/pcie_test.cpj deleted file mode 100644 index 2569394f..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/pcie_test.cpj +++ /dev/null @@ -1,11357 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Sat Nov 23 12:08:31 BRST 2013 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109344250093 -mdiAreaHeight=0.7183908045977011 -mdiAreaHeightLast=0.7011494252873564 -mdiCount=13 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice10=1 -mdiDevice11=1 -mdiDevice12=1 -mdiDevice2=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiDevice6=1 -mdiDevice7=1 -mdiDevice8=1 -mdiDevice9=1 -mdiType0=1 -mdiType1=1 -mdiType10=0 -mdiType11=0 -mdiType12=5 -mdiType2=5 -mdiType3=0 -mdiType4=1 -mdiType5=2 -mdiType6=5 -mdiType7=0 -mdiType8=1 -mdiType9=5 -mdiUnit0=5 -mdiUnit1=0 -mdiUnit10=5 -mdiUnit11=0 -mdiUnit12=5 -mdiUnit2=0 -mdiUnit3=3 -mdiUnit4=3 -mdiUnit5=3 -mdiUnit6=3 -mdiUnit7=4 -mdiUnit8=4 -mdiUnit9=4 -navigatorHeight=0.17701149425287357 -navigatorHeightLast=0.17701149425287357 -navigatorWidth=0.1794871794871795 -navigatorWidthLast=0.1794871794871795 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.3697749 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=1.0 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5482315 -unit.1.0.1.WIDTH1=1.0 -unit.1.0.1.X1=0.0 -unit.1.0.1.Y1=0.36655948 -unit.1.0.5.HEIGHT5=1.0 -unit.1.0.5.WIDTH5=1.0 -unit.1.0.5.X5=0.0 -unit.1.0.5.Y5=0.0 -unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 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-unit.1.0.port.-1.s.127.name=DataPort[127] -unit.1.0.port.-1.s.127.orderindex=-1 -unit.1.0.port.-1.s.127.visible=1 -unit.1.0.port.-1.s.13.alias= -unit.1.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.13.name=DataPort[13] -unit.1.0.port.-1.s.13.orderindex=-1 -unit.1.0.port.-1.s.13.visible=0 -unit.1.0.port.-1.s.14.alias= -unit.1.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.14.name=DataPort[14] -unit.1.0.port.-1.s.14.orderindex=-1 -unit.1.0.port.-1.s.14.visible=0 -unit.1.0.port.-1.s.15.alias= -unit.1.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.15.name=DataPort[15] -unit.1.0.port.-1.s.15.orderindex=-1 -unit.1.0.port.-1.s.15.visible=0 -unit.1.0.port.-1.s.16.alias= -unit.1.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.16.name=DataPort[16] -unit.1.0.port.-1.s.16.orderindex=-1 -unit.1.0.port.-1.s.16.visible=0 -unit.1.0.port.-1.s.17.alias= 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-unit.1.0.port.-1.s.73.orderindex=-1 -unit.1.0.port.-1.s.73.visible=1 -unit.1.0.port.-1.s.74.alias= -unit.1.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.74.name=DataPort[74] -unit.1.0.port.-1.s.74.orderindex=-1 -unit.1.0.port.-1.s.74.visible=1 -unit.1.0.port.-1.s.75.alias= -unit.1.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.75.name=DataPort[75] -unit.1.0.port.-1.s.75.orderindex=-1 -unit.1.0.port.-1.s.75.visible=1 -unit.1.0.port.-1.s.76.alias= -unit.1.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.76.name=DataPort[76] -unit.1.0.port.-1.s.76.orderindex=-1 -unit.1.0.port.-1.s.76.visible=1 -unit.1.0.port.-1.s.77.alias= -unit.1.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.77.name=DataPort[77] -unit.1.0.port.-1.s.77.orderindex=-1 -unit.1.0.port.-1.s.77.visible=1 -unit.1.0.port.-1.s.78.alias= -unit.1.0.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.78.name=DataPort[78] -unit.1.0.port.-1.s.78.orderindex=-1 -unit.1.0.port.-1.s.78.visible=1 -unit.1.0.port.-1.s.79.alias= -unit.1.0.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.79.name=DataPort[79] -unit.1.0.port.-1.s.79.orderindex=-1 -unit.1.0.port.-1.s.79.visible=1 -unit.1.0.port.-1.s.8.alias= -unit.1.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.8.name=DataPort[8] -unit.1.0.port.-1.s.8.orderindex=-1 -unit.1.0.port.-1.s.8.visible=0 -unit.1.0.port.-1.s.80.alias= -unit.1.0.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.80.name=DataPort[80] -unit.1.0.port.-1.s.80.orderindex=-1 -unit.1.0.port.-1.s.80.visible=1 -unit.1.0.port.-1.s.81.alias= -unit.1.0.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.81.name=DataPort[81] -unit.1.0.port.-1.s.81.orderindex=-1 -unit.1.0.port.-1.s.81.visible=1 -unit.1.0.port.-1.s.82.alias= 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22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.b.0.name=TriggerPort0 -unit.1.0.port.0.b.0.orderindex=-1 -unit.1.0.port.0.b.0.radix=Hex -unit.1.0.port.0.b.0.signedOffset=0.0 -unit.1.0.port.0.b.0.signedPrecision=0 -unit.1.0.port.0.b.0.signedScaleFactor=1.0 -unit.1.0.port.0.b.0.unsignedOffset=0.0 -unit.1.0.port.0.b.0.unsignedPrecision=0 -unit.1.0.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.0.b.0.visible=1 -unit.1.0.port.0.buscount=1 -unit.1.0.port.0.channelcount=32 -unit.1.0.port.0.s.0.alias= -unit.1.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= 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-unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias= -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= -unit.1.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.10.name=TriggerPort3[10] -unit.1.0.port.3.s.10.orderindex=-1 -unit.1.0.port.3.s.10.visible=1 -unit.1.0.port.3.s.11.alias= -unit.1.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.11.name=TriggerPort3[11] -unit.1.0.port.3.s.11.orderindex=-1 -unit.1.0.port.3.s.11.visible=1 -unit.1.0.port.3.s.12.alias= -unit.1.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.12.name=TriggerPort3[12] -unit.1.0.port.3.s.12.orderindex=-1 -unit.1.0.port.3.s.12.visible=1 -unit.1.0.port.3.s.13.alias= -unit.1.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.13.name=TriggerPort3[13] -unit.1.0.port.3.s.13.orderindex=-1 -unit.1.0.port.3.s.13.visible=1 -unit.1.0.port.3.s.14.alias= -unit.1.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.14.name=TriggerPort3[14] -unit.1.0.port.3.s.14.orderindex=-1 -unit.1.0.port.3.s.14.visible=1 -unit.1.0.port.3.s.15.alias= -unit.1.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.15.name=TriggerPort3[15] -unit.1.0.port.3.s.15.orderindex=-1 -unit.1.0.port.3.s.15.visible=1 -unit.1.0.port.3.s.16.alias= -unit.1.0.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.16.name=TriggerPort3[16] -unit.1.0.port.3.s.16.orderindex=-1 -unit.1.0.port.3.s.16.visible=1 -unit.1.0.port.3.s.17.alias= -unit.1.0.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.17.name=TriggerPort3[17] -unit.1.0.port.3.s.17.orderindex=-1 -unit.1.0.port.3.s.17.visible=1 -unit.1.0.port.3.s.18.alias= -unit.1.0.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.18.name=TriggerPort3[18] -unit.1.0.port.3.s.18.orderindex=-1 -unit.1.0.port.3.s.18.visible=1 -unit.1.0.port.3.s.19.alias= -unit.1.0.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.19.name=TriggerPort3[19] -unit.1.0.port.3.s.19.orderindex=-1 -unit.1.0.port.3.s.19.visible=1 -unit.1.0.port.3.s.2.alias= -unit.1.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.2.name=TriggerPort3[2] -unit.1.0.port.3.s.2.orderindex=-1 -unit.1.0.port.3.s.2.visible=1 -unit.1.0.port.3.s.20.alias= -unit.1.0.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.20.name=TriggerPort3[20] -unit.1.0.port.3.s.20.orderindex=-1 -unit.1.0.port.3.s.20.visible=1 -unit.1.0.port.3.s.21.alias= -unit.1.0.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.21.name=TriggerPort3[21] -unit.1.0.port.3.s.21.orderindex=-1 -unit.1.0.port.3.s.21.visible=1 -unit.1.0.port.3.s.22.alias= -unit.1.0.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.22.name=TriggerPort3[22] -unit.1.0.port.3.s.22.orderindex=-1 -unit.1.0.port.3.s.22.visible=1 -unit.1.0.port.3.s.23.alias= -unit.1.0.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.23.name=TriggerPort3[23] -unit.1.0.port.3.s.23.orderindex=-1 -unit.1.0.port.3.s.23.visible=1 -unit.1.0.port.3.s.24.alias= -unit.1.0.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.24.name=TriggerPort3[24] -unit.1.0.port.3.s.24.orderindex=-1 -unit.1.0.port.3.s.24.visible=1 -unit.1.0.port.3.s.25.alias= -unit.1.0.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.25.name=TriggerPort3[25] -unit.1.0.port.3.s.25.orderindex=-1 -unit.1.0.port.3.s.25.visible=1 -unit.1.0.port.3.s.26.alias= -unit.1.0.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.26.name=TriggerPort3[26] -unit.1.0.port.3.s.26.orderindex=-1 -unit.1.0.port.3.s.26.visible=1 -unit.1.0.port.3.s.27.alias= -unit.1.0.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.27.name=TriggerPort3[27] -unit.1.0.port.3.s.27.orderindex=-1 -unit.1.0.port.3.s.27.visible=1 -unit.1.0.port.3.s.28.alias= -unit.1.0.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.28.name=TriggerPort3[28] -unit.1.0.port.3.s.28.orderindex=-1 -unit.1.0.port.3.s.28.visible=1 -unit.1.0.port.3.s.29.alias= -unit.1.0.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.29.name=TriggerPort3[29] -unit.1.0.port.3.s.29.orderindex=-1 -unit.1.0.port.3.s.29.visible=1 -unit.1.0.port.3.s.3.alias= -unit.1.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.3.name=TriggerPort3[3] -unit.1.0.port.3.s.3.orderindex=-1 -unit.1.0.port.3.s.3.visible=1 -unit.1.0.port.3.s.30.alias= -unit.1.0.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 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-unit.1.1.port.-1.s.68.visible=1 -unit.1.1.port.-1.s.69.alias= -unit.1.1.port.-1.s.69.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.69.name=DataPort[69] -unit.1.1.port.-1.s.69.orderindex=-1 -unit.1.1.port.-1.s.69.visible=1 -unit.1.1.port.-1.s.7.alias= -unit.1.1.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.7.name=DataPort[7] -unit.1.1.port.-1.s.7.orderindex=-1 -unit.1.1.port.-1.s.7.visible=1 -unit.1.1.port.-1.s.70.alias= -unit.1.1.port.-1.s.70.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.70.name=DataPort[70] -unit.1.1.port.-1.s.70.orderindex=-1 -unit.1.1.port.-1.s.70.visible=1 -unit.1.1.port.-1.s.71.alias= -unit.1.1.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.71.name=DataPort[71] -unit.1.1.port.-1.s.71.orderindex=-1 -unit.1.1.port.-1.s.71.visible=1 -unit.1.1.port.-1.s.72.alias= -unit.1.1.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.72.name=DataPort[72] -unit.1.1.port.-1.s.72.orderindex=-1 -unit.1.1.port.-1.s.72.visible=1 -unit.1.1.port.-1.s.73.alias= -unit.1.1.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.73.name=DataPort[73] -unit.1.1.port.-1.s.73.orderindex=-1 -unit.1.1.port.-1.s.73.visible=1 -unit.1.1.port.-1.s.74.alias= -unit.1.1.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.74.name=DataPort[74] -unit.1.1.port.-1.s.74.orderindex=-1 -unit.1.1.port.-1.s.74.visible=1 -unit.1.1.port.-1.s.75.alias= -unit.1.1.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.75.name=DataPort[75] -unit.1.1.port.-1.s.75.orderindex=-1 -unit.1.1.port.-1.s.75.visible=1 -unit.1.1.port.-1.s.76.alias= -unit.1.1.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.76.name=DataPort[76] -unit.1.1.port.-1.s.76.orderindex=-1 -unit.1.1.port.-1.s.76.visible=1 -unit.1.1.port.-1.s.77.alias= -unit.1.1.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.77.name=DataPort[77] -unit.1.1.port.-1.s.77.orderindex=-1 -unit.1.1.port.-1.s.77.visible=1 -unit.1.1.port.-1.s.78.alias= -unit.1.1.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.78.name=DataPort[78] -unit.1.1.port.-1.s.78.orderindex=-1 -unit.1.1.port.-1.s.78.visible=1 -unit.1.1.port.-1.s.79.alias= -unit.1.1.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.79.name=DataPort[79] -unit.1.1.port.-1.s.79.orderindex=-1 -unit.1.1.port.-1.s.79.visible=1 -unit.1.1.port.-1.s.8.alias= -unit.1.1.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.8.name=DataPort[8] -unit.1.1.port.-1.s.8.orderindex=-1 -unit.1.1.port.-1.s.8.visible=1 -unit.1.1.port.-1.s.80.alias= -unit.1.1.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.80.name=DataPort[80] -unit.1.1.port.-1.s.80.orderindex=-1 -unit.1.1.port.-1.s.80.visible=1 -unit.1.1.port.-1.s.81.alias= -unit.1.1.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.81.name=DataPort[81] -unit.1.1.port.-1.s.81.orderindex=-1 -unit.1.1.port.-1.s.81.visible=1 -unit.1.1.port.-1.s.82.alias= -unit.1.1.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.82.name=DataPort[82] -unit.1.1.port.-1.s.82.orderindex=-1 -unit.1.1.port.-1.s.82.visible=1 -unit.1.1.port.-1.s.83.alias= -unit.1.1.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.83.name=DataPort[83] -unit.1.1.port.-1.s.83.orderindex=-1 -unit.1.1.port.-1.s.83.visible=1 -unit.1.1.port.-1.s.84.alias= -unit.1.1.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.84.name=DataPort[84] -unit.1.1.port.-1.s.84.orderindex=-1 -unit.1.1.port.-1.s.84.visible=1 -unit.1.1.port.-1.s.85.alias= -unit.1.1.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.85.name=DataPort[85] -unit.1.1.port.-1.s.85.orderindex=-1 -unit.1.1.port.-1.s.85.visible=1 -unit.1.1.port.-1.s.86.alias= -unit.1.1.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.86.name=DataPort[86] -unit.1.1.port.-1.s.86.orderindex=-1 -unit.1.1.port.-1.s.86.visible=1 -unit.1.1.port.-1.s.87.alias= -unit.1.1.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.87.name=DataPort[87] -unit.1.1.port.-1.s.87.orderindex=-1 -unit.1.1.port.-1.s.87.visible=1 -unit.1.1.port.-1.s.88.alias= -unit.1.1.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.88.name=DataPort[88] -unit.1.1.port.-1.s.88.orderindex=-1 -unit.1.1.port.-1.s.88.visible=1 -unit.1.1.port.-1.s.89.alias= -unit.1.1.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.89.name=DataPort[89] -unit.1.1.port.-1.s.89.orderindex=-1 -unit.1.1.port.-1.s.89.visible=1 -unit.1.1.port.-1.s.9.alias= -unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=1 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=1 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=1 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=1 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=1 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=1 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=1 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=32 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 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-unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.portcount=4 -unit.1.1.rep_trigger.clobber=1 -unit.1.1.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch -unit.1.1.rep_trigger.filename=waveform -unit.1.1.rep_trigger.format=ASCII -unit.1.1.rep_trigger.loggingEnabled=0 -unit.1.1.rep_trigger.signals=All Signals/Buses -unit.1.1.samplesPerTrigger=1 -unit.1.1.triggerCapture=1 -unit.1.1.triggerNSamplesTS=0 -unit.1.1.triggerPosition=0 -unit.1.1.triggerWindowCount=1 -unit.1.1.triggerWindowDepth=4096 -unit.1.1.triggerWindowTS=0 -unit.1.1.username=MyILA1 -unit.1.1.waveform.count=128 -unit.1.1.waveform.posn.0.channel=0 -unit.1.1.waveform.posn.0.name=DataPort[0] -unit.1.1.waveform.posn.0.type=signal -unit.1.1.waveform.posn.1.channel=1 -unit.1.1.waveform.posn.1.name=DataPort[1] -unit.1.1.waveform.posn.1.type=signal -unit.1.1.waveform.posn.10.channel=10 -unit.1.1.waveform.posn.10.name=DataPort[10] -unit.1.1.waveform.posn.10.type=signal -unit.1.1.waveform.posn.100.channel=100 -unit.1.1.waveform.posn.100.name=DataPort[100] -unit.1.1.waveform.posn.100.type=signal -unit.1.1.waveform.posn.101.channel=101 -unit.1.1.waveform.posn.101.name=DataPort[101] -unit.1.1.waveform.posn.101.type=signal -unit.1.1.waveform.posn.102.channel=102 -unit.1.1.waveform.posn.102.name=DataPort[102] -unit.1.1.waveform.posn.102.type=signal -unit.1.1.waveform.posn.103.channel=103 -unit.1.1.waveform.posn.103.name=DataPort[103] -unit.1.1.waveform.posn.103.type=signal -unit.1.1.waveform.posn.104.channel=104 -unit.1.1.waveform.posn.104.name=DataPort[104] -unit.1.1.waveform.posn.104.type=signal -unit.1.1.waveform.posn.105.channel=105 -unit.1.1.waveform.posn.105.name=DataPort[105] -unit.1.1.waveform.posn.105.type=signal -unit.1.1.waveform.posn.106.channel=106 -unit.1.1.waveform.posn.106.name=DataPort[106] -unit.1.1.waveform.posn.106.type=signal -unit.1.1.waveform.posn.107.channel=107 -unit.1.1.waveform.posn.107.name=DataPort[107] -unit.1.1.waveform.posn.107.type=signal -unit.1.1.waveform.posn.108.channel=108 -unit.1.1.waveform.posn.108.name=DataPort[108] -unit.1.1.waveform.posn.108.type=signal -unit.1.1.waveform.posn.109.channel=109 -unit.1.1.waveform.posn.109.name=DataPort[109] -unit.1.1.waveform.posn.109.type=signal -unit.1.1.waveform.posn.11.channel=11 -unit.1.1.waveform.posn.11.name=DataPort[11] -unit.1.1.waveform.posn.11.type=signal -unit.1.1.waveform.posn.110.channel=110 -unit.1.1.waveform.posn.110.name=DataPort[110] -unit.1.1.waveform.posn.110.type=signal -unit.1.1.waveform.posn.111.channel=111 -unit.1.1.waveform.posn.111.name=DataPort[111] -unit.1.1.waveform.posn.111.type=signal -unit.1.1.waveform.posn.112.channel=112 -unit.1.1.waveform.posn.112.name=DataPort[112] -unit.1.1.waveform.posn.112.type=signal -unit.1.1.waveform.posn.113.channel=113 -unit.1.1.waveform.posn.113.name=DataPort[113] -unit.1.1.waveform.posn.113.type=signal -unit.1.1.waveform.posn.114.channel=114 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-unit.1.1.waveform.posn.121.channel=121 -unit.1.1.waveform.posn.121.name=DataPort[121] -unit.1.1.waveform.posn.121.type=signal -unit.1.1.waveform.posn.122.channel=122 -unit.1.1.waveform.posn.122.name=DataPort[122] -unit.1.1.waveform.posn.122.type=signal -unit.1.1.waveform.posn.123.channel=123 -unit.1.1.waveform.posn.123.name=DataPort[123] -unit.1.1.waveform.posn.123.type=signal -unit.1.1.waveform.posn.124.channel=124 -unit.1.1.waveform.posn.124.name=DataPort[124] -unit.1.1.waveform.posn.124.type=signal -unit.1.1.waveform.posn.125.channel=125 -unit.1.1.waveform.posn.125.name=DataPort[125] -unit.1.1.waveform.posn.125.type=signal -unit.1.1.waveform.posn.126.channel=126 -unit.1.1.waveform.posn.126.name=DataPort[126] -unit.1.1.waveform.posn.126.type=signal -unit.1.1.waveform.posn.127.channel=127 -unit.1.1.waveform.posn.127.name=DataPort[127] -unit.1.1.waveform.posn.127.type=signal -unit.1.1.waveform.posn.13.channel=13 -unit.1.1.waveform.posn.13.name=DataPort[13] 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-unit.1.1.waveform.posn.35.type=signal -unit.1.1.waveform.posn.36.channel=36 -unit.1.1.waveform.posn.36.name=DataPort[36] -unit.1.1.waveform.posn.36.type=signal -unit.1.1.waveform.posn.37.channel=37 -unit.1.1.waveform.posn.37.name=DataPort[37] -unit.1.1.waveform.posn.37.type=signal -unit.1.1.waveform.posn.38.channel=38 -unit.1.1.waveform.posn.38.name=DataPort[38] -unit.1.1.waveform.posn.38.type=signal -unit.1.1.waveform.posn.39.channel=39 -unit.1.1.waveform.posn.39.name=DataPort[39] -unit.1.1.waveform.posn.39.type=signal -unit.1.1.waveform.posn.4.channel=4 -unit.1.1.waveform.posn.4.name=DataPort[4] -unit.1.1.waveform.posn.4.type=signal -unit.1.1.waveform.posn.40.channel=40 -unit.1.1.waveform.posn.40.name=DataPort[40] -unit.1.1.waveform.posn.40.type=signal -unit.1.1.waveform.posn.41.channel=41 -unit.1.1.waveform.posn.41.name=DataPort[41] -unit.1.1.waveform.posn.41.type=signal -unit.1.1.waveform.posn.42.channel=42 -unit.1.1.waveform.posn.42.name=DataPort[42] -unit.1.1.waveform.posn.42.type=signal -unit.1.1.waveform.posn.43.channel=43 -unit.1.1.waveform.posn.43.name=DataPort[43] -unit.1.1.waveform.posn.43.type=signal -unit.1.1.waveform.posn.44.channel=44 -unit.1.1.waveform.posn.44.name=DataPort[44] -unit.1.1.waveform.posn.44.type=signal -unit.1.1.waveform.posn.45.channel=45 -unit.1.1.waveform.posn.45.name=DataPort[45] -unit.1.1.waveform.posn.45.type=signal -unit.1.1.waveform.posn.46.channel=46 -unit.1.1.waveform.posn.46.name=DataPort[46] -unit.1.1.waveform.posn.46.type=signal -unit.1.1.waveform.posn.47.channel=47 -unit.1.1.waveform.posn.47.name=DataPort[47] -unit.1.1.waveform.posn.47.type=signal -unit.1.1.waveform.posn.48.channel=48 -unit.1.1.waveform.posn.48.name=DataPort[48] -unit.1.1.waveform.posn.48.type=signal -unit.1.1.waveform.posn.49.channel=49 -unit.1.1.waveform.posn.49.name=DataPort[49] -unit.1.1.waveform.posn.49.type=signal -unit.1.1.waveform.posn.5.channel=5 -unit.1.1.waveform.posn.5.name=DataPort[5] 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-unit.1.1.waveform.posn.71.type=signal -unit.1.1.waveform.posn.72.channel=72 -unit.1.1.waveform.posn.72.name=DataPort[72] -unit.1.1.waveform.posn.72.type=signal -unit.1.1.waveform.posn.73.channel=73 -unit.1.1.waveform.posn.73.name=DataPort[73] -unit.1.1.waveform.posn.73.type=signal -unit.1.1.waveform.posn.74.channel=74 -unit.1.1.waveform.posn.74.name=DataPort[74] -unit.1.1.waveform.posn.74.type=signal -unit.1.1.waveform.posn.75.channel=75 -unit.1.1.waveform.posn.75.name=DataPort[75] -unit.1.1.waveform.posn.75.type=signal -unit.1.1.waveform.posn.76.channel=76 -unit.1.1.waveform.posn.76.name=DataPort[76] -unit.1.1.waveform.posn.76.type=signal -unit.1.1.waveform.posn.77.channel=77 -unit.1.1.waveform.posn.77.name=DataPort[77] -unit.1.1.waveform.posn.77.type=signal -unit.1.1.waveform.posn.78.channel=78 -unit.1.1.waveform.posn.78.name=DataPort[78] -unit.1.1.waveform.posn.78.type=signal -unit.1.1.waveform.posn.79.channel=79 -unit.1.1.waveform.posn.79.name=DataPort[79] -unit.1.1.waveform.posn.79.type=signal -unit.1.1.waveform.posn.8.channel=8 -unit.1.1.waveform.posn.8.name=DataPort[8] -unit.1.1.waveform.posn.8.type=signal -unit.1.1.waveform.posn.80.channel=80 -unit.1.1.waveform.posn.80.name=DataPort[80] -unit.1.1.waveform.posn.80.type=signal -unit.1.1.waveform.posn.81.channel=81 -unit.1.1.waveform.posn.81.name=DataPort[81] -unit.1.1.waveform.posn.81.type=signal -unit.1.1.waveform.posn.82.channel=82 -unit.1.1.waveform.posn.82.name=DataPort[82] -unit.1.1.waveform.posn.82.type=signal -unit.1.1.waveform.posn.83.channel=83 -unit.1.1.waveform.posn.83.name=DataPort[83] -unit.1.1.waveform.posn.83.type=signal -unit.1.1.waveform.posn.84.channel=84 -unit.1.1.waveform.posn.84.name=DataPort[84] -unit.1.1.waveform.posn.84.type=signal -unit.1.1.waveform.posn.85.channel=85 -unit.1.1.waveform.posn.85.name=DataPort[85] -unit.1.1.waveform.posn.85.type=signal -unit.1.1.waveform.posn.86.channel=86 -unit.1.1.waveform.posn.86.name=DataPort[86] -unit.1.1.waveform.posn.86.type=signal -unit.1.1.waveform.posn.87.channel=87 -unit.1.1.waveform.posn.87.name=DataPort[87] -unit.1.1.waveform.posn.87.type=signal -unit.1.1.waveform.posn.88.channel=88 -unit.1.1.waveform.posn.88.name=DataPort[88] -unit.1.1.waveform.posn.88.type=signal -unit.1.1.waveform.posn.89.channel=89 -unit.1.1.waveform.posn.89.name=DataPort[89] -unit.1.1.waveform.posn.89.type=signal -unit.1.1.waveform.posn.9.channel=9 -unit.1.1.waveform.posn.9.name=DataPort[9] -unit.1.1.waveform.posn.9.type=signal -unit.1.1.waveform.posn.90.channel=90 -unit.1.1.waveform.posn.90.name=DataPort[90] -unit.1.1.waveform.posn.90.type=signal -unit.1.1.waveform.posn.91.channel=91 -unit.1.1.waveform.posn.91.name=DataPort[91] -unit.1.1.waveform.posn.91.type=signal -unit.1.1.waveform.posn.92.channel=92 -unit.1.1.waveform.posn.92.name=DataPort[92] -unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=93 -unit.1.1.waveform.posn.93.name=DataPort[93] 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-unit.1.2.port.-1.s.86.alias= -unit.1.2.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.86.name=DataPort[86] -unit.1.2.port.-1.s.86.orderindex=-1 -unit.1.2.port.-1.s.86.visible=1 -unit.1.2.port.-1.s.87.alias= -unit.1.2.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.87.name=DataPort[87] -unit.1.2.port.-1.s.87.orderindex=-1 -unit.1.2.port.-1.s.87.visible=1 -unit.1.2.port.-1.s.88.alias= -unit.1.2.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.88.name=DataPort[88] -unit.1.2.port.-1.s.88.orderindex=-1 -unit.1.2.port.-1.s.88.visible=1 -unit.1.2.port.-1.s.89.alias= -unit.1.2.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.89.name=DataPort[89] -unit.1.2.port.-1.s.89.orderindex=-1 -unit.1.2.port.-1.s.89.visible=1 -unit.1.2.port.-1.s.9.alias= -unit.1.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.9.name=DataPort[9] -unit.1.2.port.-1.s.9.orderindex=-1 -unit.1.2.port.-1.s.9.visible=1 -unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=1 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=1 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 -unit.1.2.port.-1.s.92.visible=1 -unit.1.2.port.-1.s.93.alias= -unit.1.2.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.93.name=DataPort[93] -unit.1.2.port.-1.s.93.orderindex=-1 -unit.1.2.port.-1.s.93.visible=1 -unit.1.2.port.-1.s.94.alias= -unit.1.2.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.94.name=DataPort[94] -unit.1.2.port.-1.s.94.orderindex=-1 -unit.1.2.port.-1.s.94.visible=1 -unit.1.2.port.-1.s.95.alias= -unit.1.2.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.95.name=DataPort[95] -unit.1.2.port.-1.s.95.orderindex=-1 -unit.1.2.port.-1.s.95.visible=1 -unit.1.2.port.-1.s.96.alias= -unit.1.2.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.96.name=DataPort[96] -unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=1 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex -unit.1.2.port.0.b.0.signedOffset=0.0 -unit.1.2.port.0.b.0.signedPrecision=0 -unit.1.2.port.0.b.0.signedScaleFactor=1.0 -unit.1.2.port.0.b.0.unsignedOffset=0.0 -unit.1.2.port.0.b.0.unsignedPrecision=0 -unit.1.2.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.0.b.0.visible=1 -unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=32 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 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-unit.1.2.port.3.s.9.orderindex=-1 -unit.1.2.port.3.s.9.visible=1 -unit.1.2.portcount=4 -unit.1.2.rep_trigger.clobber=1 -unit.1.2.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch -unit.1.2.rep_trigger.filename=waveform -unit.1.2.rep_trigger.format=ASCII -unit.1.2.rep_trigger.loggingEnabled=0 -unit.1.2.rep_trigger.signals=All Signals/Buses -unit.1.2.samplesPerTrigger=1 -unit.1.2.triggerCapture=1 -unit.1.2.triggerNSamplesTS=0 -unit.1.2.triggerPosition=0 -unit.1.2.triggerWindowCount=1 -unit.1.2.triggerWindowDepth=4096 -unit.1.2.triggerWindowTS=0 -unit.1.2.username=MyILA2 -unit.1.3.0.HEIGHT0=0.77652735 -unit.1.3.0.TriggerRow0=1 -unit.1.3.0.TriggerRow1=1 -unit.1.3.0.TriggerRow2=1 -unit.1.3.0.WIDTH0=0.95069337 -unit.1.3.0.X0=0.049306627 -unit.1.3.0.Y0=0.0 -unit.1.3.1.HEIGHT1=0.80546623 -unit.1.3.1.WIDTH1=0.8767334 -unit.1.3.1.X1=0.07473035 -unit.1.3.1.Y1=0.028938906 -unit.1.3.2.HEIGHT2=0.79742765 -unit.1.3.2.WIDTH2=0.8520801 -unit.1.3.2.X2=0.14791988 -unit.1.3.2.Y2=0.67363346 -unit.1.3.5.HEIGHT5=0.97588426 -unit.1.3.5.WIDTH5=1.0 -unit.1.3.5.X5=0.0 -unit.1.3.5.Y5=0.0 -unit.1.3.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsA3=XX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.3.MFBitsB0=00000000000000000000000000000000 -unit.1.3.MFBitsB1=00000000000000000000000000000000 -unit.1.3.MFBitsB2=00000000000000000000000000000000 -unit.1.3.MFBitsB3=00000000000000000000000000000000 -unit.1.3.MFCompareA0=0 -unit.1.3.MFCompareA1=0 -unit.1.3.MFCompareA2=0 -unit.1.3.MFCompareA3=0 -unit.1.3.MFCompareB0=999 -unit.1.3.MFCompareB1=999 -unit.1.3.MFCompareB2=999 -unit.1.3.MFCompareB3=999 -unit.1.3.MFCount=4 -unit.1.3.MFDisplay0=0 -unit.1.3.MFDisplay1=0 -unit.1.3.MFDisplay2=0 -unit.1.3.MFDisplay3=0 -unit.1.3.MFEventType0=3 -unit.1.3.MFEventType1=3 -unit.1.3.MFEventType2=3 -unit.1.3.MFEventType3=3 -unit.1.3.RunMode=SINGLE RUN -unit.1.3.SQCondition=All Data -unit.1.3.SQContiguous0=0 -unit.1.3.SequencerOn=0 -unit.1.3.TCActive=0 -unit.1.3.TCAdvanced0=0 -unit.1.3.TCCondition0_0=M3 -unit.1.3.TCCondition0_1= -unit.1.3.TCConditionType0=0 -unit.1.3.TCCount=1 -unit.1.3.TCEventCount0=1 -unit.1.3.TCEventType0=3 -unit.1.3.TCName0=TriggerCondition0 -unit.1.3.TCOutputEnable0=0 -unit.1.3.TCOutputHigh0=1 -unit.1.3.TCOutputMode0=0 -unit.1.3.browser_tree_state=1 -unit.1.3.browser_tree_state=0 -unit.1.3.browser_tree_state=0 -unit.1.3.browser_tree_state=0 -unit.1.3.browser_tree_state=0 -unit.1.3.browser_tree_state=0 -unit.1.3.coretype=ILA -unit.1.3.eventCount0=1 -unit.1.3.eventCount1=1 -unit.1.3.eventCount2=1 -unit.1.3.eventCount3=1 -unit.1.3.listing.count=0 -unit.1.3.plotBusColor0=-16777092 -unit.1.3.plotBusColor1=-16777092 -unit.1.3.plotBusColor2=-16777092 -unit.1.3.plotBusColor3=-16777092 -unit.1.3.plotBusColor4=-16777092 -unit.1.3.plotBusColor5=-16777092 -unit.1.3.plotBusColor6=-16777092 -unit.1.3.plotBusColor7=-16777092 -unit.1.3.plotBusCount=8 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-unit.1.3.port.-1.s.8.visible=0 -unit.1.3.port.-1.s.80.alias= -unit.1.3.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.80.name=DataPort[80] -unit.1.3.port.-1.s.80.orderindex=-1 -unit.1.3.port.-1.s.80.visible=0 -unit.1.3.port.-1.s.81.alias= -unit.1.3.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.81.name=DataPort[81] -unit.1.3.port.-1.s.81.orderindex=-1 -unit.1.3.port.-1.s.81.visible=0 -unit.1.3.port.-1.s.82.alias= -unit.1.3.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.82.name=DataPort[82] -unit.1.3.port.-1.s.82.orderindex=-1 -unit.1.3.port.-1.s.82.visible=0 -unit.1.3.port.-1.s.83.alias= -unit.1.3.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.83.name=DataPort[83] -unit.1.3.port.-1.s.83.orderindex=-1 -unit.1.3.port.-1.s.83.visible=0 -unit.1.3.port.-1.s.84.alias= -unit.1.3.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.84.name=DataPort[84] -unit.1.3.port.-1.s.84.orderindex=-1 -unit.1.3.port.-1.s.84.visible=0 -unit.1.3.port.-1.s.85.alias= -unit.1.3.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.85.name=DataPort[85] -unit.1.3.port.-1.s.85.orderindex=-1 -unit.1.3.port.-1.s.85.visible=0 -unit.1.3.port.-1.s.86.alias= -unit.1.3.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.86.name=DataPort[86] -unit.1.3.port.-1.s.86.orderindex=-1 -unit.1.3.port.-1.s.86.visible=0 -unit.1.3.port.-1.s.87.alias= -unit.1.3.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.87.name=DataPort[87] -unit.1.3.port.-1.s.87.orderindex=-1 -unit.1.3.port.-1.s.87.visible=0 -unit.1.3.port.-1.s.88.alias= -unit.1.3.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.88.name=DataPort[88] -unit.1.3.port.-1.s.88.orderindex=-1 -unit.1.3.port.-1.s.88.visible=0 -unit.1.3.port.-1.s.89.alias= -unit.1.3.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.89.name=DataPort[89] -unit.1.3.port.-1.s.89.orderindex=-1 -unit.1.3.port.-1.s.89.visible=0 -unit.1.3.port.-1.s.9.alias= -unit.1.3.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.9.name=DataPort[9] -unit.1.3.port.-1.s.9.orderindex=-1 -unit.1.3.port.-1.s.9.visible=0 -unit.1.3.port.-1.s.90.alias= -unit.1.3.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.90.name=DataPort[90] -unit.1.3.port.-1.s.90.orderindex=-1 -unit.1.3.port.-1.s.90.visible=0 -unit.1.3.port.-1.s.91.alias= -unit.1.3.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.91.name=DataPort[91] -unit.1.3.port.-1.s.91.orderindex=-1 -unit.1.3.port.-1.s.91.visible=0 -unit.1.3.port.-1.s.92.alias= -unit.1.3.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.92.name=DataPort[92] -unit.1.3.port.-1.s.92.orderindex=-1 -unit.1.3.port.-1.s.92.visible=0 -unit.1.3.port.-1.s.93.alias= -unit.1.3.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.93.name=DataPort[93] -unit.1.3.port.-1.s.93.orderindex=-1 -unit.1.3.port.-1.s.93.visible=0 -unit.1.3.port.-1.s.94.alias= -unit.1.3.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.94.name=DataPort[94] -unit.1.3.port.-1.s.94.orderindex=-1 -unit.1.3.port.-1.s.94.visible=0 -unit.1.3.port.-1.s.95.alias= -unit.1.3.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.95.name=DataPort[95] -unit.1.3.port.-1.s.95.orderindex=-1 -unit.1.3.port.-1.s.95.visible=0 -unit.1.3.port.-1.s.96.alias= -unit.1.3.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.96.name=DataPort[96] -unit.1.3.port.-1.s.96.orderindex=-1 -unit.1.3.port.-1.s.96.visible=0 -unit.1.3.port.-1.s.97.alias= -unit.1.3.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.97.name=DataPort[97] -unit.1.3.port.-1.s.97.orderindex=-1 -unit.1.3.port.-1.s.97.visible=0 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-unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 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-unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 -unit.1.3.port.3.s.7.visible=1 -unit.1.3.port.3.s.8.alias= -unit.1.3.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.8.name=TriggerPort3[8] -unit.1.3.port.3.s.8.orderindex=-1 -unit.1.3.port.3.s.8.visible=1 -unit.1.3.port.3.s.9.alias= -unit.1.3.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.9.name=TriggerPort3[9] -unit.1.3.port.3.s.9.orderindex=-1 -unit.1.3.port.3.s.9.visible=1 -unit.1.3.portcount=4 -unit.1.3.rep_trigger.clobber=1 -unit.1.3.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch -unit.1.3.rep_trigger.filename=waveform -unit.1.3.rep_trigger.format=ASCII -unit.1.3.rep_trigger.loggingEnabled=0 -unit.1.3.rep_trigger.signals=All Signals/Buses -unit.1.3.samplesPerTrigger=1 -unit.1.3.triggerCapture=1 -unit.1.3.triggerNSamplesTS=0 -unit.1.3.triggerPosition=0 -unit.1.3.triggerWindowCount=1 -unit.1.3.triggerWindowDepth=4096 -unit.1.3.triggerWindowTS=0 -unit.1.3.username=MyILA3 -unit.1.3.waveform.count=8 -unit.1.3.waveform.posn.0.channel=2147483646 -unit.1.3.waveform.posn.0.name=wb_ma_pcie_dat_in -unit.1.3.waveform.posn.0.radix=1 -unit.1.3.waveform.posn.0.type=bus -unit.1.3.waveform.posn.1.channel=2147483646 -unit.1.3.waveform.posn.1.name=wb_ma_pcie_dat_out -unit.1.3.waveform.posn.1.radix=1 -unit.1.3.waveform.posn.1.type=bus -unit.1.3.waveform.posn.10.channel=2147483646 -unit.1.3.waveform.posn.10.name=wb_pcie_stb -unit.1.3.waveform.posn.10.radix=1 -unit.1.3.waveform.posn.10.type=bus -unit.1.3.waveform.posn.100.channel=2147483646 -unit.1.3.waveform.posn.100.name=wb_pcie_stb -unit.1.3.waveform.posn.100.radix=1 -unit.1.3.waveform.posn.100.type=bus -unit.1.3.waveform.posn.101.channel=2147483646 -unit.1.3.waveform.posn.101.name=wb_pcie_stb -unit.1.3.waveform.posn.101.radix=1 -unit.1.3.waveform.posn.101.type=bus -unit.1.3.waveform.posn.102.channel=2147483646 -unit.1.3.waveform.posn.102.name=wb_pcie_stb -unit.1.3.waveform.posn.102.radix=1 -unit.1.3.waveform.posn.102.type=bus -unit.1.3.waveform.posn.103.channel=2147483646 -unit.1.3.waveform.posn.103.name=wb_pcie_stb -unit.1.3.waveform.posn.103.radix=1 -unit.1.3.waveform.posn.103.type=bus -unit.1.3.waveform.posn.104.channel=2147483646 -unit.1.3.waveform.posn.104.name=wb_pcie_stb -unit.1.3.waveform.posn.104.radix=1 -unit.1.3.waveform.posn.104.type=bus -unit.1.3.waveform.posn.105.channel=2147483646 -unit.1.3.waveform.posn.105.name=wb_pcie_stb -unit.1.3.waveform.posn.105.radix=1 -unit.1.3.waveform.posn.105.type=bus -unit.1.3.waveform.posn.106.channel=2147483646 -unit.1.3.waveform.posn.106.name=wb_pcie_stb -unit.1.3.waveform.posn.106.radix=1 -unit.1.3.waveform.posn.106.type=bus -unit.1.3.waveform.posn.107.channel=2147483646 -unit.1.3.waveform.posn.107.name=wb_pcie_stb -unit.1.3.waveform.posn.107.radix=1 -unit.1.3.waveform.posn.107.type=bus -unit.1.3.waveform.posn.108.channel=2147483646 -unit.1.3.waveform.posn.108.name=wb_pcie_stb -unit.1.3.waveform.posn.108.radix=1 -unit.1.3.waveform.posn.108.type=bus -unit.1.3.waveform.posn.109.channel=2147483646 -unit.1.3.waveform.posn.109.name=wb_pcie_stb -unit.1.3.waveform.posn.109.radix=1 -unit.1.3.waveform.posn.109.type=bus -unit.1.3.waveform.posn.11.channel=2147483646 -unit.1.3.waveform.posn.11.name=wb_pcie_stb -unit.1.3.waveform.posn.11.radix=1 -unit.1.3.waveform.posn.11.type=bus -unit.1.3.waveform.posn.110.channel=2147483646 -unit.1.3.waveform.posn.110.name=wb_pcie_stb -unit.1.3.waveform.posn.110.radix=1 -unit.1.3.waveform.posn.110.type=bus -unit.1.3.waveform.posn.111.channel=2147483646 -unit.1.3.waveform.posn.111.name=wb_pcie_stb -unit.1.3.waveform.posn.111.radix=1 -unit.1.3.waveform.posn.111.type=bus -unit.1.3.waveform.posn.112.channel=2147483646 -unit.1.3.waveform.posn.112.name=wb_pcie_stb -unit.1.3.waveform.posn.112.radix=1 -unit.1.3.waveform.posn.112.type=bus -unit.1.3.waveform.posn.113.channel=2147483646 -unit.1.3.waveform.posn.113.name=wb_pcie_stb -unit.1.3.waveform.posn.113.radix=1 -unit.1.3.waveform.posn.113.type=bus -unit.1.3.waveform.posn.114.channel=2147483646 -unit.1.3.waveform.posn.114.name=wb_pcie_stb -unit.1.3.waveform.posn.114.radix=1 -unit.1.3.waveform.posn.114.type=bus -unit.1.3.waveform.posn.115.channel=2147483646 -unit.1.3.waveform.posn.115.name=wb_pcie_stb -unit.1.3.waveform.posn.115.radix=1 -unit.1.3.waveform.posn.115.type=bus -unit.1.3.waveform.posn.116.channel=2147483646 -unit.1.3.waveform.posn.116.name=wb_pcie_stb -unit.1.3.waveform.posn.116.radix=1 -unit.1.3.waveform.posn.116.type=bus -unit.1.3.waveform.posn.117.channel=2147483646 -unit.1.3.waveform.posn.117.name=wb_pcie_stb -unit.1.3.waveform.posn.117.radix=1 -unit.1.3.waveform.posn.117.type=bus -unit.1.3.waveform.posn.118.channel=2147483646 -unit.1.3.waveform.posn.118.name=wb_pcie_stb -unit.1.3.waveform.posn.118.radix=1 -unit.1.3.waveform.posn.118.type=bus -unit.1.3.waveform.posn.119.channel=2147483646 -unit.1.3.waveform.posn.119.name=wb_pcie_stb -unit.1.3.waveform.posn.119.radix=1 -unit.1.3.waveform.posn.119.type=bus -unit.1.3.waveform.posn.12.channel=2147483646 -unit.1.3.waveform.posn.12.name=wb_pcie_stb -unit.1.3.waveform.posn.12.radix=1 -unit.1.3.waveform.posn.12.type=bus -unit.1.3.waveform.posn.120.channel=2147483646 -unit.1.3.waveform.posn.120.name=wb_pcie_stb -unit.1.3.waveform.posn.120.radix=1 -unit.1.3.waveform.posn.120.type=bus -unit.1.3.waveform.posn.121.channel=2147483646 -unit.1.3.waveform.posn.121.name=wb_pcie_stb -unit.1.3.waveform.posn.121.radix=1 -unit.1.3.waveform.posn.121.type=bus -unit.1.3.waveform.posn.122.channel=2147483646 -unit.1.3.waveform.posn.122.name=wb_pcie_stb -unit.1.3.waveform.posn.122.radix=1 -unit.1.3.waveform.posn.122.type=bus -unit.1.3.waveform.posn.123.channel=2147483646 -unit.1.3.waveform.posn.123.name=wb_pcie_stb -unit.1.3.waveform.posn.123.radix=1 -unit.1.3.waveform.posn.123.type=bus -unit.1.3.waveform.posn.124.channel=2147483646 -unit.1.3.waveform.posn.124.name=wb_pcie_stb -unit.1.3.waveform.posn.124.radix=1 -unit.1.3.waveform.posn.124.type=bus -unit.1.3.waveform.posn.125.channel=2147483646 -unit.1.3.waveform.posn.125.name=wb_pcie_stb -unit.1.3.waveform.posn.125.radix=1 -unit.1.3.waveform.posn.125.type=bus -unit.1.3.waveform.posn.126.channel=2147483646 -unit.1.3.waveform.posn.126.name=wb_pcie_stb -unit.1.3.waveform.posn.126.radix=1 -unit.1.3.waveform.posn.126.type=bus -unit.1.3.waveform.posn.127.channel=2147483646 -unit.1.3.waveform.posn.127.name=wb_pcie_stb -unit.1.3.waveform.posn.127.radix=1 -unit.1.3.waveform.posn.127.type=bus -unit.1.3.waveform.posn.13.channel=2147483646 -unit.1.3.waveform.posn.13.name=wb_pcie_stb -unit.1.3.waveform.posn.13.radix=1 -unit.1.3.waveform.posn.13.type=bus -unit.1.3.waveform.posn.14.channel=2147483646 -unit.1.3.waveform.posn.14.name=wb_pcie_stb -unit.1.3.waveform.posn.14.radix=1 -unit.1.3.waveform.posn.14.type=bus -unit.1.3.waveform.posn.15.channel=2147483646 -unit.1.3.waveform.posn.15.name=wb_pcie_stb -unit.1.3.waveform.posn.15.radix=1 -unit.1.3.waveform.posn.15.type=bus -unit.1.3.waveform.posn.16.channel=2147483646 -unit.1.3.waveform.posn.16.name=wb_pcie_stb -unit.1.3.waveform.posn.16.radix=1 -unit.1.3.waveform.posn.16.type=bus -unit.1.3.waveform.posn.17.channel=2147483646 -unit.1.3.waveform.posn.17.name=wb_pcie_stb -unit.1.3.waveform.posn.17.radix=1 -unit.1.3.waveform.posn.17.type=bus -unit.1.3.waveform.posn.18.channel=2147483646 -unit.1.3.waveform.posn.18.name=wb_pcie_stb -unit.1.3.waveform.posn.18.radix=1 -unit.1.3.waveform.posn.18.type=bus -unit.1.3.waveform.posn.19.channel=2147483646 -unit.1.3.waveform.posn.19.name=wb_pcie_stb -unit.1.3.waveform.posn.19.radix=1 -unit.1.3.waveform.posn.19.type=bus -unit.1.3.waveform.posn.2.channel=2147483646 -unit.1.3.waveform.posn.2.name=wb_ma_pcie_addr_out -unit.1.3.waveform.posn.2.radix=1 -unit.1.3.waveform.posn.2.type=bus -unit.1.3.waveform.posn.20.channel=2147483646 -unit.1.3.waveform.posn.20.name=wb_pcie_stb -unit.1.3.waveform.posn.20.radix=1 -unit.1.3.waveform.posn.20.type=bus -unit.1.3.waveform.posn.21.channel=2147483646 -unit.1.3.waveform.posn.21.name=wb_pcie_stb -unit.1.3.waveform.posn.21.radix=1 -unit.1.3.waveform.posn.21.type=bus -unit.1.3.waveform.posn.22.channel=2147483646 -unit.1.3.waveform.posn.22.name=wb_pcie_stb -unit.1.3.waveform.posn.22.radix=1 -unit.1.3.waveform.posn.22.type=bus -unit.1.3.waveform.posn.23.channel=2147483646 -unit.1.3.waveform.posn.23.name=wb_pcie_stb -unit.1.3.waveform.posn.23.radix=1 -unit.1.3.waveform.posn.23.type=bus -unit.1.3.waveform.posn.24.channel=2147483646 -unit.1.3.waveform.posn.24.name=wb_pcie_stb -unit.1.3.waveform.posn.24.radix=1 -unit.1.3.waveform.posn.24.type=bus -unit.1.3.waveform.posn.25.channel=2147483646 -unit.1.3.waveform.posn.25.name=wb_pcie_stb -unit.1.3.waveform.posn.25.radix=1 -unit.1.3.waveform.posn.25.type=bus -unit.1.3.waveform.posn.26.channel=2147483646 -unit.1.3.waveform.posn.26.name=wb_pcie_stb -unit.1.3.waveform.posn.26.radix=1 -unit.1.3.waveform.posn.26.type=bus -unit.1.3.waveform.posn.27.channel=2147483646 -unit.1.3.waveform.posn.27.name=wb_pcie_stb -unit.1.3.waveform.posn.27.radix=1 -unit.1.3.waveform.posn.27.type=bus -unit.1.3.waveform.posn.28.channel=2147483646 -unit.1.3.waveform.posn.28.name=wb_pcie_stb -unit.1.3.waveform.posn.28.radix=1 -unit.1.3.waveform.posn.28.type=bus -unit.1.3.waveform.posn.29.channel=2147483646 -unit.1.3.waveform.posn.29.name=wb_pcie_stb -unit.1.3.waveform.posn.29.radix=1 -unit.1.3.waveform.posn.29.type=bus -unit.1.3.waveform.posn.3.channel=2147483646 -unit.1.3.waveform.posn.3.name=wb_pcie_cyc -unit.1.3.waveform.posn.3.radix=1 -unit.1.3.waveform.posn.3.type=bus -unit.1.3.waveform.posn.30.channel=2147483646 -unit.1.3.waveform.posn.30.name=wb_pcie_stb -unit.1.3.waveform.posn.30.radix=1 -unit.1.3.waveform.posn.30.type=bus -unit.1.3.waveform.posn.31.channel=2147483646 -unit.1.3.waveform.posn.31.name=wb_pcie_stb -unit.1.3.waveform.posn.31.radix=1 -unit.1.3.waveform.posn.31.type=bus -unit.1.3.waveform.posn.32.channel=2147483646 -unit.1.3.waveform.posn.32.name=wb_pcie_stb -unit.1.3.waveform.posn.32.radix=1 -unit.1.3.waveform.posn.32.type=bus -unit.1.3.waveform.posn.33.channel=2147483646 -unit.1.3.waveform.posn.33.name=wb_pcie_stb -unit.1.3.waveform.posn.33.radix=1 -unit.1.3.waveform.posn.33.type=bus -unit.1.3.waveform.posn.34.channel=2147483646 -unit.1.3.waveform.posn.34.name=wb_pcie_stb -unit.1.3.waveform.posn.34.radix=1 -unit.1.3.waveform.posn.34.type=bus -unit.1.3.waveform.posn.35.channel=2147483646 -unit.1.3.waveform.posn.35.name=wb_pcie_stb -unit.1.3.waveform.posn.35.radix=1 -unit.1.3.waveform.posn.35.type=bus -unit.1.3.waveform.posn.36.channel=2147483646 -unit.1.3.waveform.posn.36.name=wb_pcie_stb -unit.1.3.waveform.posn.36.radix=1 -unit.1.3.waveform.posn.36.type=bus -unit.1.3.waveform.posn.37.channel=2147483646 -unit.1.3.waveform.posn.37.name=wb_pcie_stb -unit.1.3.waveform.posn.37.radix=1 -unit.1.3.waveform.posn.37.type=bus -unit.1.3.waveform.posn.38.channel=2147483646 -unit.1.3.waveform.posn.38.name=wb_pcie_stb -unit.1.3.waveform.posn.38.radix=1 -unit.1.3.waveform.posn.38.type=bus -unit.1.3.waveform.posn.39.channel=2147483646 -unit.1.3.waveform.posn.39.name=wb_pcie_stb -unit.1.3.waveform.posn.39.radix=1 -unit.1.3.waveform.posn.39.type=bus -unit.1.3.waveform.posn.4.channel=2147483646 -unit.1.3.waveform.posn.4.name=wb_pcie_sel -unit.1.3.waveform.posn.4.radix=1 -unit.1.3.waveform.posn.4.type=bus -unit.1.3.waveform.posn.40.channel=2147483646 -unit.1.3.waveform.posn.40.name=wb_pcie_stb -unit.1.3.waveform.posn.40.radix=1 -unit.1.3.waveform.posn.40.type=bus -unit.1.3.waveform.posn.41.channel=2147483646 -unit.1.3.waveform.posn.41.name=wb_pcie_stb -unit.1.3.waveform.posn.41.radix=1 -unit.1.3.waveform.posn.41.type=bus -unit.1.3.waveform.posn.42.channel=2147483646 -unit.1.3.waveform.posn.42.name=wb_pcie_stb -unit.1.3.waveform.posn.42.radix=1 -unit.1.3.waveform.posn.42.type=bus -unit.1.3.waveform.posn.43.channel=2147483646 -unit.1.3.waveform.posn.43.name=wb_pcie_stb -unit.1.3.waveform.posn.43.radix=1 -unit.1.3.waveform.posn.43.type=bus -unit.1.3.waveform.posn.44.channel=2147483646 -unit.1.3.waveform.posn.44.name=wb_pcie_stb -unit.1.3.waveform.posn.44.radix=1 -unit.1.3.waveform.posn.44.type=bus -unit.1.3.waveform.posn.45.channel=2147483646 -unit.1.3.waveform.posn.45.name=wb_pcie_stb -unit.1.3.waveform.posn.45.radix=1 -unit.1.3.waveform.posn.45.type=bus -unit.1.3.waveform.posn.46.channel=2147483646 -unit.1.3.waveform.posn.46.name=wb_pcie_stb -unit.1.3.waveform.posn.46.radix=1 -unit.1.3.waveform.posn.46.type=bus -unit.1.3.waveform.posn.47.channel=2147483646 -unit.1.3.waveform.posn.47.name=wb_pcie_stb -unit.1.3.waveform.posn.47.radix=1 -unit.1.3.waveform.posn.47.type=bus -unit.1.3.waveform.posn.48.channel=2147483646 -unit.1.3.waveform.posn.48.name=wb_pcie_stb -unit.1.3.waveform.posn.48.radix=1 -unit.1.3.waveform.posn.48.type=bus -unit.1.3.waveform.posn.49.channel=2147483646 -unit.1.3.waveform.posn.49.name=wb_pcie_stb -unit.1.3.waveform.posn.49.radix=1 -unit.1.3.waveform.posn.49.type=bus -unit.1.3.waveform.posn.5.channel=2147483646 -unit.1.3.waveform.posn.5.name=wb_ma_pcie_we_out -unit.1.3.waveform.posn.5.radix=1 -unit.1.3.waveform.posn.5.type=bus -unit.1.3.waveform.posn.50.channel=2147483646 -unit.1.3.waveform.posn.50.name=wb_pcie_stb -unit.1.3.waveform.posn.50.radix=1 -unit.1.3.waveform.posn.50.type=bus -unit.1.3.waveform.posn.51.channel=2147483646 -unit.1.3.waveform.posn.51.name=wb_pcie_stb -unit.1.3.waveform.posn.51.radix=1 -unit.1.3.waveform.posn.51.type=bus -unit.1.3.waveform.posn.52.channel=2147483646 -unit.1.3.waveform.posn.52.name=wb_pcie_stb -unit.1.3.waveform.posn.52.radix=1 -unit.1.3.waveform.posn.52.type=bus -unit.1.3.waveform.posn.53.channel=2147483646 -unit.1.3.waveform.posn.53.name=wb_pcie_stb -unit.1.3.waveform.posn.53.radix=1 -unit.1.3.waveform.posn.53.type=bus -unit.1.3.waveform.posn.54.channel=2147483646 -unit.1.3.waveform.posn.54.name=wb_pcie_stb -unit.1.3.waveform.posn.54.radix=1 -unit.1.3.waveform.posn.54.type=bus -unit.1.3.waveform.posn.55.channel=2147483646 -unit.1.3.waveform.posn.55.name=wb_pcie_stb -unit.1.3.waveform.posn.55.radix=1 -unit.1.3.waveform.posn.55.type=bus -unit.1.3.waveform.posn.56.channel=2147483646 -unit.1.3.waveform.posn.56.name=wb_pcie_stb -unit.1.3.waveform.posn.56.radix=1 -unit.1.3.waveform.posn.56.type=bus -unit.1.3.waveform.posn.57.channel=2147483646 -unit.1.3.waveform.posn.57.name=wb_pcie_stb -unit.1.3.waveform.posn.57.radix=1 -unit.1.3.waveform.posn.57.type=bus -unit.1.3.waveform.posn.58.channel=2147483646 -unit.1.3.waveform.posn.58.name=wb_pcie_stb -unit.1.3.waveform.posn.58.radix=1 -unit.1.3.waveform.posn.58.type=bus -unit.1.3.waveform.posn.59.channel=2147483646 -unit.1.3.waveform.posn.59.name=wb_pcie_stb -unit.1.3.waveform.posn.59.radix=1 -unit.1.3.waveform.posn.59.type=bus -unit.1.3.waveform.posn.6.channel=2147483646 -unit.1.3.waveform.posn.6.name=wb_ma_pcie_ack_in -unit.1.3.waveform.posn.6.radix=1 -unit.1.3.waveform.posn.6.type=bus -unit.1.3.waveform.posn.60.channel=2147483646 -unit.1.3.waveform.posn.60.name=wb_pcie_stb -unit.1.3.waveform.posn.60.radix=1 -unit.1.3.waveform.posn.60.type=bus -unit.1.3.waveform.posn.61.channel=2147483646 -unit.1.3.waveform.posn.61.name=wb_pcie_stb -unit.1.3.waveform.posn.61.radix=1 -unit.1.3.waveform.posn.61.type=bus -unit.1.3.waveform.posn.62.channel=2147483646 -unit.1.3.waveform.posn.62.name=wb_pcie_stb -unit.1.3.waveform.posn.62.radix=1 -unit.1.3.waveform.posn.62.type=bus -unit.1.3.waveform.posn.63.channel=2147483646 -unit.1.3.waveform.posn.63.name=wb_pcie_stb -unit.1.3.waveform.posn.63.radix=1 -unit.1.3.waveform.posn.63.type=bus -unit.1.3.waveform.posn.64.channel=2147483646 -unit.1.3.waveform.posn.64.name=wb_pcie_stb -unit.1.3.waveform.posn.64.radix=1 -unit.1.3.waveform.posn.64.type=bus -unit.1.3.waveform.posn.65.channel=2147483646 -unit.1.3.waveform.posn.65.name=wb_pcie_stb -unit.1.3.waveform.posn.65.radix=1 -unit.1.3.waveform.posn.65.type=bus -unit.1.3.waveform.posn.66.channel=2147483646 -unit.1.3.waveform.posn.66.name=wb_pcie_stb -unit.1.3.waveform.posn.66.radix=1 -unit.1.3.waveform.posn.66.type=bus -unit.1.3.waveform.posn.67.channel=2147483646 -unit.1.3.waveform.posn.67.name=wb_pcie_stb -unit.1.3.waveform.posn.67.radix=1 -unit.1.3.waveform.posn.67.type=bus -unit.1.3.waveform.posn.68.channel=2147483646 -unit.1.3.waveform.posn.68.name=wb_pcie_stb -unit.1.3.waveform.posn.68.radix=1 -unit.1.3.waveform.posn.68.type=bus -unit.1.3.waveform.posn.69.channel=2147483646 -unit.1.3.waveform.posn.69.name=wb_pcie_stb -unit.1.3.waveform.posn.69.radix=1 -unit.1.3.waveform.posn.69.type=bus -unit.1.3.waveform.posn.7.channel=2147483646 -unit.1.3.waveform.posn.7.name=wb_pcie_stb -unit.1.3.waveform.posn.7.radix=1 -unit.1.3.waveform.posn.7.type=bus -unit.1.3.waveform.posn.70.channel=2147483646 -unit.1.3.waveform.posn.70.name=wb_pcie_stb -unit.1.3.waveform.posn.70.radix=1 -unit.1.3.waveform.posn.70.type=bus -unit.1.3.waveform.posn.71.channel=2147483646 -unit.1.3.waveform.posn.71.name=wb_pcie_stb -unit.1.3.waveform.posn.71.radix=1 -unit.1.3.waveform.posn.71.type=bus -unit.1.3.waveform.posn.72.channel=2147483646 -unit.1.3.waveform.posn.72.name=wb_pcie_stb -unit.1.3.waveform.posn.72.radix=1 -unit.1.3.waveform.posn.72.type=bus -unit.1.3.waveform.posn.73.channel=2147483646 -unit.1.3.waveform.posn.73.name=wb_pcie_stb -unit.1.3.waveform.posn.73.radix=1 -unit.1.3.waveform.posn.73.type=bus -unit.1.3.waveform.posn.74.channel=2147483646 -unit.1.3.waveform.posn.74.name=wb_pcie_stb -unit.1.3.waveform.posn.74.radix=1 -unit.1.3.waveform.posn.74.type=bus -unit.1.3.waveform.posn.75.channel=2147483646 -unit.1.3.waveform.posn.75.name=wb_pcie_stb -unit.1.3.waveform.posn.75.radix=1 -unit.1.3.waveform.posn.75.type=bus -unit.1.3.waveform.posn.76.channel=2147483646 -unit.1.3.waveform.posn.76.name=wb_pcie_stb -unit.1.3.waveform.posn.76.radix=1 -unit.1.3.waveform.posn.76.type=bus -unit.1.3.waveform.posn.77.channel=2147483646 -unit.1.3.waveform.posn.77.name=wb_pcie_stb -unit.1.3.waveform.posn.77.radix=1 -unit.1.3.waveform.posn.77.type=bus -unit.1.3.waveform.posn.78.channel=2147483646 -unit.1.3.waveform.posn.78.name=wb_pcie_stb -unit.1.3.waveform.posn.78.radix=1 -unit.1.3.waveform.posn.78.type=bus -unit.1.3.waveform.posn.79.channel=2147483646 -unit.1.3.waveform.posn.79.name=wb_pcie_stb -unit.1.3.waveform.posn.79.radix=1 -unit.1.3.waveform.posn.79.type=bus -unit.1.3.waveform.posn.8.channel=2147483646 -unit.1.3.waveform.posn.8.name=wb_pcie_stb -unit.1.3.waveform.posn.8.radix=1 -unit.1.3.waveform.posn.8.type=bus -unit.1.3.waveform.posn.80.channel=2147483646 -unit.1.3.waveform.posn.80.name=wb_pcie_stb -unit.1.3.waveform.posn.80.radix=1 -unit.1.3.waveform.posn.80.type=bus -unit.1.3.waveform.posn.81.channel=2147483646 -unit.1.3.waveform.posn.81.name=wb_pcie_stb -unit.1.3.waveform.posn.81.radix=1 -unit.1.3.waveform.posn.81.type=bus -unit.1.3.waveform.posn.82.channel=2147483646 -unit.1.3.waveform.posn.82.name=wb_pcie_stb -unit.1.3.waveform.posn.82.radix=1 -unit.1.3.waveform.posn.82.type=bus -unit.1.3.waveform.posn.83.channel=2147483646 -unit.1.3.waveform.posn.83.name=wb_pcie_stb -unit.1.3.waveform.posn.83.radix=1 -unit.1.3.waveform.posn.83.type=bus -unit.1.3.waveform.posn.84.channel=2147483646 -unit.1.3.waveform.posn.84.name=wb_pcie_stb -unit.1.3.waveform.posn.84.radix=1 -unit.1.3.waveform.posn.84.type=bus -unit.1.3.waveform.posn.85.channel=2147483646 -unit.1.3.waveform.posn.85.name=wb_pcie_stb -unit.1.3.waveform.posn.85.radix=1 -unit.1.3.waveform.posn.85.type=bus -unit.1.3.waveform.posn.86.channel=2147483646 -unit.1.3.waveform.posn.86.name=wb_pcie_stb -unit.1.3.waveform.posn.86.radix=1 -unit.1.3.waveform.posn.86.type=bus -unit.1.3.waveform.posn.87.channel=2147483646 -unit.1.3.waveform.posn.87.name=wb_pcie_stb -unit.1.3.waveform.posn.87.radix=1 -unit.1.3.waveform.posn.87.type=bus -unit.1.3.waveform.posn.88.channel=2147483646 -unit.1.3.waveform.posn.88.name=wb_pcie_stb -unit.1.3.waveform.posn.88.radix=1 -unit.1.3.waveform.posn.88.type=bus -unit.1.3.waveform.posn.89.channel=2147483646 -unit.1.3.waveform.posn.89.name=wb_pcie_stb -unit.1.3.waveform.posn.89.radix=1 -unit.1.3.waveform.posn.89.type=bus -unit.1.3.waveform.posn.9.channel=2147483646 -unit.1.3.waveform.posn.9.name=wb_pcie_stb -unit.1.3.waveform.posn.9.radix=1 -unit.1.3.waveform.posn.9.type=bus -unit.1.3.waveform.posn.90.channel=2147483646 -unit.1.3.waveform.posn.90.name=wb_pcie_stb -unit.1.3.waveform.posn.90.radix=1 -unit.1.3.waveform.posn.90.type=bus -unit.1.3.waveform.posn.91.channel=2147483646 -unit.1.3.waveform.posn.91.name=wb_pcie_stb -unit.1.3.waveform.posn.91.radix=1 -unit.1.3.waveform.posn.91.type=bus -unit.1.3.waveform.posn.92.channel=2147483646 -unit.1.3.waveform.posn.92.name=wb_pcie_stb -unit.1.3.waveform.posn.92.radix=1 -unit.1.3.waveform.posn.92.type=bus -unit.1.3.waveform.posn.93.channel=2147483646 -unit.1.3.waveform.posn.93.name=wb_pcie_stb -unit.1.3.waveform.posn.93.radix=1 -unit.1.3.waveform.posn.93.type=bus -unit.1.3.waveform.posn.94.channel=2147483646 -unit.1.3.waveform.posn.94.name=wb_pcie_stb -unit.1.3.waveform.posn.94.radix=1 -unit.1.3.waveform.posn.94.type=bus -unit.1.3.waveform.posn.95.channel=2147483646 -unit.1.3.waveform.posn.95.name=wb_pcie_stb -unit.1.3.waveform.posn.95.radix=1 -unit.1.3.waveform.posn.95.type=bus -unit.1.3.waveform.posn.96.channel=2147483646 -unit.1.3.waveform.posn.96.name=wb_pcie_stb -unit.1.3.waveform.posn.96.radix=1 -unit.1.3.waveform.posn.96.type=bus -unit.1.3.waveform.posn.97.channel=2147483646 -unit.1.3.waveform.posn.97.name=wb_pcie_stb -unit.1.3.waveform.posn.97.radix=1 -unit.1.3.waveform.posn.97.type=bus -unit.1.3.waveform.posn.98.channel=2147483646 -unit.1.3.waveform.posn.98.name=wb_pcie_stb -unit.1.3.waveform.posn.98.radix=1 -unit.1.3.waveform.posn.98.type=bus -unit.1.3.waveform.posn.99.channel=2147483646 -unit.1.3.waveform.posn.99.name=wb_pcie_stb -unit.1.3.waveform.posn.99.radix=1 -unit.1.3.waveform.posn.99.type=bus -unit.1.4.0.HEIGHT0=0.73472667 -unit.1.4.0.TriggerRow0=1 -unit.1.4.0.TriggerRow1=1 -unit.1.4.0.TriggerRow2=1 -unit.1.4.0.WIDTH0=0.9753467 -unit.1.4.0.X0=0.024653314 -unit.1.4.0.Y0=0.0 -unit.1.4.1.HEIGHT1=0.97588426 -unit.1.4.1.WIDTH1=1.0 -unit.1.4.1.X1=0.0 -unit.1.4.1.Y1=0.0 -unit.1.4.5.HEIGHT5=1.0 -unit.1.4.5.WIDTH5=1.0 -unit.1.4.5.X5=0.0 -unit.1.4.5.Y5=0.0 -unit.1.4.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsA3=XXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.4.MFBitsB0=00000000000000000000000000000000 -unit.1.4.MFBitsB1=00000000000000000000000000000000 -unit.1.4.MFBitsB2=00000000000000000000000000000000 -unit.1.4.MFBitsB3=00000000000000000000000000000000 -unit.1.4.MFCompareA0=0 -unit.1.4.MFCompareA1=0 -unit.1.4.MFCompareA2=0 -unit.1.4.MFCompareA3=0 -unit.1.4.MFCompareB0=999 -unit.1.4.MFCompareB1=999 -unit.1.4.MFCompareB2=999 -unit.1.4.MFCompareB3=999 -unit.1.4.MFCount=4 -unit.1.4.MFDisplay0=0 -unit.1.4.MFDisplay1=0 -unit.1.4.MFDisplay2=0 -unit.1.4.MFDisplay3=0 -unit.1.4.MFEventType0=3 -unit.1.4.MFEventType1=3 -unit.1.4.MFEventType2=3 -unit.1.4.MFEventType3=3 -unit.1.4.RunMode=SINGLE RUN -unit.1.4.SQCondition=All Data -unit.1.4.SQContiguous0=0 -unit.1.4.SequencerOn=0 -unit.1.4.TCActive=0 -unit.1.4.TCAdvanced0=0 -unit.1.4.TCCondition0_0=M3 -unit.1.4.TCCondition0_1= -unit.1.4.TCConditionType0=0 -unit.1.4.TCCount=1 -unit.1.4.TCEventCount0=1 -unit.1.4.TCEventType0=3 -unit.1.4.TCName0=TriggerCondition0 -unit.1.4.TCOutputEnable0=0 -unit.1.4.TCOutputHigh0=1 -unit.1.4.TCOutputMode0=0 -unit.1.4.browser_tree_state=1 -unit.1.4.browser_tree_state=0 -unit.1.4.browser_tree_state=0 -unit.1.4.coretype=ILA -unit.1.4.eventCount0=1 -unit.1.4.eventCount1=1 -unit.1.4.eventCount2=1 -unit.1.4.eventCount3=1 -unit.1.4.plotBusColor0=-16777092 -unit.1.4.plotBusColor1=-16777092 -unit.1.4.plotBusColor2=-16777092 -unit.1.4.plotBusColor3=-16777092 -unit.1.4.plotBusColor4=-16777092 -unit.1.4.plotBusColor5=-16777092 -unit.1.4.plotBusColor6=-16777092 -unit.1.4.plotBusColor7=-16777092 -unit.1.4.plotBusCount=8 -unit.1.4.plotBusName0=cbar_master_i_9_dat -unit.1.4.plotBusName1=cbar_master_o_9_ack -unit.1.4.plotBusName2=cbar_master_o_9_adr -unit.1.4.plotBusName3=cbar_master_o_9_cyc -unit.1.4.plotBusName4=cbar_master_o_9_dat -unit.1.4.plotBusName5=cbar_master_o_9_sel -unit.1.4.plotBusName6=cbar_master_o_9_stb -unit.1.4.plotBusName7=cbar_master_o_9_we -unit.1.4.plotBusX=cbar_master_i_9_dat -unit.1.4.plotBusY=cbar_master_i_9_dat -unit.1.4.plotDataTimeMode=1 -unit.1.4.plotDisplayMode=line -unit.1.4.plotMaxX=0.0 -unit.1.4.plotMaxY=0.0 -unit.1.4.plotMinX=0.0 -unit.1.4.plotMinY=0.0 -unit.1.4.plotSelectedBus=0 -unit.1.4.port.-1.b.0.alias=cbar_master_i_9_dat -unit.1.4.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.0.name=DataPort -unit.1.4.port.-1.b.0.orderindex=-1 -unit.1.4.port.-1.b.0.radix=Hex -unit.1.4.port.-1.b.0.signedOffset=0.0 -unit.1.4.port.-1.b.0.signedPrecision=0 -unit.1.4.port.-1.b.0.signedScaleFactor=1.0 -unit.1.4.port.-1.b.0.tokencount=0 -unit.1.4.port.-1.b.0.unsignedOffset=0.0 -unit.1.4.port.-1.b.0.unsignedPrecision=0 -unit.1.4.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.0.visible=1 -unit.1.4.port.-1.b.1.alias=cbar_master_o_9_ack -unit.1.4.port.-1.b.1.channellist=103 -unit.1.4.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.1.name=DataPort -unit.1.4.port.-1.b.1.orderindex=-1 -unit.1.4.port.-1.b.1.radix=Hex -unit.1.4.port.-1.b.1.signedOffset=0.0 -unit.1.4.port.-1.b.1.signedPrecision=0 -unit.1.4.port.-1.b.1.signedScaleFactor=1.0 -unit.1.4.port.-1.b.1.tokencount=0 -unit.1.4.port.-1.b.1.unsignedOffset=0.0 -unit.1.4.port.-1.b.1.unsignedPrecision=0 -unit.1.4.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.1.visible=1 -unit.1.4.port.-1.b.2.alias=cbar_master_o_9_adr -unit.1.4.port.-1.b.2.channellist=64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 -unit.1.4.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.2.name=DataPort -unit.1.4.port.-1.b.2.orderindex=-1 -unit.1.4.port.-1.b.2.radix=Hex -unit.1.4.port.-1.b.2.signedOffset=0.0 -unit.1.4.port.-1.b.2.signedPrecision=0 -unit.1.4.port.-1.b.2.signedScaleFactor=1.0 -unit.1.4.port.-1.b.2.tokencount=0 -unit.1.4.port.-1.b.2.unsignedOffset=0.0 -unit.1.4.port.-1.b.2.unsignedPrecision=0 -unit.1.4.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.2.visible=1 -unit.1.4.port.-1.b.3.alias=cbar_master_o_9_cyc -unit.1.4.port.-1.b.3.channellist=96 -unit.1.4.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.3.name=DataPort -unit.1.4.port.-1.b.3.orderindex=-1 -unit.1.4.port.-1.b.3.radix=Hex -unit.1.4.port.-1.b.3.signedOffset=0.0 -unit.1.4.port.-1.b.3.signedPrecision=0 -unit.1.4.port.-1.b.3.signedScaleFactor=1.0 -unit.1.4.port.-1.b.3.tokencount=0 -unit.1.4.port.-1.b.3.unsignedOffset=0.0 -unit.1.4.port.-1.b.3.unsignedPrecision=0 -unit.1.4.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.3.visible=1 -unit.1.4.port.-1.b.4.alias=cbar_master_o_9_dat -unit.1.4.port.-1.b.4.channellist=32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.4.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.4.name=DataPort -unit.1.4.port.-1.b.4.orderindex=-1 -unit.1.4.port.-1.b.4.radix=Hex -unit.1.4.port.-1.b.4.signedOffset=0.0 -unit.1.4.port.-1.b.4.signedPrecision=0 -unit.1.4.port.-1.b.4.signedScaleFactor=1.0 -unit.1.4.port.-1.b.4.tokencount=0 -unit.1.4.port.-1.b.4.unsignedOffset=0.0 -unit.1.4.port.-1.b.4.unsignedPrecision=0 -unit.1.4.port.-1.b.4.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.4.visible=1 -unit.1.4.port.-1.b.5.alias=cbar_master_o_9_sel -unit.1.4.port.-1.b.5.channellist=97 98 99 100 -unit.1.4.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.5.name=DataPort -unit.1.4.port.-1.b.5.orderindex=-1 -unit.1.4.port.-1.b.5.radix=Hex -unit.1.4.port.-1.b.5.signedOffset=0.0 -unit.1.4.port.-1.b.5.signedPrecision=0 -unit.1.4.port.-1.b.5.signedScaleFactor=1.0 -unit.1.4.port.-1.b.5.tokencount=0 -unit.1.4.port.-1.b.5.unsignedOffset=0.0 -unit.1.4.port.-1.b.5.unsignedPrecision=0 -unit.1.4.port.-1.b.5.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.5.visible=1 -unit.1.4.port.-1.b.6.alias=cbar_master_o_9_stb -unit.1.4.port.-1.b.6.channellist=101 -unit.1.4.port.-1.b.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.6.name=DataPort -unit.1.4.port.-1.b.6.orderindex=-1 -unit.1.4.port.-1.b.6.radix=Hex -unit.1.4.port.-1.b.6.signedOffset=0.0 -unit.1.4.port.-1.b.6.signedPrecision=0 -unit.1.4.port.-1.b.6.signedScaleFactor=1.0 -unit.1.4.port.-1.b.6.tokencount=0 -unit.1.4.port.-1.b.6.unsignedOffset=0.0 -unit.1.4.port.-1.b.6.unsignedPrecision=0 -unit.1.4.port.-1.b.6.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.6.visible=1 -unit.1.4.port.-1.b.7.alias=cbar_master_o_9_we -unit.1.4.port.-1.b.7.channellist=102 -unit.1.4.port.-1.b.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.b.7.name=DataPort -unit.1.4.port.-1.b.7.orderindex=-1 -unit.1.4.port.-1.b.7.radix=Hex -unit.1.4.port.-1.b.7.signedOffset=0.0 -unit.1.4.port.-1.b.7.signedPrecision=0 -unit.1.4.port.-1.b.7.signedScaleFactor=1.0 -unit.1.4.port.-1.b.7.tokencount=0 -unit.1.4.port.-1.b.7.unsignedOffset=0.0 -unit.1.4.port.-1.b.7.unsignedPrecision=0 -unit.1.4.port.-1.b.7.unsignedScaleFactor=1.0 -unit.1.4.port.-1.b.7.visible=1 -unit.1.4.port.-1.buscount=8 -unit.1.4.port.-1.channelcount=128 -unit.1.4.port.-1.s.0.alias= -unit.1.4.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.0.name=DataPort[0] -unit.1.4.port.-1.s.0.orderindex=-1 -unit.1.4.port.-1.s.0.visible=0 -unit.1.4.port.-1.s.1.alias= -unit.1.4.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.1.name=DataPort[1] -unit.1.4.port.-1.s.1.orderindex=-1 -unit.1.4.port.-1.s.1.visible=0 -unit.1.4.port.-1.s.10.alias= -unit.1.4.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.10.name=DataPort[10] -unit.1.4.port.-1.s.10.orderindex=-1 -unit.1.4.port.-1.s.10.visible=0 -unit.1.4.port.-1.s.100.alias= -unit.1.4.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.100.name=DataPort[100] -unit.1.4.port.-1.s.100.orderindex=-1 -unit.1.4.port.-1.s.100.visible=0 -unit.1.4.port.-1.s.101.alias= -unit.1.4.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.101.name=DataPort[101] -unit.1.4.port.-1.s.101.orderindex=-1 -unit.1.4.port.-1.s.101.visible=0 -unit.1.4.port.-1.s.102.alias= -unit.1.4.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.102.name=DataPort[102] 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-unit.1.4.port.-1.s.96.orderindex=-1 -unit.1.4.port.-1.s.96.visible=0 -unit.1.4.port.-1.s.97.alias= -unit.1.4.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.97.name=DataPort[97] -unit.1.4.port.-1.s.97.orderindex=-1 -unit.1.4.port.-1.s.97.visible=0 -unit.1.4.port.-1.s.98.alias= -unit.1.4.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.98.name=DataPort[98] -unit.1.4.port.-1.s.98.orderindex=-1 -unit.1.4.port.-1.s.98.visible=0 -unit.1.4.port.-1.s.99.alias= -unit.1.4.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.-1.s.99.name=DataPort[99] -unit.1.4.port.-1.s.99.orderindex=-1 -unit.1.4.port.-1.s.99.visible=0 -unit.1.4.port.0.b.0.alias= -unit.1.4.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.b.0.name=TriggerPort0 -unit.1.4.port.0.b.0.orderindex=-1 -unit.1.4.port.0.b.0.radix=Hex -unit.1.4.port.0.b.0.signedOffset=0.0 -unit.1.4.port.0.b.0.signedPrecision=0 -unit.1.4.port.0.b.0.signedScaleFactor=1.0 -unit.1.4.port.0.b.0.unsignedOffset=0.0 -unit.1.4.port.0.b.0.unsignedPrecision=0 -unit.1.4.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.0.b.0.visible=1 -unit.1.4.port.0.buscount=1 -unit.1.4.port.0.channelcount=32 -unit.1.4.port.0.s.0.alias= -unit.1.4.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.0.name=TriggerPort0[0] -unit.1.4.port.0.s.0.orderindex=-1 -unit.1.4.port.0.s.0.visible=1 -unit.1.4.port.0.s.1.alias= -unit.1.4.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.1.name=TriggerPort0[1] -unit.1.4.port.0.s.1.orderindex=-1 -unit.1.4.port.0.s.1.visible=1 -unit.1.4.port.0.s.10.alias= -unit.1.4.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.10.name=TriggerPort0[10] -unit.1.4.port.0.s.10.orderindex=-1 -unit.1.4.port.0.s.10.visible=1 -unit.1.4.port.0.s.11.alias= -unit.1.4.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.11.name=TriggerPort0[11] -unit.1.4.port.0.s.11.orderindex=-1 -unit.1.4.port.0.s.11.visible=1 -unit.1.4.port.0.s.12.alias= -unit.1.4.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.12.name=TriggerPort0[12] -unit.1.4.port.0.s.12.orderindex=-1 -unit.1.4.port.0.s.12.visible=1 -unit.1.4.port.0.s.13.alias= -unit.1.4.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.13.name=TriggerPort0[13] -unit.1.4.port.0.s.13.orderindex=-1 -unit.1.4.port.0.s.13.visible=1 -unit.1.4.port.0.s.14.alias= -unit.1.4.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.14.name=TriggerPort0[14] -unit.1.4.port.0.s.14.orderindex=-1 -unit.1.4.port.0.s.14.visible=1 -unit.1.4.port.0.s.15.alias= -unit.1.4.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.15.name=TriggerPort0[15] -unit.1.4.port.0.s.15.orderindex=-1 -unit.1.4.port.0.s.15.visible=1 -unit.1.4.port.0.s.16.alias= -unit.1.4.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.16.name=TriggerPort0[16] -unit.1.4.port.0.s.16.orderindex=-1 -unit.1.4.port.0.s.16.visible=1 -unit.1.4.port.0.s.17.alias= -unit.1.4.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.17.name=TriggerPort0[17] -unit.1.4.port.0.s.17.orderindex=-1 -unit.1.4.port.0.s.17.visible=1 -unit.1.4.port.0.s.18.alias= -unit.1.4.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.18.name=TriggerPort0[18] -unit.1.4.port.0.s.18.orderindex=-1 -unit.1.4.port.0.s.18.visible=1 -unit.1.4.port.0.s.19.alias= -unit.1.4.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.19.name=TriggerPort0[19] -unit.1.4.port.0.s.19.orderindex=-1 -unit.1.4.port.0.s.19.visible=1 -unit.1.4.port.0.s.2.alias= -unit.1.4.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.2.name=TriggerPort0[2] -unit.1.4.port.0.s.2.orderindex=-1 -unit.1.4.port.0.s.2.visible=1 -unit.1.4.port.0.s.20.alias= -unit.1.4.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.20.name=TriggerPort0[20] -unit.1.4.port.0.s.20.orderindex=-1 -unit.1.4.port.0.s.20.visible=1 -unit.1.4.port.0.s.21.alias= -unit.1.4.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.21.name=TriggerPort0[21] -unit.1.4.port.0.s.21.orderindex=-1 -unit.1.4.port.0.s.21.visible=1 -unit.1.4.port.0.s.22.alias= -unit.1.4.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.22.name=TriggerPort0[22] -unit.1.4.port.0.s.22.orderindex=-1 -unit.1.4.port.0.s.22.visible=1 -unit.1.4.port.0.s.23.alias= -unit.1.4.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.23.name=TriggerPort0[23] -unit.1.4.port.0.s.23.orderindex=-1 -unit.1.4.port.0.s.23.visible=1 -unit.1.4.port.0.s.24.alias= -unit.1.4.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.24.name=TriggerPort0[24] -unit.1.4.port.0.s.24.orderindex=-1 -unit.1.4.port.0.s.24.visible=1 -unit.1.4.port.0.s.25.alias= -unit.1.4.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.25.name=TriggerPort0[25] -unit.1.4.port.0.s.25.orderindex=-1 -unit.1.4.port.0.s.25.visible=1 -unit.1.4.port.0.s.26.alias= -unit.1.4.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.26.name=TriggerPort0[26] -unit.1.4.port.0.s.26.orderindex=-1 -unit.1.4.port.0.s.26.visible=1 -unit.1.4.port.0.s.27.alias= -unit.1.4.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.27.name=TriggerPort0[27] -unit.1.4.port.0.s.27.orderindex=-1 -unit.1.4.port.0.s.27.visible=1 -unit.1.4.port.0.s.28.alias= -unit.1.4.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.28.name=TriggerPort0[28] -unit.1.4.port.0.s.28.orderindex=-1 -unit.1.4.port.0.s.28.visible=1 -unit.1.4.port.0.s.29.alias= -unit.1.4.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.29.name=TriggerPort0[29] -unit.1.4.port.0.s.29.orderindex=-1 -unit.1.4.port.0.s.29.visible=1 -unit.1.4.port.0.s.3.alias= -unit.1.4.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.3.name=TriggerPort0[3] -unit.1.4.port.0.s.3.orderindex=-1 -unit.1.4.port.0.s.3.visible=1 -unit.1.4.port.0.s.30.alias= -unit.1.4.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.30.name=TriggerPort0[30] -unit.1.4.port.0.s.30.orderindex=-1 -unit.1.4.port.0.s.30.visible=1 -unit.1.4.port.0.s.31.alias= -unit.1.4.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.31.name=TriggerPort0[31] -unit.1.4.port.0.s.31.orderindex=-1 -unit.1.4.port.0.s.31.visible=1 -unit.1.4.port.0.s.4.alias= -unit.1.4.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.4.name=TriggerPort0[4] -unit.1.4.port.0.s.4.orderindex=-1 -unit.1.4.port.0.s.4.visible=1 -unit.1.4.port.0.s.5.alias= -unit.1.4.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.5.name=TriggerPort0[5] -unit.1.4.port.0.s.5.orderindex=-1 -unit.1.4.port.0.s.5.visible=1 -unit.1.4.port.0.s.6.alias= -unit.1.4.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.6.name=TriggerPort0[6] -unit.1.4.port.0.s.6.orderindex=-1 -unit.1.4.port.0.s.6.visible=1 -unit.1.4.port.0.s.7.alias= -unit.1.4.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.7.name=TriggerPort0[7] -unit.1.4.port.0.s.7.orderindex=-1 -unit.1.4.port.0.s.7.visible=1 -unit.1.4.port.0.s.8.alias= -unit.1.4.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.8.name=TriggerPort0[8] -unit.1.4.port.0.s.8.orderindex=-1 -unit.1.4.port.0.s.8.visible=1 -unit.1.4.port.0.s.9.alias= -unit.1.4.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.0.s.9.name=TriggerPort0[9] -unit.1.4.port.0.s.9.orderindex=-1 -unit.1.4.port.0.s.9.visible=1 -unit.1.4.port.1.b.0.alias= -unit.1.4.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.b.0.name=TriggerPort1 -unit.1.4.port.1.b.0.orderindex=-1 -unit.1.4.port.1.b.0.radix=Hex -unit.1.4.port.1.b.0.signedOffset=0.0 -unit.1.4.port.1.b.0.signedPrecision=0 -unit.1.4.port.1.b.0.signedScaleFactor=1.0 -unit.1.4.port.1.b.0.unsignedOffset=0.0 -unit.1.4.port.1.b.0.unsignedPrecision=0 -unit.1.4.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.1.b.0.visible=1 -unit.1.4.port.1.buscount=1 -unit.1.4.port.1.channelcount=32 -unit.1.4.port.1.s.0.alias= -unit.1.4.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.0.name=TriggerPort1[0] -unit.1.4.port.1.s.0.orderindex=-1 -unit.1.4.port.1.s.0.visible=1 -unit.1.4.port.1.s.1.alias= -unit.1.4.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.1.name=TriggerPort1[1] -unit.1.4.port.1.s.1.orderindex=-1 -unit.1.4.port.1.s.1.visible=1 -unit.1.4.port.1.s.10.alias= -unit.1.4.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.10.name=TriggerPort1[10] -unit.1.4.port.1.s.10.orderindex=-1 -unit.1.4.port.1.s.10.visible=1 -unit.1.4.port.1.s.11.alias= -unit.1.4.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.11.name=TriggerPort1[11] -unit.1.4.port.1.s.11.orderindex=-1 -unit.1.4.port.1.s.11.visible=1 -unit.1.4.port.1.s.12.alias= -unit.1.4.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.12.name=TriggerPort1[12] -unit.1.4.port.1.s.12.orderindex=-1 -unit.1.4.port.1.s.12.visible=1 -unit.1.4.port.1.s.13.alias= -unit.1.4.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.13.name=TriggerPort1[13] -unit.1.4.port.1.s.13.orderindex=-1 -unit.1.4.port.1.s.13.visible=1 -unit.1.4.port.1.s.14.alias= -unit.1.4.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.14.name=TriggerPort1[14] -unit.1.4.port.1.s.14.orderindex=-1 -unit.1.4.port.1.s.14.visible=1 -unit.1.4.port.1.s.15.alias= -unit.1.4.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.15.name=TriggerPort1[15] -unit.1.4.port.1.s.15.orderindex=-1 -unit.1.4.port.1.s.15.visible=1 -unit.1.4.port.1.s.16.alias= -unit.1.4.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.16.name=TriggerPort1[16] -unit.1.4.port.1.s.16.orderindex=-1 -unit.1.4.port.1.s.16.visible=1 -unit.1.4.port.1.s.17.alias= -unit.1.4.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.17.name=TriggerPort1[17] -unit.1.4.port.1.s.17.orderindex=-1 -unit.1.4.port.1.s.17.visible=1 -unit.1.4.port.1.s.18.alias= -unit.1.4.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.18.name=TriggerPort1[18] -unit.1.4.port.1.s.18.orderindex=-1 -unit.1.4.port.1.s.18.visible=1 -unit.1.4.port.1.s.19.alias= -unit.1.4.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.19.name=TriggerPort1[19] -unit.1.4.port.1.s.19.orderindex=-1 -unit.1.4.port.1.s.19.visible=1 -unit.1.4.port.1.s.2.alias= -unit.1.4.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.2.name=TriggerPort1[2] -unit.1.4.port.1.s.2.orderindex=-1 -unit.1.4.port.1.s.2.visible=1 -unit.1.4.port.1.s.20.alias= -unit.1.4.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.20.name=TriggerPort1[20] -unit.1.4.port.1.s.20.orderindex=-1 -unit.1.4.port.1.s.20.visible=1 -unit.1.4.port.1.s.21.alias= -unit.1.4.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.21.name=TriggerPort1[21] -unit.1.4.port.1.s.21.orderindex=-1 -unit.1.4.port.1.s.21.visible=1 -unit.1.4.port.1.s.22.alias= -unit.1.4.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.22.name=TriggerPort1[22] -unit.1.4.port.1.s.22.orderindex=-1 -unit.1.4.port.1.s.22.visible=1 -unit.1.4.port.1.s.23.alias= -unit.1.4.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.23.name=TriggerPort1[23] -unit.1.4.port.1.s.23.orderindex=-1 -unit.1.4.port.1.s.23.visible=1 -unit.1.4.port.1.s.24.alias= -unit.1.4.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.24.name=TriggerPort1[24] -unit.1.4.port.1.s.24.orderindex=-1 -unit.1.4.port.1.s.24.visible=1 -unit.1.4.port.1.s.25.alias= -unit.1.4.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.25.name=TriggerPort1[25] -unit.1.4.port.1.s.25.orderindex=-1 -unit.1.4.port.1.s.25.visible=1 -unit.1.4.port.1.s.26.alias= -unit.1.4.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.26.name=TriggerPort1[26] -unit.1.4.port.1.s.26.orderindex=-1 -unit.1.4.port.1.s.26.visible=1 -unit.1.4.port.1.s.27.alias= -unit.1.4.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.27.name=TriggerPort1[27] -unit.1.4.port.1.s.27.orderindex=-1 -unit.1.4.port.1.s.27.visible=1 -unit.1.4.port.1.s.28.alias= -unit.1.4.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.28.name=TriggerPort1[28] -unit.1.4.port.1.s.28.orderindex=-1 -unit.1.4.port.1.s.28.visible=1 -unit.1.4.port.1.s.29.alias= -unit.1.4.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.29.name=TriggerPort1[29] -unit.1.4.port.1.s.29.orderindex=-1 -unit.1.4.port.1.s.29.visible=1 -unit.1.4.port.1.s.3.alias= -unit.1.4.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.3.name=TriggerPort1[3] -unit.1.4.port.1.s.3.orderindex=-1 -unit.1.4.port.1.s.3.visible=1 -unit.1.4.port.1.s.30.alias= -unit.1.4.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.30.name=TriggerPort1[30] -unit.1.4.port.1.s.30.orderindex=-1 -unit.1.4.port.1.s.30.visible=1 -unit.1.4.port.1.s.31.alias= -unit.1.4.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.31.name=TriggerPort1[31] -unit.1.4.port.1.s.31.orderindex=-1 -unit.1.4.port.1.s.31.visible=1 -unit.1.4.port.1.s.4.alias= -unit.1.4.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.4.name=TriggerPort1[4] -unit.1.4.port.1.s.4.orderindex=-1 -unit.1.4.port.1.s.4.visible=1 -unit.1.4.port.1.s.5.alias= -unit.1.4.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.5.name=TriggerPort1[5] -unit.1.4.port.1.s.5.orderindex=-1 -unit.1.4.port.1.s.5.visible=1 -unit.1.4.port.1.s.6.alias= -unit.1.4.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.6.name=TriggerPort1[6] -unit.1.4.port.1.s.6.orderindex=-1 -unit.1.4.port.1.s.6.visible=1 -unit.1.4.port.1.s.7.alias= -unit.1.4.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.7.name=TriggerPort1[7] -unit.1.4.port.1.s.7.orderindex=-1 -unit.1.4.port.1.s.7.visible=1 -unit.1.4.port.1.s.8.alias= -unit.1.4.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.8.name=TriggerPort1[8] -unit.1.4.port.1.s.8.orderindex=-1 -unit.1.4.port.1.s.8.visible=1 -unit.1.4.port.1.s.9.alias= -unit.1.4.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.1.s.9.name=TriggerPort1[9] -unit.1.4.port.1.s.9.orderindex=-1 -unit.1.4.port.1.s.9.visible=1 -unit.1.4.port.2.b.0.alias= -unit.1.4.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.b.0.name=TriggerPort2 -unit.1.4.port.2.b.0.orderindex=-1 -unit.1.4.port.2.b.0.radix=Hex -unit.1.4.port.2.b.0.signedOffset=0.0 -unit.1.4.port.2.b.0.signedPrecision=0 -unit.1.4.port.2.b.0.signedScaleFactor=1.0 -unit.1.4.port.2.b.0.unsignedOffset=0.0 -unit.1.4.port.2.b.0.unsignedPrecision=0 -unit.1.4.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.2.b.0.visible=1 -unit.1.4.port.2.buscount=1 -unit.1.4.port.2.channelcount=32 -unit.1.4.port.2.s.0.alias= -unit.1.4.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.0.name=TriggerPort2[0] -unit.1.4.port.2.s.0.orderindex=-1 -unit.1.4.port.2.s.0.visible=1 -unit.1.4.port.2.s.1.alias= -unit.1.4.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.1.name=TriggerPort2[1] -unit.1.4.port.2.s.1.orderindex=-1 -unit.1.4.port.2.s.1.visible=1 -unit.1.4.port.2.s.10.alias= -unit.1.4.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.10.name=TriggerPort2[10] -unit.1.4.port.2.s.10.orderindex=-1 -unit.1.4.port.2.s.10.visible=1 -unit.1.4.port.2.s.11.alias= -unit.1.4.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.11.name=TriggerPort2[11] -unit.1.4.port.2.s.11.orderindex=-1 -unit.1.4.port.2.s.11.visible=1 -unit.1.4.port.2.s.12.alias= -unit.1.4.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.12.name=TriggerPort2[12] -unit.1.4.port.2.s.12.orderindex=-1 -unit.1.4.port.2.s.12.visible=1 -unit.1.4.port.2.s.13.alias= -unit.1.4.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.13.name=TriggerPort2[13] -unit.1.4.port.2.s.13.orderindex=-1 -unit.1.4.port.2.s.13.visible=1 -unit.1.4.port.2.s.14.alias= -unit.1.4.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.14.name=TriggerPort2[14] -unit.1.4.port.2.s.14.orderindex=-1 -unit.1.4.port.2.s.14.visible=1 -unit.1.4.port.2.s.15.alias= -unit.1.4.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.15.name=TriggerPort2[15] -unit.1.4.port.2.s.15.orderindex=-1 -unit.1.4.port.2.s.15.visible=1 -unit.1.4.port.2.s.16.alias= -unit.1.4.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.16.name=TriggerPort2[16] -unit.1.4.port.2.s.16.orderindex=-1 -unit.1.4.port.2.s.16.visible=1 -unit.1.4.port.2.s.17.alias= -unit.1.4.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.17.name=TriggerPort2[17] -unit.1.4.port.2.s.17.orderindex=-1 -unit.1.4.port.2.s.17.visible=1 -unit.1.4.port.2.s.18.alias= -unit.1.4.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.18.name=TriggerPort2[18] -unit.1.4.port.2.s.18.orderindex=-1 -unit.1.4.port.2.s.18.visible=1 -unit.1.4.port.2.s.19.alias= -unit.1.4.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.19.name=TriggerPort2[19] -unit.1.4.port.2.s.19.orderindex=-1 -unit.1.4.port.2.s.19.visible=1 -unit.1.4.port.2.s.2.alias= -unit.1.4.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.2.name=TriggerPort2[2] -unit.1.4.port.2.s.2.orderindex=-1 -unit.1.4.port.2.s.2.visible=1 -unit.1.4.port.2.s.20.alias= -unit.1.4.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.20.name=TriggerPort2[20] -unit.1.4.port.2.s.20.orderindex=-1 -unit.1.4.port.2.s.20.visible=1 -unit.1.4.port.2.s.21.alias= -unit.1.4.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.21.name=TriggerPort2[21] -unit.1.4.port.2.s.21.orderindex=-1 -unit.1.4.port.2.s.21.visible=1 -unit.1.4.port.2.s.22.alias= -unit.1.4.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.22.name=TriggerPort2[22] -unit.1.4.port.2.s.22.orderindex=-1 -unit.1.4.port.2.s.22.visible=1 -unit.1.4.port.2.s.23.alias= -unit.1.4.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.23.name=TriggerPort2[23] -unit.1.4.port.2.s.23.orderindex=-1 -unit.1.4.port.2.s.23.visible=1 -unit.1.4.port.2.s.24.alias= -unit.1.4.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.24.name=TriggerPort2[24] -unit.1.4.port.2.s.24.orderindex=-1 -unit.1.4.port.2.s.24.visible=1 -unit.1.4.port.2.s.25.alias= -unit.1.4.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.25.name=TriggerPort2[25] -unit.1.4.port.2.s.25.orderindex=-1 -unit.1.4.port.2.s.25.visible=1 -unit.1.4.port.2.s.26.alias= -unit.1.4.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.26.name=TriggerPort2[26] -unit.1.4.port.2.s.26.orderindex=-1 -unit.1.4.port.2.s.26.visible=1 -unit.1.4.port.2.s.27.alias= -unit.1.4.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.27.name=TriggerPort2[27] -unit.1.4.port.2.s.27.orderindex=-1 -unit.1.4.port.2.s.27.visible=1 -unit.1.4.port.2.s.28.alias= -unit.1.4.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.28.name=TriggerPort2[28] -unit.1.4.port.2.s.28.orderindex=-1 -unit.1.4.port.2.s.28.visible=1 -unit.1.4.port.2.s.29.alias= -unit.1.4.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.29.name=TriggerPort2[29] -unit.1.4.port.2.s.29.orderindex=-1 -unit.1.4.port.2.s.29.visible=1 -unit.1.4.port.2.s.3.alias= -unit.1.4.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.3.name=TriggerPort2[3] -unit.1.4.port.2.s.3.orderindex=-1 -unit.1.4.port.2.s.3.visible=1 -unit.1.4.port.2.s.30.alias= -unit.1.4.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.30.name=TriggerPort2[30] -unit.1.4.port.2.s.30.orderindex=-1 -unit.1.4.port.2.s.30.visible=1 -unit.1.4.port.2.s.31.alias= -unit.1.4.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.31.name=TriggerPort2[31] -unit.1.4.port.2.s.31.orderindex=-1 -unit.1.4.port.2.s.31.visible=1 -unit.1.4.port.2.s.4.alias= -unit.1.4.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.4.name=TriggerPort2[4] -unit.1.4.port.2.s.4.orderindex=-1 -unit.1.4.port.2.s.4.visible=1 -unit.1.4.port.2.s.5.alias= -unit.1.4.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.5.name=TriggerPort2[5] -unit.1.4.port.2.s.5.orderindex=-1 -unit.1.4.port.2.s.5.visible=1 -unit.1.4.port.2.s.6.alias= -unit.1.4.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.6.name=TriggerPort2[6] -unit.1.4.port.2.s.6.orderindex=-1 -unit.1.4.port.2.s.6.visible=1 -unit.1.4.port.2.s.7.alias= -unit.1.4.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.7.name=TriggerPort2[7] -unit.1.4.port.2.s.7.orderindex=-1 -unit.1.4.port.2.s.7.visible=1 -unit.1.4.port.2.s.8.alias= -unit.1.4.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.8.name=TriggerPort2[8] -unit.1.4.port.2.s.8.orderindex=-1 -unit.1.4.port.2.s.8.visible=1 -unit.1.4.port.2.s.9.alias= -unit.1.4.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.2.s.9.name=TriggerPort2[9] -unit.1.4.port.2.s.9.orderindex=-1 -unit.1.4.port.2.s.9.visible=1 -unit.1.4.port.3.b.0.alias= -unit.1.4.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.4.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.b.0.name=TriggerPort3 -unit.1.4.port.3.b.0.orderindex=-1 -unit.1.4.port.3.b.0.radix=Hex -unit.1.4.port.3.b.0.signedOffset=0.0 -unit.1.4.port.3.b.0.signedPrecision=0 -unit.1.4.port.3.b.0.signedScaleFactor=1.0 -unit.1.4.port.3.b.0.unsignedOffset=0.0 -unit.1.4.port.3.b.0.unsignedPrecision=0 -unit.1.4.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.4.port.3.b.0.visible=1 -unit.1.4.port.3.buscount=1 -unit.1.4.port.3.channelcount=32 -unit.1.4.port.3.s.0.alias= -unit.1.4.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.0.name=TriggerPort3[0] -unit.1.4.port.3.s.0.orderindex=-1 -unit.1.4.port.3.s.0.visible=1 -unit.1.4.port.3.s.1.alias= -unit.1.4.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.1.name=TriggerPort3[1] -unit.1.4.port.3.s.1.orderindex=-1 -unit.1.4.port.3.s.1.visible=1 -unit.1.4.port.3.s.10.alias= -unit.1.4.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.10.name=TriggerPort3[10] -unit.1.4.port.3.s.10.orderindex=-1 -unit.1.4.port.3.s.10.visible=1 -unit.1.4.port.3.s.11.alias= -unit.1.4.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.11.name=TriggerPort3[11] -unit.1.4.port.3.s.11.orderindex=-1 -unit.1.4.port.3.s.11.visible=1 -unit.1.4.port.3.s.12.alias= -unit.1.4.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.12.name=TriggerPort3[12] -unit.1.4.port.3.s.12.orderindex=-1 -unit.1.4.port.3.s.12.visible=1 -unit.1.4.port.3.s.13.alias= -unit.1.4.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.13.name=TriggerPort3[13] -unit.1.4.port.3.s.13.orderindex=-1 -unit.1.4.port.3.s.13.visible=1 -unit.1.4.port.3.s.14.alias= -unit.1.4.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.14.name=TriggerPort3[14] -unit.1.4.port.3.s.14.orderindex=-1 -unit.1.4.port.3.s.14.visible=1 -unit.1.4.port.3.s.15.alias= -unit.1.4.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.15.name=TriggerPort3[15] -unit.1.4.port.3.s.15.orderindex=-1 -unit.1.4.port.3.s.15.visible=1 -unit.1.4.port.3.s.16.alias= -unit.1.4.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.16.name=TriggerPort3[16] -unit.1.4.port.3.s.16.orderindex=-1 -unit.1.4.port.3.s.16.visible=1 -unit.1.4.port.3.s.17.alias= -unit.1.4.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.17.name=TriggerPort3[17] -unit.1.4.port.3.s.17.orderindex=-1 -unit.1.4.port.3.s.17.visible=1 -unit.1.4.port.3.s.18.alias= -unit.1.4.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.18.name=TriggerPort3[18] -unit.1.4.port.3.s.18.orderindex=-1 -unit.1.4.port.3.s.18.visible=1 -unit.1.4.port.3.s.19.alias= -unit.1.4.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.19.name=TriggerPort3[19] -unit.1.4.port.3.s.19.orderindex=-1 -unit.1.4.port.3.s.19.visible=1 -unit.1.4.port.3.s.2.alias= -unit.1.4.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.2.name=TriggerPort3[2] -unit.1.4.port.3.s.2.orderindex=-1 -unit.1.4.port.3.s.2.visible=1 -unit.1.4.port.3.s.20.alias= -unit.1.4.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.4.port.3.s.20.name=TriggerPort3[20] -unit.1.4.port.3.s.20.orderindex=-1 -unit.1.4.port.3.s.20.visible=1 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-unit.1.4.waveform.posn.37.channel=127 -unit.1.4.waveform.posn.37.name=DataPort[127] -unit.1.4.waveform.posn.37.type=signal -unit.1.4.waveform.posn.38.channel=127 -unit.1.4.waveform.posn.38.name=DataPort[127] -unit.1.4.waveform.posn.38.type=signal -unit.1.4.waveform.posn.39.channel=127 -unit.1.4.waveform.posn.39.name=DataPort[127] -unit.1.4.waveform.posn.39.type=signal -unit.1.4.waveform.posn.4.channel=2147483646 -unit.1.4.waveform.posn.4.name=cbar_master_o_9_cyc -unit.1.4.waveform.posn.4.radix=1 -unit.1.4.waveform.posn.4.type=bus -unit.1.4.waveform.posn.40.channel=127 -unit.1.4.waveform.posn.40.name=DataPort[127] -unit.1.4.waveform.posn.40.type=signal -unit.1.4.waveform.posn.41.channel=127 -unit.1.4.waveform.posn.41.name=DataPort[127] -unit.1.4.waveform.posn.41.type=signal -unit.1.4.waveform.posn.42.channel=127 -unit.1.4.waveform.posn.42.name=DataPort[127] -unit.1.4.waveform.posn.42.type=signal -unit.1.4.waveform.posn.43.channel=127 -unit.1.4.waveform.posn.43.name=DataPort[127] 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-unit.1.4.waveform.posn.50.name=DataPort[127] -unit.1.4.waveform.posn.50.type=signal -unit.1.4.waveform.posn.51.channel=127 -unit.1.4.waveform.posn.51.name=DataPort[127] -unit.1.4.waveform.posn.51.type=signal -unit.1.4.waveform.posn.52.channel=127 -unit.1.4.waveform.posn.52.name=DataPort[127] -unit.1.4.waveform.posn.52.type=signal -unit.1.4.waveform.posn.53.channel=127 -unit.1.4.waveform.posn.53.name=DataPort[127] -unit.1.4.waveform.posn.53.type=signal -unit.1.4.waveform.posn.54.channel=127 -unit.1.4.waveform.posn.54.name=DataPort[127] -unit.1.4.waveform.posn.54.type=signal -unit.1.4.waveform.posn.55.channel=127 -unit.1.4.waveform.posn.55.name=DataPort[127] -unit.1.4.waveform.posn.55.type=signal -unit.1.4.waveform.posn.56.channel=127 -unit.1.4.waveform.posn.56.name=DataPort[127] -unit.1.4.waveform.posn.56.type=signal -unit.1.4.waveform.posn.57.channel=127 -unit.1.4.waveform.posn.57.name=DataPort[127] -unit.1.4.waveform.posn.57.type=signal -unit.1.4.waveform.posn.58.channel=127 -unit.1.4.waveform.posn.58.name=DataPort[127] -unit.1.4.waveform.posn.58.type=signal -unit.1.4.waveform.posn.59.channel=127 -unit.1.4.waveform.posn.59.name=DataPort[127] -unit.1.4.waveform.posn.59.type=signal -unit.1.4.waveform.posn.6.channel=2147483646 -unit.1.4.waveform.posn.6.name=cbar_master_o_9_we -unit.1.4.waveform.posn.6.radix=1 -unit.1.4.waveform.posn.6.type=bus -unit.1.4.waveform.posn.60.channel=127 -unit.1.4.waveform.posn.60.name=DataPort[127] -unit.1.4.waveform.posn.60.type=signal -unit.1.4.waveform.posn.61.channel=127 -unit.1.4.waveform.posn.61.name=DataPort[127] -unit.1.4.waveform.posn.61.type=signal -unit.1.4.waveform.posn.62.channel=127 -unit.1.4.waveform.posn.62.name=DataPort[127] -unit.1.4.waveform.posn.62.type=signal -unit.1.4.waveform.posn.63.channel=127 -unit.1.4.waveform.posn.63.name=DataPort[127] -unit.1.4.waveform.posn.63.type=signal -unit.1.4.waveform.posn.64.channel=127 -unit.1.4.waveform.posn.64.name=DataPort[127] -unit.1.4.waveform.posn.64.type=signal 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-unit.1.4.waveform.posn.71.type=signal -unit.1.4.waveform.posn.72.channel=127 -unit.1.4.waveform.posn.72.name=DataPort[127] -unit.1.4.waveform.posn.72.type=signal -unit.1.4.waveform.posn.73.channel=127 -unit.1.4.waveform.posn.73.name=DataPort[127] -unit.1.4.waveform.posn.73.type=signal -unit.1.4.waveform.posn.74.channel=127 -unit.1.4.waveform.posn.74.name=DataPort[127] -unit.1.4.waveform.posn.74.type=signal -unit.1.4.waveform.posn.75.channel=127 -unit.1.4.waveform.posn.75.name=DataPort[127] -unit.1.4.waveform.posn.75.type=signal -unit.1.4.waveform.posn.76.channel=127 -unit.1.4.waveform.posn.76.name=DataPort[127] -unit.1.4.waveform.posn.76.type=signal -unit.1.4.waveform.posn.77.channel=127 -unit.1.4.waveform.posn.77.name=DataPort[127] -unit.1.4.waveform.posn.77.type=signal -unit.1.4.waveform.posn.78.channel=127 -unit.1.4.waveform.posn.78.name=DataPort[127] -unit.1.4.waveform.posn.78.type=signal -unit.1.4.waveform.posn.79.channel=127 -unit.1.4.waveform.posn.79.name=DataPort[127] -unit.1.4.waveform.posn.79.type=signal -unit.1.4.waveform.posn.8.channel=104 -unit.1.4.waveform.posn.8.name=DataPort[104] -unit.1.4.waveform.posn.8.type=signal -unit.1.4.waveform.posn.80.channel=127 -unit.1.4.waveform.posn.80.name=DataPort[127] -unit.1.4.waveform.posn.80.type=signal -unit.1.4.waveform.posn.81.channel=127 -unit.1.4.waveform.posn.81.name=DataPort[127] -unit.1.4.waveform.posn.81.type=signal -unit.1.4.waveform.posn.82.channel=127 -unit.1.4.waveform.posn.82.name=DataPort[127] -unit.1.4.waveform.posn.82.type=signal -unit.1.4.waveform.posn.83.channel=127 -unit.1.4.waveform.posn.83.name=DataPort[127] -unit.1.4.waveform.posn.83.type=signal -unit.1.4.waveform.posn.84.channel=127 -unit.1.4.waveform.posn.84.name=DataPort[127] -unit.1.4.waveform.posn.84.type=signal -unit.1.4.waveform.posn.85.channel=127 -unit.1.4.waveform.posn.85.name=DataPort[127] -unit.1.4.waveform.posn.85.type=signal -unit.1.4.waveform.posn.86.channel=127 -unit.1.4.waveform.posn.86.name=DataPort[127] -unit.1.4.waveform.posn.86.type=signal -unit.1.4.waveform.posn.87.channel=127 -unit.1.4.waveform.posn.87.name=DataPort[127] -unit.1.4.waveform.posn.87.type=signal -unit.1.4.waveform.posn.88.channel=127 -unit.1.4.waveform.posn.88.name=DataPort[127] -unit.1.4.waveform.posn.88.type=signal -unit.1.4.waveform.posn.89.channel=127 -unit.1.4.waveform.posn.89.name=DataPort[127] -unit.1.4.waveform.posn.89.type=signal -unit.1.4.waveform.posn.9.channel=105 -unit.1.4.waveform.posn.9.name=DataPort[105] -unit.1.4.waveform.posn.9.type=signal -unit.1.4.waveform.posn.90.channel=127 -unit.1.4.waveform.posn.90.name=DataPort[127] -unit.1.4.waveform.posn.90.type=signal -unit.1.4.waveform.posn.91.channel=127 -unit.1.4.waveform.posn.91.name=DataPort[127] -unit.1.4.waveform.posn.91.type=signal -unit.1.4.waveform.posn.92.channel=127 -unit.1.4.waveform.posn.92.name=DataPort[127] -unit.1.4.waveform.posn.92.type=signal -unit.1.4.waveform.posn.93.channel=127 -unit.1.4.waveform.posn.93.name=DataPort[127] -unit.1.4.waveform.posn.93.type=signal -unit.1.4.waveform.posn.94.channel=127 -unit.1.4.waveform.posn.94.name=DataPort[127] -unit.1.4.waveform.posn.94.type=signal -unit.1.4.waveform.posn.95.channel=127 -unit.1.4.waveform.posn.95.name=DataPort[127] -unit.1.4.waveform.posn.95.type=signal -unit.1.4.waveform.posn.96.channel=127 -unit.1.4.waveform.posn.96.name=DataPort[127] -unit.1.4.waveform.posn.96.type=signal -unit.1.4.waveform.posn.97.channel=127 -unit.1.4.waveform.posn.97.name=DataPort[127] -unit.1.4.waveform.posn.97.type=signal -unit.1.4.waveform.posn.98.channel=127 -unit.1.4.waveform.posn.98.name=DataPort[127] -unit.1.4.waveform.posn.98.type=signal -unit.1.4.waveform.posn.99.channel=127 -unit.1.4.waveform.posn.99.name=DataPort[127] -unit.1.4.waveform.posn.99.type=signal -unit.1.5.0.HEIGHT0=0.6028939 -unit.1.5.0.TriggerRow0=1 -unit.1.5.0.TriggerRow1=1 -unit.1.5.0.TriggerRow2=1 -unit.1.5.0.WIDTH0=0.92604005 -unit.1.5.0.X0=0.07395994 -unit.1.5.0.Y0=0.0 -unit.1.5.1.HEIGHT1=1.0032154 -unit.1.5.1.WIDTH1=1.0 -unit.1.5.1.X1=-0.0030816642 -unit.1.5.1.Y1=-0.003215434 -unit.1.5.5.HEIGHT5=0.97588426 -unit.1.5.5.WIDTH5=1.0 -unit.1.5.5.X5=0.0 -unit.1.5.5.Y5=0.0 -unit.1.5.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA2=XXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsA3=XXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.5.MFBitsB0=00000000000000000000000000000000 -unit.1.5.MFBitsB1=00000000000000000000000000000000 -unit.1.5.MFBitsB2=00000000000000000000000000000000 -unit.1.5.MFBitsB3=00000000000000000000000000000000 -unit.1.5.MFCompareA0=0 -unit.1.5.MFCompareA1=0 -unit.1.5.MFCompareA2=0 -unit.1.5.MFCompareA3=0 -unit.1.5.MFCompareB0=999 -unit.1.5.MFCompareB1=999 -unit.1.5.MFCompareB2=999 -unit.1.5.MFCompareB3=999 -unit.1.5.MFCount=4 -unit.1.5.MFDisplay0=0 -unit.1.5.MFDisplay1=0 -unit.1.5.MFDisplay2=0 -unit.1.5.MFDisplay3=0 -unit.1.5.MFEventType0=3 -unit.1.5.MFEventType1=3 -unit.1.5.MFEventType2=3 -unit.1.5.MFEventType3=3 -unit.1.5.RunMode=SINGLE RUN -unit.1.5.SQCondition=M3 -unit.1.5.SQContiguous0=0 -unit.1.5.SequencerOn=0 -unit.1.5.TCActive=0 -unit.1.5.TCAdvanced0=0 -unit.1.5.TCCondition0_0=M3 -unit.1.5.TCCondition0_1= -unit.1.5.TCConditionType0=0 -unit.1.5.TCCount=1 -unit.1.5.TCEventCount0=1 -unit.1.5.TCEventType0=3 -unit.1.5.TCName0=TriggerCondition0 -unit.1.5.TCOutputEnable0=0 -unit.1.5.TCOutputHigh0=1 -unit.1.5.TCOutputMode0=0 -unit.1.5.browser_tree_state=1 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.browser_tree_state=0 -unit.1.5.coretype=ILA -unit.1.5.eventCount0=1 -unit.1.5.eventCount1=1 -unit.1.5.eventCount2=1 -unit.1.5.eventCount3=1 -unit.1.5.plotBusColor0=-16777092 -unit.1.5.plotBusColor1=-16777092 -unit.1.5.plotBusColor10=-16777092 -unit.1.5.plotBusColor11=-16777092 -unit.1.5.plotBusColor12=-16777092 -unit.1.5.plotBusColor13=-16777092 -unit.1.5.plotBusColor14=-16777092 -unit.1.5.plotBusColor15=-16777092 -unit.1.5.plotBusColor16=-16777092 -unit.1.5.plotBusColor17=-16777092 -unit.1.5.plotBusColor18=-16777092 -unit.1.5.plotBusColor19=-16777092 -unit.1.5.plotBusColor2=-16777092 -unit.1.5.plotBusColor20=-16777092 -unit.1.5.plotBusColor3=-16777092 -unit.1.5.plotBusColor4=-16777092 -unit.1.5.plotBusColor5=-16777092 -unit.1.5.plotBusColor6=-16777092 -unit.1.5.plotBusColor7=-16777092 -unit.1.5.plotBusColor8=-16777092 -unit.1.5.plotBusColor9=-16777092 -unit.1.5.plotBusCount=21 -unit.1.5.plotBusName0=memc_cmd_addr(15 downto 0) -unit.1.5.plotBusName1=memc_wr_data(79 downto 64) -unit.1.5.plotBusName10=memarb_acc_req -unit.1.5.plotBusName11=memc_wr_data(15 downto 0) -unit.1.5.plotBusName12=memc_cmd_en -unit.1.5.plotBusName13=memc_cmd_instr -unit.1.5.plotBusName14=memc_cmd_rdy -unit.1.5.plotBusName15=memc_ui_rst -unit.1.5.plotBusName16=memc_wr_data(207 downto 192) -unit.1.5.plotBusName17=memc_wr_en -unit.1.5.plotBusName18=memc_wr_end -unit.1.5.plotBusName19=memc_wr_mask -unit.1.5.plotBusName2=memc_wr_data(143 downto 128) -unit.1.5.plotBusName20=memc_wr_rdy -unit.1.5.plotBusName3=bpm_acq_ext_dreq -unit.1.5.plotBusName4=bpm_acq_ext_eof -unit.1.5.plotBusName5=bpm_acq_ext_sof -unit.1.5.plotBusName6=bpm_acq_ext_stall -unit.1.5.plotBusName7=bpm_acq_ext_valid -unit.1.5.plotBusName8=clk_200mhz_rstn -unit.1.5.plotBusName9=memarb_acc_gnt -unit.1.5.plotBusX=bpm_acq_ext_dreq -unit.1.5.plotBusY=memc_wr_rdy -unit.1.5.plotDataTimeMode=1 -unit.1.5.plotDisplayMode=line -unit.1.5.plotMaxX=0.0 -unit.1.5.plotMaxY=0.0 -unit.1.5.plotMinX=0.0 -unit.1.5.plotMinY=0.0 -unit.1.5.plotSelectedBus=0 -unit.1.5.port.-1.b.0.alias=bpm_acq_ext_dreq -unit.1.5.port.-1.b.0.channellist=65 -unit.1.5.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.0.name=DataPort -unit.1.5.port.-1.b.0.orderindex=-1 -unit.1.5.port.-1.b.0.radix=Hex -unit.1.5.port.-1.b.0.signedOffset=0.0 -unit.1.5.port.-1.b.0.signedPrecision=0 -unit.1.5.port.-1.b.0.signedScaleFactor=1.0 -unit.1.5.port.-1.b.0.tokencount=0 -unit.1.5.port.-1.b.0.unsignedOffset=0.0 -unit.1.5.port.-1.b.0.unsignedPrecision=0 -unit.1.5.port.-1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.0.visible=1 -unit.1.5.port.-1.b.1.alias=bpm_acq_ext_eof -unit.1.5.port.-1.b.1.channellist=66 -unit.1.5.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.1.name=DataPort -unit.1.5.port.-1.b.1.orderindex=-1 -unit.1.5.port.-1.b.1.radix=Hex -unit.1.5.port.-1.b.1.signedOffset=0.0 -unit.1.5.port.-1.b.1.signedPrecision=0 -unit.1.5.port.-1.b.1.signedScaleFactor=1.0 -unit.1.5.port.-1.b.1.tokencount=0 -unit.1.5.port.-1.b.1.unsignedOffset=0.0 -unit.1.5.port.-1.b.1.unsignedPrecision=0 -unit.1.5.port.-1.b.1.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.1.visible=1 -unit.1.5.port.-1.b.10.alias=memc_cmd_instr -unit.1.5.port.-1.b.10.channellist=119 120 121 -unit.1.5.port.-1.b.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.10.name=DataPort -unit.1.5.port.-1.b.10.orderindex=-1 -unit.1.5.port.-1.b.10.radix=Hex -unit.1.5.port.-1.b.10.signedOffset=0.0 -unit.1.5.port.-1.b.10.signedPrecision=0 -unit.1.5.port.-1.b.10.signedScaleFactor=1.0 -unit.1.5.port.-1.b.10.tokencount=0 -unit.1.5.port.-1.b.10.unsignedOffset=0.0 -unit.1.5.port.-1.b.10.unsignedPrecision=0 -unit.1.5.port.-1.b.10.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.10.visible=1 -unit.1.5.port.-1.b.11.alias=memc_cmd_rdy -unit.1.5.port.-1.b.11.channellist=117 -unit.1.5.port.-1.b.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.11.name=DataPort -unit.1.5.port.-1.b.11.orderindex=-1 -unit.1.5.port.-1.b.11.radix=Hex -unit.1.5.port.-1.b.11.signedOffset=0.0 -unit.1.5.port.-1.b.11.signedPrecision=0 -unit.1.5.port.-1.b.11.signedScaleFactor=1.0 -unit.1.5.port.-1.b.11.tokencount=0 -unit.1.5.port.-1.b.11.unsignedOffset=0.0 -unit.1.5.port.-1.b.11.unsignedPrecision=0 -unit.1.5.port.-1.b.11.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.11.visible=1 -unit.1.5.port.-1.b.12.alias=memc_ui_rst -unit.1.5.port.-1.b.12.channellist=123 -unit.1.5.port.-1.b.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.12.name=DataPort -unit.1.5.port.-1.b.12.orderindex=-1 -unit.1.5.port.-1.b.12.radix=Hex -unit.1.5.port.-1.b.12.signedOffset=0.0 -unit.1.5.port.-1.b.12.signedPrecision=0 -unit.1.5.port.-1.b.12.signedScaleFactor=1.0 -unit.1.5.port.-1.b.12.tokencount=0 -unit.1.5.port.-1.b.12.unsignedOffset=0.0 -unit.1.5.port.-1.b.12.unsignedPrecision=0 -unit.1.5.port.-1.b.12.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.12.visible=1 -unit.1.5.port.-1.b.13.alias=memc_wr_data(143 downto 128) -unit.1.5.port.-1.b.13.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -unit.1.5.port.-1.b.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.13.name=DataPort -unit.1.5.port.-1.b.13.orderindex=-1 -unit.1.5.port.-1.b.13.radix=Signed -unit.1.5.port.-1.b.13.signedOffset=0.0 -unit.1.5.port.-1.b.13.signedPrecision=0 -unit.1.5.port.-1.b.13.signedScaleFactor=1.0 -unit.1.5.port.-1.b.13.tokencount=0 -unit.1.5.port.-1.b.13.unsignedOffset=0.0 -unit.1.5.port.-1.b.13.unsignedPrecision=0 -unit.1.5.port.-1.b.13.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.13.visible=1 -unit.1.5.port.-1.b.14.alias=memc_wr_data(15 downto 0) -unit.1.5.port.-1.b.14.channellist=32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 -unit.1.5.port.-1.b.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.14.name=DataPort -unit.1.5.port.-1.b.14.orderindex=-1 -unit.1.5.port.-1.b.14.radix=Signed -unit.1.5.port.-1.b.14.signedOffset=0.0 -unit.1.5.port.-1.b.14.signedPrecision=0 -unit.1.5.port.-1.b.14.signedScaleFactor=1.0 -unit.1.5.port.-1.b.14.tokencount=0 -unit.1.5.port.-1.b.14.unsignedOffset=0.0 -unit.1.5.port.-1.b.14.unsignedPrecision=0 -unit.1.5.port.-1.b.14.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.14.visible=1 -unit.1.5.port.-1.b.15.alias=memc_wr_data(207 downto 192) -unit.1.5.port.-1.b.15.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.-1.b.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.15.name=DataPort -unit.1.5.port.-1.b.15.orderindex=-1 -unit.1.5.port.-1.b.15.radix=Signed -unit.1.5.port.-1.b.15.signedOffset=0.0 -unit.1.5.port.-1.b.15.signedPrecision=0 -unit.1.5.port.-1.b.15.signedScaleFactor=1.0 -unit.1.5.port.-1.b.15.tokencount=0 -unit.1.5.port.-1.b.15.unsignedOffset=0.0 -unit.1.5.port.-1.b.15.unsignedPrecision=0 -unit.1.5.port.-1.b.15.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.15.visible=1 -unit.1.5.port.-1.b.16.alias=memc_wr_data(79 downto 64) -unit.1.5.port.-1.b.16.channellist=48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 -unit.1.5.port.-1.b.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.16.name=DataPort -unit.1.5.port.-1.b.16.orderindex=-1 -unit.1.5.port.-1.b.16.radix=Signed -unit.1.5.port.-1.b.16.signedOffset=0.0 -unit.1.5.port.-1.b.16.signedPrecision=0 -unit.1.5.port.-1.b.16.signedScaleFactor=1.0 -unit.1.5.port.-1.b.16.tokencount=0 -unit.1.5.port.-1.b.16.unsignedOffset=0.0 -unit.1.5.port.-1.b.16.unsignedPrecision=0 -unit.1.5.port.-1.b.16.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.16.visible=1 -unit.1.5.port.-1.b.17.alias=memc_wr_en -unit.1.5.port.-1.b.17.channellist=99 -unit.1.5.port.-1.b.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.17.name=DataPort -unit.1.5.port.-1.b.17.orderindex=-1 -unit.1.5.port.-1.b.17.radix=Hex -unit.1.5.port.-1.b.17.signedOffset=0.0 -unit.1.5.port.-1.b.17.signedPrecision=0 -unit.1.5.port.-1.b.17.signedScaleFactor=1.0 -unit.1.5.port.-1.b.17.tokencount=0 -unit.1.5.port.-1.b.17.unsignedOffset=0.0 -unit.1.5.port.-1.b.17.unsignedPrecision=0 -unit.1.5.port.-1.b.17.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.17.visible=1 -unit.1.5.port.-1.b.18.alias=memc_wr_end -unit.1.5.port.-1.b.18.channellist=116 -unit.1.5.port.-1.b.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.18.name=DataPort -unit.1.5.port.-1.b.18.orderindex=-1 -unit.1.5.port.-1.b.18.radix=Hex -unit.1.5.port.-1.b.18.signedOffset=0.0 -unit.1.5.port.-1.b.18.signedPrecision=0 -unit.1.5.port.-1.b.18.signedScaleFactor=1.0 -unit.1.5.port.-1.b.18.tokencount=0 -unit.1.5.port.-1.b.18.unsignedOffset=0.0 -unit.1.5.port.-1.b.18.unsignedPrecision=0 -unit.1.5.port.-1.b.18.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.18.visible=1 -unit.1.5.port.-1.b.19.alias=memc_wr_mask -unit.1.5.port.-1.b.19.channellist=100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 -unit.1.5.port.-1.b.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.19.name=DataPort -unit.1.5.port.-1.b.19.orderindex=-1 -unit.1.5.port.-1.b.19.radix=Hex -unit.1.5.port.-1.b.19.signedOffset=0.0 -unit.1.5.port.-1.b.19.signedPrecision=0 -unit.1.5.port.-1.b.19.signedScaleFactor=1.0 -unit.1.5.port.-1.b.19.tokencount=0 -unit.1.5.port.-1.b.19.unsignedOffset=0.0 -unit.1.5.port.-1.b.19.unsignedPrecision=0 -unit.1.5.port.-1.b.19.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.19.visible=1 -unit.1.5.port.-1.b.2.alias=bpm_acq_ext_sof -unit.1.5.port.-1.b.2.channellist=67 -unit.1.5.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.2.name=DataPort -unit.1.5.port.-1.b.2.orderindex=-1 -unit.1.5.port.-1.b.2.radix=Hex -unit.1.5.port.-1.b.2.signedOffset=0.0 -unit.1.5.port.-1.b.2.signedPrecision=0 -unit.1.5.port.-1.b.2.signedScaleFactor=1.0 -unit.1.5.port.-1.b.2.tokencount=0 -unit.1.5.port.-1.b.2.unsignedOffset=0.0 -unit.1.5.port.-1.b.2.unsignedPrecision=0 -unit.1.5.port.-1.b.2.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.2.visible=1 -unit.1.5.port.-1.b.20.alias=memc_wr_rdy -unit.1.5.port.-1.b.20.channellist=98 -unit.1.5.port.-1.b.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.20.name=DataPort -unit.1.5.port.-1.b.20.orderindex=-1 -unit.1.5.port.-1.b.20.radix=Hex -unit.1.5.port.-1.b.20.signedOffset=0.0 -unit.1.5.port.-1.b.20.signedPrecision=0 -unit.1.5.port.-1.b.20.signedScaleFactor=1.0 -unit.1.5.port.-1.b.20.tokencount=0 -unit.1.5.port.-1.b.20.unsignedOffset=0.0 -unit.1.5.port.-1.b.20.unsignedPrecision=0 -unit.1.5.port.-1.b.20.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.20.visible=1 -unit.1.5.port.-1.b.3.alias=bpm_acq_ext_stall -unit.1.5.port.-1.b.3.channellist=64 -unit.1.5.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.3.name=DataPort -unit.1.5.port.-1.b.3.orderindex=-1 -unit.1.5.port.-1.b.3.radix=Hex -unit.1.5.port.-1.b.3.signedOffset=0.0 -unit.1.5.port.-1.b.3.signedPrecision=0 -unit.1.5.port.-1.b.3.signedScaleFactor=1.0 -unit.1.5.port.-1.b.3.tokencount=0 -unit.1.5.port.-1.b.3.unsignedOffset=0.0 -unit.1.5.port.-1.b.3.unsignedPrecision=0 -unit.1.5.port.-1.b.3.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.3.visible=1 -unit.1.5.port.-1.b.4.alias=bpm_acq_ext_valid -unit.1.5.port.-1.b.4.channellist=68 -unit.1.5.port.-1.b.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.4.name=DataPort -unit.1.5.port.-1.b.4.orderindex=-1 -unit.1.5.port.-1.b.4.radix=Hex -unit.1.5.port.-1.b.4.signedOffset=0.0 -unit.1.5.port.-1.b.4.signedPrecision=0 -unit.1.5.port.-1.b.4.signedScaleFactor=1.0 -unit.1.5.port.-1.b.4.tokencount=0 -unit.1.5.port.-1.b.4.unsignedOffset=0.0 -unit.1.5.port.-1.b.4.unsignedPrecision=0 -unit.1.5.port.-1.b.4.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.4.visible=1 -unit.1.5.port.-1.b.5.alias=clk_200mhz_rstn -unit.1.5.port.-1.b.5.channellist=122 -unit.1.5.port.-1.b.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.5.name=DataPort -unit.1.5.port.-1.b.5.orderindex=-1 -unit.1.5.port.-1.b.5.radix=Hex -unit.1.5.port.-1.b.5.signedOffset=0.0 -unit.1.5.port.-1.b.5.signedPrecision=0 -unit.1.5.port.-1.b.5.signedScaleFactor=1.0 -unit.1.5.port.-1.b.5.tokencount=0 -unit.1.5.port.-1.b.5.unsignedOffset=0.0 -unit.1.5.port.-1.b.5.unsignedPrecision=0 -unit.1.5.port.-1.b.5.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.5.visible=1 -unit.1.5.port.-1.b.6.alias=memarb_acc_gnt -unit.1.5.port.-1.b.6.channellist=96 -unit.1.5.port.-1.b.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.6.name=DataPort -unit.1.5.port.-1.b.6.orderindex=-1 -unit.1.5.port.-1.b.6.radix=Hex -unit.1.5.port.-1.b.6.signedOffset=0.0 -unit.1.5.port.-1.b.6.signedPrecision=0 -unit.1.5.port.-1.b.6.signedScaleFactor=1.0 -unit.1.5.port.-1.b.6.tokencount=0 -unit.1.5.port.-1.b.6.unsignedOffset=0.0 -unit.1.5.port.-1.b.6.unsignedPrecision=0 -unit.1.5.port.-1.b.6.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.6.visible=1 -unit.1.5.port.-1.b.7.alias=memarb_acc_req -unit.1.5.port.-1.b.7.channellist=97 -unit.1.5.port.-1.b.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.7.name=DataPort -unit.1.5.port.-1.b.7.orderindex=-1 -unit.1.5.port.-1.b.7.radix=Hex -unit.1.5.port.-1.b.7.signedOffset=0.0 -unit.1.5.port.-1.b.7.signedPrecision=0 -unit.1.5.port.-1.b.7.signedScaleFactor=1.0 -unit.1.5.port.-1.b.7.tokencount=0 -unit.1.5.port.-1.b.7.unsignedOffset=0.0 -unit.1.5.port.-1.b.7.unsignedPrecision=0 -unit.1.5.port.-1.b.7.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.7.visible=1 -unit.1.5.port.-1.b.8.alias=memc_cmd_addr(15 downto 0) -unit.1.5.port.-1.b.8.channellist=69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 -unit.1.5.port.-1.b.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.8.name=DataPort -unit.1.5.port.-1.b.8.orderindex=-1 -unit.1.5.port.-1.b.8.radix=Hex -unit.1.5.port.-1.b.8.signedOffset=0.0 -unit.1.5.port.-1.b.8.signedPrecision=0 -unit.1.5.port.-1.b.8.signedScaleFactor=1.0 -unit.1.5.port.-1.b.8.tokencount=0 -unit.1.5.port.-1.b.8.unsignedOffset=0.0 -unit.1.5.port.-1.b.8.unsignedPrecision=0 -unit.1.5.port.-1.b.8.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.8.visible=1 -unit.1.5.port.-1.b.9.alias=memc_cmd_en -unit.1.5.port.-1.b.9.channellist=118 -unit.1.5.port.-1.b.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.b.9.name=DataPort -unit.1.5.port.-1.b.9.orderindex=-1 -unit.1.5.port.-1.b.9.radix=Hex -unit.1.5.port.-1.b.9.signedOffset=0.0 -unit.1.5.port.-1.b.9.signedPrecision=0 -unit.1.5.port.-1.b.9.signedScaleFactor=1.0 -unit.1.5.port.-1.b.9.tokencount=0 -unit.1.5.port.-1.b.9.unsignedOffset=0.0 -unit.1.5.port.-1.b.9.unsignedPrecision=0 -unit.1.5.port.-1.b.9.unsignedScaleFactor=1.0 -unit.1.5.port.-1.b.9.visible=1 -unit.1.5.port.-1.buscount=21 -unit.1.5.port.-1.channelcount=128 -unit.1.5.port.-1.s.0.alias= -unit.1.5.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.0.name=DataPort[0] -unit.1.5.port.-1.s.0.orderindex=-1 -unit.1.5.port.-1.s.0.visible=0 -unit.1.5.port.-1.s.1.alias= -unit.1.5.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.1.name=DataPort[1] -unit.1.5.port.-1.s.1.orderindex=-1 -unit.1.5.port.-1.s.1.visible=0 -unit.1.5.port.-1.s.10.alias= -unit.1.5.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.10.name=DataPort[10] -unit.1.5.port.-1.s.10.orderindex=-1 -unit.1.5.port.-1.s.10.visible=0 -unit.1.5.port.-1.s.100.alias= -unit.1.5.port.-1.s.100.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.100.name=DataPort[100] -unit.1.5.port.-1.s.100.orderindex=-1 -unit.1.5.port.-1.s.100.visible=0 -unit.1.5.port.-1.s.101.alias= -unit.1.5.port.-1.s.101.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.101.name=DataPort[101] -unit.1.5.port.-1.s.101.orderindex=-1 -unit.1.5.port.-1.s.101.visible=0 -unit.1.5.port.-1.s.102.alias= -unit.1.5.port.-1.s.102.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.102.name=DataPort[102] -unit.1.5.port.-1.s.102.orderindex=-1 -unit.1.5.port.-1.s.102.visible=0 -unit.1.5.port.-1.s.103.alias= -unit.1.5.port.-1.s.103.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.103.name=DataPort[103] -unit.1.5.port.-1.s.103.orderindex=-1 -unit.1.5.port.-1.s.103.visible=0 -unit.1.5.port.-1.s.104.alias= -unit.1.5.port.-1.s.104.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.104.name=DataPort[104] -unit.1.5.port.-1.s.104.orderindex=-1 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-unit.1.5.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.-1.s.99.name=DataPort[99] -unit.1.5.port.-1.s.99.orderindex=-1 -unit.1.5.port.-1.s.99.visible=0 -unit.1.5.port.0.b.0.alias= -unit.1.5.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.b.0.name=TriggerPort0 -unit.1.5.port.0.b.0.orderindex=-1 -unit.1.5.port.0.b.0.radix=Hex -unit.1.5.port.0.b.0.signedOffset=0.0 -unit.1.5.port.0.b.0.signedPrecision=0 -unit.1.5.port.0.b.0.signedScaleFactor=1.0 -unit.1.5.port.0.b.0.unsignedOffset=0.0 -unit.1.5.port.0.b.0.unsignedPrecision=0 -unit.1.5.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.0.b.0.visible=1 -unit.1.5.port.0.buscount=1 -unit.1.5.port.0.channelcount=32 -unit.1.5.port.0.s.0.alias= -unit.1.5.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.0.name=TriggerPort0[0] -unit.1.5.port.0.s.0.orderindex=-1 -unit.1.5.port.0.s.0.visible=1 -unit.1.5.port.0.s.1.alias= -unit.1.5.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.1.name=TriggerPort0[1] -unit.1.5.port.0.s.1.orderindex=-1 -unit.1.5.port.0.s.1.visible=1 -unit.1.5.port.0.s.10.alias= -unit.1.5.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.10.name=TriggerPort0[10] -unit.1.5.port.0.s.10.orderindex=-1 -unit.1.5.port.0.s.10.visible=1 -unit.1.5.port.0.s.11.alias= -unit.1.5.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.11.name=TriggerPort0[11] -unit.1.5.port.0.s.11.orderindex=-1 -unit.1.5.port.0.s.11.visible=1 -unit.1.5.port.0.s.12.alias= -unit.1.5.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.12.name=TriggerPort0[12] -unit.1.5.port.0.s.12.orderindex=-1 -unit.1.5.port.0.s.12.visible=1 -unit.1.5.port.0.s.13.alias= -unit.1.5.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.13.name=TriggerPort0[13] -unit.1.5.port.0.s.13.orderindex=-1 -unit.1.5.port.0.s.13.visible=1 -unit.1.5.port.0.s.14.alias= -unit.1.5.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.14.name=TriggerPort0[14] -unit.1.5.port.0.s.14.orderindex=-1 -unit.1.5.port.0.s.14.visible=1 -unit.1.5.port.0.s.15.alias= -unit.1.5.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.15.name=TriggerPort0[15] -unit.1.5.port.0.s.15.orderindex=-1 -unit.1.5.port.0.s.15.visible=1 -unit.1.5.port.0.s.16.alias= -unit.1.5.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.16.name=TriggerPort0[16] -unit.1.5.port.0.s.16.orderindex=-1 -unit.1.5.port.0.s.16.visible=1 -unit.1.5.port.0.s.17.alias= -unit.1.5.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.17.name=TriggerPort0[17] -unit.1.5.port.0.s.17.orderindex=-1 -unit.1.5.port.0.s.17.visible=1 -unit.1.5.port.0.s.18.alias= -unit.1.5.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.18.name=TriggerPort0[18] -unit.1.5.port.0.s.18.orderindex=-1 -unit.1.5.port.0.s.18.visible=1 -unit.1.5.port.0.s.19.alias= -unit.1.5.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.19.name=TriggerPort0[19] -unit.1.5.port.0.s.19.orderindex=-1 -unit.1.5.port.0.s.19.visible=1 -unit.1.5.port.0.s.2.alias= -unit.1.5.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.2.name=TriggerPort0[2] -unit.1.5.port.0.s.2.orderindex=-1 -unit.1.5.port.0.s.2.visible=1 -unit.1.5.port.0.s.20.alias= -unit.1.5.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.20.name=TriggerPort0[20] -unit.1.5.port.0.s.20.orderindex=-1 -unit.1.5.port.0.s.20.visible=1 -unit.1.5.port.0.s.21.alias= -unit.1.5.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.21.name=TriggerPort0[21] -unit.1.5.port.0.s.21.orderindex=-1 -unit.1.5.port.0.s.21.visible=1 -unit.1.5.port.0.s.22.alias= -unit.1.5.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.22.name=TriggerPort0[22] -unit.1.5.port.0.s.22.orderindex=-1 -unit.1.5.port.0.s.22.visible=1 -unit.1.5.port.0.s.23.alias= -unit.1.5.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.23.name=TriggerPort0[23] -unit.1.5.port.0.s.23.orderindex=-1 -unit.1.5.port.0.s.23.visible=1 -unit.1.5.port.0.s.24.alias= -unit.1.5.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.24.name=TriggerPort0[24] -unit.1.5.port.0.s.24.orderindex=-1 -unit.1.5.port.0.s.24.visible=1 -unit.1.5.port.0.s.25.alias= -unit.1.5.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.25.name=TriggerPort0[25] -unit.1.5.port.0.s.25.orderindex=-1 -unit.1.5.port.0.s.25.visible=1 -unit.1.5.port.0.s.26.alias= -unit.1.5.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.26.name=TriggerPort0[26] -unit.1.5.port.0.s.26.orderindex=-1 -unit.1.5.port.0.s.26.visible=1 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-unit.1.5.port.0.s.7.visible=1 -unit.1.5.port.0.s.8.alias= -unit.1.5.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.8.name=TriggerPort0[8] -unit.1.5.port.0.s.8.orderindex=-1 -unit.1.5.port.0.s.8.visible=1 -unit.1.5.port.0.s.9.alias= -unit.1.5.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.0.s.9.name=TriggerPort0[9] -unit.1.5.port.0.s.9.orderindex=-1 -unit.1.5.port.0.s.9.visible=1 -unit.1.5.port.1.b.0.alias= -unit.1.5.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.b.0.name=TriggerPort1 -unit.1.5.port.1.b.0.orderindex=-1 -unit.1.5.port.1.b.0.radix=Hex -unit.1.5.port.1.b.0.signedOffset=0.0 -unit.1.5.port.1.b.0.signedPrecision=0 -unit.1.5.port.1.b.0.signedScaleFactor=1.0 -unit.1.5.port.1.b.0.unsignedOffset=0.0 -unit.1.5.port.1.b.0.unsignedPrecision=0 -unit.1.5.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.1.b.0.visible=1 -unit.1.5.port.1.buscount=1 -unit.1.5.port.1.channelcount=32 -unit.1.5.port.1.s.0.alias= -unit.1.5.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.0.name=TriggerPort1[0] -unit.1.5.port.1.s.0.orderindex=-1 -unit.1.5.port.1.s.0.visible=1 -unit.1.5.port.1.s.1.alias= -unit.1.5.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.1.name=TriggerPort1[1] -unit.1.5.port.1.s.1.orderindex=-1 -unit.1.5.port.1.s.1.visible=1 -unit.1.5.port.1.s.10.alias= -unit.1.5.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.10.name=TriggerPort1[10] -unit.1.5.port.1.s.10.orderindex=-1 -unit.1.5.port.1.s.10.visible=1 -unit.1.5.port.1.s.11.alias= -unit.1.5.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.11.name=TriggerPort1[11] -unit.1.5.port.1.s.11.orderindex=-1 -unit.1.5.port.1.s.11.visible=1 -unit.1.5.port.1.s.12.alias= -unit.1.5.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.12.name=TriggerPort1[12] -unit.1.5.port.1.s.12.orderindex=-1 -unit.1.5.port.1.s.12.visible=1 -unit.1.5.port.1.s.13.alias= -unit.1.5.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.13.name=TriggerPort1[13] -unit.1.5.port.1.s.13.orderindex=-1 -unit.1.5.port.1.s.13.visible=1 -unit.1.5.port.1.s.14.alias= -unit.1.5.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.14.name=TriggerPort1[14] -unit.1.5.port.1.s.14.orderindex=-1 -unit.1.5.port.1.s.14.visible=1 -unit.1.5.port.1.s.15.alias= -unit.1.5.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.15.name=TriggerPort1[15] -unit.1.5.port.1.s.15.orderindex=-1 -unit.1.5.port.1.s.15.visible=1 -unit.1.5.port.1.s.16.alias= -unit.1.5.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.16.name=TriggerPort1[16] -unit.1.5.port.1.s.16.orderindex=-1 -unit.1.5.port.1.s.16.visible=1 -unit.1.5.port.1.s.17.alias= -unit.1.5.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.17.name=TriggerPort1[17] -unit.1.5.port.1.s.17.orderindex=-1 -unit.1.5.port.1.s.17.visible=1 -unit.1.5.port.1.s.18.alias= -unit.1.5.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.18.name=TriggerPort1[18] -unit.1.5.port.1.s.18.orderindex=-1 -unit.1.5.port.1.s.18.visible=1 -unit.1.5.port.1.s.19.alias= -unit.1.5.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.19.name=TriggerPort1[19] -unit.1.5.port.1.s.19.orderindex=-1 -unit.1.5.port.1.s.19.visible=1 -unit.1.5.port.1.s.2.alias= -unit.1.5.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.2.name=TriggerPort1[2] -unit.1.5.port.1.s.2.orderindex=-1 -unit.1.5.port.1.s.2.visible=1 -unit.1.5.port.1.s.20.alias= -unit.1.5.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.20.name=TriggerPort1[20] -unit.1.5.port.1.s.20.orderindex=-1 -unit.1.5.port.1.s.20.visible=1 -unit.1.5.port.1.s.21.alias= -unit.1.5.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.21.name=TriggerPort1[21] -unit.1.5.port.1.s.21.orderindex=-1 -unit.1.5.port.1.s.21.visible=1 -unit.1.5.port.1.s.22.alias= -unit.1.5.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.22.name=TriggerPort1[22] -unit.1.5.port.1.s.22.orderindex=-1 -unit.1.5.port.1.s.22.visible=1 -unit.1.5.port.1.s.23.alias= -unit.1.5.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.23.name=TriggerPort1[23] -unit.1.5.port.1.s.23.orderindex=-1 -unit.1.5.port.1.s.23.visible=1 -unit.1.5.port.1.s.24.alias= -unit.1.5.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.24.name=TriggerPort1[24] -unit.1.5.port.1.s.24.orderindex=-1 -unit.1.5.port.1.s.24.visible=1 -unit.1.5.port.1.s.25.alias= -unit.1.5.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.25.name=TriggerPort1[25] -unit.1.5.port.1.s.25.orderindex=-1 -unit.1.5.port.1.s.25.visible=1 -unit.1.5.port.1.s.26.alias= -unit.1.5.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.26.name=TriggerPort1[26] -unit.1.5.port.1.s.26.orderindex=-1 -unit.1.5.port.1.s.26.visible=1 -unit.1.5.port.1.s.27.alias= -unit.1.5.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.27.name=TriggerPort1[27] -unit.1.5.port.1.s.27.orderindex=-1 -unit.1.5.port.1.s.27.visible=1 -unit.1.5.port.1.s.28.alias= -unit.1.5.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.28.name=TriggerPort1[28] -unit.1.5.port.1.s.28.orderindex=-1 -unit.1.5.port.1.s.28.visible=1 -unit.1.5.port.1.s.29.alias= -unit.1.5.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.29.name=TriggerPort1[29] -unit.1.5.port.1.s.29.orderindex=-1 -unit.1.5.port.1.s.29.visible=1 -unit.1.5.port.1.s.3.alias= -unit.1.5.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.3.name=TriggerPort1[3] -unit.1.5.port.1.s.3.orderindex=-1 -unit.1.5.port.1.s.3.visible=1 -unit.1.5.port.1.s.30.alias= -unit.1.5.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.30.name=TriggerPort1[30] -unit.1.5.port.1.s.30.orderindex=-1 -unit.1.5.port.1.s.30.visible=1 -unit.1.5.port.1.s.31.alias= -unit.1.5.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.31.name=TriggerPort1[31] -unit.1.5.port.1.s.31.orderindex=-1 -unit.1.5.port.1.s.31.visible=1 -unit.1.5.port.1.s.4.alias= -unit.1.5.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.4.name=TriggerPort1[4] -unit.1.5.port.1.s.4.orderindex=-1 -unit.1.5.port.1.s.4.visible=1 -unit.1.5.port.1.s.5.alias= -unit.1.5.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.5.name=TriggerPort1[5] -unit.1.5.port.1.s.5.orderindex=-1 -unit.1.5.port.1.s.5.visible=1 -unit.1.5.port.1.s.6.alias= -unit.1.5.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.6.name=TriggerPort1[6] -unit.1.5.port.1.s.6.orderindex=-1 -unit.1.5.port.1.s.6.visible=1 -unit.1.5.port.1.s.7.alias= -unit.1.5.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.7.name=TriggerPort1[7] -unit.1.5.port.1.s.7.orderindex=-1 -unit.1.5.port.1.s.7.visible=1 -unit.1.5.port.1.s.8.alias= -unit.1.5.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.8.name=TriggerPort1[8] -unit.1.5.port.1.s.8.orderindex=-1 -unit.1.5.port.1.s.8.visible=1 -unit.1.5.port.1.s.9.alias= -unit.1.5.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.1.s.9.name=TriggerPort1[9] -unit.1.5.port.1.s.9.orderindex=-1 -unit.1.5.port.1.s.9.visible=1 -unit.1.5.port.2.b.0.alias= -unit.1.5.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.b.0.name=TriggerPort2 -unit.1.5.port.2.b.0.orderindex=-1 -unit.1.5.port.2.b.0.radix=Hex -unit.1.5.port.2.b.0.signedOffset=0.0 -unit.1.5.port.2.b.0.signedPrecision=0 -unit.1.5.port.2.b.0.signedScaleFactor=1.0 -unit.1.5.port.2.b.0.unsignedOffset=0.0 -unit.1.5.port.2.b.0.unsignedPrecision=0 -unit.1.5.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.2.b.0.visible=1 -unit.1.5.port.2.buscount=1 -unit.1.5.port.2.channelcount=32 -unit.1.5.port.2.s.0.alias= -unit.1.5.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.0.name=TriggerPort2[0] -unit.1.5.port.2.s.0.orderindex=-1 -unit.1.5.port.2.s.0.visible=1 -unit.1.5.port.2.s.1.alias= -unit.1.5.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.1.name=TriggerPort2[1] -unit.1.5.port.2.s.1.orderindex=-1 -unit.1.5.port.2.s.1.visible=1 -unit.1.5.port.2.s.10.alias= -unit.1.5.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.10.name=TriggerPort2[10] -unit.1.5.port.2.s.10.orderindex=-1 -unit.1.5.port.2.s.10.visible=1 -unit.1.5.port.2.s.11.alias= -unit.1.5.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.11.name=TriggerPort2[11] -unit.1.5.port.2.s.11.orderindex=-1 -unit.1.5.port.2.s.11.visible=1 -unit.1.5.port.2.s.12.alias= -unit.1.5.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.12.name=TriggerPort2[12] -unit.1.5.port.2.s.12.orderindex=-1 -unit.1.5.port.2.s.12.visible=1 -unit.1.5.port.2.s.13.alias= -unit.1.5.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.13.name=TriggerPort2[13] -unit.1.5.port.2.s.13.orderindex=-1 -unit.1.5.port.2.s.13.visible=1 -unit.1.5.port.2.s.14.alias= -unit.1.5.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.14.name=TriggerPort2[14] -unit.1.5.port.2.s.14.orderindex=-1 -unit.1.5.port.2.s.14.visible=1 -unit.1.5.port.2.s.15.alias= -unit.1.5.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.15.name=TriggerPort2[15] -unit.1.5.port.2.s.15.orderindex=-1 -unit.1.5.port.2.s.15.visible=1 -unit.1.5.port.2.s.16.alias= -unit.1.5.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.16.name=TriggerPort2[16] -unit.1.5.port.2.s.16.orderindex=-1 -unit.1.5.port.2.s.16.visible=1 -unit.1.5.port.2.s.17.alias= -unit.1.5.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.17.name=TriggerPort2[17] -unit.1.5.port.2.s.17.orderindex=-1 -unit.1.5.port.2.s.17.visible=1 -unit.1.5.port.2.s.18.alias= -unit.1.5.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.18.name=TriggerPort2[18] -unit.1.5.port.2.s.18.orderindex=-1 -unit.1.5.port.2.s.18.visible=1 -unit.1.5.port.2.s.19.alias= -unit.1.5.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.19.name=TriggerPort2[19] -unit.1.5.port.2.s.19.orderindex=-1 -unit.1.5.port.2.s.19.visible=1 -unit.1.5.port.2.s.2.alias= -unit.1.5.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.2.name=TriggerPort2[2] -unit.1.5.port.2.s.2.orderindex=-1 -unit.1.5.port.2.s.2.visible=1 -unit.1.5.port.2.s.20.alias= -unit.1.5.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.20.name=TriggerPort2[20] -unit.1.5.port.2.s.20.orderindex=-1 -unit.1.5.port.2.s.20.visible=1 -unit.1.5.port.2.s.21.alias= -unit.1.5.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.21.name=TriggerPort2[21] -unit.1.5.port.2.s.21.orderindex=-1 -unit.1.5.port.2.s.21.visible=1 -unit.1.5.port.2.s.22.alias= -unit.1.5.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.22.name=TriggerPort2[22] -unit.1.5.port.2.s.22.orderindex=-1 -unit.1.5.port.2.s.22.visible=1 -unit.1.5.port.2.s.23.alias= -unit.1.5.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.23.name=TriggerPort2[23] -unit.1.5.port.2.s.23.orderindex=-1 -unit.1.5.port.2.s.23.visible=1 -unit.1.5.port.2.s.24.alias= -unit.1.5.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.24.name=TriggerPort2[24] -unit.1.5.port.2.s.24.orderindex=-1 -unit.1.5.port.2.s.24.visible=1 -unit.1.5.port.2.s.25.alias= -unit.1.5.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.25.name=TriggerPort2[25] -unit.1.5.port.2.s.25.orderindex=-1 -unit.1.5.port.2.s.25.visible=1 -unit.1.5.port.2.s.26.alias= -unit.1.5.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.26.name=TriggerPort2[26] -unit.1.5.port.2.s.26.orderindex=-1 -unit.1.5.port.2.s.26.visible=1 -unit.1.5.port.2.s.27.alias= -unit.1.5.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.27.name=TriggerPort2[27] -unit.1.5.port.2.s.27.orderindex=-1 -unit.1.5.port.2.s.27.visible=1 -unit.1.5.port.2.s.28.alias= -unit.1.5.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.28.name=TriggerPort2[28] -unit.1.5.port.2.s.28.orderindex=-1 -unit.1.5.port.2.s.28.visible=1 -unit.1.5.port.2.s.29.alias= -unit.1.5.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.29.name=TriggerPort2[29] -unit.1.5.port.2.s.29.orderindex=-1 -unit.1.5.port.2.s.29.visible=1 -unit.1.5.port.2.s.3.alias= -unit.1.5.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.3.name=TriggerPort2[3] -unit.1.5.port.2.s.3.orderindex=-1 -unit.1.5.port.2.s.3.visible=1 -unit.1.5.port.2.s.30.alias= -unit.1.5.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.30.name=TriggerPort2[30] -unit.1.5.port.2.s.30.orderindex=-1 -unit.1.5.port.2.s.30.visible=1 -unit.1.5.port.2.s.31.alias= -unit.1.5.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.31.name=TriggerPort2[31] -unit.1.5.port.2.s.31.orderindex=-1 -unit.1.5.port.2.s.31.visible=1 -unit.1.5.port.2.s.4.alias= -unit.1.5.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.4.name=TriggerPort2[4] -unit.1.5.port.2.s.4.orderindex=-1 -unit.1.5.port.2.s.4.visible=1 -unit.1.5.port.2.s.5.alias= -unit.1.5.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.5.name=TriggerPort2[5] -unit.1.5.port.2.s.5.orderindex=-1 -unit.1.5.port.2.s.5.visible=1 -unit.1.5.port.2.s.6.alias= -unit.1.5.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.6.name=TriggerPort2[6] -unit.1.5.port.2.s.6.orderindex=-1 -unit.1.5.port.2.s.6.visible=1 -unit.1.5.port.2.s.7.alias= -unit.1.5.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.7.name=TriggerPort2[7] -unit.1.5.port.2.s.7.orderindex=-1 -unit.1.5.port.2.s.7.visible=1 -unit.1.5.port.2.s.8.alias= -unit.1.5.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.8.name=TriggerPort2[8] -unit.1.5.port.2.s.8.orderindex=-1 -unit.1.5.port.2.s.8.visible=1 -unit.1.5.port.2.s.9.alias= -unit.1.5.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.2.s.9.name=TriggerPort2[9] -unit.1.5.port.2.s.9.orderindex=-1 -unit.1.5.port.2.s.9.visible=1 -unit.1.5.port.3.b.0.alias= -unit.1.5.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.5.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.b.0.name=TriggerPort3 -unit.1.5.port.3.b.0.orderindex=-1 -unit.1.5.port.3.b.0.radix=Hex -unit.1.5.port.3.b.0.signedOffset=0.0 -unit.1.5.port.3.b.0.signedPrecision=0 -unit.1.5.port.3.b.0.signedScaleFactor=1.0 -unit.1.5.port.3.b.0.unsignedOffset=0.0 -unit.1.5.port.3.b.0.unsignedPrecision=0 -unit.1.5.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.5.port.3.b.0.visible=1 -unit.1.5.port.3.buscount=1 -unit.1.5.port.3.channelcount=32 -unit.1.5.port.3.s.0.alias= -unit.1.5.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.0.name=TriggerPort3[0] -unit.1.5.port.3.s.0.orderindex=-1 -unit.1.5.port.3.s.0.visible=1 -unit.1.5.port.3.s.1.alias= -unit.1.5.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.1.name=TriggerPort3[1] -unit.1.5.port.3.s.1.orderindex=-1 -unit.1.5.port.3.s.1.visible=1 -unit.1.5.port.3.s.10.alias= -unit.1.5.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.10.name=TriggerPort3[10] -unit.1.5.port.3.s.10.orderindex=-1 -unit.1.5.port.3.s.10.visible=1 -unit.1.5.port.3.s.11.alias= -unit.1.5.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.11.name=TriggerPort3[11] -unit.1.5.port.3.s.11.orderindex=-1 -unit.1.5.port.3.s.11.visible=1 -unit.1.5.port.3.s.12.alias= -unit.1.5.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.12.name=TriggerPort3[12] -unit.1.5.port.3.s.12.orderindex=-1 -unit.1.5.port.3.s.12.visible=1 -unit.1.5.port.3.s.13.alias= -unit.1.5.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.13.name=TriggerPort3[13] -unit.1.5.port.3.s.13.orderindex=-1 -unit.1.5.port.3.s.13.visible=1 -unit.1.5.port.3.s.14.alias= -unit.1.5.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.14.name=TriggerPort3[14] -unit.1.5.port.3.s.14.orderindex=-1 -unit.1.5.port.3.s.14.visible=1 -unit.1.5.port.3.s.15.alias= -unit.1.5.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.15.name=TriggerPort3[15] -unit.1.5.port.3.s.15.orderindex=-1 -unit.1.5.port.3.s.15.visible=1 -unit.1.5.port.3.s.16.alias= -unit.1.5.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.16.name=TriggerPort3[16] -unit.1.5.port.3.s.16.orderindex=-1 -unit.1.5.port.3.s.16.visible=1 -unit.1.5.port.3.s.17.alias= -unit.1.5.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.17.name=TriggerPort3[17] -unit.1.5.port.3.s.17.orderindex=-1 -unit.1.5.port.3.s.17.visible=1 -unit.1.5.port.3.s.18.alias= -unit.1.5.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.18.name=TriggerPort3[18] -unit.1.5.port.3.s.18.orderindex=-1 -unit.1.5.port.3.s.18.visible=1 -unit.1.5.port.3.s.19.alias= -unit.1.5.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.19.name=TriggerPort3[19] -unit.1.5.port.3.s.19.orderindex=-1 -unit.1.5.port.3.s.19.visible=1 -unit.1.5.port.3.s.2.alias= -unit.1.5.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.2.name=TriggerPort3[2] -unit.1.5.port.3.s.2.orderindex=-1 -unit.1.5.port.3.s.2.visible=1 -unit.1.5.port.3.s.20.alias= -unit.1.5.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.20.name=TriggerPort3[20] -unit.1.5.port.3.s.20.orderindex=-1 -unit.1.5.port.3.s.20.visible=1 -unit.1.5.port.3.s.21.alias= -unit.1.5.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.21.name=TriggerPort3[21] -unit.1.5.port.3.s.21.orderindex=-1 -unit.1.5.port.3.s.21.visible=1 -unit.1.5.port.3.s.22.alias= -unit.1.5.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.22.name=TriggerPort3[22] -unit.1.5.port.3.s.22.orderindex=-1 -unit.1.5.port.3.s.22.visible=1 -unit.1.5.port.3.s.23.alias= -unit.1.5.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.23.name=TriggerPort3[23] -unit.1.5.port.3.s.23.orderindex=-1 -unit.1.5.port.3.s.23.visible=1 -unit.1.5.port.3.s.24.alias= -unit.1.5.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.24.name=TriggerPort3[24] -unit.1.5.port.3.s.24.orderindex=-1 -unit.1.5.port.3.s.24.visible=1 -unit.1.5.port.3.s.25.alias= -unit.1.5.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.25.name=TriggerPort3[25] -unit.1.5.port.3.s.25.orderindex=-1 -unit.1.5.port.3.s.25.visible=1 -unit.1.5.port.3.s.26.alias= -unit.1.5.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.26.name=TriggerPort3[26] -unit.1.5.port.3.s.26.orderindex=-1 -unit.1.5.port.3.s.26.visible=1 -unit.1.5.port.3.s.27.alias= -unit.1.5.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.27.name=TriggerPort3[27] -unit.1.5.port.3.s.27.orderindex=-1 -unit.1.5.port.3.s.27.visible=1 -unit.1.5.port.3.s.28.alias= -unit.1.5.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.28.name=TriggerPort3[28] -unit.1.5.port.3.s.28.orderindex=-1 -unit.1.5.port.3.s.28.visible=1 -unit.1.5.port.3.s.29.alias= -unit.1.5.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.29.name=TriggerPort3[29] -unit.1.5.port.3.s.29.orderindex=-1 -unit.1.5.port.3.s.29.visible=1 -unit.1.5.port.3.s.3.alias= -unit.1.5.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.3.name=TriggerPort3[3] -unit.1.5.port.3.s.3.orderindex=-1 -unit.1.5.port.3.s.3.visible=1 -unit.1.5.port.3.s.30.alias= -unit.1.5.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.30.name=TriggerPort3[30] -unit.1.5.port.3.s.30.orderindex=-1 -unit.1.5.port.3.s.30.visible=1 -unit.1.5.port.3.s.31.alias= -unit.1.5.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.31.name=TriggerPort3[31] -unit.1.5.port.3.s.31.orderindex=-1 -unit.1.5.port.3.s.31.visible=1 -unit.1.5.port.3.s.4.alias= -unit.1.5.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.4.name=TriggerPort3[4] -unit.1.5.port.3.s.4.orderindex=-1 -unit.1.5.port.3.s.4.visible=1 -unit.1.5.port.3.s.5.alias= -unit.1.5.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.5.name=TriggerPort3[5] -unit.1.5.port.3.s.5.orderindex=-1 -unit.1.5.port.3.s.5.visible=1 -unit.1.5.port.3.s.6.alias= -unit.1.5.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.6.name=TriggerPort3[6] -unit.1.5.port.3.s.6.orderindex=-1 -unit.1.5.port.3.s.6.visible=1 -unit.1.5.port.3.s.7.alias= -unit.1.5.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.7.name=TriggerPort3[7] -unit.1.5.port.3.s.7.orderindex=-1 -unit.1.5.port.3.s.7.visible=1 -unit.1.5.port.3.s.8.alias= -unit.1.5.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.8.name=TriggerPort3[8] -unit.1.5.port.3.s.8.orderindex=-1 -unit.1.5.port.3.s.8.visible=1 -unit.1.5.port.3.s.9.alias= -unit.1.5.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.5.port.3.s.9.name=TriggerPort3[9] -unit.1.5.port.3.s.9.orderindex=-1 -unit.1.5.port.3.s.9.visible=1 -unit.1.5.portcount=4 -unit.1.5.rep_trigger.clobber=1 -unit.1.5.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch -unit.1.5.rep_trigger.filename=waveform -unit.1.5.rep_trigger.format=ASCII -unit.1.5.rep_trigger.loggingEnabled=0 -unit.1.5.rep_trigger.signals=All Signals/Buses -unit.1.5.samplesPerTrigger=1 -unit.1.5.triggerCapture=1 -unit.1.5.triggerNSamplesTS=0 -unit.1.5.triggerPosition=0 -unit.1.5.triggerWindowCount=1 -unit.1.5.triggerWindowDepth=512 -unit.1.5.triggerWindowTS=0 -unit.1.5.username=MyILA5 -unit.1.5.waveform.count=21 -unit.1.5.waveform.posn.0.channel=2147483646 -unit.1.5.waveform.posn.0.name=memc_cmd_addr(15 downto 0) -unit.1.5.waveform.posn.0.radix=1 -unit.1.5.waveform.posn.0.type=bus -unit.1.5.waveform.posn.1.channel=2147483646 -unit.1.5.waveform.posn.1.name=memc_wr_data(207 downto 192) -unit.1.5.waveform.posn.1.radix=3 -unit.1.5.waveform.posn.1.type=bus -unit.1.5.waveform.posn.10.channel=2147483646 -unit.1.5.waveform.posn.10.name=clk_200mhz_rstn -unit.1.5.waveform.posn.10.radix=1 -unit.1.5.waveform.posn.10.type=bus -unit.1.5.waveform.posn.100.channel=2147483646 -unit.1.5.waveform.posn.100.name=memc_wr_rdy -unit.1.5.waveform.posn.100.radix=1 -unit.1.5.waveform.posn.100.type=bus -unit.1.5.waveform.posn.101.channel=2147483646 -unit.1.5.waveform.posn.101.name=memc_wr_rdy -unit.1.5.waveform.posn.101.radix=1 -unit.1.5.waveform.posn.101.type=bus -unit.1.5.waveform.posn.102.channel=2147483646 -unit.1.5.waveform.posn.102.name=memc_wr_rdy -unit.1.5.waveform.posn.102.radix=1 -unit.1.5.waveform.posn.102.type=bus -unit.1.5.waveform.posn.103.channel=2147483646 -unit.1.5.waveform.posn.103.name=memc_wr_rdy -unit.1.5.waveform.posn.103.radix=1 -unit.1.5.waveform.posn.103.type=bus -unit.1.5.waveform.posn.104.channel=2147483646 -unit.1.5.waveform.posn.104.name=memc_wr_rdy -unit.1.5.waveform.posn.104.radix=1 -unit.1.5.waveform.posn.104.type=bus -unit.1.5.waveform.posn.105.channel=2147483646 -unit.1.5.waveform.posn.105.name=memc_wr_rdy -unit.1.5.waveform.posn.105.radix=1 -unit.1.5.waveform.posn.105.type=bus -unit.1.5.waveform.posn.106.channel=2147483646 -unit.1.5.waveform.posn.106.name=memc_wr_rdy -unit.1.5.waveform.posn.106.radix=1 -unit.1.5.waveform.posn.106.type=bus -unit.1.5.waveform.posn.107.channel=2147483646 -unit.1.5.waveform.posn.107.name=memc_wr_rdy -unit.1.5.waveform.posn.107.radix=1 -unit.1.5.waveform.posn.107.type=bus -unit.1.5.waveform.posn.108.channel=2147483646 -unit.1.5.waveform.posn.108.name=memc_wr_rdy -unit.1.5.waveform.posn.108.radix=1 -unit.1.5.waveform.posn.108.type=bus -unit.1.5.waveform.posn.109.channel=2147483646 -unit.1.5.waveform.posn.109.name=memc_wr_rdy -unit.1.5.waveform.posn.109.radix=1 -unit.1.5.waveform.posn.109.type=bus -unit.1.5.waveform.posn.11.channel=2147483646 -unit.1.5.waveform.posn.11.name=memc_ui_rst -unit.1.5.waveform.posn.11.radix=1 -unit.1.5.waveform.posn.11.type=bus -unit.1.5.waveform.posn.110.channel=2147483646 -unit.1.5.waveform.posn.110.name=memc_wr_rdy -unit.1.5.waveform.posn.110.radix=1 -unit.1.5.waveform.posn.110.type=bus -unit.1.5.waveform.posn.12.channel=2147483646 -unit.1.5.waveform.posn.12.name=memarb_acc_gnt -unit.1.5.waveform.posn.12.radix=1 -unit.1.5.waveform.posn.12.type=bus -unit.1.5.waveform.posn.13.channel=2147483646 -unit.1.5.waveform.posn.13.name=memarb_acc_req -unit.1.5.waveform.posn.13.radix=1 -unit.1.5.waveform.posn.13.type=bus -unit.1.5.waveform.posn.14.channel=2147483646 -unit.1.5.waveform.posn.14.name=memc_cmd_en -unit.1.5.waveform.posn.14.radix=1 -unit.1.5.waveform.posn.14.type=bus -unit.1.5.waveform.posn.15.channel=2147483646 -unit.1.5.waveform.posn.15.name=memc_cmd_instr -unit.1.5.waveform.posn.15.radix=1 -unit.1.5.waveform.posn.15.type=bus -unit.1.5.waveform.posn.16.channel=2147483646 -unit.1.5.waveform.posn.16.name=memc_cmd_rdy -unit.1.5.waveform.posn.16.radix=1 -unit.1.5.waveform.posn.16.type=bus -unit.1.5.waveform.posn.17.channel=2147483646 -unit.1.5.waveform.posn.17.name=memc_wr_en -unit.1.5.waveform.posn.17.radix=1 -unit.1.5.waveform.posn.17.type=bus -unit.1.5.waveform.posn.18.channel=2147483646 -unit.1.5.waveform.posn.18.name=memc_wr_end -unit.1.5.waveform.posn.18.radix=1 -unit.1.5.waveform.posn.18.type=bus -unit.1.5.waveform.posn.19.channel=2147483646 -unit.1.5.waveform.posn.19.name=memc_wr_mask -unit.1.5.waveform.posn.19.radix=1 -unit.1.5.waveform.posn.19.type=bus -unit.1.5.waveform.posn.2.channel=2147483646 -unit.1.5.waveform.posn.2.name=memc_wr_data(143 downto 128) -unit.1.5.waveform.posn.2.radix=3 -unit.1.5.waveform.posn.2.type=bus -unit.1.5.waveform.posn.20.channel=2147483646 -unit.1.5.waveform.posn.20.name=memc_wr_rdy -unit.1.5.waveform.posn.20.radix=1 -unit.1.5.waveform.posn.20.type=bus -unit.1.5.waveform.posn.21.channel=2147483646 -unit.1.5.waveform.posn.21.name=memc_wr_rdy -unit.1.5.waveform.posn.21.radix=1 -unit.1.5.waveform.posn.21.type=bus -unit.1.5.waveform.posn.22.channel=2147483646 -unit.1.5.waveform.posn.22.name=memc_wr_rdy -unit.1.5.waveform.posn.22.radix=1 -unit.1.5.waveform.posn.22.type=bus -unit.1.5.waveform.posn.23.channel=2147483646 -unit.1.5.waveform.posn.23.name=memc_wr_rdy -unit.1.5.waveform.posn.23.radix=1 -unit.1.5.waveform.posn.23.type=bus -unit.1.5.waveform.posn.24.channel=2147483646 -unit.1.5.waveform.posn.24.name=memc_wr_rdy -unit.1.5.waveform.posn.24.radix=1 -unit.1.5.waveform.posn.24.type=bus -unit.1.5.waveform.posn.25.channel=2147483646 -unit.1.5.waveform.posn.25.name=memc_wr_rdy -unit.1.5.waveform.posn.25.radix=1 -unit.1.5.waveform.posn.25.type=bus -unit.1.5.waveform.posn.26.channel=2147483646 -unit.1.5.waveform.posn.26.name=memc_wr_rdy -unit.1.5.waveform.posn.26.radix=1 -unit.1.5.waveform.posn.26.type=bus -unit.1.5.waveform.posn.27.channel=2147483646 -unit.1.5.waveform.posn.27.name=memc_wr_rdy -unit.1.5.waveform.posn.27.radix=1 -unit.1.5.waveform.posn.27.type=bus -unit.1.5.waveform.posn.28.channel=2147483646 -unit.1.5.waveform.posn.28.name=memc_wr_rdy -unit.1.5.waveform.posn.28.radix=1 -unit.1.5.waveform.posn.28.type=bus -unit.1.5.waveform.posn.29.channel=2147483646 -unit.1.5.waveform.posn.29.name=memc_wr_rdy -unit.1.5.waveform.posn.29.radix=1 -unit.1.5.waveform.posn.29.type=bus -unit.1.5.waveform.posn.3.channel=2147483646 -unit.1.5.waveform.posn.3.name=memc_wr_data(79 downto 64) -unit.1.5.waveform.posn.3.radix=3 -unit.1.5.waveform.posn.3.type=bus -unit.1.5.waveform.posn.30.channel=2147483646 -unit.1.5.waveform.posn.30.name=memc_wr_rdy -unit.1.5.waveform.posn.30.radix=1 -unit.1.5.waveform.posn.30.type=bus -unit.1.5.waveform.posn.31.channel=2147483646 -unit.1.5.waveform.posn.31.name=memc_wr_rdy -unit.1.5.waveform.posn.31.radix=1 -unit.1.5.waveform.posn.31.type=bus -unit.1.5.waveform.posn.32.channel=2147483646 -unit.1.5.waveform.posn.32.name=memc_wr_rdy -unit.1.5.waveform.posn.32.radix=1 -unit.1.5.waveform.posn.32.type=bus -unit.1.5.waveform.posn.33.channel=2147483646 -unit.1.5.waveform.posn.33.name=memc_wr_rdy -unit.1.5.waveform.posn.33.radix=1 -unit.1.5.waveform.posn.33.type=bus -unit.1.5.waveform.posn.34.channel=2147483646 -unit.1.5.waveform.posn.34.name=memc_wr_rdy -unit.1.5.waveform.posn.34.radix=1 -unit.1.5.waveform.posn.34.type=bus -unit.1.5.waveform.posn.35.channel=2147483646 -unit.1.5.waveform.posn.35.name=memc_wr_rdy -unit.1.5.waveform.posn.35.radix=1 -unit.1.5.waveform.posn.35.type=bus -unit.1.5.waveform.posn.36.channel=2147483646 -unit.1.5.waveform.posn.36.name=memc_wr_rdy -unit.1.5.waveform.posn.36.radix=1 -unit.1.5.waveform.posn.36.type=bus -unit.1.5.waveform.posn.37.channel=2147483646 -unit.1.5.waveform.posn.37.name=memc_wr_rdy -unit.1.5.waveform.posn.37.radix=1 -unit.1.5.waveform.posn.37.type=bus -unit.1.5.waveform.posn.38.channel=2147483646 -unit.1.5.waveform.posn.38.name=memc_wr_rdy -unit.1.5.waveform.posn.38.radix=1 -unit.1.5.waveform.posn.38.type=bus -unit.1.5.waveform.posn.39.channel=2147483646 -unit.1.5.waveform.posn.39.name=memc_wr_rdy -unit.1.5.waveform.posn.39.radix=1 -unit.1.5.waveform.posn.39.type=bus -unit.1.5.waveform.posn.4.channel=2147483646 -unit.1.5.waveform.posn.4.name=memc_wr_data(15 downto 0) -unit.1.5.waveform.posn.4.radix=3 -unit.1.5.waveform.posn.4.type=bus -unit.1.5.waveform.posn.40.channel=2147483646 -unit.1.5.waveform.posn.40.name=memc_wr_rdy -unit.1.5.waveform.posn.40.radix=1 -unit.1.5.waveform.posn.40.type=bus -unit.1.5.waveform.posn.41.channel=2147483646 -unit.1.5.waveform.posn.41.name=memc_wr_rdy -unit.1.5.waveform.posn.41.radix=1 -unit.1.5.waveform.posn.41.type=bus -unit.1.5.waveform.posn.42.channel=2147483646 -unit.1.5.waveform.posn.42.name=memc_wr_rdy -unit.1.5.waveform.posn.42.radix=1 -unit.1.5.waveform.posn.42.type=bus -unit.1.5.waveform.posn.43.channel=2147483646 -unit.1.5.waveform.posn.43.name=memc_wr_rdy -unit.1.5.waveform.posn.43.radix=1 -unit.1.5.waveform.posn.43.type=bus -unit.1.5.waveform.posn.44.channel=2147483646 -unit.1.5.waveform.posn.44.name=memc_wr_rdy -unit.1.5.waveform.posn.44.radix=1 -unit.1.5.waveform.posn.44.type=bus -unit.1.5.waveform.posn.45.channel=2147483646 -unit.1.5.waveform.posn.45.name=memc_wr_rdy -unit.1.5.waveform.posn.45.radix=1 -unit.1.5.waveform.posn.45.type=bus -unit.1.5.waveform.posn.46.channel=2147483646 -unit.1.5.waveform.posn.46.name=memc_wr_rdy -unit.1.5.waveform.posn.46.radix=1 -unit.1.5.waveform.posn.46.type=bus -unit.1.5.waveform.posn.47.channel=2147483646 -unit.1.5.waveform.posn.47.name=memc_wr_rdy -unit.1.5.waveform.posn.47.radix=1 -unit.1.5.waveform.posn.47.type=bus -unit.1.5.waveform.posn.48.channel=2147483646 -unit.1.5.waveform.posn.48.name=memc_wr_rdy -unit.1.5.waveform.posn.48.radix=1 -unit.1.5.waveform.posn.48.type=bus -unit.1.5.waveform.posn.49.channel=2147483646 -unit.1.5.waveform.posn.49.name=memc_wr_rdy -unit.1.5.waveform.posn.49.radix=1 -unit.1.5.waveform.posn.49.type=bus -unit.1.5.waveform.posn.5.channel=2147483646 -unit.1.5.waveform.posn.5.name=bpm_acq_ext_stall -unit.1.5.waveform.posn.5.radix=1 -unit.1.5.waveform.posn.5.type=bus -unit.1.5.waveform.posn.50.channel=2147483646 -unit.1.5.waveform.posn.50.name=memc_wr_rdy -unit.1.5.waveform.posn.50.radix=1 -unit.1.5.waveform.posn.50.type=bus -unit.1.5.waveform.posn.51.channel=2147483646 -unit.1.5.waveform.posn.51.name=memc_wr_rdy -unit.1.5.waveform.posn.51.radix=1 -unit.1.5.waveform.posn.51.type=bus -unit.1.5.waveform.posn.52.channel=2147483646 -unit.1.5.waveform.posn.52.name=memc_wr_rdy -unit.1.5.waveform.posn.52.radix=1 -unit.1.5.waveform.posn.52.type=bus -unit.1.5.waveform.posn.53.channel=2147483646 -unit.1.5.waveform.posn.53.name=memc_wr_rdy -unit.1.5.waveform.posn.53.radix=1 -unit.1.5.waveform.posn.53.type=bus -unit.1.5.waveform.posn.54.channel=2147483646 -unit.1.5.waveform.posn.54.name=memc_wr_rdy -unit.1.5.waveform.posn.54.radix=1 -unit.1.5.waveform.posn.54.type=bus -unit.1.5.waveform.posn.55.channel=2147483646 -unit.1.5.waveform.posn.55.name=memc_wr_rdy -unit.1.5.waveform.posn.55.radix=1 -unit.1.5.waveform.posn.55.type=bus -unit.1.5.waveform.posn.56.channel=2147483646 -unit.1.5.waveform.posn.56.name=memc_wr_rdy -unit.1.5.waveform.posn.56.radix=1 -unit.1.5.waveform.posn.56.type=bus -unit.1.5.waveform.posn.57.channel=2147483646 -unit.1.5.waveform.posn.57.name=memc_wr_rdy -unit.1.5.waveform.posn.57.radix=1 -unit.1.5.waveform.posn.57.type=bus -unit.1.5.waveform.posn.58.channel=2147483646 -unit.1.5.waveform.posn.58.name=memc_wr_rdy -unit.1.5.waveform.posn.58.radix=1 -unit.1.5.waveform.posn.58.type=bus -unit.1.5.waveform.posn.59.channel=2147483646 -unit.1.5.waveform.posn.59.name=memc_wr_rdy -unit.1.5.waveform.posn.59.radix=1 -unit.1.5.waveform.posn.59.type=bus -unit.1.5.waveform.posn.6.channel=2147483646 -unit.1.5.waveform.posn.6.name=bpm_acq_ext_dreq -unit.1.5.waveform.posn.6.radix=1 -unit.1.5.waveform.posn.6.type=bus -unit.1.5.waveform.posn.60.channel=2147483646 -unit.1.5.waveform.posn.60.name=memc_wr_rdy -unit.1.5.waveform.posn.60.radix=1 -unit.1.5.waveform.posn.60.type=bus -unit.1.5.waveform.posn.61.channel=2147483646 -unit.1.5.waveform.posn.61.name=memc_wr_rdy -unit.1.5.waveform.posn.61.radix=1 -unit.1.5.waveform.posn.61.type=bus -unit.1.5.waveform.posn.62.channel=2147483646 -unit.1.5.waveform.posn.62.name=memc_wr_rdy -unit.1.5.waveform.posn.62.radix=1 -unit.1.5.waveform.posn.62.type=bus -unit.1.5.waveform.posn.63.channel=2147483646 -unit.1.5.waveform.posn.63.name=memc_wr_rdy -unit.1.5.waveform.posn.63.radix=1 -unit.1.5.waveform.posn.63.type=bus -unit.1.5.waveform.posn.64.channel=2147483646 -unit.1.5.waveform.posn.64.name=memc_wr_rdy -unit.1.5.waveform.posn.64.radix=1 -unit.1.5.waveform.posn.64.type=bus -unit.1.5.waveform.posn.65.channel=2147483646 -unit.1.5.waveform.posn.65.name=memc_wr_rdy -unit.1.5.waveform.posn.65.radix=1 -unit.1.5.waveform.posn.65.type=bus -unit.1.5.waveform.posn.66.channel=2147483646 -unit.1.5.waveform.posn.66.name=memc_wr_rdy -unit.1.5.waveform.posn.66.radix=1 -unit.1.5.waveform.posn.66.type=bus -unit.1.5.waveform.posn.67.channel=2147483646 -unit.1.5.waveform.posn.67.name=memc_wr_rdy -unit.1.5.waveform.posn.67.radix=1 -unit.1.5.waveform.posn.67.type=bus -unit.1.5.waveform.posn.68.channel=2147483646 -unit.1.5.waveform.posn.68.name=memc_wr_rdy -unit.1.5.waveform.posn.68.radix=1 -unit.1.5.waveform.posn.68.type=bus -unit.1.5.waveform.posn.69.channel=2147483646 -unit.1.5.waveform.posn.69.name=memc_wr_rdy -unit.1.5.waveform.posn.69.radix=1 -unit.1.5.waveform.posn.69.type=bus -unit.1.5.waveform.posn.7.channel=2147483646 -unit.1.5.waveform.posn.7.name=bpm_acq_ext_eof -unit.1.5.waveform.posn.7.radix=1 -unit.1.5.waveform.posn.7.type=bus -unit.1.5.waveform.posn.70.channel=2147483646 -unit.1.5.waveform.posn.70.name=memc_wr_rdy -unit.1.5.waveform.posn.70.radix=1 -unit.1.5.waveform.posn.70.type=bus -unit.1.5.waveform.posn.71.channel=2147483646 -unit.1.5.waveform.posn.71.name=memc_wr_rdy -unit.1.5.waveform.posn.71.radix=1 -unit.1.5.waveform.posn.71.type=bus -unit.1.5.waveform.posn.72.channel=2147483646 -unit.1.5.waveform.posn.72.name=memc_wr_rdy -unit.1.5.waveform.posn.72.radix=1 -unit.1.5.waveform.posn.72.type=bus -unit.1.5.waveform.posn.73.channel=2147483646 -unit.1.5.waveform.posn.73.name=memc_wr_rdy -unit.1.5.waveform.posn.73.radix=1 -unit.1.5.waveform.posn.73.type=bus -unit.1.5.waveform.posn.74.channel=2147483646 -unit.1.5.waveform.posn.74.name=memc_wr_rdy -unit.1.5.waveform.posn.74.radix=1 -unit.1.5.waveform.posn.74.type=bus -unit.1.5.waveform.posn.75.channel=2147483646 -unit.1.5.waveform.posn.75.name=memc_wr_rdy -unit.1.5.waveform.posn.75.radix=1 -unit.1.5.waveform.posn.75.type=bus -unit.1.5.waveform.posn.76.channel=2147483646 -unit.1.5.waveform.posn.76.name=memc_wr_rdy -unit.1.5.waveform.posn.76.radix=1 -unit.1.5.waveform.posn.76.type=bus -unit.1.5.waveform.posn.77.channel=2147483646 -unit.1.5.waveform.posn.77.name=memc_wr_rdy -unit.1.5.waveform.posn.77.radix=1 -unit.1.5.waveform.posn.77.type=bus -unit.1.5.waveform.posn.78.channel=2147483646 -unit.1.5.waveform.posn.78.name=memc_wr_rdy -unit.1.5.waveform.posn.78.radix=1 -unit.1.5.waveform.posn.78.type=bus -unit.1.5.waveform.posn.79.channel=2147483646 -unit.1.5.waveform.posn.79.name=memc_wr_rdy -unit.1.5.waveform.posn.79.radix=1 -unit.1.5.waveform.posn.79.type=bus -unit.1.5.waveform.posn.8.channel=2147483646 -unit.1.5.waveform.posn.8.name=bpm_acq_ext_sof -unit.1.5.waveform.posn.8.radix=1 -unit.1.5.waveform.posn.8.type=bus -unit.1.5.waveform.posn.80.channel=2147483646 -unit.1.5.waveform.posn.80.name=memc_wr_rdy -unit.1.5.waveform.posn.80.radix=1 -unit.1.5.waveform.posn.80.type=bus -unit.1.5.waveform.posn.81.channel=2147483646 -unit.1.5.waveform.posn.81.name=memc_wr_rdy -unit.1.5.waveform.posn.81.radix=1 -unit.1.5.waveform.posn.81.type=bus -unit.1.5.waveform.posn.82.channel=2147483646 -unit.1.5.waveform.posn.82.name=memc_wr_rdy -unit.1.5.waveform.posn.82.radix=1 -unit.1.5.waveform.posn.82.type=bus -unit.1.5.waveform.posn.83.channel=2147483646 -unit.1.5.waveform.posn.83.name=memc_wr_rdy -unit.1.5.waveform.posn.83.radix=1 -unit.1.5.waveform.posn.83.type=bus -unit.1.5.waveform.posn.84.channel=2147483646 -unit.1.5.waveform.posn.84.name=memc_wr_rdy -unit.1.5.waveform.posn.84.radix=1 -unit.1.5.waveform.posn.84.type=bus -unit.1.5.waveform.posn.85.channel=2147483646 -unit.1.5.waveform.posn.85.name=memc_wr_rdy -unit.1.5.waveform.posn.85.radix=1 -unit.1.5.waveform.posn.85.type=bus -unit.1.5.waveform.posn.86.channel=2147483646 -unit.1.5.waveform.posn.86.name=memc_wr_rdy -unit.1.5.waveform.posn.86.radix=1 -unit.1.5.waveform.posn.86.type=bus -unit.1.5.waveform.posn.87.channel=2147483646 -unit.1.5.waveform.posn.87.name=memc_wr_rdy -unit.1.5.waveform.posn.87.radix=1 -unit.1.5.waveform.posn.87.type=bus -unit.1.5.waveform.posn.88.channel=2147483646 -unit.1.5.waveform.posn.88.name=memc_wr_rdy -unit.1.5.waveform.posn.88.radix=1 -unit.1.5.waveform.posn.88.type=bus -unit.1.5.waveform.posn.89.channel=2147483646 -unit.1.5.waveform.posn.89.name=memc_wr_rdy -unit.1.5.waveform.posn.89.radix=1 -unit.1.5.waveform.posn.89.type=bus -unit.1.5.waveform.posn.9.channel=2147483646 -unit.1.5.waveform.posn.9.name=bpm_acq_ext_valid -unit.1.5.waveform.posn.9.radix=1 -unit.1.5.waveform.posn.9.type=bus -unit.1.5.waveform.posn.90.channel=2147483646 -unit.1.5.waveform.posn.90.name=memc_wr_rdy -unit.1.5.waveform.posn.90.radix=1 -unit.1.5.waveform.posn.90.type=bus -unit.1.5.waveform.posn.91.channel=2147483646 -unit.1.5.waveform.posn.91.name=memc_wr_rdy -unit.1.5.waveform.posn.91.radix=1 -unit.1.5.waveform.posn.91.type=bus -unit.1.5.waveform.posn.92.channel=2147483646 -unit.1.5.waveform.posn.92.name=memc_wr_rdy -unit.1.5.waveform.posn.92.radix=1 -unit.1.5.waveform.posn.92.type=bus -unit.1.5.waveform.posn.93.channel=2147483646 -unit.1.5.waveform.posn.93.name=memc_wr_rdy -unit.1.5.waveform.posn.93.radix=1 -unit.1.5.waveform.posn.93.type=bus -unit.1.5.waveform.posn.94.channel=2147483646 -unit.1.5.waveform.posn.94.name=memc_wr_rdy -unit.1.5.waveform.posn.94.radix=1 -unit.1.5.waveform.posn.94.type=bus -unit.1.5.waveform.posn.95.channel=2147483646 -unit.1.5.waveform.posn.95.name=memc_wr_rdy -unit.1.5.waveform.posn.95.radix=1 -unit.1.5.waveform.posn.95.type=bus -unit.1.5.waveform.posn.96.channel=2147483646 -unit.1.5.waveform.posn.96.name=memc_wr_rdy -unit.1.5.waveform.posn.96.radix=1 -unit.1.5.waveform.posn.96.type=bus -unit.1.5.waveform.posn.97.channel=2147483646 -unit.1.5.waveform.posn.97.name=memc_wr_rdy -unit.1.5.waveform.posn.97.radix=1 -unit.1.5.waveform.posn.97.type=bus -unit.1.5.waveform.posn.98.channel=2147483646 -unit.1.5.waveform.posn.98.name=memc_wr_rdy -unit.1.5.waveform.posn.98.radix=1 -unit.1.5.waveform.posn.98.type=bus -unit.1.5.waveform.posn.99.channel=2147483646 -unit.1.5.waveform.posn.99.name=memc_wr_rdy -unit.1.5.waveform.posn.99.radix=1 -unit.1.5.waveform.posn.99.type=bus diff --git a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/sys_pll.vhd deleted file mode 100644 index 036e6b5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/ml_605/dbe_bpm_fmc516/Manifest.py b/hdl/top/ml_605/dbe_bpm_fmc516/Manifest.py deleted file mode 100644 index 74f16aae..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc516/Manifest.py +++ /dev/null @@ -1,3 +0,0 @@ -files = [ "dbe_bpm_fmc516.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_bpm_fmc516.ucf" ]; - -modules = { "local" : ["../../.." ] }; diff --git a/hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj b/hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj deleted file mode 100644 index 306aecb0..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj +++ /dev/null @@ -1,6917 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Mon Jun 17 16:36:50 BRT 2013 -avoidUserRegDevice1=2,3,4 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109364250093 -mdiAreaHeight=0.7060773480662983 -mdiAreaHeightLast=0.6718232044198895 -mdiCount=10 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice2=1 -mdiDevice3=1 -mdiDevice4=1 -mdiDevice5=1 -mdiDevice6=1 -mdiDevice7=1 -mdiDevice8=1 -mdiDevice9=1 -mdiType0=5 -mdiType1=1 -mdiType2=2 -mdiType3=5 -mdiType4=0 -mdiType5=1 -mdiType6=0 -mdiType7=0 -mdiType8=0 -mdiType9=1 -mdiUnit0=1 -mdiUnit1=0 -mdiUnit2=0 -mdiUnit3=0 -mdiUnit4=1 -mdiUnit5=1 -mdiUnit6=0 -mdiUnit7=2 -mdiUnit8=3 -mdiUnit9=3 -navigatorHeight=0.1712707182320442 -navigatorHeightLast=0.1712707182320442 -navigatorWidth=0.17852684144818975 -navigatorWidthLast=0.17852684144818975 -signalDisplayPath=0 -unit.-1.-1.username= -unit.1.-1.coretype=SYSTEM MONITOR -unit.1.-1.port.-1.buscount=0 -unit.1.-1.port.-1.channelcount=0 -unit.1.-1.portcount=0 -unit.1.-1.username= -unit.1.0.0.HEIGHT0=0.4638365 -unit.1.0.0.TriggerRow0=1 -unit.1.0.0.TriggerRow1=1 -unit.1.0.0.TriggerRow2=1 -unit.1.0.0.WIDTH0=0.99769586 -unit.1.0.0.X0=0.0 -unit.1.0.0.Y0=0.0 -unit.1.0.1.HEIGHT1=0.5393082 -unit.1.0.1.WIDTH1=0.99769586 -unit.1.0.1.X1=0.0 -unit.1.0.1.Y1=0.3616352 -unit.1.0.2.HEIGHT2=0.3726415 -unit.1.0.2.WIDTH2=0.9239631 -unit.1.0.2.X2=0.07373272 -unit.1.0.2.Y2=0.5267296 -unit.1.0.5.HEIGHT5=0.8915094 -unit.1.0.5.WIDTH5=0.9485407 -unit.1.0.5.X5=0.049155146 -unit.1.0.5.Y5=0.007861636 -unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.0.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXX0XXXXXXXX -unit.1.0.MFBitsA3=XXXXXXXXXXXXXXXXXX01XXXXXXXXXXXX -unit.1.0.MFBitsB0=00000000000000000000000000000000 -unit.1.0.MFBitsB1=00000000000000000000000000000000 -unit.1.0.MFBitsB2=00000000000000000000000000000000 -unit.1.0.MFBitsB3=00000000000000000000000000000000 -unit.1.0.MFCompareA0=0 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-unit.1.0.port.-1.s.94.name=DataPort[94] -unit.1.0.port.-1.s.94.orderindex=-1 -unit.1.0.port.-1.s.94.visible=1 -unit.1.0.port.-1.s.95.alias= -unit.1.0.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.95.name=DataPort[95] -unit.1.0.port.-1.s.95.orderindex=-1 -unit.1.0.port.-1.s.95.visible=1 -unit.1.0.port.-1.s.96.alias= -unit.1.0.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.96.name=DataPort[96] -unit.1.0.port.-1.s.96.orderindex=-1 -unit.1.0.port.-1.s.96.visible=1 -unit.1.0.port.-1.s.97.alias= -unit.1.0.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.97.name=DataPort[97] -unit.1.0.port.-1.s.97.orderindex=-1 -unit.1.0.port.-1.s.97.visible=1 -unit.1.0.port.-1.s.98.alias= -unit.1.0.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.98.name=DataPort[98] -unit.1.0.port.-1.s.98.orderindex=-1 -unit.1.0.port.-1.s.98.visible=1 -unit.1.0.port.-1.s.99.alias= -unit.1.0.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.99.name=DataPort[99] -unit.1.0.port.-1.s.99.orderindex=-1 -unit.1.0.port.-1.s.99.visible=1 -unit.1.0.port.0.b.0.alias= -unit.1.0.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.b.0.name=TriggerPort0 -unit.1.0.port.0.b.0.orderindex=-1 -unit.1.0.port.0.b.0.radix=Hex -unit.1.0.port.0.b.0.signedOffset=0.0 -unit.1.0.port.0.b.0.signedPrecision=0 -unit.1.0.port.0.b.0.signedScaleFactor=1.0 -unit.1.0.port.0.b.0.unsignedOffset=0.0 -unit.1.0.port.0.b.0.unsignedPrecision=0 -unit.1.0.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.0.b.0.visible=1 -unit.1.0.port.0.buscount=1 -unit.1.0.port.0.channelcount=32 -unit.1.0.port.0.s.0.alias= -unit.1.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.0.name=TriggerPort0[0] -unit.1.0.port.0.s.0.orderindex=-1 -unit.1.0.port.0.s.0.visible=1 -unit.1.0.port.0.s.1.alias= -unit.1.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.1.name=TriggerPort0[1] -unit.1.0.port.0.s.1.orderindex=-1 -unit.1.0.port.0.s.1.visible=1 -unit.1.0.port.0.s.10.alias= -unit.1.0.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.10.name=TriggerPort0[10] -unit.1.0.port.0.s.10.orderindex=-1 -unit.1.0.port.0.s.10.visible=1 -unit.1.0.port.0.s.11.alias= -unit.1.0.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.11.name=TriggerPort0[11] -unit.1.0.port.0.s.11.orderindex=-1 -unit.1.0.port.0.s.11.visible=1 -unit.1.0.port.0.s.12.alias= -unit.1.0.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.12.name=TriggerPort0[12] -unit.1.0.port.0.s.12.orderindex=-1 -unit.1.0.port.0.s.12.visible=1 -unit.1.0.port.0.s.13.alias= -unit.1.0.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.13.name=TriggerPort0[13] -unit.1.0.port.0.s.13.orderindex=-1 -unit.1.0.port.0.s.13.visible=1 -unit.1.0.port.0.s.14.alias= -unit.1.0.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.14.name=TriggerPort0[14] -unit.1.0.port.0.s.14.orderindex=-1 -unit.1.0.port.0.s.14.visible=1 -unit.1.0.port.0.s.15.alias= -unit.1.0.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.15.name=TriggerPort0[15] -unit.1.0.port.0.s.15.orderindex=-1 -unit.1.0.port.0.s.15.visible=1 -unit.1.0.port.0.s.16.alias= -unit.1.0.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.16.name=TriggerPort0[16] -unit.1.0.port.0.s.16.orderindex=-1 -unit.1.0.port.0.s.16.visible=1 -unit.1.0.port.0.s.17.alias= -unit.1.0.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.17.name=TriggerPort0[17] -unit.1.0.port.0.s.17.orderindex=-1 -unit.1.0.port.0.s.17.visible=1 -unit.1.0.port.0.s.18.alias= -unit.1.0.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.18.name=TriggerPort0[18] -unit.1.0.port.0.s.18.orderindex=-1 -unit.1.0.port.0.s.18.visible=1 -unit.1.0.port.0.s.19.alias= -unit.1.0.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.19.name=TriggerPort0[19] -unit.1.0.port.0.s.19.orderindex=-1 -unit.1.0.port.0.s.19.visible=1 -unit.1.0.port.0.s.2.alias= -unit.1.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.2.name=TriggerPort0[2] -unit.1.0.port.0.s.2.orderindex=-1 -unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias=DataPort[43] -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias= -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias= -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias= -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= -unit.1.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.10.name=TriggerPort3[10] -unit.1.0.port.3.s.10.orderindex=-1 -unit.1.0.port.3.s.10.visible=1 -unit.1.0.port.3.s.11.alias= -unit.1.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.11.name=TriggerPort3[11] -unit.1.0.port.3.s.11.orderindex=-1 -unit.1.0.port.3.s.11.visible=1 -unit.1.0.port.3.s.12.alias= -unit.1.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.12.name=TriggerPort3[12] -unit.1.0.port.3.s.12.orderindex=-1 -unit.1.0.port.3.s.12.visible=1 -unit.1.0.port.3.s.13.alias= -unit.1.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.13.name=TriggerPort3[13] -unit.1.0.port.3.s.13.orderindex=-1 -unit.1.0.port.3.s.13.visible=1 -unit.1.0.port.3.s.14.alias= -unit.1.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.14.name=TriggerPort3[14] -unit.1.0.port.3.s.14.orderindex=-1 -unit.1.0.port.3.s.14.visible=1 -unit.1.0.port.3.s.15.alias= -unit.1.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.15.name=TriggerPort3[15] -unit.1.0.port.3.s.15.orderindex=-1 -unit.1.0.port.3.s.15.visible=1 -unit.1.0.port.3.s.16.alias= -unit.1.0.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.16.name=TriggerPort3[16] -unit.1.0.port.3.s.16.orderindex=-1 -unit.1.0.port.3.s.16.visible=1 -unit.1.0.port.3.s.17.alias= -unit.1.0.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.17.name=TriggerPort3[17] -unit.1.0.port.3.s.17.orderindex=-1 -unit.1.0.port.3.s.17.visible=1 -unit.1.0.port.3.s.18.alias= -unit.1.0.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.18.name=TriggerPort3[18] -unit.1.0.port.3.s.18.orderindex=-1 -unit.1.0.port.3.s.18.visible=1 -unit.1.0.port.3.s.19.alias= -unit.1.0.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.19.name=TriggerPort3[19] -unit.1.0.port.3.s.19.orderindex=-1 -unit.1.0.port.3.s.19.visible=1 -unit.1.0.port.3.s.2.alias= -unit.1.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.2.name=TriggerPort3[2] -unit.1.0.port.3.s.2.orderindex=-1 -unit.1.0.port.3.s.2.visible=1 -unit.1.0.port.3.s.20.alias= -unit.1.0.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.20.name=TriggerPort3[20] -unit.1.0.port.3.s.20.orderindex=-1 -unit.1.0.port.3.s.20.visible=1 -unit.1.0.port.3.s.21.alias= -unit.1.0.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.21.name=TriggerPort3[21] -unit.1.0.port.3.s.21.orderindex=-1 -unit.1.0.port.3.s.21.visible=1 -unit.1.0.port.3.s.22.alias= -unit.1.0.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.22.name=TriggerPort3[22] -unit.1.0.port.3.s.22.orderindex=-1 -unit.1.0.port.3.s.22.visible=1 -unit.1.0.port.3.s.23.alias= -unit.1.0.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.23.name=TriggerPort3[23] -unit.1.0.port.3.s.23.orderindex=-1 -unit.1.0.port.3.s.23.visible=1 -unit.1.0.port.3.s.24.alias= -unit.1.0.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.24.name=TriggerPort3[24] -unit.1.0.port.3.s.24.orderindex=-1 -unit.1.0.port.3.s.24.visible=1 -unit.1.0.port.3.s.25.alias= -unit.1.0.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.25.name=TriggerPort3[25] -unit.1.0.port.3.s.25.orderindex=-1 -unit.1.0.port.3.s.25.visible=1 -unit.1.0.port.3.s.26.alias= -unit.1.0.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.26.name=TriggerPort3[26] -unit.1.0.port.3.s.26.orderindex=-1 -unit.1.0.port.3.s.26.visible=1 -unit.1.0.port.3.s.27.alias= -unit.1.0.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.27.name=TriggerPort3[27] -unit.1.0.port.3.s.27.orderindex=-1 -unit.1.0.port.3.s.27.visible=1 -unit.1.0.port.3.s.28.alias= -unit.1.0.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.28.name=TriggerPort3[28] -unit.1.0.port.3.s.28.orderindex=-1 -unit.1.0.port.3.s.28.visible=1 -unit.1.0.port.3.s.29.alias= -unit.1.0.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.29.name=TriggerPort3[29] -unit.1.0.port.3.s.29.orderindex=-1 -unit.1.0.port.3.s.29.visible=1 -unit.1.0.port.3.s.3.alias= -unit.1.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.3.name=TriggerPort3[3] -unit.1.0.port.3.s.3.orderindex=-1 -unit.1.0.port.3.s.3.visible=1 -unit.1.0.port.3.s.30.alias= -unit.1.0.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=MyILA0 -unit.1.0.waveform.count=12 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=fmc516_ch1_data_load -unit.1.0.waveform.posn.0.radix=1 -unit.1.0.waveform.posn.0.type=bus -unit.1.0.waveform.posn.1.channel=2147483646 -unit.1.0.waveform.posn.1.name=fmc516_ch1_clk_dly -unit.1.0.waveform.posn.1.radix=4 -unit.1.0.waveform.posn.1.type=bus -unit.1.0.waveform.posn.10.channel=2147483646 -unit.1.0.waveform.posn.10.name=fmc_mmcm_lock -unit.1.0.waveform.posn.10.radix=1 -unit.1.0.waveform.posn.10.type=bus -unit.1.0.waveform.posn.100.channel=127 -unit.1.0.waveform.posn.100.name=DataPort[127] -unit.1.0.waveform.posn.100.type=signal -unit.1.0.waveform.posn.101.channel=127 -unit.1.0.waveform.posn.101.name=DataPort[127] -unit.1.0.waveform.posn.101.type=signal -unit.1.0.waveform.posn.102.channel=127 -unit.1.0.waveform.posn.102.name=DataPort[127] -unit.1.0.waveform.posn.102.type=signal -unit.1.0.waveform.posn.103.channel=127 -unit.1.0.waveform.posn.103.name=DataPort[127] -unit.1.0.waveform.posn.103.type=signal -unit.1.0.waveform.posn.104.channel=127 -unit.1.0.waveform.posn.104.name=DataPort[127] -unit.1.0.waveform.posn.104.type=signal -unit.1.0.waveform.posn.105.channel=127 -unit.1.0.waveform.posn.105.name=DataPort[127] -unit.1.0.waveform.posn.105.type=signal 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-unit.1.0.waveform.posn.112.name=DataPort[127] -unit.1.0.waveform.posn.112.type=signal -unit.1.0.waveform.posn.113.channel=127 -unit.1.0.waveform.posn.113.name=DataPort[127] -unit.1.0.waveform.posn.113.type=signal -unit.1.0.waveform.posn.114.channel=127 -unit.1.0.waveform.posn.114.name=DataPort[127] -unit.1.0.waveform.posn.114.type=signal -unit.1.0.waveform.posn.115.channel=127 -unit.1.0.waveform.posn.115.name=DataPort[127] -unit.1.0.waveform.posn.115.type=signal -unit.1.0.waveform.posn.116.channel=127 -unit.1.0.waveform.posn.116.name=DataPort[127] -unit.1.0.waveform.posn.116.type=signal -unit.1.0.waveform.posn.117.channel=127 -unit.1.0.waveform.posn.117.name=DataPort[127] -unit.1.0.waveform.posn.117.type=signal -unit.1.0.waveform.posn.118.channel=127 -unit.1.0.waveform.posn.118.name=DataPort[127] -unit.1.0.waveform.posn.118.type=signal -unit.1.0.waveform.posn.119.channel=127 -unit.1.0.waveform.posn.119.name=DataPort[127] -unit.1.0.waveform.posn.119.type=signal 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-unit.1.0.waveform.posn.4.name=fmc516_adc_ch2 -unit.1.0.waveform.posn.4.radix=3 -unit.1.0.waveform.posn.4.type=bus -unit.1.0.waveform.posn.5.channel=2147483646 -unit.1.0.waveform.posn.5.name=fmc516_debug_empty -unit.1.0.waveform.posn.5.radix=1 -unit.1.0.waveform.posn.5.type=bus -unit.1.0.waveform.posn.6.channel=2147483646 -unit.1.0.waveform.posn.6.name=fmc516_debug_dull -unit.1.0.waveform.posn.6.radix=1 -unit.1.0.waveform.posn.6.type=bus -unit.1.0.waveform.posn.7.channel=2147483646 -unit.1.0.waveform.posn.7.name=fmc516_debug_valid -unit.1.0.waveform.posn.7.radix=1 -unit.1.0.waveform.posn.7.type=bus -unit.1.0.waveform.posn.8.channel=2147483646 -unit.1.0.waveform.posn.8.name=fmc_adc_valid -unit.1.0.waveform.posn.8.radix=1 -unit.1.0.waveform.posn.8.type=bus -unit.1.0.waveform.posn.9.channel=2147483646 -unit.1.0.waveform.posn.9.name=fmc_lmk_lock -unit.1.0.waveform.posn.9.radix=1 -unit.1.0.waveform.posn.9.type=bus -unit.1.1.0.HEIGHT0=0.3710692 -unit.1.1.0.TriggerRow0=1 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-unit.1.1.MFDisplay0=0 -unit.1.1.MFDisplay1=0 -unit.1.1.MFDisplay2=0 -unit.1.1.MFDisplay3=0 -unit.1.1.MFEventType0=3 -unit.1.1.MFEventType1=3 -unit.1.1.MFEventType2=3 -unit.1.1.MFEventType3=3 -unit.1.1.RunMode=SINGLE RUN -unit.1.1.SQCondition=All Data -unit.1.1.SQContiguous0=0 -unit.1.1.SequencerOn=0 -unit.1.1.TCActive=0 -unit.1.1.TCAdvanced0=0 -unit.1.1.TCCondition0_0=M0 -unit.1.1.TCCondition0_1= -unit.1.1.TCConditionType0=0 -unit.1.1.TCCount=1 -unit.1.1.TCEventCount0=1 -unit.1.1.TCEventType0=3 -unit.1.1.TCName0=TriggerCondition0 -unit.1.1.TCOutputEnable0=0 -unit.1.1.TCOutputHigh0=1 -unit.1.1.TCOutputMode0=0 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=1 -unit.1.1.browser_tree_state=0 -unit.1.1.coretype=ILA -unit.1.1.eventCount0=1 -unit.1.1.eventCount1=1 -unit.1.1.eventCount2=1 -unit.1.1.eventCount3=1 -unit.1.1.plotBusColor0=-3407821 -unit.1.1.plotBusColor1=-16777092 -unit.1.1.plotBusCount=2 -unit.1.1.plotBusName0=fmc_adc_data_ch3 -unit.1.1.plotBusName1=fmc_adc_data_ch0 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-unit.1.1.port.-1.s.71.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.71.name=DataPort[71] -unit.1.1.port.-1.s.71.orderindex=-1 -unit.1.1.port.-1.s.71.visible=1 -unit.1.1.port.-1.s.72.alias= -unit.1.1.port.-1.s.72.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.72.name=DataPort[72] -unit.1.1.port.-1.s.72.orderindex=-1 -unit.1.1.port.-1.s.72.visible=1 -unit.1.1.port.-1.s.73.alias= -unit.1.1.port.-1.s.73.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.73.name=DataPort[73] -unit.1.1.port.-1.s.73.orderindex=-1 -unit.1.1.port.-1.s.73.visible=1 -unit.1.1.port.-1.s.74.alias= -unit.1.1.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.74.name=DataPort[74] -unit.1.1.port.-1.s.74.orderindex=-1 -unit.1.1.port.-1.s.74.visible=1 -unit.1.1.port.-1.s.75.alias= -unit.1.1.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.75.name=DataPort[75] -unit.1.1.port.-1.s.75.orderindex=-1 -unit.1.1.port.-1.s.75.visible=1 -unit.1.1.port.-1.s.76.alias= -unit.1.1.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.76.name=DataPort[76] -unit.1.1.port.-1.s.76.orderindex=-1 -unit.1.1.port.-1.s.76.visible=1 -unit.1.1.port.-1.s.77.alias= -unit.1.1.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.77.name=DataPort[77] -unit.1.1.port.-1.s.77.orderindex=-1 -unit.1.1.port.-1.s.77.visible=1 -unit.1.1.port.-1.s.78.alias= -unit.1.1.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.78.name=DataPort[78] -unit.1.1.port.-1.s.78.orderindex=-1 -unit.1.1.port.-1.s.78.visible=1 -unit.1.1.port.-1.s.79.alias= -unit.1.1.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.79.name=DataPort[79] -unit.1.1.port.-1.s.79.orderindex=-1 -unit.1.1.port.-1.s.79.visible=1 -unit.1.1.port.-1.s.8.alias= -unit.1.1.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.8.name=DataPort[8] -unit.1.1.port.-1.s.8.orderindex=-1 -unit.1.1.port.-1.s.8.visible=0 -unit.1.1.port.-1.s.80.alias= -unit.1.1.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.80.name=DataPort[80] -unit.1.1.port.-1.s.80.orderindex=-1 -unit.1.1.port.-1.s.80.visible=1 -unit.1.1.port.-1.s.81.alias= -unit.1.1.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.81.name=DataPort[81] -unit.1.1.port.-1.s.81.orderindex=-1 -unit.1.1.port.-1.s.81.visible=1 -unit.1.1.port.-1.s.82.alias= -unit.1.1.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.82.name=DataPort[82] -unit.1.1.port.-1.s.82.orderindex=-1 -unit.1.1.port.-1.s.82.visible=1 -unit.1.1.port.-1.s.83.alias= -unit.1.1.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.83.name=DataPort[83] -unit.1.1.port.-1.s.83.orderindex=-1 -unit.1.1.port.-1.s.83.visible=1 -unit.1.1.port.-1.s.84.alias= -unit.1.1.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.84.name=DataPort[84] -unit.1.1.port.-1.s.84.orderindex=-1 -unit.1.1.port.-1.s.84.visible=1 -unit.1.1.port.-1.s.85.alias= -unit.1.1.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.85.name=DataPort[85] -unit.1.1.port.-1.s.85.orderindex=-1 -unit.1.1.port.-1.s.85.visible=1 -unit.1.1.port.-1.s.86.alias= -unit.1.1.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.86.name=DataPort[86] -unit.1.1.port.-1.s.86.orderindex=-1 -unit.1.1.port.-1.s.86.visible=1 -unit.1.1.port.-1.s.87.alias= -unit.1.1.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.87.name=DataPort[87] -unit.1.1.port.-1.s.87.orderindex=-1 -unit.1.1.port.-1.s.87.visible=1 -unit.1.1.port.-1.s.88.alias= -unit.1.1.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.88.name=DataPort[88] -unit.1.1.port.-1.s.88.orderindex=-1 -unit.1.1.port.-1.s.88.visible=1 -unit.1.1.port.-1.s.89.alias= -unit.1.1.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.89.name=DataPort[89] -unit.1.1.port.-1.s.89.orderindex=-1 -unit.1.1.port.-1.s.89.visible=1 -unit.1.1.port.-1.s.9.alias= -unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=1 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=1 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=1 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=1 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=1 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=1 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=1 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=1 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=1 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=1 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=32 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias= -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 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-unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.portcount=4 -unit.1.1.rep_trigger.clobber=1 -unit.1.1.rep_trigger.dir=/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_fmc516 -unit.1.1.rep_trigger.filename=waveform -unit.1.1.rep_trigger.format=ASCII -unit.1.1.rep_trigger.loggingEnabled=0 -unit.1.1.rep_trigger.signals=All Signals/Buses -unit.1.1.samplesPerTrigger=1 -unit.1.1.triggerCapture=1 -unit.1.1.triggerNSamplesTS=0 -unit.1.1.triggerPosition=0 -unit.1.1.triggerWindowCount=1 -unit.1.1.triggerWindowDepth=4096 -unit.1.1.triggerWindowTS=0 -unit.1.1.username=MyILA1 -unit.1.1.waveform.count=98 -unit.1.1.waveform.posn.0.channel=2147483646 -unit.1.1.waveform.posn.0.name=fmc_adc_data_ch0 -unit.1.1.waveform.posn.0.radix=3 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-unit.1.1.waveform.posn.105.name=DataPort[127] -unit.1.1.waveform.posn.105.type=signal -unit.1.1.waveform.posn.106.channel=127 -unit.1.1.waveform.posn.106.name=DataPort[127] -unit.1.1.waveform.posn.106.type=signal -unit.1.1.waveform.posn.107.channel=127 -unit.1.1.waveform.posn.107.name=DataPort[127] -unit.1.1.waveform.posn.107.type=signal -unit.1.1.waveform.posn.108.channel=127 -unit.1.1.waveform.posn.108.name=DataPort[127] -unit.1.1.waveform.posn.108.type=signal -unit.1.1.waveform.posn.109.channel=127 -unit.1.1.waveform.posn.109.name=DataPort[127] -unit.1.1.waveform.posn.109.type=signal -unit.1.1.waveform.posn.11.channel=41 -unit.1.1.waveform.posn.11.name=DataPort[41] -unit.1.1.waveform.posn.11.type=signal -unit.1.1.waveform.posn.110.channel=127 -unit.1.1.waveform.posn.110.name=DataPort[127] -unit.1.1.waveform.posn.110.type=signal -unit.1.1.waveform.posn.111.channel=127 -unit.1.1.waveform.posn.111.name=DataPort[127] -unit.1.1.waveform.posn.111.type=signal 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-unit.1.1.waveform.posn.19.name=DataPort[49] -unit.1.1.waveform.posn.19.type=signal -unit.1.1.waveform.posn.2.channel=32 -unit.1.1.waveform.posn.2.name=DataPort[32] -unit.1.1.waveform.posn.2.type=signal -unit.1.1.waveform.posn.20.channel=50 -unit.1.1.waveform.posn.20.name=DataPort[50] -unit.1.1.waveform.posn.20.type=signal -unit.1.1.waveform.posn.21.channel=51 -unit.1.1.waveform.posn.21.name=DataPort[51] -unit.1.1.waveform.posn.21.type=signal -unit.1.1.waveform.posn.22.channel=52 -unit.1.1.waveform.posn.22.name=DataPort[52] -unit.1.1.waveform.posn.22.type=signal -unit.1.1.waveform.posn.23.channel=53 -unit.1.1.waveform.posn.23.name=DataPort[53] -unit.1.1.waveform.posn.23.type=signal -unit.1.1.waveform.posn.24.channel=54 -unit.1.1.waveform.posn.24.name=DataPort[54] -unit.1.1.waveform.posn.24.type=signal -unit.1.1.waveform.posn.25.channel=55 -unit.1.1.waveform.posn.25.name=DataPort[55] -unit.1.1.waveform.posn.25.type=signal -unit.1.1.waveform.posn.26.channel=56 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-unit.1.1.waveform.posn.62.name=DataPort[92] -unit.1.1.waveform.posn.62.type=signal -unit.1.1.waveform.posn.63.channel=93 -unit.1.1.waveform.posn.63.name=DataPort[93] -unit.1.1.waveform.posn.63.type=signal -unit.1.1.waveform.posn.64.channel=94 -unit.1.1.waveform.posn.64.name=DataPort[94] -unit.1.1.waveform.posn.64.type=signal -unit.1.1.waveform.posn.65.channel=95 -unit.1.1.waveform.posn.65.name=DataPort[95] -unit.1.1.waveform.posn.65.type=signal -unit.1.1.waveform.posn.66.channel=96 -unit.1.1.waveform.posn.66.name=DataPort[96] -unit.1.1.waveform.posn.66.type=signal -unit.1.1.waveform.posn.67.channel=97 -unit.1.1.waveform.posn.67.name=DataPort[97] -unit.1.1.waveform.posn.67.type=signal -unit.1.1.waveform.posn.68.channel=98 -unit.1.1.waveform.posn.68.name=DataPort[98] -unit.1.1.waveform.posn.68.type=signal -unit.1.1.waveform.posn.69.channel=99 -unit.1.1.waveform.posn.69.name=DataPort[99] -unit.1.1.waveform.posn.69.type=signal -unit.1.1.waveform.posn.7.channel=37 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-unit.1.1.waveform.posn.77.name=DataPort[107] -unit.1.1.waveform.posn.77.type=signal -unit.1.1.waveform.posn.78.channel=108 -unit.1.1.waveform.posn.78.name=DataPort[108] -unit.1.1.waveform.posn.78.type=signal -unit.1.1.waveform.posn.79.channel=109 -unit.1.1.waveform.posn.79.name=DataPort[109] -unit.1.1.waveform.posn.79.type=signal -unit.1.1.waveform.posn.8.channel=38 -unit.1.1.waveform.posn.8.name=DataPort[38] -unit.1.1.waveform.posn.8.type=signal -unit.1.1.waveform.posn.80.channel=110 -unit.1.1.waveform.posn.80.name=DataPort[110] -unit.1.1.waveform.posn.80.type=signal -unit.1.1.waveform.posn.81.channel=111 -unit.1.1.waveform.posn.81.name=DataPort[111] -unit.1.1.waveform.posn.81.type=signal -unit.1.1.waveform.posn.82.channel=112 -unit.1.1.waveform.posn.82.name=DataPort[112] -unit.1.1.waveform.posn.82.type=signal -unit.1.1.waveform.posn.83.channel=113 -unit.1.1.waveform.posn.83.name=DataPort[113] -unit.1.1.waveform.posn.83.type=signal -unit.1.1.waveform.posn.84.channel=114 -unit.1.1.waveform.posn.84.name=DataPort[114] -unit.1.1.waveform.posn.84.type=signal -unit.1.1.waveform.posn.85.channel=115 -unit.1.1.waveform.posn.85.name=DataPort[115] -unit.1.1.waveform.posn.85.type=signal -unit.1.1.waveform.posn.86.channel=116 -unit.1.1.waveform.posn.86.name=DataPort[116] -unit.1.1.waveform.posn.86.type=signal -unit.1.1.waveform.posn.87.channel=117 -unit.1.1.waveform.posn.87.name=DataPort[117] -unit.1.1.waveform.posn.87.type=signal -unit.1.1.waveform.posn.88.channel=118 -unit.1.1.waveform.posn.88.name=DataPort[118] -unit.1.1.waveform.posn.88.type=signal -unit.1.1.waveform.posn.89.channel=119 -unit.1.1.waveform.posn.89.name=DataPort[119] -unit.1.1.waveform.posn.89.type=signal -unit.1.1.waveform.posn.9.channel=39 -unit.1.1.waveform.posn.9.name=DataPort[39] -unit.1.1.waveform.posn.9.type=signal -unit.1.1.waveform.posn.90.channel=120 -unit.1.1.waveform.posn.90.name=DataPort[120] -unit.1.1.waveform.posn.90.type=signal -unit.1.1.waveform.posn.91.channel=121 -unit.1.1.waveform.posn.91.name=DataPort[121] -unit.1.1.waveform.posn.91.type=signal -unit.1.1.waveform.posn.92.channel=122 -unit.1.1.waveform.posn.92.name=DataPort[122] -unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=123 -unit.1.1.waveform.posn.93.name=DataPort[123] -unit.1.1.waveform.posn.93.type=signal -unit.1.1.waveform.posn.94.channel=124 -unit.1.1.waveform.posn.94.name=DataPort[124] -unit.1.1.waveform.posn.94.type=signal -unit.1.1.waveform.posn.95.channel=125 -unit.1.1.waveform.posn.95.name=DataPort[125] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=126 -unit.1.1.waveform.posn.96.name=DataPort[126] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal -unit.1.2.0.HEIGHT0=0.3710692 -unit.1.2.0.TriggerRow0=1 -unit.1.2.0.TriggerRow1=1 -unit.1.2.0.TriggerRow2=1 -unit.1.2.0.WIDTH0=0.9239631 -unit.1.2.0.X0=0.07373272 -unit.1.2.0.Y0=0.0 -unit.1.2.5.HEIGHT5=0.84889644 -unit.1.2.5.WIDTH5=0.8520801 -unit.1.2.5.X5=-0.062403698 -unit.1.2.5.Y5=0.22410867 -unit.1.2.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsA3=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -unit.1.2.MFBitsB0=00000000000000000000000000000000 -unit.1.2.MFBitsB1=00000000000000000000000000000000 -unit.1.2.MFBitsB2=00000000000000000000000000000000 -unit.1.2.MFBitsB3=00000000000000000000000000000000 -unit.1.2.MFCompareA0=0 -unit.1.2.MFCompareA1=0 -unit.1.2.MFCompareA2=0 -unit.1.2.MFCompareA3=0 -unit.1.2.MFCompareB0=999 -unit.1.2.MFCompareB1=999 -unit.1.2.MFCompareB2=999 -unit.1.2.MFCompareB3=999 -unit.1.2.MFCount=4 -unit.1.2.MFDisplay0=0 -unit.1.2.MFDisplay1=0 -unit.1.2.MFDisplay2=0 -unit.1.2.MFDisplay3=0 -unit.1.2.MFEventType0=3 -unit.1.2.MFEventType1=3 -unit.1.2.MFEventType2=3 -unit.1.2.MFEventType3=3 -unit.1.2.RunMode=SINGLE RUN -unit.1.2.SQCondition=All Data -unit.1.2.SQContiguous0=0 -unit.1.2.SequencerOn=0 -unit.1.2.TCActive=0 -unit.1.2.TCAdvanced0=0 -unit.1.2.TCCondition0_0=M0 -unit.1.2.TCCondition0_1= -unit.1.2.TCConditionType0=0 -unit.1.2.TCCount=1 -unit.1.2.TCEventCount0=1 -unit.1.2.TCEventType0=3 -unit.1.2.TCName0=TriggerCondition0 -unit.1.2.TCOutputEnable0=0 -unit.1.2.TCOutputHigh0=1 -unit.1.2.TCOutputMode0=0 -unit.1.2.coretype=ILA -unit.1.2.eventCount0=1 -unit.1.2.eventCount1=1 -unit.1.2.eventCount2=1 -unit.1.2.eventCount3=1 -unit.1.2.plotBusCount=0 -unit.1.2.plotBusX= -unit.1.2.plotBusY= -unit.1.2.plotDataTimeMode=1 -unit.1.2.plotDisplayMode=line -unit.1.2.plotMaxX=0.0 -unit.1.2.plotMaxY=0.0 -unit.1.2.plotMinX=0.0 -unit.1.2.plotMinY=0.0 -unit.1.2.plotSelectedBus=0 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-unit.1.2.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.82.name=DataPort[82] -unit.1.2.port.-1.s.82.orderindex=-1 -unit.1.2.port.-1.s.82.visible=1 -unit.1.2.port.-1.s.83.alias= -unit.1.2.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.83.name=DataPort[83] -unit.1.2.port.-1.s.83.orderindex=-1 -unit.1.2.port.-1.s.83.visible=1 -unit.1.2.port.-1.s.84.alias= -unit.1.2.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.84.name=DataPort[84] -unit.1.2.port.-1.s.84.orderindex=-1 -unit.1.2.port.-1.s.84.visible=1 -unit.1.2.port.-1.s.85.alias= -unit.1.2.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.85.name=DataPort[85] -unit.1.2.port.-1.s.85.orderindex=-1 -unit.1.2.port.-1.s.85.visible=1 -unit.1.2.port.-1.s.86.alias= -unit.1.2.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.86.name=DataPort[86] -unit.1.2.port.-1.s.86.orderindex=-1 -unit.1.2.port.-1.s.86.visible=1 -unit.1.2.port.-1.s.87.alias= -unit.1.2.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.87.name=DataPort[87] -unit.1.2.port.-1.s.87.orderindex=-1 -unit.1.2.port.-1.s.87.visible=1 -unit.1.2.port.-1.s.88.alias= -unit.1.2.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.88.name=DataPort[88] -unit.1.2.port.-1.s.88.orderindex=-1 -unit.1.2.port.-1.s.88.visible=1 -unit.1.2.port.-1.s.89.alias= -unit.1.2.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.89.name=DataPort[89] -unit.1.2.port.-1.s.89.orderindex=-1 -unit.1.2.port.-1.s.89.visible=1 -unit.1.2.port.-1.s.9.alias= -unit.1.2.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.9.name=DataPort[9] -unit.1.2.port.-1.s.9.orderindex=-1 -unit.1.2.port.-1.s.9.visible=1 -unit.1.2.port.-1.s.90.alias= -unit.1.2.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.90.name=DataPort[90] -unit.1.2.port.-1.s.90.orderindex=-1 -unit.1.2.port.-1.s.90.visible=1 -unit.1.2.port.-1.s.91.alias= -unit.1.2.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.91.name=DataPort[91] -unit.1.2.port.-1.s.91.orderindex=-1 -unit.1.2.port.-1.s.91.visible=1 -unit.1.2.port.-1.s.92.alias= -unit.1.2.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.92.name=DataPort[92] -unit.1.2.port.-1.s.92.orderindex=-1 -unit.1.2.port.-1.s.92.visible=1 -unit.1.2.port.-1.s.93.alias= -unit.1.2.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.93.name=DataPort[93] -unit.1.2.port.-1.s.93.orderindex=-1 -unit.1.2.port.-1.s.93.visible=1 -unit.1.2.port.-1.s.94.alias= -unit.1.2.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.94.name=DataPort[94] -unit.1.2.port.-1.s.94.orderindex=-1 -unit.1.2.port.-1.s.94.visible=1 -unit.1.2.port.-1.s.95.alias= -unit.1.2.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.95.name=DataPort[95] -unit.1.2.port.-1.s.95.orderindex=-1 -unit.1.2.port.-1.s.95.visible=1 -unit.1.2.port.-1.s.96.alias= -unit.1.2.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.96.name=DataPort[96] -unit.1.2.port.-1.s.96.orderindex=-1 -unit.1.2.port.-1.s.96.visible=1 -unit.1.2.port.-1.s.97.alias= -unit.1.2.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.97.name=DataPort[97] -unit.1.2.port.-1.s.97.orderindex=-1 -unit.1.2.port.-1.s.97.visible=1 -unit.1.2.port.-1.s.98.alias= -unit.1.2.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.98.name=DataPort[98] -unit.1.2.port.-1.s.98.orderindex=-1 -unit.1.2.port.-1.s.98.visible=1 -unit.1.2.port.-1.s.99.alias= -unit.1.2.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.-1.s.99.name=DataPort[99] -unit.1.2.port.-1.s.99.orderindex=-1 -unit.1.2.port.-1.s.99.visible=1 -unit.1.2.port.0.b.0.alias= -unit.1.2.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.b.0.name=TriggerPort0 -unit.1.2.port.0.b.0.orderindex=-1 -unit.1.2.port.0.b.0.radix=Hex -unit.1.2.port.0.b.0.signedOffset=0.0 -unit.1.2.port.0.b.0.signedPrecision=0 -unit.1.2.port.0.b.0.signedScaleFactor=1.0 -unit.1.2.port.0.b.0.unsignedOffset=0.0 -unit.1.2.port.0.b.0.unsignedPrecision=0 -unit.1.2.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.0.b.0.visible=1 -unit.1.2.port.0.buscount=1 -unit.1.2.port.0.channelcount=32 -unit.1.2.port.0.s.0.alias= -unit.1.2.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.0.name=TriggerPort0[0] -unit.1.2.port.0.s.0.orderindex=-1 -unit.1.2.port.0.s.0.visible=1 -unit.1.2.port.0.s.1.alias= -unit.1.2.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.1.name=TriggerPort0[1] -unit.1.2.port.0.s.1.orderindex=-1 -unit.1.2.port.0.s.1.visible=1 -unit.1.2.port.0.s.10.alias= -unit.1.2.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.10.name=TriggerPort0[10] -unit.1.2.port.0.s.10.orderindex=-1 -unit.1.2.port.0.s.10.visible=1 -unit.1.2.port.0.s.11.alias= -unit.1.2.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.11.name=TriggerPort0[11] -unit.1.2.port.0.s.11.orderindex=-1 -unit.1.2.port.0.s.11.visible=1 -unit.1.2.port.0.s.12.alias= -unit.1.2.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.12.name=TriggerPort0[12] -unit.1.2.port.0.s.12.orderindex=-1 -unit.1.2.port.0.s.12.visible=1 -unit.1.2.port.0.s.13.alias= -unit.1.2.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.13.name=TriggerPort0[13] -unit.1.2.port.0.s.13.orderindex=-1 -unit.1.2.port.0.s.13.visible=1 -unit.1.2.port.0.s.14.alias= -unit.1.2.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.14.name=TriggerPort0[14] -unit.1.2.port.0.s.14.orderindex=-1 -unit.1.2.port.0.s.14.visible=1 -unit.1.2.port.0.s.15.alias= -unit.1.2.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.15.name=TriggerPort0[15] -unit.1.2.port.0.s.15.orderindex=-1 -unit.1.2.port.0.s.15.visible=1 -unit.1.2.port.0.s.16.alias= -unit.1.2.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.16.name=TriggerPort0[16] -unit.1.2.port.0.s.16.orderindex=-1 -unit.1.2.port.0.s.16.visible=1 -unit.1.2.port.0.s.17.alias= -unit.1.2.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.17.name=TriggerPort0[17] -unit.1.2.port.0.s.17.orderindex=-1 -unit.1.2.port.0.s.17.visible=1 -unit.1.2.port.0.s.18.alias= -unit.1.2.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.18.name=TriggerPort0[18] -unit.1.2.port.0.s.18.orderindex=-1 -unit.1.2.port.0.s.18.visible=1 -unit.1.2.port.0.s.19.alias= -unit.1.2.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.19.name=TriggerPort0[19] -unit.1.2.port.0.s.19.orderindex=-1 -unit.1.2.port.0.s.19.visible=1 -unit.1.2.port.0.s.2.alias= -unit.1.2.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.2.name=TriggerPort0[2] -unit.1.2.port.0.s.2.orderindex=-1 -unit.1.2.port.0.s.2.visible=1 -unit.1.2.port.0.s.20.alias= -unit.1.2.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.20.name=TriggerPort0[20] -unit.1.2.port.0.s.20.orderindex=-1 -unit.1.2.port.0.s.20.visible=1 -unit.1.2.port.0.s.21.alias= -unit.1.2.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.21.name=TriggerPort0[21] -unit.1.2.port.0.s.21.orderindex=-1 -unit.1.2.port.0.s.21.visible=1 -unit.1.2.port.0.s.22.alias= -unit.1.2.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.22.name=TriggerPort0[22] -unit.1.2.port.0.s.22.orderindex=-1 -unit.1.2.port.0.s.22.visible=1 -unit.1.2.port.0.s.23.alias= -unit.1.2.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.23.name=TriggerPort0[23] -unit.1.2.port.0.s.23.orderindex=-1 -unit.1.2.port.0.s.23.visible=1 -unit.1.2.port.0.s.24.alias= -unit.1.2.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.24.name=TriggerPort0[24] -unit.1.2.port.0.s.24.orderindex=-1 -unit.1.2.port.0.s.24.visible=1 -unit.1.2.port.0.s.25.alias= -unit.1.2.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.25.name=TriggerPort0[25] -unit.1.2.port.0.s.25.orderindex=-1 -unit.1.2.port.0.s.25.visible=1 -unit.1.2.port.0.s.26.alias= -unit.1.2.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.26.name=TriggerPort0[26] -unit.1.2.port.0.s.26.orderindex=-1 -unit.1.2.port.0.s.26.visible=1 -unit.1.2.port.0.s.27.alias= -unit.1.2.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.27.name=TriggerPort0[27] -unit.1.2.port.0.s.27.orderindex=-1 -unit.1.2.port.0.s.27.visible=1 -unit.1.2.port.0.s.28.alias= -unit.1.2.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.28.name=TriggerPort0[28] -unit.1.2.port.0.s.28.orderindex=-1 -unit.1.2.port.0.s.28.visible=1 -unit.1.2.port.0.s.29.alias= -unit.1.2.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.29.name=TriggerPort0[29] -unit.1.2.port.0.s.29.orderindex=-1 -unit.1.2.port.0.s.29.visible=1 -unit.1.2.port.0.s.3.alias= -unit.1.2.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.3.name=TriggerPort0[3] -unit.1.2.port.0.s.3.orderindex=-1 -unit.1.2.port.0.s.3.visible=1 -unit.1.2.port.0.s.30.alias= -unit.1.2.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.30.name=TriggerPort0[30] -unit.1.2.port.0.s.30.orderindex=-1 -unit.1.2.port.0.s.30.visible=1 -unit.1.2.port.0.s.31.alias= -unit.1.2.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.31.name=TriggerPort0[31] -unit.1.2.port.0.s.31.orderindex=-1 -unit.1.2.port.0.s.31.visible=1 -unit.1.2.port.0.s.4.alias= -unit.1.2.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.4.name=TriggerPort0[4] -unit.1.2.port.0.s.4.orderindex=-1 -unit.1.2.port.0.s.4.visible=1 -unit.1.2.port.0.s.5.alias= -unit.1.2.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.5.name=TriggerPort0[5] -unit.1.2.port.0.s.5.orderindex=-1 -unit.1.2.port.0.s.5.visible=1 -unit.1.2.port.0.s.6.alias= -unit.1.2.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.6.name=TriggerPort0[6] -unit.1.2.port.0.s.6.orderindex=-1 -unit.1.2.port.0.s.6.visible=1 -unit.1.2.port.0.s.7.alias= -unit.1.2.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.7.name=TriggerPort0[7] -unit.1.2.port.0.s.7.orderindex=-1 -unit.1.2.port.0.s.7.visible=1 -unit.1.2.port.0.s.8.alias= -unit.1.2.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.8.name=TriggerPort0[8] -unit.1.2.port.0.s.8.orderindex=-1 -unit.1.2.port.0.s.8.visible=1 -unit.1.2.port.0.s.9.alias= -unit.1.2.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.0.s.9.name=TriggerPort0[9] -unit.1.2.port.0.s.9.orderindex=-1 -unit.1.2.port.0.s.9.visible=1 -unit.1.2.port.1.b.0.alias= -unit.1.2.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.b.0.name=TriggerPort1 -unit.1.2.port.1.b.0.orderindex=-1 -unit.1.2.port.1.b.0.radix=Hex -unit.1.2.port.1.b.0.signedOffset=0.0 -unit.1.2.port.1.b.0.signedPrecision=0 -unit.1.2.port.1.b.0.signedScaleFactor=1.0 -unit.1.2.port.1.b.0.unsignedOffset=0.0 -unit.1.2.port.1.b.0.unsignedPrecision=0 -unit.1.2.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.1.b.0.visible=1 -unit.1.2.port.1.buscount=1 -unit.1.2.port.1.channelcount=32 -unit.1.2.port.1.s.0.alias= -unit.1.2.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.0.name=TriggerPort1[0] -unit.1.2.port.1.s.0.orderindex=-1 -unit.1.2.port.1.s.0.visible=1 -unit.1.2.port.1.s.1.alias= -unit.1.2.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.1.name=TriggerPort1[1] -unit.1.2.port.1.s.1.orderindex=-1 -unit.1.2.port.1.s.1.visible=1 -unit.1.2.port.1.s.10.alias= -unit.1.2.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.10.name=TriggerPort1[10] -unit.1.2.port.1.s.10.orderindex=-1 -unit.1.2.port.1.s.10.visible=1 -unit.1.2.port.1.s.11.alias= -unit.1.2.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.11.name=TriggerPort1[11] -unit.1.2.port.1.s.11.orderindex=-1 -unit.1.2.port.1.s.11.visible=1 -unit.1.2.port.1.s.12.alias= -unit.1.2.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.12.name=TriggerPort1[12] -unit.1.2.port.1.s.12.orderindex=-1 -unit.1.2.port.1.s.12.visible=1 -unit.1.2.port.1.s.13.alias= -unit.1.2.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.13.name=TriggerPort1[13] -unit.1.2.port.1.s.13.orderindex=-1 -unit.1.2.port.1.s.13.visible=1 -unit.1.2.port.1.s.14.alias= -unit.1.2.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.14.name=TriggerPort1[14] -unit.1.2.port.1.s.14.orderindex=-1 -unit.1.2.port.1.s.14.visible=1 -unit.1.2.port.1.s.15.alias= -unit.1.2.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.15.name=TriggerPort1[15] -unit.1.2.port.1.s.15.orderindex=-1 -unit.1.2.port.1.s.15.visible=1 -unit.1.2.port.1.s.16.alias= -unit.1.2.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.16.name=TriggerPort1[16] -unit.1.2.port.1.s.16.orderindex=-1 -unit.1.2.port.1.s.16.visible=1 -unit.1.2.port.1.s.17.alias= -unit.1.2.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.17.name=TriggerPort1[17] -unit.1.2.port.1.s.17.orderindex=-1 -unit.1.2.port.1.s.17.visible=1 -unit.1.2.port.1.s.18.alias= -unit.1.2.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.18.name=TriggerPort1[18] -unit.1.2.port.1.s.18.orderindex=-1 -unit.1.2.port.1.s.18.visible=1 -unit.1.2.port.1.s.19.alias= -unit.1.2.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.19.name=TriggerPort1[19] -unit.1.2.port.1.s.19.orderindex=-1 -unit.1.2.port.1.s.19.visible=1 -unit.1.2.port.1.s.2.alias= -unit.1.2.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.2.name=TriggerPort1[2] -unit.1.2.port.1.s.2.orderindex=-1 -unit.1.2.port.1.s.2.visible=1 -unit.1.2.port.1.s.20.alias= -unit.1.2.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.20.name=TriggerPort1[20] -unit.1.2.port.1.s.20.orderindex=-1 -unit.1.2.port.1.s.20.visible=1 -unit.1.2.port.1.s.21.alias= -unit.1.2.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.21.name=TriggerPort1[21] -unit.1.2.port.1.s.21.orderindex=-1 -unit.1.2.port.1.s.21.visible=1 -unit.1.2.port.1.s.22.alias= -unit.1.2.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.22.name=TriggerPort1[22] -unit.1.2.port.1.s.22.orderindex=-1 -unit.1.2.port.1.s.22.visible=1 -unit.1.2.port.1.s.23.alias= -unit.1.2.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.23.name=TriggerPort1[23] -unit.1.2.port.1.s.23.orderindex=-1 -unit.1.2.port.1.s.23.visible=1 -unit.1.2.port.1.s.24.alias= -unit.1.2.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.24.name=TriggerPort1[24] -unit.1.2.port.1.s.24.orderindex=-1 -unit.1.2.port.1.s.24.visible=1 -unit.1.2.port.1.s.25.alias= -unit.1.2.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.25.name=TriggerPort1[25] -unit.1.2.port.1.s.25.orderindex=-1 -unit.1.2.port.1.s.25.visible=1 -unit.1.2.port.1.s.26.alias= -unit.1.2.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.26.name=TriggerPort1[26] -unit.1.2.port.1.s.26.orderindex=-1 -unit.1.2.port.1.s.26.visible=1 -unit.1.2.port.1.s.27.alias= -unit.1.2.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.27.name=TriggerPort1[27] -unit.1.2.port.1.s.27.orderindex=-1 -unit.1.2.port.1.s.27.visible=1 -unit.1.2.port.1.s.28.alias= -unit.1.2.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.28.name=TriggerPort1[28] -unit.1.2.port.1.s.28.orderindex=-1 -unit.1.2.port.1.s.28.visible=1 -unit.1.2.port.1.s.29.alias= -unit.1.2.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.29.name=TriggerPort1[29] -unit.1.2.port.1.s.29.orderindex=-1 -unit.1.2.port.1.s.29.visible=1 -unit.1.2.port.1.s.3.alias= -unit.1.2.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.3.name=TriggerPort1[3] -unit.1.2.port.1.s.3.orderindex=-1 -unit.1.2.port.1.s.3.visible=1 -unit.1.2.port.1.s.30.alias= -unit.1.2.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.30.name=TriggerPort1[30] -unit.1.2.port.1.s.30.orderindex=-1 -unit.1.2.port.1.s.30.visible=1 -unit.1.2.port.1.s.31.alias= -unit.1.2.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.31.name=TriggerPort1[31] -unit.1.2.port.1.s.31.orderindex=-1 -unit.1.2.port.1.s.31.visible=1 -unit.1.2.port.1.s.4.alias= -unit.1.2.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.4.name=TriggerPort1[4] -unit.1.2.port.1.s.4.orderindex=-1 -unit.1.2.port.1.s.4.visible=1 -unit.1.2.port.1.s.5.alias= -unit.1.2.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.5.name=TriggerPort1[5] -unit.1.2.port.1.s.5.orderindex=-1 -unit.1.2.port.1.s.5.visible=1 -unit.1.2.port.1.s.6.alias= -unit.1.2.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.6.name=TriggerPort1[6] -unit.1.2.port.1.s.6.orderindex=-1 -unit.1.2.port.1.s.6.visible=1 -unit.1.2.port.1.s.7.alias= -unit.1.2.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.7.name=TriggerPort1[7] -unit.1.2.port.1.s.7.orderindex=-1 -unit.1.2.port.1.s.7.visible=1 -unit.1.2.port.1.s.8.alias= -unit.1.2.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.8.name=TriggerPort1[8] -unit.1.2.port.1.s.8.orderindex=-1 -unit.1.2.port.1.s.8.visible=1 -unit.1.2.port.1.s.9.alias= -unit.1.2.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.1.s.9.name=TriggerPort1[9] -unit.1.2.port.1.s.9.orderindex=-1 -unit.1.2.port.1.s.9.visible=1 -unit.1.2.port.2.b.0.alias= -unit.1.2.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.b.0.name=TriggerPort2 -unit.1.2.port.2.b.0.orderindex=-1 -unit.1.2.port.2.b.0.radix=Hex -unit.1.2.port.2.b.0.signedOffset=0.0 -unit.1.2.port.2.b.0.signedPrecision=0 -unit.1.2.port.2.b.0.signedScaleFactor=1.0 -unit.1.2.port.2.b.0.unsignedOffset=0.0 -unit.1.2.port.2.b.0.unsignedPrecision=0 -unit.1.2.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.2.port.2.b.0.visible=1 -unit.1.2.port.2.buscount=1 -unit.1.2.port.2.channelcount=32 -unit.1.2.port.2.s.0.alias= -unit.1.2.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.0.name=TriggerPort2[0] -unit.1.2.port.2.s.0.orderindex=-1 -unit.1.2.port.2.s.0.visible=1 -unit.1.2.port.2.s.1.alias= -unit.1.2.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.1.name=TriggerPort2[1] -unit.1.2.port.2.s.1.orderindex=-1 -unit.1.2.port.2.s.1.visible=1 -unit.1.2.port.2.s.10.alias= -unit.1.2.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.10.name=TriggerPort2[10] -unit.1.2.port.2.s.10.orderindex=-1 -unit.1.2.port.2.s.10.visible=1 -unit.1.2.port.2.s.11.alias= -unit.1.2.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.11.name=TriggerPort2[11] -unit.1.2.port.2.s.11.orderindex=-1 -unit.1.2.port.2.s.11.visible=1 -unit.1.2.port.2.s.12.alias= -unit.1.2.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.12.name=TriggerPort2[12] -unit.1.2.port.2.s.12.orderindex=-1 -unit.1.2.port.2.s.12.visible=1 -unit.1.2.port.2.s.13.alias= -unit.1.2.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.13.name=TriggerPort2[13] -unit.1.2.port.2.s.13.orderindex=-1 -unit.1.2.port.2.s.13.visible=1 -unit.1.2.port.2.s.14.alias= -unit.1.2.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.14.name=TriggerPort2[14] -unit.1.2.port.2.s.14.orderindex=-1 -unit.1.2.port.2.s.14.visible=1 -unit.1.2.port.2.s.15.alias= -unit.1.2.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.15.name=TriggerPort2[15] -unit.1.2.port.2.s.15.orderindex=-1 -unit.1.2.port.2.s.15.visible=1 -unit.1.2.port.2.s.16.alias= -unit.1.2.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.16.name=TriggerPort2[16] -unit.1.2.port.2.s.16.orderindex=-1 -unit.1.2.port.2.s.16.visible=1 -unit.1.2.port.2.s.17.alias= -unit.1.2.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.17.name=TriggerPort2[17] -unit.1.2.port.2.s.17.orderindex=-1 -unit.1.2.port.2.s.17.visible=1 -unit.1.2.port.2.s.18.alias= -unit.1.2.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.18.name=TriggerPort2[18] -unit.1.2.port.2.s.18.orderindex=-1 -unit.1.2.port.2.s.18.visible=1 -unit.1.2.port.2.s.19.alias= -unit.1.2.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.19.name=TriggerPort2[19] -unit.1.2.port.2.s.19.orderindex=-1 -unit.1.2.port.2.s.19.visible=1 -unit.1.2.port.2.s.2.alias= -unit.1.2.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.2.name=TriggerPort2[2] -unit.1.2.port.2.s.2.orderindex=-1 -unit.1.2.port.2.s.2.visible=1 -unit.1.2.port.2.s.20.alias= -unit.1.2.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.20.name=TriggerPort2[20] -unit.1.2.port.2.s.20.orderindex=-1 -unit.1.2.port.2.s.20.visible=1 -unit.1.2.port.2.s.21.alias= -unit.1.2.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.21.name=TriggerPort2[21] -unit.1.2.port.2.s.21.orderindex=-1 -unit.1.2.port.2.s.21.visible=1 -unit.1.2.port.2.s.22.alias= -unit.1.2.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.22.name=TriggerPort2[22] -unit.1.2.port.2.s.22.orderindex=-1 -unit.1.2.port.2.s.22.visible=1 -unit.1.2.port.2.s.23.alias= -unit.1.2.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.23.name=TriggerPort2[23] -unit.1.2.port.2.s.23.orderindex=-1 -unit.1.2.port.2.s.23.visible=1 -unit.1.2.port.2.s.24.alias= -unit.1.2.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.24.name=TriggerPort2[24] -unit.1.2.port.2.s.24.orderindex=-1 -unit.1.2.port.2.s.24.visible=1 -unit.1.2.port.2.s.25.alias= -unit.1.2.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.25.name=TriggerPort2[25] -unit.1.2.port.2.s.25.orderindex=-1 -unit.1.2.port.2.s.25.visible=1 -unit.1.2.port.2.s.26.alias= -unit.1.2.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.26.name=TriggerPort2[26] -unit.1.2.port.2.s.26.orderindex=-1 -unit.1.2.port.2.s.26.visible=1 -unit.1.2.port.2.s.27.alias= -unit.1.2.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.27.name=TriggerPort2[27] -unit.1.2.port.2.s.27.orderindex=-1 -unit.1.2.port.2.s.27.visible=1 -unit.1.2.port.2.s.28.alias= -unit.1.2.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.28.name=TriggerPort2[28] -unit.1.2.port.2.s.28.orderindex=-1 -unit.1.2.port.2.s.28.visible=1 -unit.1.2.port.2.s.29.alias= -unit.1.2.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.29.name=TriggerPort2[29] -unit.1.2.port.2.s.29.orderindex=-1 -unit.1.2.port.2.s.29.visible=1 -unit.1.2.port.2.s.3.alias= -unit.1.2.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.3.name=TriggerPort2[3] -unit.1.2.port.2.s.3.orderindex=-1 -unit.1.2.port.2.s.3.visible=1 -unit.1.2.port.2.s.30.alias= -unit.1.2.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.30.name=TriggerPort2[30] -unit.1.2.port.2.s.30.orderindex=-1 -unit.1.2.port.2.s.30.visible=1 -unit.1.2.port.2.s.31.alias= -unit.1.2.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.31.name=TriggerPort2[31] -unit.1.2.port.2.s.31.orderindex=-1 -unit.1.2.port.2.s.31.visible=1 -unit.1.2.port.2.s.4.alias= -unit.1.2.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.4.name=TriggerPort2[4] -unit.1.2.port.2.s.4.orderindex=-1 -unit.1.2.port.2.s.4.visible=1 -unit.1.2.port.2.s.5.alias= -unit.1.2.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.5.name=TriggerPort2[5] -unit.1.2.port.2.s.5.orderindex=-1 -unit.1.2.port.2.s.5.visible=1 -unit.1.2.port.2.s.6.alias= -unit.1.2.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.6.name=TriggerPort2[6] -unit.1.2.port.2.s.6.orderindex=-1 -unit.1.2.port.2.s.6.visible=1 -unit.1.2.port.2.s.7.alias= -unit.1.2.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.7.name=TriggerPort2[7] -unit.1.2.port.2.s.7.orderindex=-1 -unit.1.2.port.2.s.7.visible=1 -unit.1.2.port.2.s.8.alias= -unit.1.2.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.8.name=TriggerPort2[8] -unit.1.2.port.2.s.8.orderindex=-1 -unit.1.2.port.2.s.8.visible=1 -unit.1.2.port.2.s.9.alias= -unit.1.2.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.2.s.9.name=TriggerPort2[9] -unit.1.2.port.2.s.9.orderindex=-1 -unit.1.2.port.2.s.9.visible=1 -unit.1.2.port.3.b.0.alias= -unit.1.2.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.2.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.2.port.3.b.0.name=TriggerPort3 -unit.1.2.port.3.b.0.orderindex=-1 -unit.1.2.port.3.b.0.radix=Hex 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-unit.1.3.port.-1.s.97.visible=1 -unit.1.3.port.-1.s.98.alias= -unit.1.3.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.98.name=DataPort[98] -unit.1.3.port.-1.s.98.orderindex=-1 -unit.1.3.port.-1.s.98.visible=1 -unit.1.3.port.-1.s.99.alias= -unit.1.3.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.-1.s.99.name=DataPort[99] -unit.1.3.port.-1.s.99.orderindex=-1 -unit.1.3.port.-1.s.99.visible=1 -unit.1.3.port.0.b.0.alias= -unit.1.3.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.b.0.name=TriggerPort0 -unit.1.3.port.0.b.0.orderindex=-1 -unit.1.3.port.0.b.0.radix=Hex -unit.1.3.port.0.b.0.signedOffset=0.0 -unit.1.3.port.0.b.0.signedPrecision=0 -unit.1.3.port.0.b.0.signedScaleFactor=1.0 -unit.1.3.port.0.b.0.unsignedOffset=0.0 -unit.1.3.port.0.b.0.unsignedPrecision=0 -unit.1.3.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.0.b.0.visible=1 -unit.1.3.port.0.buscount=1 -unit.1.3.port.0.channelcount=32 -unit.1.3.port.0.s.0.alias= -unit.1.3.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.0.name=TriggerPort0[0] -unit.1.3.port.0.s.0.orderindex=-1 -unit.1.3.port.0.s.0.visible=1 -unit.1.3.port.0.s.1.alias= -unit.1.3.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.1.name=TriggerPort0[1] -unit.1.3.port.0.s.1.orderindex=-1 -unit.1.3.port.0.s.1.visible=1 -unit.1.3.port.0.s.10.alias= -unit.1.3.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.10.name=TriggerPort0[10] -unit.1.3.port.0.s.10.orderindex=-1 -unit.1.3.port.0.s.10.visible=1 -unit.1.3.port.0.s.11.alias= -unit.1.3.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.11.name=TriggerPort0[11] -unit.1.3.port.0.s.11.orderindex=-1 -unit.1.3.port.0.s.11.visible=1 -unit.1.3.port.0.s.12.alias= -unit.1.3.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.12.name=TriggerPort0[12] -unit.1.3.port.0.s.12.orderindex=-1 -unit.1.3.port.0.s.12.visible=1 -unit.1.3.port.0.s.13.alias= -unit.1.3.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.13.name=TriggerPort0[13] -unit.1.3.port.0.s.13.orderindex=-1 -unit.1.3.port.0.s.13.visible=1 -unit.1.3.port.0.s.14.alias= -unit.1.3.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.14.name=TriggerPort0[14] -unit.1.3.port.0.s.14.orderindex=-1 -unit.1.3.port.0.s.14.visible=1 -unit.1.3.port.0.s.15.alias= -unit.1.3.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.15.name=TriggerPort0[15] -unit.1.3.port.0.s.15.orderindex=-1 -unit.1.3.port.0.s.15.visible=1 -unit.1.3.port.0.s.16.alias= -unit.1.3.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.16.name=TriggerPort0[16] -unit.1.3.port.0.s.16.orderindex=-1 -unit.1.3.port.0.s.16.visible=1 -unit.1.3.port.0.s.17.alias= -unit.1.3.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.17.name=TriggerPort0[17] -unit.1.3.port.0.s.17.orderindex=-1 -unit.1.3.port.0.s.17.visible=1 -unit.1.3.port.0.s.18.alias= -unit.1.3.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.18.name=TriggerPort0[18] -unit.1.3.port.0.s.18.orderindex=-1 -unit.1.3.port.0.s.18.visible=1 -unit.1.3.port.0.s.19.alias= -unit.1.3.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.19.name=TriggerPort0[19] -unit.1.3.port.0.s.19.orderindex=-1 -unit.1.3.port.0.s.19.visible=1 -unit.1.3.port.0.s.2.alias= -unit.1.3.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.2.name=TriggerPort0[2] -unit.1.3.port.0.s.2.orderindex=-1 -unit.1.3.port.0.s.2.visible=1 -unit.1.3.port.0.s.20.alias= -unit.1.3.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.20.name=TriggerPort0[20] -unit.1.3.port.0.s.20.orderindex=-1 -unit.1.3.port.0.s.20.visible=1 -unit.1.3.port.0.s.21.alias= -unit.1.3.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.21.name=TriggerPort0[21] -unit.1.3.port.0.s.21.orderindex=-1 -unit.1.3.port.0.s.21.visible=1 -unit.1.3.port.0.s.22.alias= -unit.1.3.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.22.name=TriggerPort0[22] -unit.1.3.port.0.s.22.orderindex=-1 -unit.1.3.port.0.s.22.visible=1 -unit.1.3.port.0.s.23.alias= -unit.1.3.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.23.name=TriggerPort0[23] -unit.1.3.port.0.s.23.orderindex=-1 -unit.1.3.port.0.s.23.visible=1 -unit.1.3.port.0.s.24.alias= -unit.1.3.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.24.name=TriggerPort0[24] -unit.1.3.port.0.s.24.orderindex=-1 -unit.1.3.port.0.s.24.visible=1 -unit.1.3.port.0.s.25.alias= -unit.1.3.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.25.name=TriggerPort0[25] -unit.1.3.port.0.s.25.orderindex=-1 -unit.1.3.port.0.s.25.visible=1 -unit.1.3.port.0.s.26.alias= -unit.1.3.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.26.name=TriggerPort0[26] -unit.1.3.port.0.s.26.orderindex=-1 -unit.1.3.port.0.s.26.visible=1 -unit.1.3.port.0.s.27.alias= -unit.1.3.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.27.name=TriggerPort0[27] -unit.1.3.port.0.s.27.orderindex=-1 -unit.1.3.port.0.s.27.visible=1 -unit.1.3.port.0.s.28.alias= -unit.1.3.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.28.name=TriggerPort0[28] -unit.1.3.port.0.s.28.orderindex=-1 -unit.1.3.port.0.s.28.visible=1 -unit.1.3.port.0.s.29.alias= -unit.1.3.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.29.name=TriggerPort0[29] -unit.1.3.port.0.s.29.orderindex=-1 -unit.1.3.port.0.s.29.visible=1 -unit.1.3.port.0.s.3.alias= -unit.1.3.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.3.name=TriggerPort0[3] -unit.1.3.port.0.s.3.orderindex=-1 -unit.1.3.port.0.s.3.visible=1 -unit.1.3.port.0.s.30.alias= -unit.1.3.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.30.name=TriggerPort0[30] -unit.1.3.port.0.s.30.orderindex=-1 -unit.1.3.port.0.s.30.visible=1 -unit.1.3.port.0.s.31.alias= -unit.1.3.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.31.name=TriggerPort0[31] -unit.1.3.port.0.s.31.orderindex=-1 -unit.1.3.port.0.s.31.visible=1 -unit.1.3.port.0.s.4.alias= -unit.1.3.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.4.name=TriggerPort0[4] -unit.1.3.port.0.s.4.orderindex=-1 -unit.1.3.port.0.s.4.visible=1 -unit.1.3.port.0.s.5.alias= -unit.1.3.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.5.name=TriggerPort0[5] -unit.1.3.port.0.s.5.orderindex=-1 -unit.1.3.port.0.s.5.visible=1 -unit.1.3.port.0.s.6.alias= -unit.1.3.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.6.name=TriggerPort0[6] -unit.1.3.port.0.s.6.orderindex=-1 -unit.1.3.port.0.s.6.visible=1 -unit.1.3.port.0.s.7.alias= -unit.1.3.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.7.name=TriggerPort0[7] -unit.1.3.port.0.s.7.orderindex=-1 -unit.1.3.port.0.s.7.visible=1 -unit.1.3.port.0.s.8.alias= -unit.1.3.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.8.name=TriggerPort0[8] -unit.1.3.port.0.s.8.orderindex=-1 -unit.1.3.port.0.s.8.visible=1 -unit.1.3.port.0.s.9.alias= -unit.1.3.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.0.s.9.name=TriggerPort0[9] -unit.1.3.port.0.s.9.orderindex=-1 -unit.1.3.port.0.s.9.visible=1 -unit.1.3.port.1.b.0.alias= -unit.1.3.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.b.0.name=TriggerPort1 -unit.1.3.port.1.b.0.orderindex=-1 -unit.1.3.port.1.b.0.radix=Hex -unit.1.3.port.1.b.0.signedOffset=0.0 -unit.1.3.port.1.b.0.signedPrecision=0 -unit.1.3.port.1.b.0.signedScaleFactor=1.0 -unit.1.3.port.1.b.0.unsignedOffset=0.0 -unit.1.3.port.1.b.0.unsignedPrecision=0 -unit.1.3.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.1.b.0.visible=1 -unit.1.3.port.1.buscount=1 -unit.1.3.port.1.channelcount=32 -unit.1.3.port.1.s.0.alias= -unit.1.3.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.0.name=TriggerPort1[0] -unit.1.3.port.1.s.0.orderindex=-1 -unit.1.3.port.1.s.0.visible=1 -unit.1.3.port.1.s.1.alias= -unit.1.3.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.1.name=TriggerPort1[1] -unit.1.3.port.1.s.1.orderindex=-1 -unit.1.3.port.1.s.1.visible=1 -unit.1.3.port.1.s.10.alias= -unit.1.3.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.10.name=TriggerPort1[10] -unit.1.3.port.1.s.10.orderindex=-1 -unit.1.3.port.1.s.10.visible=1 -unit.1.3.port.1.s.11.alias= -unit.1.3.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.11.name=TriggerPort1[11] -unit.1.3.port.1.s.11.orderindex=-1 -unit.1.3.port.1.s.11.visible=1 -unit.1.3.port.1.s.12.alias= -unit.1.3.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.12.name=TriggerPort1[12] -unit.1.3.port.1.s.12.orderindex=-1 -unit.1.3.port.1.s.12.visible=1 -unit.1.3.port.1.s.13.alias= -unit.1.3.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.13.name=TriggerPort1[13] -unit.1.3.port.1.s.13.orderindex=-1 -unit.1.3.port.1.s.13.visible=1 -unit.1.3.port.1.s.14.alias= -unit.1.3.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.14.name=TriggerPort1[14] -unit.1.3.port.1.s.14.orderindex=-1 -unit.1.3.port.1.s.14.visible=1 -unit.1.3.port.1.s.15.alias= -unit.1.3.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.15.name=TriggerPort1[15] -unit.1.3.port.1.s.15.orderindex=-1 -unit.1.3.port.1.s.15.visible=1 -unit.1.3.port.1.s.16.alias= -unit.1.3.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.16.name=TriggerPort1[16] -unit.1.3.port.1.s.16.orderindex=-1 -unit.1.3.port.1.s.16.visible=1 -unit.1.3.port.1.s.17.alias= -unit.1.3.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.17.name=TriggerPort1[17] -unit.1.3.port.1.s.17.orderindex=-1 -unit.1.3.port.1.s.17.visible=1 -unit.1.3.port.1.s.18.alias= -unit.1.3.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.18.name=TriggerPort1[18] -unit.1.3.port.1.s.18.orderindex=-1 -unit.1.3.port.1.s.18.visible=1 -unit.1.3.port.1.s.19.alias= -unit.1.3.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.19.name=TriggerPort1[19] -unit.1.3.port.1.s.19.orderindex=-1 -unit.1.3.port.1.s.19.visible=1 -unit.1.3.port.1.s.2.alias= -unit.1.3.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.2.name=TriggerPort1[2] -unit.1.3.port.1.s.2.orderindex=-1 -unit.1.3.port.1.s.2.visible=1 -unit.1.3.port.1.s.20.alias= -unit.1.3.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.20.name=TriggerPort1[20] -unit.1.3.port.1.s.20.orderindex=-1 -unit.1.3.port.1.s.20.visible=1 -unit.1.3.port.1.s.21.alias= -unit.1.3.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.21.name=TriggerPort1[21] -unit.1.3.port.1.s.21.orderindex=-1 -unit.1.3.port.1.s.21.visible=1 -unit.1.3.port.1.s.22.alias= -unit.1.3.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.22.name=TriggerPort1[22] -unit.1.3.port.1.s.22.orderindex=-1 -unit.1.3.port.1.s.22.visible=1 -unit.1.3.port.1.s.23.alias= -unit.1.3.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.23.name=TriggerPort1[23] -unit.1.3.port.1.s.23.orderindex=-1 -unit.1.3.port.1.s.23.visible=1 -unit.1.3.port.1.s.24.alias= -unit.1.3.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.24.name=TriggerPort1[24] -unit.1.3.port.1.s.24.orderindex=-1 -unit.1.3.port.1.s.24.visible=1 -unit.1.3.port.1.s.25.alias= -unit.1.3.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.25.name=TriggerPort1[25] -unit.1.3.port.1.s.25.orderindex=-1 -unit.1.3.port.1.s.25.visible=1 -unit.1.3.port.1.s.26.alias= -unit.1.3.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.26.name=TriggerPort1[26] -unit.1.3.port.1.s.26.orderindex=-1 -unit.1.3.port.1.s.26.visible=1 -unit.1.3.port.1.s.27.alias= -unit.1.3.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.27.name=TriggerPort1[27] -unit.1.3.port.1.s.27.orderindex=-1 -unit.1.3.port.1.s.27.visible=1 -unit.1.3.port.1.s.28.alias= -unit.1.3.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.28.name=TriggerPort1[28] -unit.1.3.port.1.s.28.orderindex=-1 -unit.1.3.port.1.s.28.visible=1 -unit.1.3.port.1.s.29.alias= -unit.1.3.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.29.name=TriggerPort1[29] -unit.1.3.port.1.s.29.orderindex=-1 -unit.1.3.port.1.s.29.visible=1 -unit.1.3.port.1.s.3.alias= -unit.1.3.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.3.name=TriggerPort1[3] -unit.1.3.port.1.s.3.orderindex=-1 -unit.1.3.port.1.s.3.visible=1 -unit.1.3.port.1.s.30.alias= -unit.1.3.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.30.name=TriggerPort1[30] -unit.1.3.port.1.s.30.orderindex=-1 -unit.1.3.port.1.s.30.visible=1 -unit.1.3.port.1.s.31.alias= -unit.1.3.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.31.name=TriggerPort1[31] -unit.1.3.port.1.s.31.orderindex=-1 -unit.1.3.port.1.s.31.visible=1 -unit.1.3.port.1.s.4.alias= -unit.1.3.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.4.name=TriggerPort1[4] -unit.1.3.port.1.s.4.orderindex=-1 -unit.1.3.port.1.s.4.visible=1 -unit.1.3.port.1.s.5.alias= -unit.1.3.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.5.name=TriggerPort1[5] -unit.1.3.port.1.s.5.orderindex=-1 -unit.1.3.port.1.s.5.visible=1 -unit.1.3.port.1.s.6.alias= -unit.1.3.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.6.name=TriggerPort1[6] -unit.1.3.port.1.s.6.orderindex=-1 -unit.1.3.port.1.s.6.visible=1 -unit.1.3.port.1.s.7.alias= -unit.1.3.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.7.name=TriggerPort1[7] -unit.1.3.port.1.s.7.orderindex=-1 -unit.1.3.port.1.s.7.visible=1 -unit.1.3.port.1.s.8.alias= -unit.1.3.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.8.name=TriggerPort1[8] -unit.1.3.port.1.s.8.orderindex=-1 -unit.1.3.port.1.s.8.visible=1 -unit.1.3.port.1.s.9.alias= -unit.1.3.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.1.s.9.name=TriggerPort1[9] -unit.1.3.port.1.s.9.orderindex=-1 -unit.1.3.port.1.s.9.visible=1 -unit.1.3.port.2.b.0.alias= -unit.1.3.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.b.0.name=TriggerPort2 -unit.1.3.port.2.b.0.orderindex=-1 -unit.1.3.port.2.b.0.radix=Hex -unit.1.3.port.2.b.0.signedOffset=0.0 -unit.1.3.port.2.b.0.signedPrecision=0 -unit.1.3.port.2.b.0.signedScaleFactor=1.0 -unit.1.3.port.2.b.0.unsignedOffset=0.0 -unit.1.3.port.2.b.0.unsignedPrecision=0 -unit.1.3.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.2.b.0.visible=1 -unit.1.3.port.2.buscount=1 -unit.1.3.port.2.channelcount=32 -unit.1.3.port.2.s.0.alias= -unit.1.3.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.0.name=TriggerPort2[0] -unit.1.3.port.2.s.0.orderindex=-1 -unit.1.3.port.2.s.0.visible=1 -unit.1.3.port.2.s.1.alias= -unit.1.3.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.1.name=TriggerPort2[1] -unit.1.3.port.2.s.1.orderindex=-1 -unit.1.3.port.2.s.1.visible=1 -unit.1.3.port.2.s.10.alias= -unit.1.3.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.10.name=TriggerPort2[10] -unit.1.3.port.2.s.10.orderindex=-1 -unit.1.3.port.2.s.10.visible=1 -unit.1.3.port.2.s.11.alias= -unit.1.3.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.11.name=TriggerPort2[11] -unit.1.3.port.2.s.11.orderindex=-1 -unit.1.3.port.2.s.11.visible=1 -unit.1.3.port.2.s.12.alias= -unit.1.3.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.12.name=TriggerPort2[12] -unit.1.3.port.2.s.12.orderindex=-1 -unit.1.3.port.2.s.12.visible=1 -unit.1.3.port.2.s.13.alias= -unit.1.3.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.13.name=TriggerPort2[13] -unit.1.3.port.2.s.13.orderindex=-1 -unit.1.3.port.2.s.13.visible=1 -unit.1.3.port.2.s.14.alias= -unit.1.3.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.14.name=TriggerPort2[14] -unit.1.3.port.2.s.14.orderindex=-1 -unit.1.3.port.2.s.14.visible=1 -unit.1.3.port.2.s.15.alias= -unit.1.3.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.15.name=TriggerPort2[15] -unit.1.3.port.2.s.15.orderindex=-1 -unit.1.3.port.2.s.15.visible=1 -unit.1.3.port.2.s.16.alias= -unit.1.3.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.16.name=TriggerPort2[16] -unit.1.3.port.2.s.16.orderindex=-1 -unit.1.3.port.2.s.16.visible=1 -unit.1.3.port.2.s.17.alias= -unit.1.3.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.17.name=TriggerPort2[17] -unit.1.3.port.2.s.17.orderindex=-1 -unit.1.3.port.2.s.17.visible=1 -unit.1.3.port.2.s.18.alias= -unit.1.3.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.18.name=TriggerPort2[18] -unit.1.3.port.2.s.18.orderindex=-1 -unit.1.3.port.2.s.18.visible=1 -unit.1.3.port.2.s.19.alias= -unit.1.3.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.19.name=TriggerPort2[19] -unit.1.3.port.2.s.19.orderindex=-1 -unit.1.3.port.2.s.19.visible=1 -unit.1.3.port.2.s.2.alias= -unit.1.3.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.2.name=TriggerPort2[2] -unit.1.3.port.2.s.2.orderindex=-1 -unit.1.3.port.2.s.2.visible=1 -unit.1.3.port.2.s.20.alias= -unit.1.3.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.20.name=TriggerPort2[20] -unit.1.3.port.2.s.20.orderindex=-1 -unit.1.3.port.2.s.20.visible=1 -unit.1.3.port.2.s.21.alias= -unit.1.3.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.21.name=TriggerPort2[21] -unit.1.3.port.2.s.21.orderindex=-1 -unit.1.3.port.2.s.21.visible=1 -unit.1.3.port.2.s.22.alias= -unit.1.3.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.22.name=TriggerPort2[22] -unit.1.3.port.2.s.22.orderindex=-1 -unit.1.3.port.2.s.22.visible=1 -unit.1.3.port.2.s.23.alias= -unit.1.3.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.23.name=TriggerPort2[23] -unit.1.3.port.2.s.23.orderindex=-1 -unit.1.3.port.2.s.23.visible=1 -unit.1.3.port.2.s.24.alias= -unit.1.3.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.24.name=TriggerPort2[24] -unit.1.3.port.2.s.24.orderindex=-1 -unit.1.3.port.2.s.24.visible=1 -unit.1.3.port.2.s.25.alias= -unit.1.3.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.25.name=TriggerPort2[25] -unit.1.3.port.2.s.25.orderindex=-1 -unit.1.3.port.2.s.25.visible=1 -unit.1.3.port.2.s.26.alias= -unit.1.3.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.26.name=TriggerPort2[26] -unit.1.3.port.2.s.26.orderindex=-1 -unit.1.3.port.2.s.26.visible=1 -unit.1.3.port.2.s.27.alias= -unit.1.3.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.27.name=TriggerPort2[27] -unit.1.3.port.2.s.27.orderindex=-1 -unit.1.3.port.2.s.27.visible=1 -unit.1.3.port.2.s.28.alias= -unit.1.3.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.28.name=TriggerPort2[28] -unit.1.3.port.2.s.28.orderindex=-1 -unit.1.3.port.2.s.28.visible=1 -unit.1.3.port.2.s.29.alias= -unit.1.3.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.29.name=TriggerPort2[29] -unit.1.3.port.2.s.29.orderindex=-1 -unit.1.3.port.2.s.29.visible=1 -unit.1.3.port.2.s.3.alias= -unit.1.3.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.3.name=TriggerPort2[3] -unit.1.3.port.2.s.3.orderindex=-1 -unit.1.3.port.2.s.3.visible=1 -unit.1.3.port.2.s.30.alias= -unit.1.3.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.30.name=TriggerPort2[30] -unit.1.3.port.2.s.30.orderindex=-1 -unit.1.3.port.2.s.30.visible=1 -unit.1.3.port.2.s.31.alias= -unit.1.3.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.31.name=TriggerPort2[31] -unit.1.3.port.2.s.31.orderindex=-1 -unit.1.3.port.2.s.31.visible=1 -unit.1.3.port.2.s.4.alias= -unit.1.3.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.4.name=TriggerPort2[4] -unit.1.3.port.2.s.4.orderindex=-1 -unit.1.3.port.2.s.4.visible=1 -unit.1.3.port.2.s.5.alias= -unit.1.3.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.5.name=TriggerPort2[5] -unit.1.3.port.2.s.5.orderindex=-1 -unit.1.3.port.2.s.5.visible=1 -unit.1.3.port.2.s.6.alias= -unit.1.3.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.6.name=TriggerPort2[6] -unit.1.3.port.2.s.6.orderindex=-1 -unit.1.3.port.2.s.6.visible=1 -unit.1.3.port.2.s.7.alias= -unit.1.3.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.7.name=TriggerPort2[7] -unit.1.3.port.2.s.7.orderindex=-1 -unit.1.3.port.2.s.7.visible=1 -unit.1.3.port.2.s.8.alias= -unit.1.3.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.8.name=TriggerPort2[8] -unit.1.3.port.2.s.8.orderindex=-1 -unit.1.3.port.2.s.8.visible=1 -unit.1.3.port.2.s.9.alias= -unit.1.3.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.2.s.9.name=TriggerPort2[9] -unit.1.3.port.2.s.9.orderindex=-1 -unit.1.3.port.2.s.9.visible=1 -unit.1.3.port.3.b.0.alias= -unit.1.3.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.3.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.b.0.name=TriggerPort3 -unit.1.3.port.3.b.0.orderindex=-1 -unit.1.3.port.3.b.0.radix=Hex -unit.1.3.port.3.b.0.signedOffset=0.0 -unit.1.3.port.3.b.0.signedPrecision=0 -unit.1.3.port.3.b.0.signedScaleFactor=1.0 -unit.1.3.port.3.b.0.unsignedOffset=0.0 -unit.1.3.port.3.b.0.unsignedPrecision=0 -unit.1.3.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.3.port.3.b.0.visible=1 -unit.1.3.port.3.buscount=1 -unit.1.3.port.3.channelcount=32 -unit.1.3.port.3.s.0.alias= -unit.1.3.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.0.name=TriggerPort3[0] -unit.1.3.port.3.s.0.orderindex=-1 -unit.1.3.port.3.s.0.visible=1 -unit.1.3.port.3.s.1.alias= -unit.1.3.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.1.name=TriggerPort3[1] -unit.1.3.port.3.s.1.orderindex=-1 -unit.1.3.port.3.s.1.visible=1 -unit.1.3.port.3.s.10.alias= -unit.1.3.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.10.name=TriggerPort3[10] -unit.1.3.port.3.s.10.orderindex=-1 -unit.1.3.port.3.s.10.visible=1 -unit.1.3.port.3.s.11.alias= -unit.1.3.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.11.name=TriggerPort3[11] -unit.1.3.port.3.s.11.orderindex=-1 -unit.1.3.port.3.s.11.visible=1 -unit.1.3.port.3.s.12.alias= -unit.1.3.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.12.name=TriggerPort3[12] -unit.1.3.port.3.s.12.orderindex=-1 -unit.1.3.port.3.s.12.visible=1 -unit.1.3.port.3.s.13.alias= -unit.1.3.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.13.name=TriggerPort3[13] -unit.1.3.port.3.s.13.orderindex=-1 -unit.1.3.port.3.s.13.visible=1 -unit.1.3.port.3.s.14.alias= -unit.1.3.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.14.name=TriggerPort3[14] -unit.1.3.port.3.s.14.orderindex=-1 -unit.1.3.port.3.s.14.visible=1 -unit.1.3.port.3.s.15.alias= -unit.1.3.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.15.name=TriggerPort3[15] -unit.1.3.port.3.s.15.orderindex=-1 -unit.1.3.port.3.s.15.visible=1 -unit.1.3.port.3.s.16.alias= -unit.1.3.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.16.name=TriggerPort3[16] -unit.1.3.port.3.s.16.orderindex=-1 -unit.1.3.port.3.s.16.visible=1 -unit.1.3.port.3.s.17.alias= -unit.1.3.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.17.name=TriggerPort3[17] -unit.1.3.port.3.s.17.orderindex=-1 -unit.1.3.port.3.s.17.visible=1 -unit.1.3.port.3.s.18.alias= -unit.1.3.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.18.name=TriggerPort3[18] -unit.1.3.port.3.s.18.orderindex=-1 -unit.1.3.port.3.s.18.visible=1 -unit.1.3.port.3.s.19.alias= -unit.1.3.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.19.name=TriggerPort3[19] -unit.1.3.port.3.s.19.orderindex=-1 -unit.1.3.port.3.s.19.visible=1 -unit.1.3.port.3.s.2.alias= -unit.1.3.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.2.name=TriggerPort3[2] -unit.1.3.port.3.s.2.orderindex=-1 -unit.1.3.port.3.s.2.visible=1 -unit.1.3.port.3.s.20.alias= -unit.1.3.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.20.name=TriggerPort3[20] -unit.1.3.port.3.s.20.orderindex=-1 -unit.1.3.port.3.s.20.visible=1 -unit.1.3.port.3.s.21.alias= -unit.1.3.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.21.name=TriggerPort3[21] -unit.1.3.port.3.s.21.orderindex=-1 -unit.1.3.port.3.s.21.visible=1 -unit.1.3.port.3.s.22.alias= -unit.1.3.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.22.name=TriggerPort3[22] -unit.1.3.port.3.s.22.orderindex=-1 -unit.1.3.port.3.s.22.visible=1 -unit.1.3.port.3.s.23.alias= -unit.1.3.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.23.name=TriggerPort3[23] -unit.1.3.port.3.s.23.orderindex=-1 -unit.1.3.port.3.s.23.visible=1 -unit.1.3.port.3.s.24.alias= -unit.1.3.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.24.name=TriggerPort3[24] -unit.1.3.port.3.s.24.orderindex=-1 -unit.1.3.port.3.s.24.visible=1 -unit.1.3.port.3.s.25.alias= -unit.1.3.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.25.name=TriggerPort3[25] -unit.1.3.port.3.s.25.orderindex=-1 -unit.1.3.port.3.s.25.visible=1 -unit.1.3.port.3.s.26.alias= -unit.1.3.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.26.name=TriggerPort3[26] -unit.1.3.port.3.s.26.orderindex=-1 -unit.1.3.port.3.s.26.visible=1 -unit.1.3.port.3.s.27.alias= -unit.1.3.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.27.name=TriggerPort3[27] -unit.1.3.port.3.s.27.orderindex=-1 -unit.1.3.port.3.s.27.visible=1 -unit.1.3.port.3.s.28.alias= -unit.1.3.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.28.name=TriggerPort3[28] -unit.1.3.port.3.s.28.orderindex=-1 -unit.1.3.port.3.s.28.visible=1 -unit.1.3.port.3.s.29.alias= -unit.1.3.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.29.name=TriggerPort3[29] -unit.1.3.port.3.s.29.orderindex=-1 -unit.1.3.port.3.s.29.visible=1 -unit.1.3.port.3.s.3.alias= -unit.1.3.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.3.name=TriggerPort3[3] -unit.1.3.port.3.s.3.orderindex=-1 -unit.1.3.port.3.s.3.visible=1 -unit.1.3.port.3.s.30.alias= -unit.1.3.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.30.name=TriggerPort3[30] -unit.1.3.port.3.s.30.orderindex=-1 -unit.1.3.port.3.s.30.visible=1 -unit.1.3.port.3.s.31.alias= -unit.1.3.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.31.name=TriggerPort3[31] -unit.1.3.port.3.s.31.orderindex=-1 -unit.1.3.port.3.s.31.visible=1 -unit.1.3.port.3.s.4.alias= -unit.1.3.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.4.name=TriggerPort3[4] -unit.1.3.port.3.s.4.orderindex=-1 -unit.1.3.port.3.s.4.visible=1 -unit.1.3.port.3.s.5.alias= -unit.1.3.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.5.name=TriggerPort3[5] -unit.1.3.port.3.s.5.orderindex=-1 -unit.1.3.port.3.s.5.visible=1 -unit.1.3.port.3.s.6.alias= -unit.1.3.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.6.name=TriggerPort3[6] -unit.1.3.port.3.s.6.orderindex=-1 -unit.1.3.port.3.s.6.visible=1 -unit.1.3.port.3.s.7.alias= -unit.1.3.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.3.port.3.s.7.name=TriggerPort3[7] -unit.1.3.port.3.s.7.orderindex=-1 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-unit.1.3.waveform.posn.40.channel=40 -unit.1.3.waveform.posn.40.name=DataPort[40] -unit.1.3.waveform.posn.40.type=signal -unit.1.3.waveform.posn.41.channel=41 -unit.1.3.waveform.posn.41.name=DataPort[41] -unit.1.3.waveform.posn.41.type=signal -unit.1.3.waveform.posn.42.channel=42 -unit.1.3.waveform.posn.42.name=DataPort[42] -unit.1.3.waveform.posn.42.type=signal -unit.1.3.waveform.posn.43.channel=43 -unit.1.3.waveform.posn.43.name=DataPort[43] -unit.1.3.waveform.posn.43.type=signal -unit.1.3.waveform.posn.44.channel=44 -unit.1.3.waveform.posn.44.name=DataPort[44] -unit.1.3.waveform.posn.44.type=signal -unit.1.3.waveform.posn.45.channel=45 -unit.1.3.waveform.posn.45.name=DataPort[45] -unit.1.3.waveform.posn.45.type=signal -unit.1.3.waveform.posn.46.channel=46 -unit.1.3.waveform.posn.46.name=DataPort[46] -unit.1.3.waveform.posn.46.type=signal -unit.1.3.waveform.posn.47.channel=47 -unit.1.3.waveform.posn.47.name=DataPort[47] -unit.1.3.waveform.posn.47.type=signal -unit.1.3.waveform.posn.48.channel=48 -unit.1.3.waveform.posn.48.name=DataPort[48] -unit.1.3.waveform.posn.48.type=signal -unit.1.3.waveform.posn.49.channel=49 -unit.1.3.waveform.posn.49.name=DataPort[49] -unit.1.3.waveform.posn.49.type=signal -unit.1.3.waveform.posn.5.channel=5 -unit.1.3.waveform.posn.5.name=DataPort[5] -unit.1.3.waveform.posn.5.type=signal -unit.1.3.waveform.posn.50.channel=50 -unit.1.3.waveform.posn.50.name=DataPort[50] -unit.1.3.waveform.posn.50.type=signal -unit.1.3.waveform.posn.51.channel=51 -unit.1.3.waveform.posn.51.name=DataPort[51] -unit.1.3.waveform.posn.51.type=signal -unit.1.3.waveform.posn.52.channel=52 -unit.1.3.waveform.posn.52.name=DataPort[52] -unit.1.3.waveform.posn.52.type=signal -unit.1.3.waveform.posn.53.channel=53 -unit.1.3.waveform.posn.53.name=DataPort[53] -unit.1.3.waveform.posn.53.type=signal -unit.1.3.waveform.posn.54.channel=54 -unit.1.3.waveform.posn.54.name=DataPort[54] -unit.1.3.waveform.posn.54.type=signal -unit.1.3.waveform.posn.55.channel=55 -unit.1.3.waveform.posn.55.name=DataPort[55] -unit.1.3.waveform.posn.55.type=signal -unit.1.3.waveform.posn.56.channel=56 -unit.1.3.waveform.posn.56.name=DataPort[56] -unit.1.3.waveform.posn.56.type=signal -unit.1.3.waveform.posn.57.channel=57 -unit.1.3.waveform.posn.57.name=DataPort[57] -unit.1.3.waveform.posn.57.type=signal -unit.1.3.waveform.posn.58.channel=58 -unit.1.3.waveform.posn.58.name=DataPort[58] -unit.1.3.waveform.posn.58.type=signal -unit.1.3.waveform.posn.59.channel=59 -unit.1.3.waveform.posn.59.name=DataPort[59] -unit.1.3.waveform.posn.59.type=signal -unit.1.3.waveform.posn.6.channel=6 -unit.1.3.waveform.posn.6.name=DataPort[6] -unit.1.3.waveform.posn.6.type=signal -unit.1.3.waveform.posn.60.channel=60 -unit.1.3.waveform.posn.60.name=DataPort[60] -unit.1.3.waveform.posn.60.type=signal -unit.1.3.waveform.posn.61.channel=61 -unit.1.3.waveform.posn.61.name=DataPort[61] -unit.1.3.waveform.posn.61.type=signal -unit.1.3.waveform.posn.62.channel=62 -unit.1.3.waveform.posn.62.name=DataPort[62] -unit.1.3.waveform.posn.62.type=signal -unit.1.3.waveform.posn.63.channel=63 -unit.1.3.waveform.posn.63.name=DataPort[63] -unit.1.3.waveform.posn.63.type=signal -unit.1.3.waveform.posn.64.channel=64 -unit.1.3.waveform.posn.64.name=DataPort[64] -unit.1.3.waveform.posn.64.type=signal -unit.1.3.waveform.posn.65.channel=65 -unit.1.3.waveform.posn.65.name=DataPort[65] -unit.1.3.waveform.posn.65.type=signal -unit.1.3.waveform.posn.66.channel=66 -unit.1.3.waveform.posn.66.name=DataPort[66] -unit.1.3.waveform.posn.66.type=signal -unit.1.3.waveform.posn.67.channel=67 -unit.1.3.waveform.posn.67.name=DataPort[67] -unit.1.3.waveform.posn.67.type=signal -unit.1.3.waveform.posn.68.channel=68 -unit.1.3.waveform.posn.68.name=DataPort[68] -unit.1.3.waveform.posn.68.type=signal -unit.1.3.waveform.posn.69.channel=69 -unit.1.3.waveform.posn.69.name=DataPort[69] -unit.1.3.waveform.posn.69.type=signal -unit.1.3.waveform.posn.7.channel=7 -unit.1.3.waveform.posn.7.name=DataPort[7] -unit.1.3.waveform.posn.7.type=signal -unit.1.3.waveform.posn.70.channel=70 -unit.1.3.waveform.posn.70.name=DataPort[70] -unit.1.3.waveform.posn.70.type=signal -unit.1.3.waveform.posn.71.channel=71 -unit.1.3.waveform.posn.71.name=DataPort[71] -unit.1.3.waveform.posn.71.type=signal -unit.1.3.waveform.posn.72.channel=72 -unit.1.3.waveform.posn.72.name=DataPort[72] -unit.1.3.waveform.posn.72.type=signal -unit.1.3.waveform.posn.73.channel=73 -unit.1.3.waveform.posn.73.name=DataPort[73] -unit.1.3.waveform.posn.73.type=signal -unit.1.3.waveform.posn.74.channel=74 -unit.1.3.waveform.posn.74.name=DataPort[74] -unit.1.3.waveform.posn.74.type=signal -unit.1.3.waveform.posn.75.channel=75 -unit.1.3.waveform.posn.75.name=DataPort[75] -unit.1.3.waveform.posn.75.type=signal -unit.1.3.waveform.posn.76.channel=76 -unit.1.3.waveform.posn.76.name=DataPort[76] -unit.1.3.waveform.posn.76.type=signal -unit.1.3.waveform.posn.77.channel=77 -unit.1.3.waveform.posn.77.name=DataPort[77] -unit.1.3.waveform.posn.77.type=signal -unit.1.3.waveform.posn.78.channel=78 -unit.1.3.waveform.posn.78.name=DataPort[78] -unit.1.3.waveform.posn.78.type=signal -unit.1.3.waveform.posn.79.channel=79 -unit.1.3.waveform.posn.79.name=DataPort[79] -unit.1.3.waveform.posn.79.type=signal -unit.1.3.waveform.posn.8.channel=8 -unit.1.3.waveform.posn.8.name=DataPort[8] -unit.1.3.waveform.posn.8.type=signal -unit.1.3.waveform.posn.80.channel=80 -unit.1.3.waveform.posn.80.name=DataPort[80] -unit.1.3.waveform.posn.80.type=signal -unit.1.3.waveform.posn.81.channel=81 -unit.1.3.waveform.posn.81.name=DataPort[81] -unit.1.3.waveform.posn.81.type=signal -unit.1.3.waveform.posn.82.channel=82 -unit.1.3.waveform.posn.82.name=DataPort[82] -unit.1.3.waveform.posn.82.type=signal -unit.1.3.waveform.posn.83.channel=83 -unit.1.3.waveform.posn.83.name=DataPort[83] -unit.1.3.waveform.posn.83.type=signal -unit.1.3.waveform.posn.84.channel=84 -unit.1.3.waveform.posn.84.name=DataPort[84] -unit.1.3.waveform.posn.84.type=signal -unit.1.3.waveform.posn.85.channel=85 -unit.1.3.waveform.posn.85.name=DataPort[85] -unit.1.3.waveform.posn.85.type=signal -unit.1.3.waveform.posn.86.channel=86 -unit.1.3.waveform.posn.86.name=DataPort[86] -unit.1.3.waveform.posn.86.type=signal -unit.1.3.waveform.posn.87.channel=87 -unit.1.3.waveform.posn.87.name=DataPort[87] -unit.1.3.waveform.posn.87.type=signal -unit.1.3.waveform.posn.88.channel=88 -unit.1.3.waveform.posn.88.name=DataPort[88] -unit.1.3.waveform.posn.88.type=signal -unit.1.3.waveform.posn.89.channel=89 -unit.1.3.waveform.posn.89.name=DataPort[89] -unit.1.3.waveform.posn.89.type=signal -unit.1.3.waveform.posn.9.channel=9 -unit.1.3.waveform.posn.9.name=DataPort[9] -unit.1.3.waveform.posn.9.type=signal -unit.1.3.waveform.posn.90.channel=90 -unit.1.3.waveform.posn.90.name=DataPort[90] -unit.1.3.waveform.posn.90.type=signal -unit.1.3.waveform.posn.91.channel=91 -unit.1.3.waveform.posn.91.name=DataPort[91] -unit.1.3.waveform.posn.91.type=signal -unit.1.3.waveform.posn.92.channel=92 -unit.1.3.waveform.posn.92.name=DataPort[92] -unit.1.3.waveform.posn.92.type=signal -unit.1.3.waveform.posn.93.channel=93 -unit.1.3.waveform.posn.93.name=DataPort[93] -unit.1.3.waveform.posn.93.type=signal -unit.1.3.waveform.posn.94.channel=94 -unit.1.3.waveform.posn.94.name=DataPort[94] -unit.1.3.waveform.posn.94.type=signal -unit.1.3.waveform.posn.95.channel=95 -unit.1.3.waveform.posn.95.name=DataPort[95] -unit.1.3.waveform.posn.95.type=signal -unit.1.3.waveform.posn.96.channel=96 -unit.1.3.waveform.posn.96.name=DataPort[96] -unit.1.3.waveform.posn.96.type=signal -unit.1.3.waveform.posn.97.channel=97 -unit.1.3.waveform.posn.97.name=DataPort[97] -unit.1.3.waveform.posn.97.type=signal -unit.1.3.waveform.posn.98.channel=98 -unit.1.3.waveform.posn.98.name=DataPort[98] -unit.1.3.waveform.posn.98.type=signal -unit.1.3.waveform.posn.99.channel=99 -unit.1.3.waveform.posn.99.name=DataPort[99] -unit.1.3.waveform.posn.99.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd deleted file mode 100644 index 21542e5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc516/clk_gen.vhd +++ /dev/null @@ -1,47 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT" - ) - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf b/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf deleted file mode 100644 index 680e3658..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf +++ /dev/null @@ -1,327 +0,0 @@ -####################################################################### -# FMC516 Constraints -####################################################################### - -NET "adc_data_ch0_p_i[0]" LOC = AB32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[0]" LOC = AC32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[1]" LOC = AC33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[1]" LOC = AB33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[2]" LOC = AD32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[2]" LOC = AE32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[3]" LOC = AD34 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[3]" LOC = AC34 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[4]" LOC = AG31 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[4]" LOC = AF31 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[5]" LOC = AA26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[5]" LOC = AB26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[6]" LOC = AA25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[6]" LOC = Y26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_p_i[7]" LOC = AB28 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch0_n_i[7]" LOC = AC28 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; - -NET "adc_data_ch1_p_i[0]" LOC = AN19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[0]" LOC = AN20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[1]" LOC = AP19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[1]" LOC = AN18 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[2]" LOC = AM20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[2]" LOC = AL20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[3]" LOC = AM18 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[3]" LOC = AL18 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[4]" LOC = AK22 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[4]" LOC = AJ22 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[5]" LOC = AF19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[5]" LOC = AE19 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[6]" LOC = AC20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[6]" LOC = AD20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_p_i[7]" LOC = AF20 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch1_n_i[7]" LOC = AF21 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; - -NET "adc_data_ch2_p_i[0]" LOC = AJ24 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[0]" LOC = AK24 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[1]" LOC = AL29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[1]" LOC = AK29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[2]" LOC = AK27 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[2]" LOC = AJ27 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[3]" LOC = AN30 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[3]" LOC = AM30 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[4]" LOC = AM25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[4]" LOC = AL25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[5]" LOC = AP27 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[5]" LOC = AP26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[6]" LOC = AK23 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[6]" LOC = AL24 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_p_i[7]" LOC = AH25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; -NET "adc_data_ch2_n_i[7]" LOC = AJ25 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_0; - -NET "adc_data_ch3_p_i[0]" LOC = AJ31 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[0]" LOC = AJ32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[1]" LOC = AH33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[1]" LOC = AH32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[2]" LOC = AE28 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[2]" LOC = AE29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[3]" LOC = AJ29 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[3]" LOC = AJ30 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[4]" LOC = AF26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[4]" LOC = AE26 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[5]" LOC = AM33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[5]" LOC = AL33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[6]" LOC = AN33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[6]" LOC = AN34 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_p_i[7]" LOC = AP32 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; -NET "adc_data_ch3_n_i[7]" LOC = AP33 | IOSTANDARD = LVDSEXT_25 | TNM = TNM_ADC_DATA_1; - -NET "sys_i2c_scl_b" LOC = AK9; # Not directly connected to FMC HPC pins. There is a level shifter in the middle -NET "sys_i2c_sda_b" LOC = AE9; # Not directly connected to FMC HPC pins. There is a level shifter in the middle - -NET "adc_clk_div_rst_p_o" LOC = AM23 | IOSTANDARD = LVDS_25; -NET "adc_clk_div_rst_n_o" LOC = AL23 | IOSTANDARD = LVDS_25; - -NET "fmc_leds_o[0]" LOC = AP22 | IOSTANDARD = LVCMOS25; -NET "fmc_leds_o[1]" LOC = AN23 | IOSTANDARD = LVCMOS25; - -NET "sys_spi_clk_o" LOC = AG25 | IOSTANDARD = LVCMOS25; -NET "sys_spi_data_b" LOC = AG26 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc0_n_o" LOC = AE27 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc1_n_o" LOC = AD27 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc2_n_o" LOC = AH30 | IOSTANDARD = LVCMOS25; -NET "sys_spi_cs_adc3_n_o" LOC = AH29 | IOSTANDARD = LVCMOS25; - -NET "m2c_trig_p_i" LOC = AE33 | IOSTANDARD = LVDS_25; -NET "m2c_trig_n_i" LOC = AF33 | IOSTANDARD = LVDS_25; -NET "c2m_trig_p_o" LOC = AD29 | IOSTANDARD = LVDS_25; -NET "c2m_trig_n_o" LOC = AC29 | IOSTANDARD = LVDS_25; - -NET "lmk_lock_i" LOC = T33 | IOSTANDARD = LVCMOS25; -NET "lmk_sync_o" LOC = T34 | IOSTANDARD = LVCMOS25; -NET "lmk_uwire_latch_en_o" LOC = U31 | IOSTANDARD = LVCMOS25; -NET "lmk_uwire_data_o" LOC = U30 | IOSTANDARD = LVCMOS25; -NET "lmk_uwire_clock_o" LOC = U28 | IOSTANDARD = LVCMOS25; - -NET "vcxo_i2c_sda_b" LOC = V32 | IOSTANDARD = LVCMOS25; -NET "vcxo_i2c_scl_b" LOC = U33 | IOSTANDARD = LVCMOS25; -NET "vcxo_pd_l_o" LOC = V33 | IOSTANDARD = LVCMOS25; - -NET "fmc_id_dq_b" LOC = V30 | IOSTANDARD = LVCMOS25; -NET "fmc_key_dq_b" LOC = W30 | IOSTANDARD = LVCMOS25; - -NET "fmc_pwr_good_i" LOC = AH23 | IOSTANDARD = LVCMOS25; -NET "fmc_clk_sel_o" LOC = V29 | IOSTANDARD = LVCMOS25; -NET "fmc_reset_adcs_n_o" LOC = U32 | IOSTANDARD = LVCMOS25; -NET "fmc_prsnt_m2c_l_i" LOC = AP25; - -# MMCM Status <-> Led signals GPIO_LED_C -NET "fmc_mmcm_lock_o" LOC="AP24" | IOSTANDARD = "LVCMOS25"; -# LMK clock distribution Status <-> Led signals GPIO_LED_W -NET "fmc_lmk_lock_o" LOC="AD21" | IOSTANDARD = "LVCMOS25"; - -####################################################################### -# ADC Clock Assignments (ISLA216P) -####################################################################### - -# 250 MHz Clock -# The CLOCK_DEDICATED_ROUTE=FALSE workaround is typically for source clocks which -# are not assigned to global clock input pins - -NET "adc_clk0_p_i" TNM_NET = "adc_clk0_p_i"; -TIMESPEC "TS_adc_clk0_p_i" = PERIOD "adc_clk0_p_i" 4 ns HIGH 50%; - -NET "adc_clk1_p_i" TNM_NET = "adc_clk1_p_i"; -TIMESPEC "TS_adc_clk1_p_i" = PERIOD "adc_clk1_p_i" 4 ns HIGH 50%; - -NET "adc_clk2_p_i" TNM_NET = "adc_clk2_p_i"; -TIMESPEC "TS_adc_clk2_p_i" = PERIOD "adc_clk2_p_i" 4 ns HIGH 50%; - -NET "adc_clk3_p_i" TNM_NET = "adc_clk3_p_i"; -TIMESPEC "TS_adc_clk3_p_i" = PERIOD "adc_clk3_p_i" 4 ns HIGH 50%; - -NET "adc_clk0_p_i" LOC = "AP20" | IOSTANDARD = LVDS_25; -NET "adc_clk0_n_i" LOC = "AP21" | IOSTANDARD = LVDS_25; - -NET "adc_clk1_p_i" LOC = "AD30" | IOSTANDARD = LVDS_25; -NET "adc_clk1_n_i" LOC = "AC30" | IOSTANDARD = LVDS_25; - -NET "adc_clk2_p_i" LOC = "K24" | IOSTANDARD = LVDS_25; -NET "adc_clk2_n_i" LOC = "K23" | IOSTANDARD = LVDS_25; - -NET "adc_clk3_p_i" LOC = "AE34" | IOSTANDARD = LVDS_25; -NET "adc_clk3_n_i" LOC = "AF34" | IOSTANDARD = LVDS_25; - -####################################################################### -# ADC Data <-> Clocks Constraints (ISLA216P) -# -# From the data sheet (page 11) -# -#Output Clock to Data Propagation Delay (LVDS Mode): -# tdc Rising/Falling Edge -0.1 (min) 0.16 (typ) 0.5 (max) ns -# -#Constraint recommended by an Intersil Employee -# -#TIMEGRP "datain18_p_group" OFFSET = IN -200 ps VALID 1200 ps BEFORE "clkin18_p" RISING; -# -#This is setup for a 250MHz clock (4ns period).  The ISLA216P25 specifies -# tDC as -0.1 to +0.5 ns.  The constraint adds an additional 100ps to each side -# to account for potential skew due to the pcb.  So, the tDC ends up being -0.2 -# to 0.6 ns.  The value after IN in the constraint equal tDC min (-200ps).  -# The  value after VALID = Period/2 + tDC min – tDC max (4000ps/2 + -200ps – -# 600ps = 1200ps).  (The period is divided by two because the data is DDR.) -# -# -# OFFSET -# +---+ -# -# -------- -------- -# CLK | | | | | -# -------- -------- -# -------------------------------- -# DATA | || || || | -# -------------------------------- -# -# +------+ -# VALID -# -####################################################################### - -TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk0_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_0" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk0_p_i" FALLING; - -TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk1_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_1" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk1_p_i" FALLING; - -TIMEGRP "TNM_ADC_DATA_2" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk2_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_2" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk2_p_i" FALLING; - -TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk3_p_i" RISING; -TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk3_p_i" FALLING; - -####################################################################### -# CDC FIFO Constraints -####################################################################### - -# NET "RD_CLK" TNM_NET = "RD_CLK"; -# NET "WR_CLK" TNM_NET = "WR_CLK"; -# TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; -# TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; - -####################################################################### -# Other Constraints -####################################################################### - -# Group all IDELAY-related blocks to use a single IDELAYCTRL -INST "*cmp_fmc516_adc_iface/cmp_idelayctrl" IODELAY_GROUP = adc_idelay; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IODELAY_GROUP = adc_idelay; -INST "*cmp_fmc516_adc_iface/gen_clock_chains[?].*.*/*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = adc_idelay; - -# Overrides default_delay hdl parameter for the VARIABLE mode. -# For Virtex-6: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 24; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; - -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 8; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 7; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; - -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 10; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 9; - -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[0].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[1].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[2].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[3].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[4].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[5].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[6].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; -INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25; - -# Overrides default_delay hdl parameter - INST "*cmp_fmc516_adc_iface/gen_clock_chains[0].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; - INST "*cmp_fmc516_adc_iface/gen_clock_chains[1].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; -# INST "*cmp_fmc516_adc_iface/gen_clock_chains[2].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; -# INST "*cmp_fmc516_adc_iface/gen_clock_chains[3].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5; - -####################################################################### -# Button/LEDs Contraints -####################################################################### - -NET "buttons_i[0]" LOC = D22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[1]" LOC = C22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[2]" LOC = L21 | IOSTANDARD = LVCMOS25; -NET "buttons_i[3]" LOC = L20 | IOSTANDARD = LVCMOS25; -NET "buttons_i[4]" LOC = C18 | IOSTANDARD = LVCMOS25; -NET "buttons_i[5]" LOC = B18 | IOSTANDARD = LVCMOS25; -NET "buttons_i[6]" LOC = K22 | IOSTANDARD = LVCMOS25; -NET "buttons_i[7]" LOC = K21 | IOSTANDARD = LVCMOS25; -NET "leds_o[0]" LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[1]" LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[2]" LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[3]" LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[4]" LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[5]" LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[6]" LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; -NET "leds_o[7]" LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; - -####################################################################### -# UART Constraints -####################################################################### - -NET "uart_rxd_i" LOC = J24 | IOSTANDARD = LVCMOS25; -NET "uart_txd_o" LOC = J25 | IOSTANDARD = LVCMOS25; - -####################################################################### -# Clock and Reset Contraints -####################################################################### - -NET "sys_clk_n_i" LOC = H9 | IOSTANDARD = LVDS_25; -NET "sys_clk_p_i" LOC = J9 | IOSTANDARD = LVDS_25; -NET "sys_rst_button_i" LOC = H10 | IOSTANDARD = "SSTL15" | TIG; - -####################################################################### -# Ethernet Contraints. MII 10/100 Mode -####################################################################### - -NET "mrstn_o" LOC = AH13; -NET "mcoll_pad_i" LOC = AK13; ## 114 on U80 -NET "mcrs_pad_i" LOC = AL13; ## 115 on U80 -# NET "PHY_INT" LOC = AH14; ## 32 on U80 -NET "mdc_pad_o" LOC = AP14; ## 35 on U80 -NET "md_pad_b" LOC = AN14; ## 33 on U80 -# NET "PHY_RESET" LOC = AH13; ## 36 on U80 -NET "mrx_clk_pad_i" LOC = AP11; ## 7 on U80 -NET "mrxdv_pad_i" LOC = AM13; ## 4 on U80 -NET "mrxd_pad_i[0]" LOC = AN13; ## 3 on U80 -NET "mrxd_pad_i[1]" LOC = AF14; ## 128 on U80 -NET "mrxd_pad_i[2]" LOC = AE14; ## 126 on U80 -NET "mrxd_pad_i[3]" LOC = AN12; ## 125 on U80 -# NET "PHY_RXD4" LOC = AM12; ## 124 on U80 -# NET "PHY_RXD5" LOC = AD11; ## 123 on U80 -# NET "PHY_RXD6" LOC = AC12; ## 121 on U80 -# NET "PHY_RXD7" LOC = AC13; ## 120 on U80 -NET "mrxerr_pad_i" LOC = AG12; ## 9 on U80 -NET "mtx_clk_pad_i" LOC = AD12; ## 10 on U80 -NET "mtxen_pad_o" LOC = AJ10; ## 16 on U80 -# NET "PHY_TXC_GTXCLK" LOC = AH12; ## 14 on U80 -NET "mtxd_pad_o[0]" LOC = AM11; ## 18 on U80 -NET "mtxd_pad_o[1]" LOC = AL11; ## 19 on U80 -NET "mtxd_pad_o[2]" LOC = AG10; ## 20 on U80 -NET "mtxd_pad_o[3]" LOC = AG11; ## 24 on U80 -# NET "PHY_TXD4" LOC = AL10; ## 25 on U80 -# NET "PHY_TXD5" LOC = AM10; ## 26 on U80 -# NET "PHY_TXD6" LOC = AE11; ## 28 on U80 -# NET "PHY_TXD7" LOC = AF11; ## 29 on U80 -NET "mtxerr_pad_o" LOC = AH10; ## 13 on U80 diff --git a/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd b/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd deleted file mode 100755 index 41e4039a..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd +++ /dev/null @@ -1,1364 +0,0 @@ ------------------------------------------------------------------------------- --- Title : Top FMC516 design ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2013-02-25 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: Top design for testing the integration/control of the FMC516 -------------------------------------------------------------------------------- --- Copyright (c) 2012 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2013-02-25 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_generic_pkg.all; --- Ethernet MAC Modules and SDB structure -use work.ethmac_pkg.all; --- Wishbone Fabric interface -use work.wr_fabric_pkg.all; --- Etherbone slave core -use work.etherbone_pkg.all; --- FMC516 definitions -use work.fmc_adc_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_fmc516 is -port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - uart_txd_o : out std_logic; - uart_rxd_i : in std_logic; - - ----------------------------------------- - -- PHY pins - ----------------------------------------- - - -- Clock and resets to PHY (GMII). Not used in MII mode (10/100) - mgtx_clk_o : out std_logic; - mrstn_o : out std_logic; - - -- PHY TX - mtx_clk_pad_i : in std_logic; - mtxd_pad_o : out std_logic_vector(3 downto 0); - mtxen_pad_o : out std_logic; - mtxerr_pad_o : out std_logic; - - -- PHY RX - mrx_clk_pad_i : in std_logic; - mrxd_pad_i : in std_logic_vector(3 downto 0); - mrxdv_pad_i : in std_logic; - mrxerr_pad_i : in std_logic; - mcoll_pad_i : in std_logic; - mcrs_pad_i : in std_logic; - - -- MII - mdc_pad_o : out std_logic; - md_pad_b : inout std_logic; - - ----------------------------- - -- FMC516 ports - ----------------------------- - - -- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM, - -- AD7417 temperature diodes and AD7417 supply rails - sys_i2c_scl_b : inout std_logic; - sys_i2c_sda_b : inout std_logic; - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - adc_clk0_p_i : in std_logic; - adc_clk0_n_i : in std_logic; - adc_clk1_p_i : in std_logic; - adc_clk1_n_i : in std_logic; - adc_clk2_p_i : in std_logic; - adc_clk2_n_i : in std_logic; - adc_clk3_p_i : in std_logic; - adc_clk3_n_i : in std_logic; - - -- DDR ADC data channels. - adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0); - - -- ADC clock (half of the sampling frequency) divider reset - adc_clk_div_rst_p_o : out std_logic; - adc_clk_div_rst_n_o : out std_logic; - - -- FMC Front leds. Typical uses: Over Range or Full Scale - -- condition. - fmc_leds_o : out std_logic_vector(1 downto 0); - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - sys_spi_clk_o : out std_logic; - sys_spi_data_b : inout std_logic; - sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0 - sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1 - sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2 - sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3 - - -- External Trigger To/From FMC - m2c_trig_p_i : in std_logic; - m2c_trig_n_i : in std_logic; - c2m_trig_p_o : out std_logic; - c2m_trig_n_o : out std_logic; - - -- LMK (National Semiconductor) is the clock and distribution IC, - -- programmable via Microwire Interface - lmk_lock_i : in std_logic; - lmk_sync_o : out std_logic; - lmk_uwire_latch_en_o : out std_logic; - lmk_uwire_data_o : out std_logic; - lmk_uwire_clock_o : out std_logic; - - -- Programable VCXO via I2C - vcxo_i2c_sda_b : inout std_logic; - vcxo_i2c_scl_b : inout std_logic; - vcxo_pd_l_o : out std_logic; - - -- One-wire To/From DS2431 (VMETRO Data) - fmc_id_dq_b : inout std_logic; - -- One-wire To/From DS2432 SHA-1 (SP-Devices key) - fmc_key_dq_b : inout std_logic; - - -- General board pins - fmc_pwr_good_i : in std_logic; - -- Internal/External clock distribution selection - fmc_clk_sel_o : out std_logic; - -- Reset ADCs - fmc_reset_adcs_n_o : out std_logic; - --FMC Present status - fmc_prsnt_m2c_l_i : in std_logic; - - -- General board status - fmc_mmcm_lock_o : out std_logic; - fmc_lmk_lock_o : out std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - leds_o : out std_logic_vector(7 downto 0) -); -end dbe_bpm_fmc516; - -architecture rtl of dbe_bpm_fmc516 is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 9; - -- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC, - --Etherbone, FMC516, Peripherals - -- Number of masters - constant c_masters : natural := 8; -- LM32 master, Data + Instruction, - --DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone - - constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB) - --constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB) - constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB) - - -- GPIO num pinscalc - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- TICs counter period. 100MHz clock -> msec granularity - constant c_tics_cntr_period : natural := 100000; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - -- number of the ADC reference clock used for all downstream - -- FPGA logic - constant c_adc_ref_clk : natural := 1; - - constant c_xwb_etherbone_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"0000000000000651", -- GSI - device_id => x"68202b22", - version => x"00000001", - date => x"20120912", - name => "GSI_ETHERBONE_CFG "))); - - constant c_xwb_ethmac_adapter_sdb : t_sdb_device := ( - abi_class => x"0000", -- undocumented device - abi_ver_major => x"01", - abi_ver_minor => x"01", - wbd_endian => c_sdb_endian_big, - wbd_width => x"4", --32-bit port granularity - sdb_component => ( - addr_first => x"0000000000000000", - addr_last => x"00000000000000ff", - product => ( - vendor_id => x"1000000000001215", -- LNLS - device_id => x"2ff9a28e", - version => x"00000001", - date => x"20130701", - name => "ETHMAC_ADAPTER "))); - - -- FMC516 layout. Size (0x00000FFF) is larger than needed. Just to be sure - -- no address overlaps will occur - constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800"); - - -- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter - constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400"); - - -- WB SDB (Self describing bus) layout - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory - 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size), - x"20000000"), -- 64KB RAM - 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port - 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port - 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port - 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port - 7 => f_sdb_embed_bridge(c_fmc516_bridge_sdb, x"30010000"), -- FMC516 control port - 8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well - constant c_sdb_address : t_wishbone_address := x"30000000"; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_sys_rst : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_sys : std_logic; - signal rst_button_sys_n : std_logic; - - -- Only one clock domain - signal reset_clks : std_logic_vector(0 downto 0); - signal reset_rstn : std_logic_vector(0 downto 0); - - -- 200 Mhz clocck for iodelay_ctrl - signal clk_200mhz : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - - -- Ethernet MAC signals - signal ethmac_int : std_logic; - signal ethmac_md_in : std_logic; - signal ethmac_md_out : std_logic; - signal ethmac_md_oe : std_logic; - - signal mtxd_pad_int : std_logic_vector(3 downto 0); - signal mtxen_pad_int : std_logic; - signal mtxerr_pad_int : std_logic; - signal mdc_pad_int : std_logic; - - -- Ethrnet MAC adapter signals - signal irq_rx_done : std_logic; - signal irq_tx_done : std_logic; - - -- Etherbone signals - signal wb_ebone_out : t_wishbone_master_out; - signal wb_ebone_in : t_wishbone_master_in; - - signal eb_src_i : t_wrf_source_in; - signal eb_src_o : t_wrf_source_out; - signal eb_snk_i : t_wrf_sink_in; - signal eb_snk_o : t_wrf_sink_out; - - -- DMA signals - signal dma_int : std_logic; - - -- FMC516 Signals - signal wbs_fmc516_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0); - signal wbs_fmc516_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0); - - signal fmc516_mmcm_lock_int : std_logic; - signal fmc516_lmk_lock_int : std_logic; - - signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0); - signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal fmc_debug : std_logic; - signal reset_adc_counter : unsigned(6 downto 0) := (others => '0'); - signal fmc516_fs_rst_n : std_logic; - - -- FMC516 Debug - signal fmc516_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0); - signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0); - - signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0); - - signal sys_spi_clk_int : std_logic; - --signal sys_spi_data_int : std_logic; - signal sys_spi_dout_int : std_logic; - signal sys_spi_din_int : std_logic; - signal sys_spi_miosio_oe_n_int : std_logic; - signal sys_spi_cs_adc0_n_int : std_logic; - signal sys_spi_cs_adc1_n_int : std_logic; - signal sys_spi_cs_adc2_n_int : std_logic; - signal sys_spi_cs_adc3_n_int : std_logic; - - signal lmk_lock_int : std_logic; - signal lmk_sync_int : std_logic; - signal lmk_uwire_latch_en_int : std_logic; - signal lmk_uwire_data_int : std_logic; - signal lmk_uwire_clock_int : std_logic; - - signal fmc_reset_adcs_n_int : std_logic; - signal fmc_reset_adcs_n_out : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - -- Counter signal - --signal s_counter : unsigned(c_counter_width-1 downto 0); - -- 100MHz period or 1 second - --constant s_counter_full : integer := 100000000; - - -- Chipscope control signals - signal CONTROL0 : std_logic_vector(35 downto 0); - signal CONTROL1 : std_logic_vector(35 downto 0); - signal CONTROL2 : std_logic_vector(35 downto 0); - signal CONTROL3 : std_logic_vector(35 downto 0); - - -- Chipscope ILA 0 signals - --signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - --signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - - signal TRIG_ILA0_0 : std_logic_vector(7 downto 0); - signal TRIG_ILA0_1 : std_logic_vector(15 downto 0); - signal TRIG_ILA0_2 : std_logic_vector(15 downto 0); - signal TRIG_ILA0_3 : std_logic_vector(15 downto 0); - signal TRIG_ILA0_4 : std_logic_vector(15 downto 0); - - -- Chipscope ILA 1 signals - signal TRIG_ILA1_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 2 signals - signal TRIG_ILA2_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA2_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 3 signals - signal TRIG_ILA3_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA3_3 : std_logic_vector(31 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic - ); - end component; - - -- Xilinx Megafunction - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Controller 2 port - --component chipscope_icon_2_port - --port ( - -- CONTROL0 : inout std_logic_vector(35 downto 0); - -- CONTROL1 : inout std_logic_vector(35 downto 0) - --); - --end component; - - component chipscope_icon_4_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0); - CONTROL2 : inout std_logic_vector(35 downto 0); - CONTROL3 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0) - ); - end component; - - component chipscope_ila_131072 - port ( - control: inout std_logic_vector(35 downto 0); - clk: in std_logic; - trig0: in std_logic_vector(7 downto 0); - trig1: in std_logic_vector(15 downto 0); - trig2: in std_logic_vector(15 downto 0); - trig3: in std_logic_vector(15 downto 0); - trig4: in std_logic_vector(15 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; - -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - clk_i => sys_clk_gen, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - cmp_reset : gc_reset - generic map( - g_clocks => 1 -- CLK_SYS - ) - port map( - free_clk_i => sys_clk_gen, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - reset_clks(0) <= clk_sys; - clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n; - clk_sys_rst <= not clk_sys_rstn; - mrstn_o <= clk_sys_rstn; - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - rst_button_sys_n <= not rst_button_sys; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => true, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - lm32_rstn <= clk_sys_rstn; - - cmp_lm32 : xwb_lm32 - generic map( - g_profile => "medium_icache_debug" - ) -- Including JTAG and I-cache (no divide) - port map( - clk_sys_i => clk_sys, - rst_n_i => lm32_rstn, - irq_i => lm32_interrupt, - dwb_o => cbar_slave_i(0), -- Data bus - dwb_i => cbar_slave_o(0), - iwb_o => cbar_slave_i(1), -- Instruction bus - iwb_i => cbar_slave_o(1) - ); - - -- Interrupt '0' is Ethmac. - -- Interrupt '1' is DMA completion. - -- Interrupt '2' is Button(0). - -- Interrupt '3' is Ethernet Adapter RX completion. - -- Interrupt '4' is Ethernet Adapter TX completion. - -- Interrupts 31 downto 5 are disabled - - lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done, - 4 => irq_tx_done, others => '0'); - - -- A DMA controller is master 2+3, slave 3, and interrupt 1 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(3), - slave_o => cbar_master_i(3), - r_master_i => cbar_slave_o(2), - r_master_o => cbar_slave_i(2), - w_master_i => cbar_slave_o(3), - w_master_o => cbar_slave_i(3), - interrupt_o => dma_int - ); - - -- Slave 0+1 is the RAM. Load a input file containing the embedded software - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - g_init_file => "../../../embedded-sw/dbe.ram", - --"../../top/ml_605/dbe_bpm_simple/sw/main.ram", - g_must_have_init_file => true, - g_slave1_interface_mode => PIPELINED, - g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE, - g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - ); - - -- Slave 2 is the RAM Buffer for Ethernet MAC. - cmp_ethmac_buf_ram : xwb_dpram - generic map( - g_size => c_dpram_ethbuf_size, - g_init_file => "", - g_must_have_init_file => false, - g_slave1_interface_mode => CLASSIC, - --g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE - --g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(2), - slave1_o => cbar_master_i(2), - -- Second port connected to the crossbar - slave2_i => cc_dummy_slave_in, -- CYC always low - slave2_o => open - ); - - -- The Ethernet MAC is master 4, slave 4 - cmp_xwb_ethmac : xwb_ethmac - generic map ( - --g_ma_interface_mode => PIPELINED, - g_ma_interface_mode => CLASSIC, -- NOT used for now - --g_ma_address_granularity => WORD, - g_ma_address_granularity => BYTE, -- NOT used for now - g_sl_interface_mode => PIPELINED, - --g_sl_interface_mode => CLASSIC, - --g_sl_address_granularity => WORD - g_sl_address_granularity => BYTE - ) - port map( - -- WISHBONE common - wb_clk_i => clk_sys, - wb_rst_i => clk_sys_rst, - - -- WISHBONE slave - wb_slave_in => cbar_master_o(4), - wb_slave_out => cbar_master_i(4), - - -- WISHBONE master - wb_master_in => cbar_slave_o(4), - wb_master_out => cbar_slave_i(4), - - -- PHY TX - mtx_clk_pad_i => mtx_clk_pad_i, - --mtxd_pad_o => mtxd_pad_o, - mtxd_pad_o => mtxd_pad_int, - --mtxen_pad_o => mtxen_pad_o, - mtxen_pad_o => mtxen_pad_int, - --mtxerr_pad_o => mtxerr_pad_o, - mtxerr_pad_o => mtxerr_pad_int, - - -- PHY RX - mrx_clk_pad_i => mrx_clk_pad_i, - mrxd_pad_i => mrxd_pad_i, - mrxdv_pad_i => mrxdv_pad_i, - mrxerr_pad_i => mrxerr_pad_i, - mcoll_pad_i => mcoll_pad_i, - mcrs_pad_i => mcrs_pad_i, - - -- MII - --mdc_pad_o => mdc_pad_o, - mdc_pad_o => mdc_pad_int, - md_pad_i => ethmac_md_in, - md_pad_o => ethmac_md_out, - md_padoe_o => ethmac_md_oe, - - -- Interrupt - int_o => ethmac_int - ); - - -- Tri-state buffer for MII config - md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z'; - ethmac_md_in <= md_pad_b; - - mtxd_pad_o <= mtxd_pad_int; - mtxen_pad_o <= mtxen_pad_int; - mtxerr_pad_o <= mtxerr_pad_int; - mdc_pad_o <= mdc_pad_int; - - -- The Ethernet MAC Adapter is master 5+6, slave 5 - cmp_xwb_ethmac_adapter : xwb_ethmac_adapter - port map( - clk_i => clk_sys, - rstn_i => clk_sys_rstn, - - wb_slave_o => cbar_master_i(5), - wb_slave_i => cbar_master_o(5), - - tx_ram_o => cbar_slave_i(5), - tx_ram_i => cbar_slave_o(5), - - rx_ram_o => cbar_slave_i(6), - rx_ram_i => cbar_slave_o(6), - - rx_eb_o => eb_snk_i, - rx_eb_i => eb_snk_o, - - tx_eb_o => eb_src_i, - tx_eb_i => eb_src_o, - - irq_tx_done_o => irq_tx_done, - irq_rx_done_o => irq_rx_done - ); - - -- The Etherbone is slave 6 - cmp_eb_slave_core : eb_slave_core - generic map( - g_sdb_address => x"00000000" & c_sdb_address - ) - port map - ( - clk_i => clk_sys, - nRst_i => clk_sys_rstn, - - -- EB streaming sink - snk_i => eb_snk_i, - snk_o => eb_snk_o, - - -- EB streaming source - src_i => eb_src_i, - src_o => eb_src_o, - - -- WB slave - Cfg IF - cfg_slave_o => cbar_master_i(6), - cfg_slave_i => cbar_master_o(6), - - -- WB master - Bus IF - master_o => wb_ebone_out, - master_i => wb_ebone_in - ); - - cbar_slave_i(7) <= wb_ebone_out; - wb_ebone_in <= cbar_slave_o(7); - - -- The FMC516 is slave 7 - cmp_xwb_fmc516 : xwb_fmc516 - generic map( - g_fpga_device => "VIRTEX6", - g_interface_mode => PIPELINED, - --g_address_granularity => WORD, - g_address_granularity => BYTE, - g_adc_clk_period_values => default_adc_clk_period_values, - --g_use_clk_chains => default_clk_use_chain, - -- using clock1 from FMC516 (CLK2_ M2C_P, CLK2_ M2C_M pair) - -- using clock0 from FMC516. - -- BUFIO can drive half-bank only, not the full IO bank - g_use_clk_chains => "0011", - g_use_data_chains => "1111", - g_map_clk_data_chains => (1,0,0,1), - -- Clock 1 is the adc reference clock - g_ref_clk => c_adc_ref_clk, - g_packet_size => 32, - g_sim => 0 - ) - port map( - sys_clk_i => clk_sys, - sys_rst_n_i => clk_sys_rstn, - sys_clk_200Mhz_i => clk_200mhz, - - ----------------------------- - -- Wishbone Control Interface signals - ----------------------------- - wb_slv_i => cbar_master_o(7), - wb_slv_o => cbar_master_i(7), - - ----------------------------- - -- External ports - ----------------------------- - -- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM, - -- AD7417 temperature diodes and AD7417 supply rails - sys_i2c_scl_b => sys_i2c_scl_b, - sys_i2c_sda_b => sys_i2c_sda_b, - - -- ADC clocks. One clock per ADC channel. - -- Only ch1 clock is used as all data chains - -- are sampled at the same frequency - adc_clk0_p_i => adc_clk0_p_i, - adc_clk0_n_i => adc_clk0_n_i, - adc_clk1_p_i => adc_clk1_p_i, - adc_clk1_n_i => adc_clk1_n_i, - adc_clk2_p_i => adc_clk2_p_i, - adc_clk2_n_i => adc_clk2_n_i, - adc_clk3_p_i => adc_clk3_p_i, - adc_clk3_n_i => adc_clk3_n_i, - - -- DDR ADC data channels. - adc_data_ch0_p_i => adc_data_ch0_p_i, - adc_data_ch0_n_i => adc_data_ch0_n_i, - adc_data_ch1_p_i => adc_data_ch1_p_i, - adc_data_ch1_n_i => adc_data_ch1_n_i, - adc_data_ch2_p_i => adc_data_ch2_p_i, - adc_data_ch2_n_i => adc_data_ch2_n_i, - adc_data_ch3_p_i => adc_data_ch3_p_i, - adc_data_ch3_n_i => adc_data_ch3_n_i, - - -- ADC clock (half of the sampling frequency) divider reset - adc_clk_div_rst_p_o => adc_clk_div_rst_p_o, - adc_clk_div_rst_n_o => adc_clk_div_rst_n_o, - - -- FMC Front leds. Typical uses: Over Range or Full Scale - -- condition. - fmc_leds_o => fmc_leds_o, - - -- ADC SPI control interface. Three-wire mode. Tri-stated data pin - sys_spi_clk_o => sys_spi_clk_int, - sys_spi_data_b => sys_spi_data_b, - --sys_spi_dout_o => sys_spi_dout_int, - --sys_spi_din_i => sys_spi_din_int, - sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0 - sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1 - sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2 - sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3 - --sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int, - - -- External Trigger To/From FMC - m2c_trig_p_i => m2c_trig_p_i, - m2c_trig_n_i => m2c_trig_n_i, - c2m_trig_p_o => c2m_trig_p_o, - c2m_trig_n_o => c2m_trig_n_o, - - -- LMK (National Semiconductor) is the clock and distribution IC. - -- uWire interface - lmk_lock_i => lmk_lock_int,--lmk_lock_i, - lmk_sync_o => lmk_sync_int,--lmk_sync_o, - lmk_uwire_latch_en_o => lmk_uwire_latch_en_int,--lmk_uwire_latch_en_o, - lmk_uwire_data_o => lmk_uwire_data_int,--lmk_uwire_data_o, - lmk_uwire_clock_o => lmk_uwire_clock_int,--lmk_uwire_clock_o, - - -- Programable VCXO via I2C - vcxo_i2c_sda_b => vcxo_i2c_sda_b, - vcxo_i2c_scl_b => vcxo_i2c_scl_b, - vcxo_pd_l_o => vcxo_pd_l_o, - - -- One-wire To/From DS2431 (VMETRO Data) - fmc_id_dq_b => fmc_id_dq_b, - -- One-wire To/From DS2432 SHA-1 (SP-Devices key) - fmc_key_dq_b => fmc_key_dq_b, - - -- General board pins - fmc_pwr_good_i => fmc_pwr_good_i, - -- Internal/External clock distribution selection - fmc_clk_sel_o => fmc_clk_sel_o, - -- Reset ADCs - fmc_reset_adcs_n_o => fmc_reset_adcs_n_int,--fmc_reset_adcs_n_o, - --fmc_reset_adcs_n_o => open,--fmc_reset_adcs_n_o, - --FMC Present status - fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i, - - ----------------------------- - -- ADC output signals. Continuous flow. - ----------------------------- - adc_clk_o => fmc516_fs_clk, - adc_clk2x_o => fmc516_fs_clk2x, - adc_data_o => fmc516_adc_data, - adc_data_valid_o => fmc516_adc_valid, - - ----------------------------- - -- General ADC output signals - ----------------------------- - -- Trigger to other FPGA logic - trig_hw_o => open, - trig_hw_i => '0', - -- General board status - fmc_mmcm_lock_o => fmc516_mmcm_lock_int, - fmc_lmk_lock_o => fmc516_lmk_lock_int, - - ----------------------------- - -- Wishbone Streaming Interface Source - ----------------------------- - wbs_source_i => wbs_fmc516_in_array, - wbs_source_o => wbs_fmc516_out_array, - - adc_dly_debug_o => adc_dly_debug_int, - - fifo_debug_valid_o => fmc516_debug_valid_int, - fifo_debug_full_o => fmc516_debug_full_int, - fifo_debug_empty_o => fmc516_debug_empty_int - ); - - gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate - wbs_fmc516_in_array(i) <= cc_dummy_src_com_in; - end generate; - - fmc_mmcm_lock_o <= fmc516_mmcm_lock_int; - fmc_lmk_lock_o <= fmc516_lmk_lock_int; - - -- Tri-state buffer for SPI three-wire mode - --sys_spi_data_b <= sys_spi_dout_int when sys_spi_miosio_oe_n_int = '0' else 'Z'; - --sys_spi_din_int <= sys_spi_data_b; - - sys_spi_clk_o <= sys_spi_clk_int; - sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int; - sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int; - sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int; - sys_spi_cs_adc3_n_o <= sys_spi_cs_adc3_n_int; - - lmk_lock_int <= lmk_lock_i; - lmk_sync_o <= lmk_sync_int; - lmk_uwire_latch_en_o <= lmk_uwire_latch_en_int; - lmk_uwire_data_o <= lmk_uwire_data_int; - lmk_uwire_clock_o <= lmk_uwire_clock_int; - - -- Reset FMC516 ADCs - fmc_reset_adcs_n_o <= fmc_reset_adcs_n_out; - --fmc516_fs_rst_n <= clk_sys_rstn and fmc516_mmcm_lock_int; - -- Do not use mmcm_lock as reset. - fmc516_fs_rst_n <= clk_sys_rstn; - - p_fmc516_reset_adcs : process(fmc516_fs_clk(c_adc_ref_clk)) - begin - if rising_edge(fmc516_fs_clk(c_adc_ref_clk)) then - if (fmc516_fs_rst_n = '0' or fmc_reset_adcs_n_int = '0') then - fmc_reset_adcs_n_out <= '1'; - reset_adc_counter <= (others => '0'); - elsif reset_adc_counter = "1111111" then - fmc_reset_adcs_n_out <= '1'; - else - reset_adc_counter <= reset_adc_counter + 1; - fmc_reset_adcs_n_out <= '0'; - end if; - end if; - end process; - - --p_debug : process(sys_spi_clk_int) - --begin - -- if rising_edge(sys_spi_clk_int) then - -- if (clk_sys_rstn = '0') then - -- fmc_debug <= '0'; - -- else - -- fmc_debug <= sys_spi_dout_int and - -- ((not sys_spi_cs_adc0_n_int) or - -- (not sys_spi_cs_adc1_n_int) or - -- (not sys_spi_cs_adc2_n_int) or - -- (not sys_spi_cs_adc3_n_int)); - -- end if; - -- end if; - --end process; - - -- The board peripherals components is slave 8 - cmp_xwb_dbe_periph : xwb_dbe_periph - generic map( - -- NOT used! - --g_interface_mode : t_wishbone_interface_mode := CLASSIC; - -- NOT used! - --g_address_granularity : t_wishbone_address_granularity := WORD; - g_cntr_period => c_tics_cntr_period, - g_num_leds => c_leds_num_pins, - g_num_buttons => c_buttons_num_pins - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- UART - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o, - - -- LEDs - led_out_o => gpio_leds_int, - led_in_i => gpio_leds_int, - led_oen_o => open, - - -- Buttons - button_out_o => open, - button_in_i => buttons_i, - button_oen_o => open, - - -- Wishbone - slave_i => cbar_master_o(8), - slave_o => cbar_master_i(8) - ); - - leds_o <= gpio_leds_int; - - ---- Slave 7 is the UART - --cmp_uart : xwb_simple_uart - --generic map ( - -- g_interface_mode => PIPELINED, - -- g_address_granularity => BYTE - --) - --port map ( - -- clk_sys_i => clk_sys, - -- rst_n_i => clk_sys_rstn, - -- slave_i => cbar_master_o(7), - -- slave_o => cbar_master_i(7), - -- uart_rxd_i => uart_rxd_i, - -- uart_txd_o => uart_txd_o - --); - -- - ---- Slave 8 is the LED driver - --cmp_leds : xwb_gpio_port - --generic map( - -- g_interface_mode => CLASSIC, - -- g_address_granularity => BYTE, - -- g_num_pins => c_leds_num_pins, - -- g_with_builtin_tristates => false - --) - --port map( - -- clk_sys_i => clk_sys, - -- rst_n_i => clk_sys_rstn, - -- - -- -- Wishbone - -- slave_i => cbar_master_o(8), - -- slave_o => cbar_master_i(8), - -- desc_o => open, -- Not implemented - -- - -- --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0); - -- - -- gpio_out_o => gpio_leds_int, - -- gpio_in_i => gpio_leds_int, - -- gpio_oen_o => open - --); - -- - --leds_o <= gpio_leds_int; - -- - ---- Slave 9 is the Button driver - --cmp_buttons : xwb_gpio_port - --generic map( - -- g_interface_mode => CLASSIC, - -- g_address_granularity => BYTE, - -- g_num_pins => c_buttons_num_pins, - -- g_with_builtin_tristates => false - --) - --port map( - -- clk_sys_i => clk_sys, - -- rst_n_i => clk_sys_rstn, - -- - -- -- Wishbone - -- slave_i => cbar_master_o(9), - -- slave_o => cbar_master_i(9), - -- desc_o => open, -- Not implemented - -- - -- --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0); - -- - -- gpio_out_o => open, - -- gpio_in_i => buttons_i, - -- gpio_oen_o => open - --); - - ---- Xilinx Chipscope - cmp_chipscope_icon_0 : chipscope_icon_4_port - port map ( - CONTROL0 => CONTROL0, - CONTROL1 => CONTROL1, - CONTROL2 => CONTROL2, - CONTROL3 => CONTROL3 - ); - - --cmp_chipscope_ila_0_fmc516_clk0 : chipscope_ila - --port map ( - -- CONTROL => CONTROL0, - -- --CLK => clk_sys, - -- CLK => fmc516_fs_clk(c_adc_ref_clk), - -- --CLK => fmc516_fs_clk(1), - -- TRIG0 => TRIG_ILA0_0, - -- TRIG1 => TRIG_ILA0_1, - -- TRIG2 => TRIG_ILA0_2, - -- TRIG3 => TRIG_ILA0_3 - --); - - cmp_chipscope_ila_131072_0_adc : chipscope_ila_131072 - port map ( - CONTROL => CONTROL0, - CLK => fmc516_fs_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA0_0, - TRIG1 => TRIG_ILA0_1, - TRIG2 => TRIG_ILA0_2, - TRIG3 => TRIG_ILA0_3, - TRIG4 => TRIG_ILA0_4 - ); - - TRIG_ILA0_0(0) <= '0'; - TRIG_ILA0_0(1) <= '0'; - TRIG_ILA0_0(2) <= '0'; - TRIG_ILA0_0(3) <= '0'; - TRIG_ILA0_0(4) <= '0'; - TRIG_ILA0_0(5) <= '0'; - TRIG_ILA0_0(6) <= '0'; - TRIG_ILA0_0(7) <= '0'; - - -- ADC Data - TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0); - TRIG_ILA0_2 <= fmc516_adc_data(31 downto 16); - TRIG_ILA0_3 <= fmc516_adc_data(47 downto 32); - TRIG_ILA0_4 <= fmc516_adc_data(63 downto 48); - - ---- FMC516 WBS master output data - ----TRIG_ILA0_0 <= wbs_fmc516_out_array(3).dat & - ---- wbs_fmc516_out_array(2).dat; - -- - --TRIG_ILA0_0 <= fmc516_adc_data(31 downto 16) & - -- fmc516_adc_data(15 downto 0); - --TRIG_ILA0_1 <= fmc516_adc_data(63 downto 48) & - -- fmc516_adc_data(47 downto 32); - -- - ---- FMC516 WBS master output data - ----TRIG_ILA0_1 <= wbs_fmc516_out_array(1).dat & - ---- wbs_fmc516_out_array(0).dat; - ----TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0) & - ---- fmc516_adc_data(47 downto 32); - ----TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse & - ---- adc_dly_debug_int(1).data_chain.idelay.pulse & - ---- adc_dly_debug_int(1).clk_chain.idelay.val & - ---- adc_dly_debug_int(1).data_chain.idelay.val; - ----TRIG_ILA0_1(31 downto 12) <= (others => '0'); - -- - ---- FMC516 WBS master output control signals - --TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc & - -- wbs_fmc516_out_array(1).stb & - -- wbs_fmc516_out_array(1).adr & - -- wbs_fmc516_out_array(1).sel & - -- wbs_fmc516_out_array(1).we & - -- wbs_fmc516_out_array(2).cyc & - -- wbs_fmc516_out_array(2).stb & - -- wbs_fmc516_out_array(2).adr & - -- wbs_fmc516_out_array(2).sel & - -- wbs_fmc516_out_array(2).we; - --TRIG_ILA0_2(18) <= fmc_reset_adcs_n_out; - --TRIG_ILA0_2(22 downto 19) <= fmc516_adc_valid; - --TRIG_ILA0_2(23) <= fmc516_mmcm_lock_int; - --TRIG_ILA0_2(24) <= fmc516_lmk_lock_int; - --TRIG_ILA0_2(25) <= fmc516_debug_valid_int(1); - --TRIG_ILA0_2(26) <= fmc516_debug_full_int(1); - --TRIG_ILA0_2(27) <= fmc516_debug_empty_int(1); - --TRIG_ILA0_2(31 downto 28) <= (others => '0'); - -- - ---- FMC516 WBS master output control signals - ----TRIG_ILA0_3(17 downto 0) <= wbs_fmc516_out_array(1).cyc & - ---- wbs_fmc516_out_array(1).stb & - ---- wbs_fmc516_out_array(1).adr & - ---- wbs_fmc516_out_array(1).sel & - ---- wbs_fmc516_out_array(1).we & - ---- wbs_fmc516_out_array(0).cyc & - ---- wbs_fmc516_out_array(0).stb & - ---- wbs_fmc516_out_array(0).adr & - ---- wbs_fmc516_out_array(0).sel & - ---- wbs_fmc516_out_array(0).we; - ----TRIG_ILA0_3(18) <= fmc_reset_adcs_n_out; - ----TRIG_ILA0_3(22 downto 19) <= fmc516_adc_valid; - ----TRIG_ILA0_3(23) <= fmc516_mmcm_lock_int; - ----TRIG_ILA0_3(24) <= fmc516_lmk_lock_int; - ----TRIG_ILA0_3(25) <= fmc516_debug_valid_int(1); - ----TRIG_ILA0_3(26) <= fmc516_debug_full_int(1); - ----TRIG_ILA0_3(27) <= fmc516_debug_empty_int(1); - ----TRIG_ILA0_3(31 downto 28) <= (others => '0'); - --TRIG_ILA0_3 <= (others => '0'); - -- - ---- Etherbone debuging signals - ----cmp_chipscope_ila_1_etherbone : chipscope_ila - ----port map ( - ---- CONTROL => CONTROL1, - ---- CLK => clk_sys, - ---- TRIG0 => TRIG_ILA1_0, - ---- TRIG1 => TRIG_ILA1_1, - ---- TRIG2 => TRIG_ILA1_2, - ---- TRIG3 => TRIG_ILA1_3 - ----); - -- - ----TRIG_ILA1_0 <= wb_ebone_out.dat; - ----TRIG_ILA1_1 <= wb_ebone_in.dat; - ----TRIG_ILA1_2 <= wb_ebone_out.adr; - ----TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc & - ---- wb_ebone_out.stb & - ---- wb_ebone_out.sel & - ---- wb_ebone_out.we; - ----TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack & - ---- wb_ebone_in.err & - ---- wb_ebone_in.rty & - ---- wb_ebone_in.stall & - ---- wb_ebone_in.int; - ----TRIG_ILA1_3(31 downto 12) <= (others => '0'); - -- - ----cmp_chipscope_ila_1_ethmac_rx : chipscope_ila - ----port map ( - ---- CONTROL => CONTROL1, - ---- CLK => mrx_clk_pad_i, - ---- TRIG0 => TRIG_ILA1_0, - ---- TRIG1 => TRIG_ILA1_1, - ---- TRIG2 => TRIG_ILA1_2, - ---- TRIG3 => TRIG_ILA1_3 - ----); - ---- - ----TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i & - ---- mrxdv_pad_i & - ---- mrxerr_pad_i & - ---- mcoll_pad_i & - ---- mcrs_pad_i; - ---- - ----TRIG_ILA1_0(31 downto 8) <= (others => '0'); - ----TRIG_ILA1_1 <= (others => '0'); - ----TRIG_ILA1_2 <= (others => '0'); - ----TRIG_ILA1_3 <= (others => '0'); - - cmp_chipscope_ila_1_fmc516_clk1 : chipscope_ila - port map ( - CONTROL => CONTROL1, - --CLK => fmc516_fs_clk(1), - CLK => fmc516_fs_clk(c_adc_ref_clk), - TRIG0 => TRIG_ILA1_0, - TRIG1 => TRIG_ILA1_1, - TRIG2 => TRIG_ILA1_2, - TRIG3 => TRIG_ILA1_3 - ); - - -- FMC516 WBS master output data - TRIG_ILA1_0 <= fmc516_adc_data(15 downto 0) & - fmc516_adc_data(63 downto 48); - - -- FMC516 WBS master output data - TRIG_ILA1_1 <= (others => '0'); - - -- FMC516 WBS master output control signals - TRIG_ILA1_2(17 downto 0) <= wbs_fmc516_out_array(0).cyc & - wbs_fmc516_out_array(0).stb & - wbs_fmc516_out_array(0).adr & - wbs_fmc516_out_array(0).sel & - wbs_fmc516_out_array(0).we & - wbs_fmc516_out_array(3).cyc & - wbs_fmc516_out_array(3).stb & - wbs_fmc516_out_array(3).adr & - wbs_fmc516_out_array(3).sel & - wbs_fmc516_out_array(3).we; - TRIG_ILA1_2(18) <= fmc_reset_adcs_n_out; - TRIG_ILA1_2(22 downto 19) <= fmc516_adc_valid; - TRIG_ILA1_2(23) <= fmc516_mmcm_lock_int; - TRIG_ILA1_2(24) <= fmc516_lmk_lock_int; - TRIG_ILA1_2(25) <= fmc516_debug_valid_int(0); - TRIG_ILA1_2(26) <= fmc516_debug_full_int(0); - TRIG_ILA1_2(27) <= fmc516_debug_empty_int(0); - TRIG_ILA1_2(31 downto 28) <= (others => '0'); - - TRIG_ILA1_3 <= (others => '0'); - - cmp_chipscope_ila_2_ethmac_tx : chipscope_ila - port map ( - CONTROL => CONTROL2, - CLK => mtx_clk_pad_i, - TRIG0 => TRIG_ILA2_0, - TRIG1 => TRIG_ILA2_1, - TRIG2 => TRIG_ILA2_2, - TRIG3 => TRIG_ILA2_3 - ); - - TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int & - mtxen_pad_int & - mtxerr_pad_int; - - TRIG_ILA2_0(31 downto 6) <= (others => '0'); - TRIG_ILA2_1 <= (others => '0'); - TRIG_ILA2_2 <= (others => '0'); - TRIG_ILA2_3 <= (others => '0'); - - --cmp_chipscope_ila_3_ethmac_miim : chipscope_ila - --port map ( - -- CONTROL => CONTROL3, - -- CLK => clk_sys, - -- TRIG0 => TRIG_ILA3_0, - -- TRIG1 => TRIG_ILA3_1, - -- TRIG2 => TRIG_ILA3_2, - -- TRIG3 => TRIG_ILA3_3 - --); - -- - --TRIG_ILA3_0(4 downto 0) <= mdc_pad_int & - -- ethmac_md_in & - -- ethmac_md_out & - -- ethmac_md_oe & - -- ethmac_int; - -- - --TRIG_ILA3_0(31 downto 6) <= (others => '0'); - --TRIG_ILA3_1 <= (others => '0'); - --TRIG_ILA3_2 <= (others => '0'); - --TRIG_ILA3_3 <= (others => '0'); - - -- The clocks to/from peripherals are derived from the bus clock. - -- Therefore we don't have to worry about synchronization here, just - -- keep in mind that the data/ss lines will appear longer than normal - cmp_chipscope_ila_3_fmc516_periph : chipscope_ila - port map ( - CONTROL => CONTROL3, - CLK => clk_sys, - TRIG0 => TRIG_ILA3_0, - TRIG1 => TRIG_ILA3_1, - TRIG2 => TRIG_ILA3_2, - TRIG3 => TRIG_ILA3_3 - ); - - TRIG_ILA3_0(7 downto 0) <= sys_spi_clk_int & - --sys_spi_data_int & - sys_spi_din_int & - sys_spi_dout_int & - sys_spi_miosio_oe_n_int & - sys_spi_cs_adc0_n_int & -- SPI ADC CS channel 0 - sys_spi_cs_adc1_n_int & -- SPI ADC CS channel 1 - sys_spi_cs_adc2_n_int & -- SPI ADC CS channel 2 - sys_spi_cs_adc3_n_int; -- SPI ADC CS channel 3 - - TRIG_ILA3_0(31 downto 8) <= (others => '0'); - - TRIG_ILA3_1(4 downto 0) <= lmk_lock_int & - lmk_sync_int & - lmk_uwire_latch_en_int & - lmk_uwire_data_int & - lmk_uwire_clock_int; - - TRIG_ILA3_1(31 downto 5) <= (others => '0'); - TRIG_ILA3_2 <= (others => '0'); - TRIG_ILA3_3 <= (others => '0'); - -end rtl; diff --git a/hdl/top/ml_605/dbe_bpm_fmc516/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_fmc516/sys_pll.vhd deleted file mode 100644 index 036e6b5b..00000000 --- a/hdl/top/ml_605/dbe_bpm_fmc516/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is -generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 -); -port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic -); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/ml_605/dbe_bpm_simple/Manifest.py b/hdl/top/ml_605/dbe_bpm_simple/Manifest.py deleted file mode 100644 index ca95be41..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/Manifest.py +++ /dev/null @@ -1,3 +0,0 @@ -files = [ "dbe_bpm_simple_top.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_bpm_simple_top.ucf" ]; - -modules = { "local" : ["../../.." ] }; diff --git a/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd b/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd deleted file mode 100644 index b76c00f9..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd +++ /dev/null @@ -1,47 +0,0 @@ -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity clk_gen is -port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic -); -end clk_gen; - -architecture syn of clk_gen is - - -- Internal clock signal - signal s_sys_clk : std_logic; - -begin - - -- IBUFGDS: Differential Global Clock Input Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cpm_ibufgds_clk_gen : IBUFGDS - generic map ( - DIFF_TERM => FALSE, -- Differential Termination - IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards - IOSTANDARD => "DEFAULT") - port map ( - O => s_sys_clk, -- Clock buffer output - I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port) - IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port) - ); - - -- BUFG: Global Clock Buffer - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - cmp_bufg_clk_gen : BUFG - port map ( - O => sys_clk_o, -- 1-bit output: Clock buffer output - I => s_sys_clk -- 1-bit input: Clock buffer input - ); - -end syn; diff --git a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple.cpj b/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple.cpj deleted file mode 100644 index 03cfe7b7..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple.cpj +++ /dev/null @@ -1,4074 +0,0 @@ -#ChipScope Pro Analyzer Project File, Version 3.0 -#Wed Oct 24 16:57:08 BRST 2012 -deviceChain.deviceName0=System_ACE_CF -deviceChain.deviceName1=XC6VLX240T -deviceChain.iRLength0=8 -deviceChain.iRLength1=10 -deviceChain.name0=MyDevice0 -deviceChain.name1=MyDevice1 -deviceIds=0a00109344250093 -mdiAreaHeight=0.7034482758620689 -mdiAreaHeightLast=0.3482758620689655 -mdiCount=4 -mdiDevice0=1 -mdiDevice1=1 -mdiDevice2=1 -mdiDevice3=1 -mdiType0=1 -mdiType1=1 -mdiType2=0 -mdiType3=0 -mdiUnit0=1 -mdiUnit1=0 -mdiUnit2=1 -mdiUnit3=0 -navigatorHeight=0.1793103448275862 -navigatorHeightLast=0.1793103448275862 -navigatorWidth=0.17998610145934676 -navigatorWidthLast=0.17998610145934676 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-unit.1.0.port.-1.s.74.orderindex=-1 -unit.1.0.port.-1.s.74.visible=0 -unit.1.0.port.-1.s.75.alias= -unit.1.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.75.name=DataPort[75] -unit.1.0.port.-1.s.75.orderindex=-1 -unit.1.0.port.-1.s.75.visible=0 -unit.1.0.port.-1.s.76.alias= -unit.1.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.76.name=DataPort[76] -unit.1.0.port.-1.s.76.orderindex=-1 -unit.1.0.port.-1.s.76.visible=0 -unit.1.0.port.-1.s.77.alias= -unit.1.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.77.name=DataPort[77] -unit.1.0.port.-1.s.77.orderindex=-1 -unit.1.0.port.-1.s.77.visible=0 -unit.1.0.port.-1.s.78.alias= -unit.1.0.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.78.name=DataPort[78] -unit.1.0.port.-1.s.78.orderindex=-1 -unit.1.0.port.-1.s.78.visible=0 -unit.1.0.port.-1.s.79.alias= -unit.1.0.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.79.name=DataPort[79] -unit.1.0.port.-1.s.79.orderindex=-1 -unit.1.0.port.-1.s.79.visible=0 -unit.1.0.port.-1.s.8.alias= -unit.1.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.8.name=DataPort[8] -unit.1.0.port.-1.s.8.orderindex=-1 -unit.1.0.port.-1.s.8.visible=0 -unit.1.0.port.-1.s.80.alias= -unit.1.0.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.80.name=DataPort[80] -unit.1.0.port.-1.s.80.orderindex=-1 -unit.1.0.port.-1.s.80.visible=0 -unit.1.0.port.-1.s.81.alias= -unit.1.0.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.81.name=DataPort[81] -unit.1.0.port.-1.s.81.orderindex=-1 -unit.1.0.port.-1.s.81.visible=0 -unit.1.0.port.-1.s.82.alias= -unit.1.0.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.-1.s.82.name=DataPort[82] -unit.1.0.port.-1.s.82.orderindex=-1 -unit.1.0.port.-1.s.82.visible=0 -unit.1.0.port.-1.s.83.alias= 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-unit.1.0.port.0.s.2.visible=1 -unit.1.0.port.0.s.20.alias= -unit.1.0.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.20.name=TriggerPort0[20] -unit.1.0.port.0.s.20.orderindex=-1 -unit.1.0.port.0.s.20.visible=1 -unit.1.0.port.0.s.21.alias= -unit.1.0.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.21.name=TriggerPort0[21] -unit.1.0.port.0.s.21.orderindex=-1 -unit.1.0.port.0.s.21.visible=1 -unit.1.0.port.0.s.22.alias= -unit.1.0.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.22.name=TriggerPort0[22] -unit.1.0.port.0.s.22.orderindex=-1 -unit.1.0.port.0.s.22.visible=1 -unit.1.0.port.0.s.23.alias= -unit.1.0.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.23.name=TriggerPort0[23] -unit.1.0.port.0.s.23.orderindex=-1 -unit.1.0.port.0.s.23.visible=1 -unit.1.0.port.0.s.24.alias= -unit.1.0.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.24.name=TriggerPort0[24] -unit.1.0.port.0.s.24.orderindex=-1 -unit.1.0.port.0.s.24.visible=1 -unit.1.0.port.0.s.25.alias= -unit.1.0.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.25.name=TriggerPort0[25] -unit.1.0.port.0.s.25.orderindex=-1 -unit.1.0.port.0.s.25.visible=1 -unit.1.0.port.0.s.26.alias= -unit.1.0.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.26.name=TriggerPort0[26] -unit.1.0.port.0.s.26.orderindex=-1 -unit.1.0.port.0.s.26.visible=1 -unit.1.0.port.0.s.27.alias= -unit.1.0.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.27.name=TriggerPort0[27] -unit.1.0.port.0.s.27.orderindex=-1 -unit.1.0.port.0.s.27.visible=1 -unit.1.0.port.0.s.28.alias= -unit.1.0.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.28.name=TriggerPort0[28] -unit.1.0.port.0.s.28.orderindex=-1 -unit.1.0.port.0.s.28.visible=1 -unit.1.0.port.0.s.29.alias= -unit.1.0.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.29.name=TriggerPort0[29] -unit.1.0.port.0.s.29.orderindex=-1 -unit.1.0.port.0.s.29.visible=1 -unit.1.0.port.0.s.3.alias= -unit.1.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.3.name=TriggerPort0[3] -unit.1.0.port.0.s.3.orderindex=-1 -unit.1.0.port.0.s.3.visible=1 -unit.1.0.port.0.s.30.alias= -unit.1.0.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.30.name=TriggerPort0[30] -unit.1.0.port.0.s.30.orderindex=-1 -unit.1.0.port.0.s.30.visible=1 -unit.1.0.port.0.s.31.alias= -unit.1.0.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.31.name=TriggerPort0[31] -unit.1.0.port.0.s.31.orderindex=-1 -unit.1.0.port.0.s.31.visible=1 -unit.1.0.port.0.s.4.alias= -unit.1.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.4.name=TriggerPort0[4] -unit.1.0.port.0.s.4.orderindex=-1 -unit.1.0.port.0.s.4.visible=1 -unit.1.0.port.0.s.5.alias= -unit.1.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.5.name=TriggerPort0[5] -unit.1.0.port.0.s.5.orderindex=-1 -unit.1.0.port.0.s.5.visible=1 -unit.1.0.port.0.s.6.alias= -unit.1.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.6.name=TriggerPort0[6] -unit.1.0.port.0.s.6.orderindex=-1 -unit.1.0.port.0.s.6.visible=1 -unit.1.0.port.0.s.7.alias= -unit.1.0.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.7.name=TriggerPort0[7] -unit.1.0.port.0.s.7.orderindex=-1 -unit.1.0.port.0.s.7.visible=1 -unit.1.0.port.0.s.8.alias= -unit.1.0.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.8.name=TriggerPort0[8] -unit.1.0.port.0.s.8.orderindex=-1 -unit.1.0.port.0.s.8.visible=1 -unit.1.0.port.0.s.9.alias= -unit.1.0.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.0.s.9.name=TriggerPort0[9] -unit.1.0.port.0.s.9.orderindex=-1 -unit.1.0.port.0.s.9.visible=1 -unit.1.0.port.1.b.0.alias= -unit.1.0.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.b.0.name=TriggerPort1 -unit.1.0.port.1.b.0.orderindex=-1 -unit.1.0.port.1.b.0.radix=Hex -unit.1.0.port.1.b.0.signedOffset=0.0 -unit.1.0.port.1.b.0.signedPrecision=0 -unit.1.0.port.1.b.0.signedScaleFactor=1.0 -unit.1.0.port.1.b.0.unsignedOffset=0.0 -unit.1.0.port.1.b.0.unsignedPrecision=0 -unit.1.0.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.1.b.0.visible=1 -unit.1.0.port.1.buscount=1 -unit.1.0.port.1.channelcount=32 -unit.1.0.port.1.s.0.alias= -unit.1.0.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.0.name=TriggerPort1[0] -unit.1.0.port.1.s.0.orderindex=-1 -unit.1.0.port.1.s.0.visible=1 -unit.1.0.port.1.s.1.alias= -unit.1.0.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.1.name=TriggerPort1[1] -unit.1.0.port.1.s.1.orderindex=-1 -unit.1.0.port.1.s.1.visible=1 -unit.1.0.port.1.s.10.alias= -unit.1.0.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.10.name=TriggerPort1[10] -unit.1.0.port.1.s.10.orderindex=-1 -unit.1.0.port.1.s.10.visible=1 -unit.1.0.port.1.s.11.alias= -unit.1.0.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.11.name=TriggerPort1[11] -unit.1.0.port.1.s.11.orderindex=-1 -unit.1.0.port.1.s.11.visible=1 -unit.1.0.port.1.s.12.alias= -unit.1.0.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.12.name=TriggerPort1[12] -unit.1.0.port.1.s.12.orderindex=-1 -unit.1.0.port.1.s.12.visible=1 -unit.1.0.port.1.s.13.alias= -unit.1.0.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.13.name=TriggerPort1[13] -unit.1.0.port.1.s.13.orderindex=-1 -unit.1.0.port.1.s.13.visible=1 -unit.1.0.port.1.s.14.alias= -unit.1.0.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.14.name=TriggerPort1[14] -unit.1.0.port.1.s.14.orderindex=-1 -unit.1.0.port.1.s.14.visible=1 -unit.1.0.port.1.s.15.alias= -unit.1.0.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.15.name=TriggerPort1[15] -unit.1.0.port.1.s.15.orderindex=-1 -unit.1.0.port.1.s.15.visible=1 -unit.1.0.port.1.s.16.alias= -unit.1.0.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.16.name=TriggerPort1[16] -unit.1.0.port.1.s.16.orderindex=-1 -unit.1.0.port.1.s.16.visible=1 -unit.1.0.port.1.s.17.alias= -unit.1.0.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.17.name=TriggerPort1[17] -unit.1.0.port.1.s.17.orderindex=-1 -unit.1.0.port.1.s.17.visible=1 -unit.1.0.port.1.s.18.alias= -unit.1.0.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.18.name=TriggerPort1[18] -unit.1.0.port.1.s.18.orderindex=-1 -unit.1.0.port.1.s.18.visible=1 -unit.1.0.port.1.s.19.alias= -unit.1.0.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.19.name=TriggerPort1[19] -unit.1.0.port.1.s.19.orderindex=-1 -unit.1.0.port.1.s.19.visible=1 -unit.1.0.port.1.s.2.alias= -unit.1.0.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.2.name=TriggerPort1[2] -unit.1.0.port.1.s.2.orderindex=-1 -unit.1.0.port.1.s.2.visible=1 -unit.1.0.port.1.s.20.alias= -unit.1.0.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.20.name=TriggerPort1[20] -unit.1.0.port.1.s.20.orderindex=-1 -unit.1.0.port.1.s.20.visible=1 -unit.1.0.port.1.s.21.alias= -unit.1.0.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.21.name=TriggerPort1[21] -unit.1.0.port.1.s.21.orderindex=-1 -unit.1.0.port.1.s.21.visible=1 -unit.1.0.port.1.s.22.alias= -unit.1.0.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.22.name=TriggerPort1[22] -unit.1.0.port.1.s.22.orderindex=-1 -unit.1.0.port.1.s.22.visible=1 -unit.1.0.port.1.s.23.alias= -unit.1.0.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.23.name=TriggerPort1[23] -unit.1.0.port.1.s.23.orderindex=-1 -unit.1.0.port.1.s.23.visible=1 -unit.1.0.port.1.s.24.alias= -unit.1.0.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.24.name=TriggerPort1[24] -unit.1.0.port.1.s.24.orderindex=-1 -unit.1.0.port.1.s.24.visible=1 -unit.1.0.port.1.s.25.alias= -unit.1.0.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.25.name=TriggerPort1[25] -unit.1.0.port.1.s.25.orderindex=-1 -unit.1.0.port.1.s.25.visible=1 -unit.1.0.port.1.s.26.alias= -unit.1.0.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.26.name=TriggerPort1[26] -unit.1.0.port.1.s.26.orderindex=-1 -unit.1.0.port.1.s.26.visible=1 -unit.1.0.port.1.s.27.alias= -unit.1.0.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.27.name=TriggerPort1[27] -unit.1.0.port.1.s.27.orderindex=-1 -unit.1.0.port.1.s.27.visible=1 -unit.1.0.port.1.s.28.alias= -unit.1.0.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.28.name=TriggerPort1[28] -unit.1.0.port.1.s.28.orderindex=-1 -unit.1.0.port.1.s.28.visible=1 -unit.1.0.port.1.s.29.alias= -unit.1.0.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.29.name=TriggerPort1[29] -unit.1.0.port.1.s.29.orderindex=-1 -unit.1.0.port.1.s.29.visible=1 -unit.1.0.port.1.s.3.alias= -unit.1.0.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.3.name=TriggerPort1[3] -unit.1.0.port.1.s.3.orderindex=-1 -unit.1.0.port.1.s.3.visible=1 -unit.1.0.port.1.s.30.alias= -unit.1.0.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.30.name=TriggerPort1[30] -unit.1.0.port.1.s.30.orderindex=-1 -unit.1.0.port.1.s.30.visible=1 -unit.1.0.port.1.s.31.alias= -unit.1.0.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.31.name=TriggerPort1[31] -unit.1.0.port.1.s.31.orderindex=-1 -unit.1.0.port.1.s.31.visible=1 -unit.1.0.port.1.s.4.alias= -unit.1.0.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.4.name=TriggerPort1[4] -unit.1.0.port.1.s.4.orderindex=-1 -unit.1.0.port.1.s.4.visible=1 -unit.1.0.port.1.s.5.alias= -unit.1.0.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.5.name=TriggerPort1[5] -unit.1.0.port.1.s.5.orderindex=-1 -unit.1.0.port.1.s.5.visible=1 -unit.1.0.port.1.s.6.alias= -unit.1.0.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.6.name=TriggerPort1[6] -unit.1.0.port.1.s.6.orderindex=-1 -unit.1.0.port.1.s.6.visible=1 -unit.1.0.port.1.s.7.alias= -unit.1.0.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.7.name=TriggerPort1[7] -unit.1.0.port.1.s.7.orderindex=-1 -unit.1.0.port.1.s.7.visible=1 -unit.1.0.port.1.s.8.alias= -unit.1.0.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.8.name=TriggerPort1[8] -unit.1.0.port.1.s.8.orderindex=-1 -unit.1.0.port.1.s.8.visible=1 -unit.1.0.port.1.s.9.alias= -unit.1.0.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.1.s.9.name=TriggerPort1[9] -unit.1.0.port.1.s.9.orderindex=-1 -unit.1.0.port.1.s.9.visible=1 -unit.1.0.port.2.b.0.alias= -unit.1.0.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.b.0.name=TriggerPort2 -unit.1.0.port.2.b.0.orderindex=-1 -unit.1.0.port.2.b.0.radix=Hex -unit.1.0.port.2.b.0.signedOffset=0.0 -unit.1.0.port.2.b.0.signedPrecision=0 -unit.1.0.port.2.b.0.signedScaleFactor=1.0 -unit.1.0.port.2.b.0.unsignedOffset=0.0 -unit.1.0.port.2.b.0.unsignedPrecision=0 -unit.1.0.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.2.b.0.visible=1 -unit.1.0.port.2.buscount=1 -unit.1.0.port.2.channelcount=32 -unit.1.0.port.2.s.0.alias=DataPort[64] -unit.1.0.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.0.name=TriggerPort2[0] -unit.1.0.port.2.s.0.orderindex=-1 -unit.1.0.port.2.s.0.visible=1 -unit.1.0.port.2.s.1.alias= -unit.1.0.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.1.name=TriggerPort2[1] -unit.1.0.port.2.s.1.orderindex=-1 -unit.1.0.port.2.s.1.visible=1 -unit.1.0.port.2.s.10.alias=DataPort[74] -unit.1.0.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.10.name=TriggerPort2[10] -unit.1.0.port.2.s.10.orderindex=-1 -unit.1.0.port.2.s.10.visible=1 -unit.1.0.port.2.s.11.alias= -unit.1.0.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.11.name=TriggerPort2[11] -unit.1.0.port.2.s.11.orderindex=-1 -unit.1.0.port.2.s.11.visible=1 -unit.1.0.port.2.s.12.alias= -unit.1.0.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.12.name=TriggerPort2[12] -unit.1.0.port.2.s.12.orderindex=-1 -unit.1.0.port.2.s.12.visible=1 -unit.1.0.port.2.s.13.alias= -unit.1.0.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.13.name=TriggerPort2[13] -unit.1.0.port.2.s.13.orderindex=-1 -unit.1.0.port.2.s.13.visible=1 -unit.1.0.port.2.s.14.alias= -unit.1.0.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.14.name=TriggerPort2[14] -unit.1.0.port.2.s.14.orderindex=-1 -unit.1.0.port.2.s.14.visible=1 -unit.1.0.port.2.s.15.alias= -unit.1.0.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.15.name=TriggerPort2[15] -unit.1.0.port.2.s.15.orderindex=-1 -unit.1.0.port.2.s.15.visible=1 -unit.1.0.port.2.s.16.alias= -unit.1.0.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.16.name=TriggerPort2[16] -unit.1.0.port.2.s.16.orderindex=-1 -unit.1.0.port.2.s.16.visible=1 -unit.1.0.port.2.s.17.alias= -unit.1.0.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.17.name=TriggerPort2[17] -unit.1.0.port.2.s.17.orderindex=-1 -unit.1.0.port.2.s.17.visible=1 -unit.1.0.port.2.s.18.alias= -unit.1.0.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.18.name=TriggerPort2[18] -unit.1.0.port.2.s.18.orderindex=-1 -unit.1.0.port.2.s.18.visible=1 -unit.1.0.port.2.s.19.alias= -unit.1.0.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.19.name=TriggerPort2[19] -unit.1.0.port.2.s.19.orderindex=-1 -unit.1.0.port.2.s.19.visible=1 -unit.1.0.port.2.s.2.alias= -unit.1.0.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.2.name=TriggerPort2[2] -unit.1.0.port.2.s.2.orderindex=-1 -unit.1.0.port.2.s.2.visible=1 -unit.1.0.port.2.s.20.alias= -unit.1.0.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.20.name=TriggerPort2[20] -unit.1.0.port.2.s.20.orderindex=-1 -unit.1.0.port.2.s.20.visible=1 -unit.1.0.port.2.s.21.alias= -unit.1.0.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.21.name=TriggerPort2[21] -unit.1.0.port.2.s.21.orderindex=-1 -unit.1.0.port.2.s.21.visible=1 -unit.1.0.port.2.s.22.alias= -unit.1.0.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.22.name=TriggerPort2[22] -unit.1.0.port.2.s.22.orderindex=-1 -unit.1.0.port.2.s.22.visible=1 -unit.1.0.port.2.s.23.alias= -unit.1.0.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.23.name=TriggerPort2[23] -unit.1.0.port.2.s.23.orderindex=-1 -unit.1.0.port.2.s.23.visible=1 -unit.1.0.port.2.s.24.alias= -unit.1.0.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.24.name=TriggerPort2[24] -unit.1.0.port.2.s.24.orderindex=-1 -unit.1.0.port.2.s.24.visible=1 -unit.1.0.port.2.s.25.alias= -unit.1.0.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.25.name=TriggerPort2[25] -unit.1.0.port.2.s.25.orderindex=-1 -unit.1.0.port.2.s.25.visible=1 -unit.1.0.port.2.s.26.alias= -unit.1.0.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.26.name=TriggerPort2[26] -unit.1.0.port.2.s.26.orderindex=-1 -unit.1.0.port.2.s.26.visible=1 -unit.1.0.port.2.s.27.alias= -unit.1.0.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.27.name=TriggerPort2[27] -unit.1.0.port.2.s.27.orderindex=-1 -unit.1.0.port.2.s.27.visible=1 -unit.1.0.port.2.s.28.alias= -unit.1.0.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.28.name=TriggerPort2[28] -unit.1.0.port.2.s.28.orderindex=-1 -unit.1.0.port.2.s.28.visible=1 -unit.1.0.port.2.s.29.alias= -unit.1.0.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.29.name=TriggerPort2[29] -unit.1.0.port.2.s.29.orderindex=-1 -unit.1.0.port.2.s.29.visible=1 -unit.1.0.port.2.s.3.alias= -unit.1.0.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.3.name=TriggerPort2[3] -unit.1.0.port.2.s.3.orderindex=-1 -unit.1.0.port.2.s.3.visible=1 -unit.1.0.port.2.s.30.alias= -unit.1.0.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.30.name=TriggerPort2[30] -unit.1.0.port.2.s.30.orderindex=-1 -unit.1.0.port.2.s.30.visible=1 -unit.1.0.port.2.s.31.alias= -unit.1.0.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.31.name=TriggerPort2[31] -unit.1.0.port.2.s.31.orderindex=-1 -unit.1.0.port.2.s.31.visible=1 -unit.1.0.port.2.s.4.alias= -unit.1.0.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.4.name=TriggerPort2[4] -unit.1.0.port.2.s.4.orderindex=-1 -unit.1.0.port.2.s.4.visible=1 -unit.1.0.port.2.s.5.alias= -unit.1.0.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.5.name=TriggerPort2[5] -unit.1.0.port.2.s.5.orderindex=-1 -unit.1.0.port.2.s.5.visible=1 -unit.1.0.port.2.s.6.alias= -unit.1.0.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.6.name=TriggerPort2[6] -unit.1.0.port.2.s.6.orderindex=-1 -unit.1.0.port.2.s.6.visible=1 -unit.1.0.port.2.s.7.alias= -unit.1.0.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.7.name=TriggerPort2[7] -unit.1.0.port.2.s.7.orderindex=-1 -unit.1.0.port.2.s.7.visible=1 -unit.1.0.port.2.s.8.alias= -unit.1.0.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.8.name=TriggerPort2[8] -unit.1.0.port.2.s.8.orderindex=-1 -unit.1.0.port.2.s.8.visible=1 -unit.1.0.port.2.s.9.alias= -unit.1.0.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.2.s.9.name=TriggerPort2[9] -unit.1.0.port.2.s.9.orderindex=-1 -unit.1.0.port.2.s.9.visible=1 -unit.1.0.port.3.b.0.alias= -unit.1.0.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.0.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.b.0.name=TriggerPort3 -unit.1.0.port.3.b.0.orderindex=-1 -unit.1.0.port.3.b.0.radix=Hex -unit.1.0.port.3.b.0.signedOffset=0.0 -unit.1.0.port.3.b.0.signedPrecision=0 -unit.1.0.port.3.b.0.signedScaleFactor=1.0 -unit.1.0.port.3.b.0.unsignedOffset=0.0 -unit.1.0.port.3.b.0.unsignedPrecision=0 -unit.1.0.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.0.port.3.b.0.visible=1 -unit.1.0.port.3.buscount=1 -unit.1.0.port.3.channelcount=32 -unit.1.0.port.3.s.0.alias=DataPort[96] -unit.1.0.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.0.name=TriggerPort3[0] -unit.1.0.port.3.s.0.orderindex=-1 -unit.1.0.port.3.s.0.visible=1 -unit.1.0.port.3.s.1.alias= -unit.1.0.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.1.name=TriggerPort3[1] -unit.1.0.port.3.s.1.orderindex=-1 -unit.1.0.port.3.s.1.visible=1 -unit.1.0.port.3.s.10.alias= -unit.1.0.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.10.name=TriggerPort3[10] -unit.1.0.port.3.s.10.orderindex=-1 -unit.1.0.port.3.s.10.visible=1 -unit.1.0.port.3.s.11.alias= -unit.1.0.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.11.name=TriggerPort3[11] -unit.1.0.port.3.s.11.orderindex=-1 -unit.1.0.port.3.s.11.visible=1 -unit.1.0.port.3.s.12.alias= -unit.1.0.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.12.name=TriggerPort3[12] -unit.1.0.port.3.s.12.orderindex=-1 -unit.1.0.port.3.s.12.visible=1 -unit.1.0.port.3.s.13.alias= -unit.1.0.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.13.name=TriggerPort3[13] -unit.1.0.port.3.s.13.orderindex=-1 -unit.1.0.port.3.s.13.visible=1 -unit.1.0.port.3.s.14.alias= -unit.1.0.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.14.name=TriggerPort3[14] -unit.1.0.port.3.s.14.orderindex=-1 -unit.1.0.port.3.s.14.visible=1 -unit.1.0.port.3.s.15.alias= -unit.1.0.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.15.name=TriggerPort3[15] -unit.1.0.port.3.s.15.orderindex=-1 -unit.1.0.port.3.s.15.visible=1 -unit.1.0.port.3.s.16.alias= -unit.1.0.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.16.name=TriggerPort3[16] -unit.1.0.port.3.s.16.orderindex=-1 -unit.1.0.port.3.s.16.visible=1 -unit.1.0.port.3.s.17.alias= -unit.1.0.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.17.name=TriggerPort3[17] -unit.1.0.port.3.s.17.orderindex=-1 -unit.1.0.port.3.s.17.visible=1 -unit.1.0.port.3.s.18.alias= -unit.1.0.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.18.name=TriggerPort3[18] -unit.1.0.port.3.s.18.orderindex=-1 -unit.1.0.port.3.s.18.visible=1 -unit.1.0.port.3.s.19.alias= -unit.1.0.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.19.name=TriggerPort3[19] -unit.1.0.port.3.s.19.orderindex=-1 -unit.1.0.port.3.s.19.visible=1 -unit.1.0.port.3.s.2.alias= -unit.1.0.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.2.name=TriggerPort3[2] -unit.1.0.port.3.s.2.orderindex=-1 -unit.1.0.port.3.s.2.visible=1 -unit.1.0.port.3.s.20.alias= -unit.1.0.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.20.name=TriggerPort3[20] -unit.1.0.port.3.s.20.orderindex=-1 -unit.1.0.port.3.s.20.visible=1 -unit.1.0.port.3.s.21.alias= -unit.1.0.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.21.name=TriggerPort3[21] -unit.1.0.port.3.s.21.orderindex=-1 -unit.1.0.port.3.s.21.visible=1 -unit.1.0.port.3.s.22.alias= -unit.1.0.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.22.name=TriggerPort3[22] -unit.1.0.port.3.s.22.orderindex=-1 -unit.1.0.port.3.s.22.visible=1 -unit.1.0.port.3.s.23.alias= -unit.1.0.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.23.name=TriggerPort3[23] -unit.1.0.port.3.s.23.orderindex=-1 -unit.1.0.port.3.s.23.visible=1 -unit.1.0.port.3.s.24.alias= -unit.1.0.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.24.name=TriggerPort3[24] -unit.1.0.port.3.s.24.orderindex=-1 -unit.1.0.port.3.s.24.visible=1 -unit.1.0.port.3.s.25.alias= -unit.1.0.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.25.name=TriggerPort3[25] -unit.1.0.port.3.s.25.orderindex=-1 -unit.1.0.port.3.s.25.visible=1 -unit.1.0.port.3.s.26.alias= -unit.1.0.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.26.name=TriggerPort3[26] -unit.1.0.port.3.s.26.orderindex=-1 -unit.1.0.port.3.s.26.visible=1 -unit.1.0.port.3.s.27.alias= -unit.1.0.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.27.name=TriggerPort3[27] -unit.1.0.port.3.s.27.orderindex=-1 -unit.1.0.port.3.s.27.visible=1 -unit.1.0.port.3.s.28.alias= -unit.1.0.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.28.name=TriggerPort3[28] -unit.1.0.port.3.s.28.orderindex=-1 -unit.1.0.port.3.s.28.visible=1 -unit.1.0.port.3.s.29.alias= -unit.1.0.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.29.name=TriggerPort3[29] -unit.1.0.port.3.s.29.orderindex=-1 -unit.1.0.port.3.s.29.visible=1 -unit.1.0.port.3.s.3.alias= -unit.1.0.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.3.name=TriggerPort3[3] -unit.1.0.port.3.s.3.orderindex=-1 -unit.1.0.port.3.s.3.visible=1 -unit.1.0.port.3.s.30.alias= -unit.1.0.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.30.name=TriggerPort3[30] -unit.1.0.port.3.s.30.orderindex=-1 -unit.1.0.port.3.s.30.visible=1 -unit.1.0.port.3.s.31.alias= -unit.1.0.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.31.name=TriggerPort3[31] -unit.1.0.port.3.s.31.orderindex=-1 -unit.1.0.port.3.s.31.visible=1 -unit.1.0.port.3.s.4.alias= -unit.1.0.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.4.name=TriggerPort3[4] -unit.1.0.port.3.s.4.orderindex=-1 -unit.1.0.port.3.s.4.visible=1 -unit.1.0.port.3.s.5.alias= -unit.1.0.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.5.name=TriggerPort3[5] -unit.1.0.port.3.s.5.orderindex=-1 -unit.1.0.port.3.s.5.visible=1 -unit.1.0.port.3.s.6.alias= -unit.1.0.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.6.name=TriggerPort3[6] -unit.1.0.port.3.s.6.orderindex=-1 -unit.1.0.port.3.s.6.visible=1 -unit.1.0.port.3.s.7.alias= -unit.1.0.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.7.name=TriggerPort3[7] -unit.1.0.port.3.s.7.orderindex=-1 -unit.1.0.port.3.s.7.visible=1 -unit.1.0.port.3.s.8.alias= -unit.1.0.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.8.name=TriggerPort3[8] -unit.1.0.port.3.s.8.orderindex=-1 -unit.1.0.port.3.s.8.visible=1 -unit.1.0.port.3.s.9.alias= -unit.1.0.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.0.port.3.s.9.name=TriggerPort3[9] -unit.1.0.port.3.s.9.orderindex=-1 -unit.1.0.port.3.s.9.visible=1 -unit.1.0.portcount=4 -unit.1.0.rep_trigger.clobber=1 -unit.1.0.rep_trigger.dir=/home/lerwys -unit.1.0.rep_trigger.filename=waveform -unit.1.0.rep_trigger.format=ASCII -unit.1.0.rep_trigger.loggingEnabled=0 -unit.1.0.rep_trigger.signals=All Signals/Buses -unit.1.0.samplesPerTrigger=1 -unit.1.0.triggerCapture=1 -unit.1.0.triggerNSamplesTS=0 -unit.1.0.triggerPosition=0 -unit.1.0.triggerWindowCount=1 -unit.1.0.triggerWindowDepth=4096 -unit.1.0.triggerWindowTS=0 -unit.1.0.username=MyILA0 -unit.1.0.waveform.count=14 -unit.1.0.waveform.posn.0.channel=2147483646 -unit.1.0.waveform.posn.0.name=cbar_master_o(3).dat -unit.1.0.waveform.posn.0.radix=1 -unit.1.0.waveform.posn.0.type=bus -unit.1.0.waveform.posn.1.channel=2147483646 -unit.1.0.waveform.posn.1.name=cbar_master_i(3).dat -unit.1.0.waveform.posn.1.radix=1 -unit.1.0.waveform.posn.1.type=bus -unit.1.0.waveform.posn.10.channel=2147483646 -unit.1.0.waveform.posn.10.name=cbar_master_i(3).rty -unit.1.0.waveform.posn.10.radix=1 -unit.1.0.waveform.posn.10.type=bus -unit.1.0.waveform.posn.100.channel=127 -unit.1.0.waveform.posn.100.name=DataPort[127] -unit.1.0.waveform.posn.100.type=signal -unit.1.0.waveform.posn.101.channel=127 -unit.1.0.waveform.posn.101.name=DataPort[127] -unit.1.0.waveform.posn.101.type=signal -unit.1.0.waveform.posn.102.channel=127 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-unit.1.0.waveform.posn.11.channel=2147483646 -unit.1.0.waveform.posn.11.name=\ cbar_master_i(3).err -unit.1.0.waveform.posn.11.radix=1 -unit.1.0.waveform.posn.11.type=bus -unit.1.0.waveform.posn.110.channel=127 -unit.1.0.waveform.posn.110.name=DataPort[127] -unit.1.0.waveform.posn.110.type=signal -unit.1.0.waveform.posn.111.channel=127 -unit.1.0.waveform.posn.111.name=DataPort[127] -unit.1.0.waveform.posn.111.type=signal -unit.1.0.waveform.posn.112.channel=127 -unit.1.0.waveform.posn.112.name=DataPort[127] -unit.1.0.waveform.posn.112.type=signal -unit.1.0.waveform.posn.113.channel=127 -unit.1.0.waveform.posn.113.name=DataPort[127] -unit.1.0.waveform.posn.113.type=signal -unit.1.0.waveform.posn.114.channel=127 -unit.1.0.waveform.posn.114.name=DataPort[127] -unit.1.0.waveform.posn.114.type=signal -unit.1.0.waveform.posn.115.channel=127 -unit.1.0.waveform.posn.115.name=DataPort[127] -unit.1.0.waveform.posn.115.type=signal -unit.1.0.waveform.posn.116.channel=127 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-unit.1.1.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.9.name=DataPort[9] -unit.1.1.port.-1.s.9.orderindex=-1 -unit.1.1.port.-1.s.9.visible=0 -unit.1.1.port.-1.s.90.alias= -unit.1.1.port.-1.s.90.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.90.name=DataPort[90] -unit.1.1.port.-1.s.90.orderindex=-1 -unit.1.1.port.-1.s.90.visible=0 -unit.1.1.port.-1.s.91.alias= -unit.1.1.port.-1.s.91.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.91.name=DataPort[91] -unit.1.1.port.-1.s.91.orderindex=-1 -unit.1.1.port.-1.s.91.visible=0 -unit.1.1.port.-1.s.92.alias= -unit.1.1.port.-1.s.92.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.92.name=DataPort[92] -unit.1.1.port.-1.s.92.orderindex=-1 -unit.1.1.port.-1.s.92.visible=0 -unit.1.1.port.-1.s.93.alias= -unit.1.1.port.-1.s.93.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.93.name=DataPort[93] -unit.1.1.port.-1.s.93.orderindex=-1 -unit.1.1.port.-1.s.93.visible=0 -unit.1.1.port.-1.s.94.alias= -unit.1.1.port.-1.s.94.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.94.name=DataPort[94] -unit.1.1.port.-1.s.94.orderindex=-1 -unit.1.1.port.-1.s.94.visible=0 -unit.1.1.port.-1.s.95.alias= -unit.1.1.port.-1.s.95.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.95.name=DataPort[95] -unit.1.1.port.-1.s.95.orderindex=-1 -unit.1.1.port.-1.s.95.visible=0 -unit.1.1.port.-1.s.96.alias= -unit.1.1.port.-1.s.96.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.96.name=DataPort[96] -unit.1.1.port.-1.s.96.orderindex=-1 -unit.1.1.port.-1.s.96.visible=0 -unit.1.1.port.-1.s.97.alias= -unit.1.1.port.-1.s.97.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.97.name=DataPort[97] -unit.1.1.port.-1.s.97.orderindex=-1 -unit.1.1.port.-1.s.97.visible=0 -unit.1.1.port.-1.s.98.alias= -unit.1.1.port.-1.s.98.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.98.name=DataPort[98] -unit.1.1.port.-1.s.98.orderindex=-1 -unit.1.1.port.-1.s.98.visible=0 -unit.1.1.port.-1.s.99.alias= -unit.1.1.port.-1.s.99.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.-1.s.99.name=DataPort[99] -unit.1.1.port.-1.s.99.orderindex=-1 -unit.1.1.port.-1.s.99.visible=0 -unit.1.1.port.0.b.0.alias= -unit.1.1.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.b.0.name=TriggerPort0 -unit.1.1.port.0.b.0.orderindex=-1 -unit.1.1.port.0.b.0.radix=Hex -unit.1.1.port.0.b.0.signedOffset=0.0 -unit.1.1.port.0.b.0.signedPrecision=0 -unit.1.1.port.0.b.0.signedScaleFactor=1.0 -unit.1.1.port.0.b.0.unsignedOffset=0.0 -unit.1.1.port.0.b.0.unsignedPrecision=0 -unit.1.1.port.0.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.0.b.0.visible=1 -unit.1.1.port.0.buscount=1 -unit.1.1.port.0.channelcount=32 -unit.1.1.port.0.s.0.alias= -unit.1.1.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.0.name=TriggerPort0[0] -unit.1.1.port.0.s.0.orderindex=-1 -unit.1.1.port.0.s.0.visible=1 -unit.1.1.port.0.s.1.alias= -unit.1.1.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.1.name=TriggerPort0[1] -unit.1.1.port.0.s.1.orderindex=-1 -unit.1.1.port.0.s.1.visible=1 -unit.1.1.port.0.s.10.alias= -unit.1.1.port.0.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.10.name=TriggerPort0[10] -unit.1.1.port.0.s.10.orderindex=-1 -unit.1.1.port.0.s.10.visible=1 -unit.1.1.port.0.s.11.alias= -unit.1.1.port.0.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.11.name=TriggerPort0[11] -unit.1.1.port.0.s.11.orderindex=-1 -unit.1.1.port.0.s.11.visible=1 -unit.1.1.port.0.s.12.alias= -unit.1.1.port.0.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.12.name=TriggerPort0[12] -unit.1.1.port.0.s.12.orderindex=-1 -unit.1.1.port.0.s.12.visible=1 -unit.1.1.port.0.s.13.alias= -unit.1.1.port.0.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.13.name=TriggerPort0[13] -unit.1.1.port.0.s.13.orderindex=-1 -unit.1.1.port.0.s.13.visible=1 -unit.1.1.port.0.s.14.alias= -unit.1.1.port.0.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.14.name=TriggerPort0[14] -unit.1.1.port.0.s.14.orderindex=-1 -unit.1.1.port.0.s.14.visible=1 -unit.1.1.port.0.s.15.alias= -unit.1.1.port.0.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.15.name=TriggerPort0[15] -unit.1.1.port.0.s.15.orderindex=-1 -unit.1.1.port.0.s.15.visible=1 -unit.1.1.port.0.s.16.alias= -unit.1.1.port.0.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.16.name=TriggerPort0[16] -unit.1.1.port.0.s.16.orderindex=-1 -unit.1.1.port.0.s.16.visible=1 -unit.1.1.port.0.s.17.alias= -unit.1.1.port.0.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.17.name=TriggerPort0[17] -unit.1.1.port.0.s.17.orderindex=-1 -unit.1.1.port.0.s.17.visible=1 -unit.1.1.port.0.s.18.alias= -unit.1.1.port.0.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.18.name=TriggerPort0[18] -unit.1.1.port.0.s.18.orderindex=-1 -unit.1.1.port.0.s.18.visible=1 -unit.1.1.port.0.s.19.alias= -unit.1.1.port.0.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.19.name=TriggerPort0[19] -unit.1.1.port.0.s.19.orderindex=-1 -unit.1.1.port.0.s.19.visible=1 -unit.1.1.port.0.s.2.alias= -unit.1.1.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.2.name=TriggerPort0[2] -unit.1.1.port.0.s.2.orderindex=-1 -unit.1.1.port.0.s.2.visible=1 -unit.1.1.port.0.s.20.alias= -unit.1.1.port.0.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.20.name=TriggerPort0[20] -unit.1.1.port.0.s.20.orderindex=-1 -unit.1.1.port.0.s.20.visible=1 -unit.1.1.port.0.s.21.alias= -unit.1.1.port.0.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.21.name=TriggerPort0[21] -unit.1.1.port.0.s.21.orderindex=-1 -unit.1.1.port.0.s.21.visible=1 -unit.1.1.port.0.s.22.alias= -unit.1.1.port.0.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.22.name=TriggerPort0[22] -unit.1.1.port.0.s.22.orderindex=-1 -unit.1.1.port.0.s.22.visible=1 -unit.1.1.port.0.s.23.alias= -unit.1.1.port.0.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.23.name=TriggerPort0[23] -unit.1.1.port.0.s.23.orderindex=-1 -unit.1.1.port.0.s.23.visible=1 -unit.1.1.port.0.s.24.alias= -unit.1.1.port.0.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.24.name=TriggerPort0[24] -unit.1.1.port.0.s.24.orderindex=-1 -unit.1.1.port.0.s.24.visible=1 -unit.1.1.port.0.s.25.alias= -unit.1.1.port.0.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.25.name=TriggerPort0[25] -unit.1.1.port.0.s.25.orderindex=-1 -unit.1.1.port.0.s.25.visible=1 -unit.1.1.port.0.s.26.alias= -unit.1.1.port.0.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.26.name=TriggerPort0[26] -unit.1.1.port.0.s.26.orderindex=-1 -unit.1.1.port.0.s.26.visible=1 -unit.1.1.port.0.s.27.alias= -unit.1.1.port.0.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.27.name=TriggerPort0[27] -unit.1.1.port.0.s.27.orderindex=-1 -unit.1.1.port.0.s.27.visible=1 -unit.1.1.port.0.s.28.alias= -unit.1.1.port.0.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.28.name=TriggerPort0[28] -unit.1.1.port.0.s.28.orderindex=-1 -unit.1.1.port.0.s.28.visible=1 -unit.1.1.port.0.s.29.alias= -unit.1.1.port.0.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.29.name=TriggerPort0[29] -unit.1.1.port.0.s.29.orderindex=-1 -unit.1.1.port.0.s.29.visible=1 -unit.1.1.port.0.s.3.alias= -unit.1.1.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.3.name=TriggerPort0[3] -unit.1.1.port.0.s.3.orderindex=-1 -unit.1.1.port.0.s.3.visible=1 -unit.1.1.port.0.s.30.alias= -unit.1.1.port.0.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.30.name=TriggerPort0[30] -unit.1.1.port.0.s.30.orderindex=-1 -unit.1.1.port.0.s.30.visible=1 -unit.1.1.port.0.s.31.alias= -unit.1.1.port.0.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.31.name=TriggerPort0[31] -unit.1.1.port.0.s.31.orderindex=-1 -unit.1.1.port.0.s.31.visible=1 -unit.1.1.port.0.s.4.alias= -unit.1.1.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.4.name=TriggerPort0[4] -unit.1.1.port.0.s.4.orderindex=-1 -unit.1.1.port.0.s.4.visible=1 -unit.1.1.port.0.s.5.alias= -unit.1.1.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.5.name=TriggerPort0[5] -unit.1.1.port.0.s.5.orderindex=-1 -unit.1.1.port.0.s.5.visible=1 -unit.1.1.port.0.s.6.alias= -unit.1.1.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.6.name=TriggerPort0[6] -unit.1.1.port.0.s.6.orderindex=-1 -unit.1.1.port.0.s.6.visible=1 -unit.1.1.port.0.s.7.alias= -unit.1.1.port.0.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.7.name=TriggerPort0[7] -unit.1.1.port.0.s.7.orderindex=-1 -unit.1.1.port.0.s.7.visible=1 -unit.1.1.port.0.s.8.alias= -unit.1.1.port.0.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.8.name=TriggerPort0[8] -unit.1.1.port.0.s.8.orderindex=-1 -unit.1.1.port.0.s.8.visible=1 -unit.1.1.port.0.s.9.alias= -unit.1.1.port.0.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.0.s.9.name=TriggerPort0[9] -unit.1.1.port.0.s.9.orderindex=-1 -unit.1.1.port.0.s.9.visible=1 -unit.1.1.port.1.b.0.alias= -unit.1.1.port.1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.b.0.name=TriggerPort1 -unit.1.1.port.1.b.0.orderindex=-1 -unit.1.1.port.1.b.0.radix=Hex -unit.1.1.port.1.b.0.signedOffset=0.0 -unit.1.1.port.1.b.0.signedPrecision=0 -unit.1.1.port.1.b.0.signedScaleFactor=1.0 -unit.1.1.port.1.b.0.unsignedOffset=0.0 -unit.1.1.port.1.b.0.unsignedPrecision=0 -unit.1.1.port.1.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.1.b.0.visible=1 -unit.1.1.port.1.buscount=1 -unit.1.1.port.1.channelcount=32 -unit.1.1.port.1.s.0.alias= -unit.1.1.port.1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.0.name=TriggerPort1[0] -unit.1.1.port.1.s.0.orderindex=-1 -unit.1.1.port.1.s.0.visible=1 -unit.1.1.port.1.s.1.alias= -unit.1.1.port.1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.1.name=TriggerPort1[1] -unit.1.1.port.1.s.1.orderindex=-1 -unit.1.1.port.1.s.1.visible=1 -unit.1.1.port.1.s.10.alias= -unit.1.1.port.1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.10.name=TriggerPort1[10] -unit.1.1.port.1.s.10.orderindex=-1 -unit.1.1.port.1.s.10.visible=1 -unit.1.1.port.1.s.11.alias= -unit.1.1.port.1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.11.name=TriggerPort1[11] -unit.1.1.port.1.s.11.orderindex=-1 -unit.1.1.port.1.s.11.visible=1 -unit.1.1.port.1.s.12.alias= -unit.1.1.port.1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.12.name=TriggerPort1[12] -unit.1.1.port.1.s.12.orderindex=-1 -unit.1.1.port.1.s.12.visible=1 -unit.1.1.port.1.s.13.alias= -unit.1.1.port.1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.13.name=TriggerPort1[13] -unit.1.1.port.1.s.13.orderindex=-1 -unit.1.1.port.1.s.13.visible=1 -unit.1.1.port.1.s.14.alias= -unit.1.1.port.1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.14.name=TriggerPort1[14] -unit.1.1.port.1.s.14.orderindex=-1 -unit.1.1.port.1.s.14.visible=1 -unit.1.1.port.1.s.15.alias= -unit.1.1.port.1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.15.name=TriggerPort1[15] -unit.1.1.port.1.s.15.orderindex=-1 -unit.1.1.port.1.s.15.visible=1 -unit.1.1.port.1.s.16.alias= -unit.1.1.port.1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.16.name=TriggerPort1[16] -unit.1.1.port.1.s.16.orderindex=-1 -unit.1.1.port.1.s.16.visible=1 -unit.1.1.port.1.s.17.alias= -unit.1.1.port.1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.17.name=TriggerPort1[17] -unit.1.1.port.1.s.17.orderindex=-1 -unit.1.1.port.1.s.17.visible=1 -unit.1.1.port.1.s.18.alias= -unit.1.1.port.1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.18.name=TriggerPort1[18] -unit.1.1.port.1.s.18.orderindex=-1 -unit.1.1.port.1.s.18.visible=1 -unit.1.1.port.1.s.19.alias= -unit.1.1.port.1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.19.name=TriggerPort1[19] -unit.1.1.port.1.s.19.orderindex=-1 -unit.1.1.port.1.s.19.visible=1 -unit.1.1.port.1.s.2.alias= -unit.1.1.port.1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.2.name=TriggerPort1[2] -unit.1.1.port.1.s.2.orderindex=-1 -unit.1.1.port.1.s.2.visible=1 -unit.1.1.port.1.s.20.alias= -unit.1.1.port.1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.20.name=TriggerPort1[20] -unit.1.1.port.1.s.20.orderindex=-1 -unit.1.1.port.1.s.20.visible=1 -unit.1.1.port.1.s.21.alias= -unit.1.1.port.1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.21.name=TriggerPort1[21] -unit.1.1.port.1.s.21.orderindex=-1 -unit.1.1.port.1.s.21.visible=1 -unit.1.1.port.1.s.22.alias= -unit.1.1.port.1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.22.name=TriggerPort1[22] -unit.1.1.port.1.s.22.orderindex=-1 -unit.1.1.port.1.s.22.visible=1 -unit.1.1.port.1.s.23.alias= -unit.1.1.port.1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.23.name=TriggerPort1[23] -unit.1.1.port.1.s.23.orderindex=-1 -unit.1.1.port.1.s.23.visible=1 -unit.1.1.port.1.s.24.alias= -unit.1.1.port.1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.24.name=TriggerPort1[24] -unit.1.1.port.1.s.24.orderindex=-1 -unit.1.1.port.1.s.24.visible=1 -unit.1.1.port.1.s.25.alias= -unit.1.1.port.1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.25.name=TriggerPort1[25] -unit.1.1.port.1.s.25.orderindex=-1 -unit.1.1.port.1.s.25.visible=1 -unit.1.1.port.1.s.26.alias= -unit.1.1.port.1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.26.name=TriggerPort1[26] -unit.1.1.port.1.s.26.orderindex=-1 -unit.1.1.port.1.s.26.visible=1 -unit.1.1.port.1.s.27.alias= -unit.1.1.port.1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.27.name=TriggerPort1[27] -unit.1.1.port.1.s.27.orderindex=-1 -unit.1.1.port.1.s.27.visible=1 -unit.1.1.port.1.s.28.alias= -unit.1.1.port.1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.28.name=TriggerPort1[28] -unit.1.1.port.1.s.28.orderindex=-1 -unit.1.1.port.1.s.28.visible=1 -unit.1.1.port.1.s.29.alias= -unit.1.1.port.1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.29.name=TriggerPort1[29] -unit.1.1.port.1.s.29.orderindex=-1 -unit.1.1.port.1.s.29.visible=1 -unit.1.1.port.1.s.3.alias= -unit.1.1.port.1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.3.name=TriggerPort1[3] -unit.1.1.port.1.s.3.orderindex=-1 -unit.1.1.port.1.s.3.visible=1 -unit.1.1.port.1.s.30.alias= -unit.1.1.port.1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.30.name=TriggerPort1[30] -unit.1.1.port.1.s.30.orderindex=-1 -unit.1.1.port.1.s.30.visible=1 -unit.1.1.port.1.s.31.alias= -unit.1.1.port.1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.31.name=TriggerPort1[31] -unit.1.1.port.1.s.31.orderindex=-1 -unit.1.1.port.1.s.31.visible=1 -unit.1.1.port.1.s.4.alias= -unit.1.1.port.1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.4.name=TriggerPort1[4] -unit.1.1.port.1.s.4.orderindex=-1 -unit.1.1.port.1.s.4.visible=1 -unit.1.1.port.1.s.5.alias= -unit.1.1.port.1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.5.name=TriggerPort1[5] -unit.1.1.port.1.s.5.orderindex=-1 -unit.1.1.port.1.s.5.visible=1 -unit.1.1.port.1.s.6.alias= -unit.1.1.port.1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.6.name=TriggerPort1[6] -unit.1.1.port.1.s.6.orderindex=-1 -unit.1.1.port.1.s.6.visible=1 -unit.1.1.port.1.s.7.alias=DataPort[39] -unit.1.1.port.1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.7.name=TriggerPort1[7] -unit.1.1.port.1.s.7.orderindex=-1 -unit.1.1.port.1.s.7.visible=1 -unit.1.1.port.1.s.8.alias= -unit.1.1.port.1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.8.name=TriggerPort1[8] -unit.1.1.port.1.s.8.orderindex=-1 -unit.1.1.port.1.s.8.visible=1 -unit.1.1.port.1.s.9.alias= -unit.1.1.port.1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.1.s.9.name=TriggerPort1[9] -unit.1.1.port.1.s.9.orderindex=-1 -unit.1.1.port.1.s.9.visible=1 -unit.1.1.port.2.b.0.alias= -unit.1.1.port.2.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.2.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.b.0.name=TriggerPort2 -unit.1.1.port.2.b.0.orderindex=-1 -unit.1.1.port.2.b.0.radix=Hex -unit.1.1.port.2.b.0.signedOffset=0.0 -unit.1.1.port.2.b.0.signedPrecision=0 -unit.1.1.port.2.b.0.signedScaleFactor=1.0 -unit.1.1.port.2.b.0.unsignedOffset=0.0 -unit.1.1.port.2.b.0.unsignedPrecision=0 -unit.1.1.port.2.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.2.b.0.visible=1 -unit.1.1.port.2.buscount=1 -unit.1.1.port.2.channelcount=32 -unit.1.1.port.2.s.0.alias= -unit.1.1.port.2.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.0.name=TriggerPort2[0] -unit.1.1.port.2.s.0.orderindex=-1 -unit.1.1.port.2.s.0.visible=1 -unit.1.1.port.2.s.1.alias= -unit.1.1.port.2.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.1.name=TriggerPort2[1] -unit.1.1.port.2.s.1.orderindex=-1 -unit.1.1.port.2.s.1.visible=1 -unit.1.1.port.2.s.10.alias= -unit.1.1.port.2.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.10.name=TriggerPort2[10] -unit.1.1.port.2.s.10.orderindex=-1 -unit.1.1.port.2.s.10.visible=1 -unit.1.1.port.2.s.11.alias= -unit.1.1.port.2.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.11.name=TriggerPort2[11] -unit.1.1.port.2.s.11.orderindex=-1 -unit.1.1.port.2.s.11.visible=1 -unit.1.1.port.2.s.12.alias= -unit.1.1.port.2.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.12.name=TriggerPort2[12] -unit.1.1.port.2.s.12.orderindex=-1 -unit.1.1.port.2.s.12.visible=1 -unit.1.1.port.2.s.13.alias= -unit.1.1.port.2.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.13.name=TriggerPort2[13] -unit.1.1.port.2.s.13.orderindex=-1 -unit.1.1.port.2.s.13.visible=1 -unit.1.1.port.2.s.14.alias= -unit.1.1.port.2.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.14.name=TriggerPort2[14] -unit.1.1.port.2.s.14.orderindex=-1 -unit.1.1.port.2.s.14.visible=1 -unit.1.1.port.2.s.15.alias= -unit.1.1.port.2.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.15.name=TriggerPort2[15] -unit.1.1.port.2.s.15.orderindex=-1 -unit.1.1.port.2.s.15.visible=1 -unit.1.1.port.2.s.16.alias= -unit.1.1.port.2.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.16.name=TriggerPort2[16] -unit.1.1.port.2.s.16.orderindex=-1 -unit.1.1.port.2.s.16.visible=1 -unit.1.1.port.2.s.17.alias= -unit.1.1.port.2.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.17.name=TriggerPort2[17] -unit.1.1.port.2.s.17.orderindex=-1 -unit.1.1.port.2.s.17.visible=1 -unit.1.1.port.2.s.18.alias= -unit.1.1.port.2.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.18.name=TriggerPort2[18] -unit.1.1.port.2.s.18.orderindex=-1 -unit.1.1.port.2.s.18.visible=1 -unit.1.1.port.2.s.19.alias= -unit.1.1.port.2.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.19.name=TriggerPort2[19] -unit.1.1.port.2.s.19.orderindex=-1 -unit.1.1.port.2.s.19.visible=1 -unit.1.1.port.2.s.2.alias= -unit.1.1.port.2.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.2.name=TriggerPort2[2] -unit.1.1.port.2.s.2.orderindex=-1 -unit.1.1.port.2.s.2.visible=1 -unit.1.1.port.2.s.20.alias= -unit.1.1.port.2.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.20.name=TriggerPort2[20] -unit.1.1.port.2.s.20.orderindex=-1 -unit.1.1.port.2.s.20.visible=1 -unit.1.1.port.2.s.21.alias= -unit.1.1.port.2.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.21.name=TriggerPort2[21] -unit.1.1.port.2.s.21.orderindex=-1 -unit.1.1.port.2.s.21.visible=1 -unit.1.1.port.2.s.22.alias= -unit.1.1.port.2.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.22.name=TriggerPort2[22] -unit.1.1.port.2.s.22.orderindex=-1 -unit.1.1.port.2.s.22.visible=1 -unit.1.1.port.2.s.23.alias= -unit.1.1.port.2.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.23.name=TriggerPort2[23] -unit.1.1.port.2.s.23.orderindex=-1 -unit.1.1.port.2.s.23.visible=1 -unit.1.1.port.2.s.24.alias= -unit.1.1.port.2.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.24.name=TriggerPort2[24] -unit.1.1.port.2.s.24.orderindex=-1 -unit.1.1.port.2.s.24.visible=1 -unit.1.1.port.2.s.25.alias= -unit.1.1.port.2.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.25.name=TriggerPort2[25] -unit.1.1.port.2.s.25.orderindex=-1 -unit.1.1.port.2.s.25.visible=1 -unit.1.1.port.2.s.26.alias= -unit.1.1.port.2.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.26.name=TriggerPort2[26] -unit.1.1.port.2.s.26.orderindex=-1 -unit.1.1.port.2.s.26.visible=1 -unit.1.1.port.2.s.27.alias= -unit.1.1.port.2.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.27.name=TriggerPort2[27] -unit.1.1.port.2.s.27.orderindex=-1 -unit.1.1.port.2.s.27.visible=1 -unit.1.1.port.2.s.28.alias= -unit.1.1.port.2.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.28.name=TriggerPort2[28] -unit.1.1.port.2.s.28.orderindex=-1 -unit.1.1.port.2.s.28.visible=1 -unit.1.1.port.2.s.29.alias= -unit.1.1.port.2.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.29.name=TriggerPort2[29] -unit.1.1.port.2.s.29.orderindex=-1 -unit.1.1.port.2.s.29.visible=1 -unit.1.1.port.2.s.3.alias= -unit.1.1.port.2.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.3.name=TriggerPort2[3] -unit.1.1.port.2.s.3.orderindex=-1 -unit.1.1.port.2.s.3.visible=1 -unit.1.1.port.2.s.30.alias= -unit.1.1.port.2.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.30.name=TriggerPort2[30] -unit.1.1.port.2.s.30.orderindex=-1 -unit.1.1.port.2.s.30.visible=1 -unit.1.1.port.2.s.31.alias= -unit.1.1.port.2.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.31.name=TriggerPort2[31] -unit.1.1.port.2.s.31.orderindex=-1 -unit.1.1.port.2.s.31.visible=1 -unit.1.1.port.2.s.4.alias= -unit.1.1.port.2.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.4.name=TriggerPort2[4] -unit.1.1.port.2.s.4.orderindex=-1 -unit.1.1.port.2.s.4.visible=1 -unit.1.1.port.2.s.5.alias= -unit.1.1.port.2.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.5.name=TriggerPort2[5] -unit.1.1.port.2.s.5.orderindex=-1 -unit.1.1.port.2.s.5.visible=1 -unit.1.1.port.2.s.6.alias= -unit.1.1.port.2.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.6.name=TriggerPort2[6] -unit.1.1.port.2.s.6.orderindex=-1 -unit.1.1.port.2.s.6.visible=1 -unit.1.1.port.2.s.7.alias= -unit.1.1.port.2.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.7.name=TriggerPort2[7] -unit.1.1.port.2.s.7.orderindex=-1 -unit.1.1.port.2.s.7.visible=1 -unit.1.1.port.2.s.8.alias= -unit.1.1.port.2.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.8.name=TriggerPort2[8] -unit.1.1.port.2.s.8.orderindex=-1 -unit.1.1.port.2.s.8.visible=1 -unit.1.1.port.2.s.9.alias= -unit.1.1.port.2.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.2.s.9.name=TriggerPort2[9] -unit.1.1.port.2.s.9.orderindex=-1 -unit.1.1.port.2.s.9.visible=1 -unit.1.1.port.3.b.0.alias= -unit.1.1.port.3.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -unit.1.1.port.3.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.b.0.name=TriggerPort3 -unit.1.1.port.3.b.0.orderindex=-1 -unit.1.1.port.3.b.0.radix=Hex -unit.1.1.port.3.b.0.signedOffset=0.0 -unit.1.1.port.3.b.0.signedPrecision=0 -unit.1.1.port.3.b.0.signedScaleFactor=1.0 -unit.1.1.port.3.b.0.unsignedOffset=0.0 -unit.1.1.port.3.b.0.unsignedPrecision=0 -unit.1.1.port.3.b.0.unsignedScaleFactor=1.0 -unit.1.1.port.3.b.0.visible=1 -unit.1.1.port.3.buscount=1 -unit.1.1.port.3.channelcount=32 -unit.1.1.port.3.s.0.alias= -unit.1.1.port.3.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.0.name=TriggerPort3[0] -unit.1.1.port.3.s.0.orderindex=-1 -unit.1.1.port.3.s.0.visible=1 -unit.1.1.port.3.s.1.alias= -unit.1.1.port.3.s.1.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.1.name=TriggerPort3[1] -unit.1.1.port.3.s.1.orderindex=-1 -unit.1.1.port.3.s.1.visible=1 -unit.1.1.port.3.s.10.alias= -unit.1.1.port.3.s.10.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.10.name=TriggerPort3[10] -unit.1.1.port.3.s.10.orderindex=-1 -unit.1.1.port.3.s.10.visible=1 -unit.1.1.port.3.s.11.alias= -unit.1.1.port.3.s.11.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.11.name=TriggerPort3[11] -unit.1.1.port.3.s.11.orderindex=-1 -unit.1.1.port.3.s.11.visible=1 -unit.1.1.port.3.s.12.alias= -unit.1.1.port.3.s.12.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.12.name=TriggerPort3[12] -unit.1.1.port.3.s.12.orderindex=-1 -unit.1.1.port.3.s.12.visible=1 -unit.1.1.port.3.s.13.alias= -unit.1.1.port.3.s.13.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.13.name=TriggerPort3[13] -unit.1.1.port.3.s.13.orderindex=-1 -unit.1.1.port.3.s.13.visible=1 -unit.1.1.port.3.s.14.alias= -unit.1.1.port.3.s.14.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.14.name=TriggerPort3[14] -unit.1.1.port.3.s.14.orderindex=-1 -unit.1.1.port.3.s.14.visible=1 -unit.1.1.port.3.s.15.alias= -unit.1.1.port.3.s.15.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.15.name=TriggerPort3[15] -unit.1.1.port.3.s.15.orderindex=-1 -unit.1.1.port.3.s.15.visible=1 -unit.1.1.port.3.s.16.alias= -unit.1.1.port.3.s.16.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.16.name=TriggerPort3[16] -unit.1.1.port.3.s.16.orderindex=-1 -unit.1.1.port.3.s.16.visible=1 -unit.1.1.port.3.s.17.alias= -unit.1.1.port.3.s.17.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.17.name=TriggerPort3[17] -unit.1.1.port.3.s.17.orderindex=-1 -unit.1.1.port.3.s.17.visible=1 -unit.1.1.port.3.s.18.alias= -unit.1.1.port.3.s.18.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.18.name=TriggerPort3[18] -unit.1.1.port.3.s.18.orderindex=-1 -unit.1.1.port.3.s.18.visible=1 -unit.1.1.port.3.s.19.alias= -unit.1.1.port.3.s.19.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.19.name=TriggerPort3[19] -unit.1.1.port.3.s.19.orderindex=-1 -unit.1.1.port.3.s.19.visible=1 -unit.1.1.port.3.s.2.alias= -unit.1.1.port.3.s.2.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.2.name=TriggerPort3[2] -unit.1.1.port.3.s.2.orderindex=-1 -unit.1.1.port.3.s.2.visible=1 -unit.1.1.port.3.s.20.alias= -unit.1.1.port.3.s.20.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.20.name=TriggerPort3[20] -unit.1.1.port.3.s.20.orderindex=-1 -unit.1.1.port.3.s.20.visible=1 -unit.1.1.port.3.s.21.alias= -unit.1.1.port.3.s.21.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.21.name=TriggerPort3[21] -unit.1.1.port.3.s.21.orderindex=-1 -unit.1.1.port.3.s.21.visible=1 -unit.1.1.port.3.s.22.alias= -unit.1.1.port.3.s.22.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.22.name=TriggerPort3[22] -unit.1.1.port.3.s.22.orderindex=-1 -unit.1.1.port.3.s.22.visible=1 -unit.1.1.port.3.s.23.alias= -unit.1.1.port.3.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.23.name=TriggerPort3[23] -unit.1.1.port.3.s.23.orderindex=-1 -unit.1.1.port.3.s.23.visible=1 -unit.1.1.port.3.s.24.alias= -unit.1.1.port.3.s.24.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.24.name=TriggerPort3[24] -unit.1.1.port.3.s.24.orderindex=-1 -unit.1.1.port.3.s.24.visible=1 -unit.1.1.port.3.s.25.alias= -unit.1.1.port.3.s.25.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.25.name=TriggerPort3[25] -unit.1.1.port.3.s.25.orderindex=-1 -unit.1.1.port.3.s.25.visible=1 -unit.1.1.port.3.s.26.alias= -unit.1.1.port.3.s.26.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.26.name=TriggerPort3[26] -unit.1.1.port.3.s.26.orderindex=-1 -unit.1.1.port.3.s.26.visible=1 -unit.1.1.port.3.s.27.alias= -unit.1.1.port.3.s.27.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.27.name=TriggerPort3[27] -unit.1.1.port.3.s.27.orderindex=-1 -unit.1.1.port.3.s.27.visible=1 -unit.1.1.port.3.s.28.alias= -unit.1.1.port.3.s.28.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.28.name=TriggerPort3[28] -unit.1.1.port.3.s.28.orderindex=-1 -unit.1.1.port.3.s.28.visible=1 -unit.1.1.port.3.s.29.alias= -unit.1.1.port.3.s.29.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.29.name=TriggerPort3[29] -unit.1.1.port.3.s.29.orderindex=-1 -unit.1.1.port.3.s.29.visible=1 -unit.1.1.port.3.s.3.alias= -unit.1.1.port.3.s.3.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.3.name=TriggerPort3[3] -unit.1.1.port.3.s.3.orderindex=-1 -unit.1.1.port.3.s.3.visible=1 -unit.1.1.port.3.s.30.alias= -unit.1.1.port.3.s.30.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.30.name=TriggerPort3[30] -unit.1.1.port.3.s.30.orderindex=-1 -unit.1.1.port.3.s.30.visible=1 -unit.1.1.port.3.s.31.alias= -unit.1.1.port.3.s.31.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.31.name=TriggerPort3[31] -unit.1.1.port.3.s.31.orderindex=-1 -unit.1.1.port.3.s.31.visible=1 -unit.1.1.port.3.s.4.alias= -unit.1.1.port.3.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.4.name=TriggerPort3[4] -unit.1.1.port.3.s.4.orderindex=-1 -unit.1.1.port.3.s.4.visible=1 -unit.1.1.port.3.s.5.alias= -unit.1.1.port.3.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.5.name=TriggerPort3[5] -unit.1.1.port.3.s.5.orderindex=-1 -unit.1.1.port.3.s.5.visible=1 -unit.1.1.port.3.s.6.alias= -unit.1.1.port.3.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.6.name=TriggerPort3[6] -unit.1.1.port.3.s.6.orderindex=-1 -unit.1.1.port.3.s.6.visible=1 -unit.1.1.port.3.s.7.alias= -unit.1.1.port.3.s.7.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.7.name=TriggerPort3[7] -unit.1.1.port.3.s.7.orderindex=-1 -unit.1.1.port.3.s.7.visible=1 -unit.1.1.port.3.s.8.alias= -unit.1.1.port.3.s.8.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.8.name=TriggerPort3[8] -unit.1.1.port.3.s.8.orderindex=-1 -unit.1.1.port.3.s.8.visible=1 -unit.1.1.port.3.s.9.alias= -unit.1.1.port.3.s.9.color=java.awt.Color[r\=0,g\=0,b\=124] -unit.1.1.port.3.s.9.name=TriggerPort3[9] -unit.1.1.port.3.s.9.orderindex=-1 -unit.1.1.port.3.s.9.visible=1 -unit.1.1.portcount=4 -unit.1.1.rep_trigger.clobber=1 -unit.1.1.rep_trigger.dir=/home/lerwys -unit.1.1.rep_trigger.filename=waveform -unit.1.1.rep_trigger.format=ASCII -unit.1.1.rep_trigger.loggingEnabled=0 -unit.1.1.rep_trigger.signals=All Signals/Buses -unit.1.1.samplesPerTrigger=1 -unit.1.1.triggerCapture=1 -unit.1.1.triggerNSamplesTS=0 -unit.1.1.triggerPosition=0 -unit.1.1.triggerWindowCount=1 -unit.1.1.triggerWindowDepth=4096 -unit.1.1.triggerWindowTS=0 -unit.1.1.username=MyILA1 -unit.1.1.waveform.count=14 -unit.1.1.waveform.posn.0.channel=2147483646 -unit.1.1.waveform.posn.0.name=wbs_src_o(0).sel -unit.1.1.waveform.posn.0.radix=1 -unit.1.1.waveform.posn.0.type=bus -unit.1.1.waveform.posn.1.channel=2147483646 -unit.1.1.waveform.posn.1.name=wbs_src_o(0).dat_cha -unit.1.1.waveform.posn.1.radix=1 -unit.1.1.waveform.posn.1.type=bus -unit.1.1.waveform.posn.10.channel=2147483646 -unit.1.1.waveform.posn.10.name=wbs_src_i(0).err -unit.1.1.waveform.posn.10.radix=1 -unit.1.1.waveform.posn.10.type=bus -unit.1.1.waveform.posn.100.channel=127 -unit.1.1.waveform.posn.100.name=DataPort[127] -unit.1.1.waveform.posn.100.type=signal -unit.1.1.waveform.posn.101.channel=127 -unit.1.1.waveform.posn.101.name=DataPort[127] -unit.1.1.waveform.posn.101.type=signal -unit.1.1.waveform.posn.102.channel=127 -unit.1.1.waveform.posn.102.name=DataPort[127] -unit.1.1.waveform.posn.102.type=signal -unit.1.1.waveform.posn.103.channel=127 -unit.1.1.waveform.posn.103.name=DataPort[127] -unit.1.1.waveform.posn.103.type=signal -unit.1.1.waveform.posn.104.channel=127 -unit.1.1.waveform.posn.104.name=DataPort[127] -unit.1.1.waveform.posn.104.type=signal -unit.1.1.waveform.posn.105.channel=127 -unit.1.1.waveform.posn.105.name=DataPort[127] -unit.1.1.waveform.posn.105.type=signal -unit.1.1.waveform.posn.106.channel=127 -unit.1.1.waveform.posn.106.name=DataPort[127] -unit.1.1.waveform.posn.106.type=signal -unit.1.1.waveform.posn.107.channel=127 -unit.1.1.waveform.posn.107.name=DataPort[127] -unit.1.1.waveform.posn.107.type=signal -unit.1.1.waveform.posn.108.channel=127 -unit.1.1.waveform.posn.108.name=DataPort[127] -unit.1.1.waveform.posn.108.type=signal -unit.1.1.waveform.posn.109.channel=127 -unit.1.1.waveform.posn.109.name=DataPort[127] -unit.1.1.waveform.posn.109.type=signal -unit.1.1.waveform.posn.11.channel=2147483646 -unit.1.1.waveform.posn.11.name=wbs_src_i(0).ack -unit.1.1.waveform.posn.11.radix=1 -unit.1.1.waveform.posn.11.type=bus -unit.1.1.waveform.posn.110.channel=127 -unit.1.1.waveform.posn.110.name=DataPort[127] -unit.1.1.waveform.posn.110.type=signal -unit.1.1.waveform.posn.111.channel=127 -unit.1.1.waveform.posn.111.name=DataPort[127] -unit.1.1.waveform.posn.111.type=signal -unit.1.1.waveform.posn.112.channel=127 -unit.1.1.waveform.posn.112.name=DataPort[127] -unit.1.1.waveform.posn.112.type=signal -unit.1.1.waveform.posn.113.channel=127 -unit.1.1.waveform.posn.113.name=DataPort[127] -unit.1.1.waveform.posn.113.type=signal -unit.1.1.waveform.posn.114.channel=127 -unit.1.1.waveform.posn.114.name=DataPort[127] -unit.1.1.waveform.posn.114.type=signal -unit.1.1.waveform.posn.115.channel=127 -unit.1.1.waveform.posn.115.name=DataPort[127] -unit.1.1.waveform.posn.115.type=signal -unit.1.1.waveform.posn.116.channel=127 -unit.1.1.waveform.posn.116.name=DataPort[127] -unit.1.1.waveform.posn.116.type=signal -unit.1.1.waveform.posn.117.channel=127 -unit.1.1.waveform.posn.117.name=DataPort[127] -unit.1.1.waveform.posn.117.type=signal -unit.1.1.waveform.posn.118.channel=127 -unit.1.1.waveform.posn.118.name=DataPort[127] -unit.1.1.waveform.posn.118.type=signal -unit.1.1.waveform.posn.119.channel=127 -unit.1.1.waveform.posn.119.name=DataPort[127] -unit.1.1.waveform.posn.119.type=signal -unit.1.1.waveform.posn.12.channel=2147483646 -unit.1.1.waveform.posn.12.name=zeros1 -unit.1.1.waveform.posn.12.radix=1 -unit.1.1.waveform.posn.12.type=bus -unit.1.1.waveform.posn.120.channel=127 -unit.1.1.waveform.posn.120.name=DataPort[127] -unit.1.1.waveform.posn.120.type=signal -unit.1.1.waveform.posn.121.channel=127 -unit.1.1.waveform.posn.121.name=DataPort[127] -unit.1.1.waveform.posn.121.type=signal -unit.1.1.waveform.posn.122.channel=127 -unit.1.1.waveform.posn.122.name=DataPort[127] -unit.1.1.waveform.posn.122.type=signal -unit.1.1.waveform.posn.123.channel=127 -unit.1.1.waveform.posn.123.name=DataPort[127] -unit.1.1.waveform.posn.123.type=signal -unit.1.1.waveform.posn.124.channel=127 -unit.1.1.waveform.posn.124.name=DataPort[127] -unit.1.1.waveform.posn.124.type=signal -unit.1.1.waveform.posn.125.channel=127 -unit.1.1.waveform.posn.125.name=DataPort[127] -unit.1.1.waveform.posn.125.type=signal -unit.1.1.waveform.posn.126.channel=127 -unit.1.1.waveform.posn.126.name=DataPort[127] -unit.1.1.waveform.posn.126.type=signal -unit.1.1.waveform.posn.127.channel=127 -unit.1.1.waveform.posn.127.name=DataPort[127] -unit.1.1.waveform.posn.127.type=signal -unit.1.1.waveform.posn.13.channel=2147483646 -unit.1.1.waveform.posn.13.name=zeros2 -unit.1.1.waveform.posn.13.radix=1 -unit.1.1.waveform.posn.13.type=bus -unit.1.1.waveform.posn.14.channel=127 -unit.1.1.waveform.posn.14.name=DataPort[127] -unit.1.1.waveform.posn.14.type=signal -unit.1.1.waveform.posn.15.channel=127 -unit.1.1.waveform.posn.15.name=DataPort[127] -unit.1.1.waveform.posn.15.type=signal -unit.1.1.waveform.posn.16.channel=127 -unit.1.1.waveform.posn.16.name=DataPort[127] -unit.1.1.waveform.posn.16.type=signal -unit.1.1.waveform.posn.17.channel=127 -unit.1.1.waveform.posn.17.name=DataPort[127] -unit.1.1.waveform.posn.17.type=signal -unit.1.1.waveform.posn.18.channel=127 -unit.1.1.waveform.posn.18.name=DataPort[127] -unit.1.1.waveform.posn.18.type=signal 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-unit.1.1.waveform.posn.25.type=signal -unit.1.1.waveform.posn.26.channel=127 -unit.1.1.waveform.posn.26.name=DataPort[127] -unit.1.1.waveform.posn.26.type=signal -unit.1.1.waveform.posn.27.channel=127 -unit.1.1.waveform.posn.27.name=DataPort[127] -unit.1.1.waveform.posn.27.type=signal -unit.1.1.waveform.posn.28.channel=127 -unit.1.1.waveform.posn.28.name=DataPort[127] -unit.1.1.waveform.posn.28.type=signal -unit.1.1.waveform.posn.29.channel=127 -unit.1.1.waveform.posn.29.name=DataPort[127] -unit.1.1.waveform.posn.29.type=signal -unit.1.1.waveform.posn.3.channel=2147483646 -unit.1.1.waveform.posn.3.name=wbs_src_o(0).we -unit.1.1.waveform.posn.3.radix=1 -unit.1.1.waveform.posn.3.type=bus -unit.1.1.waveform.posn.30.channel=127 -unit.1.1.waveform.posn.30.name=DataPort[127] -unit.1.1.waveform.posn.30.type=signal -unit.1.1.waveform.posn.31.channel=127 -unit.1.1.waveform.posn.31.name=DataPort[127] -unit.1.1.waveform.posn.31.type=signal -unit.1.1.waveform.posn.32.channel=127 -unit.1.1.waveform.posn.32.name=DataPort[127] -unit.1.1.waveform.posn.32.type=signal -unit.1.1.waveform.posn.33.channel=127 -unit.1.1.waveform.posn.33.name=DataPort[127] -unit.1.1.waveform.posn.33.type=signal -unit.1.1.waveform.posn.34.channel=127 -unit.1.1.waveform.posn.34.name=DataPort[127] -unit.1.1.waveform.posn.34.type=signal -unit.1.1.waveform.posn.35.channel=127 -unit.1.1.waveform.posn.35.name=DataPort[127] -unit.1.1.waveform.posn.35.type=signal -unit.1.1.waveform.posn.36.channel=127 -unit.1.1.waveform.posn.36.name=DataPort[127] -unit.1.1.waveform.posn.36.type=signal -unit.1.1.waveform.posn.37.channel=127 -unit.1.1.waveform.posn.37.name=DataPort[127] -unit.1.1.waveform.posn.37.type=signal -unit.1.1.waveform.posn.38.channel=127 -unit.1.1.waveform.posn.38.name=DataPort[127] -unit.1.1.waveform.posn.38.type=signal -unit.1.1.waveform.posn.39.channel=127 -unit.1.1.waveform.posn.39.name=DataPort[127] -unit.1.1.waveform.posn.39.type=signal -unit.1.1.waveform.posn.4.channel=2147483646 -unit.1.1.waveform.posn.4.name=wbs_src_o(0).adr -unit.1.1.waveform.posn.4.radix=1 -unit.1.1.waveform.posn.4.type=bus -unit.1.1.waveform.posn.40.channel=127 -unit.1.1.waveform.posn.40.name=DataPort[127] -unit.1.1.waveform.posn.40.type=signal -unit.1.1.waveform.posn.41.channel=127 -unit.1.1.waveform.posn.41.name=DataPort[127] -unit.1.1.waveform.posn.41.type=signal -unit.1.1.waveform.posn.42.channel=127 -unit.1.1.waveform.posn.42.name=DataPort[127] -unit.1.1.waveform.posn.42.type=signal -unit.1.1.waveform.posn.43.channel=127 -unit.1.1.waveform.posn.43.name=DataPort[127] -unit.1.1.waveform.posn.43.type=signal -unit.1.1.waveform.posn.44.channel=127 -unit.1.1.waveform.posn.44.name=DataPort[127] -unit.1.1.waveform.posn.44.type=signal -unit.1.1.waveform.posn.45.channel=127 -unit.1.1.waveform.posn.45.name=DataPort[127] -unit.1.1.waveform.posn.45.type=signal -unit.1.1.waveform.posn.46.channel=127 -unit.1.1.waveform.posn.46.name=DataPort[127] -unit.1.1.waveform.posn.46.type=signal -unit.1.1.waveform.posn.47.channel=127 -unit.1.1.waveform.posn.47.name=DataPort[127] -unit.1.1.waveform.posn.47.type=signal -unit.1.1.waveform.posn.48.channel=127 -unit.1.1.waveform.posn.48.name=DataPort[127] -unit.1.1.waveform.posn.48.type=signal -unit.1.1.waveform.posn.49.channel=127 -unit.1.1.waveform.posn.49.name=DataPort[127] -unit.1.1.waveform.posn.49.type=signal -unit.1.1.waveform.posn.5.channel=2147483646 -unit.1.1.waveform.posn.5.name=wbs_src_o(0).stb -unit.1.1.waveform.posn.5.radix=1 -unit.1.1.waveform.posn.5.type=bus -unit.1.1.waveform.posn.50.channel=127 -unit.1.1.waveform.posn.50.name=DataPort[127] -unit.1.1.waveform.posn.50.type=signal -unit.1.1.waveform.posn.51.channel=127 -unit.1.1.waveform.posn.51.name=DataPort[127] -unit.1.1.waveform.posn.51.type=signal -unit.1.1.waveform.posn.52.channel=127 -unit.1.1.waveform.posn.52.name=DataPort[127] -unit.1.1.waveform.posn.52.type=signal -unit.1.1.waveform.posn.53.channel=127 -unit.1.1.waveform.posn.53.name=DataPort[127] -unit.1.1.waveform.posn.53.type=signal -unit.1.1.waveform.posn.54.channel=127 -unit.1.1.waveform.posn.54.name=DataPort[127] -unit.1.1.waveform.posn.54.type=signal -unit.1.1.waveform.posn.55.channel=127 -unit.1.1.waveform.posn.55.name=DataPort[127] -unit.1.1.waveform.posn.55.type=signal -unit.1.1.waveform.posn.56.channel=127 -unit.1.1.waveform.posn.56.name=DataPort[127] -unit.1.1.waveform.posn.56.type=signal -unit.1.1.waveform.posn.57.channel=127 -unit.1.1.waveform.posn.57.name=DataPort[127] -unit.1.1.waveform.posn.57.type=signal -unit.1.1.waveform.posn.58.channel=127 -unit.1.1.waveform.posn.58.name=DataPort[127] -unit.1.1.waveform.posn.58.type=signal -unit.1.1.waveform.posn.59.channel=127 -unit.1.1.waveform.posn.59.name=DataPort[127] -unit.1.1.waveform.posn.59.type=signal -unit.1.1.waveform.posn.6.channel=2147483646 -unit.1.1.waveform.posn.6.name=wbs_src_o(0).cyc -unit.1.1.waveform.posn.6.radix=1 -unit.1.1.waveform.posn.6.type=bus -unit.1.1.waveform.posn.60.channel=127 -unit.1.1.waveform.posn.60.name=DataPort[127] -unit.1.1.waveform.posn.60.type=signal -unit.1.1.waveform.posn.61.channel=127 -unit.1.1.waveform.posn.61.name=DataPort[127] -unit.1.1.waveform.posn.61.type=signal -unit.1.1.waveform.posn.62.channel=127 -unit.1.1.waveform.posn.62.name=DataPort[127] -unit.1.1.waveform.posn.62.type=signal -unit.1.1.waveform.posn.63.channel=127 -unit.1.1.waveform.posn.63.name=DataPort[127] -unit.1.1.waveform.posn.63.type=signal -unit.1.1.waveform.posn.64.channel=127 -unit.1.1.waveform.posn.64.name=DataPort[127] -unit.1.1.waveform.posn.64.type=signal -unit.1.1.waveform.posn.65.channel=127 -unit.1.1.waveform.posn.65.name=DataPort[127] -unit.1.1.waveform.posn.65.type=signal -unit.1.1.waveform.posn.66.channel=127 -unit.1.1.waveform.posn.66.name=DataPort[127] -unit.1.1.waveform.posn.66.type=signal -unit.1.1.waveform.posn.67.channel=127 -unit.1.1.waveform.posn.67.name=DataPort[127] -unit.1.1.waveform.posn.67.type=signal -unit.1.1.waveform.posn.68.channel=127 -unit.1.1.waveform.posn.68.name=DataPort[127] -unit.1.1.waveform.posn.68.type=signal -unit.1.1.waveform.posn.69.channel=127 -unit.1.1.waveform.posn.69.name=DataPort[127] -unit.1.1.waveform.posn.69.type=signal -unit.1.1.waveform.posn.7.channel=2147483646 -unit.1.1.waveform.posn.7.name=zeros -unit.1.1.waveform.posn.7.radix=1 -unit.1.1.waveform.posn.7.type=bus -unit.1.1.waveform.posn.70.channel=127 -unit.1.1.waveform.posn.70.name=DataPort[127] -unit.1.1.waveform.posn.70.type=signal -unit.1.1.waveform.posn.71.channel=127 -unit.1.1.waveform.posn.71.name=DataPort[127] -unit.1.1.waveform.posn.71.type=signal -unit.1.1.waveform.posn.72.channel=127 -unit.1.1.waveform.posn.72.name=DataPort[127] -unit.1.1.waveform.posn.72.type=signal -unit.1.1.waveform.posn.73.channel=127 -unit.1.1.waveform.posn.73.name=DataPort[127] -unit.1.1.waveform.posn.73.type=signal -unit.1.1.waveform.posn.74.channel=127 -unit.1.1.waveform.posn.74.name=DataPort[127] -unit.1.1.waveform.posn.74.type=signal -unit.1.1.waveform.posn.75.channel=127 -unit.1.1.waveform.posn.75.name=DataPort[127] -unit.1.1.waveform.posn.75.type=signal -unit.1.1.waveform.posn.76.channel=127 -unit.1.1.waveform.posn.76.name=DataPort[127] -unit.1.1.waveform.posn.76.type=signal -unit.1.1.waveform.posn.77.channel=127 -unit.1.1.waveform.posn.77.name=DataPort[127] -unit.1.1.waveform.posn.77.type=signal -unit.1.1.waveform.posn.78.channel=127 -unit.1.1.waveform.posn.78.name=DataPort[127] -unit.1.1.waveform.posn.78.type=signal -unit.1.1.waveform.posn.79.channel=127 -unit.1.1.waveform.posn.79.name=DataPort[127] -unit.1.1.waveform.posn.79.type=signal -unit.1.1.waveform.posn.8.channel=2147483646 -unit.1.1.waveform.posn.8.name=wbs_src_i(0).stall -unit.1.1.waveform.posn.8.radix=1 -unit.1.1.waveform.posn.8.type=bus -unit.1.1.waveform.posn.80.channel=127 -unit.1.1.waveform.posn.80.name=DataPort[127] -unit.1.1.waveform.posn.80.type=signal -unit.1.1.waveform.posn.81.channel=127 -unit.1.1.waveform.posn.81.name=DataPort[127] -unit.1.1.waveform.posn.81.type=signal -unit.1.1.waveform.posn.82.channel=127 -unit.1.1.waveform.posn.82.name=DataPort[127] -unit.1.1.waveform.posn.82.type=signal -unit.1.1.waveform.posn.83.channel=127 -unit.1.1.waveform.posn.83.name=DataPort[127] -unit.1.1.waveform.posn.83.type=signal -unit.1.1.waveform.posn.84.channel=127 -unit.1.1.waveform.posn.84.name=DataPort[127] -unit.1.1.waveform.posn.84.type=signal -unit.1.1.waveform.posn.85.channel=127 -unit.1.1.waveform.posn.85.name=DataPort[127] -unit.1.1.waveform.posn.85.type=signal -unit.1.1.waveform.posn.86.channel=127 -unit.1.1.waveform.posn.86.name=DataPort[127] -unit.1.1.waveform.posn.86.type=signal -unit.1.1.waveform.posn.87.channel=127 -unit.1.1.waveform.posn.87.name=DataPort[127] -unit.1.1.waveform.posn.87.type=signal -unit.1.1.waveform.posn.88.channel=127 -unit.1.1.waveform.posn.88.name=DataPort[127] -unit.1.1.waveform.posn.88.type=signal -unit.1.1.waveform.posn.89.channel=127 -unit.1.1.waveform.posn.89.name=DataPort[127] -unit.1.1.waveform.posn.89.type=signal -unit.1.1.waveform.posn.9.channel=2147483646 -unit.1.1.waveform.posn.9.name=wbs_src_i(0).rty -unit.1.1.waveform.posn.9.radix=1 -unit.1.1.waveform.posn.9.type=bus -unit.1.1.waveform.posn.90.channel=127 -unit.1.1.waveform.posn.90.name=DataPort[127] -unit.1.1.waveform.posn.90.type=signal -unit.1.1.waveform.posn.91.channel=127 -unit.1.1.waveform.posn.91.name=DataPort[127] -unit.1.1.waveform.posn.91.type=signal -unit.1.1.waveform.posn.92.channel=127 -unit.1.1.waveform.posn.92.name=DataPort[127] -unit.1.1.waveform.posn.92.type=signal -unit.1.1.waveform.posn.93.channel=127 -unit.1.1.waveform.posn.93.name=DataPort[127] -unit.1.1.waveform.posn.93.type=signal -unit.1.1.waveform.posn.94.channel=127 -unit.1.1.waveform.posn.94.name=DataPort[127] -unit.1.1.waveform.posn.94.type=signal -unit.1.1.waveform.posn.95.channel=127 -unit.1.1.waveform.posn.95.name=DataPort[127] -unit.1.1.waveform.posn.95.type=signal -unit.1.1.waveform.posn.96.channel=127 -unit.1.1.waveform.posn.96.name=DataPort[127] -unit.1.1.waveform.posn.96.type=signal -unit.1.1.waveform.posn.97.channel=127 -unit.1.1.waveform.posn.97.name=DataPort[127] -unit.1.1.waveform.posn.97.type=signal -unit.1.1.waveform.posn.98.channel=127 -unit.1.1.waveform.posn.98.name=DataPort[127] -unit.1.1.waveform.posn.98.type=signal -unit.1.1.waveform.posn.99.channel=127 -unit.1.1.waveform.posn.99.name=DataPort[127] -unit.1.1.waveform.posn.99.type=signal diff --git a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf b/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf deleted file mode 100644 index 7f4e5d0e..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf +++ /dev/null @@ -1,227 +0,0 @@ -NET "buttons_i[0]" LOC = D22; -NET "buttons_i[1]" LOC = C22; -NET "buttons_i[2]" LOC = L21; -NET "buttons_i[3]" LOC = L20; -NET "buttons_i[4]" LOC = C18; -NET "buttons_i[5]" LOC = B18; -NET "buttons_i[6]" LOC = K22; -NET "buttons_i[7]" LOC = K21; -NET "leds_o[0]" LOC = AC22; -NET "leds_o[1]" LOC = AC24; -NET "leds_o[2]" LOC = AE22; -NET "leds_o[3]" LOC = AE23; -NET "leds_o[4]" LOC = AB23; -NET "leds_o[5]" LOC = AG23; -NET "leds_o[6]" LOC = AE24; -NET "leds_o[7]" LOC = AD24; -NET "uart_rxd_i" LOC = J24; -NET "uart_txd_o" LOC = J25; -NET "buttons_i[7]" IOSTANDARD = LVCMOS25; -NET "buttons_i[6]" IOSTANDARD = LVCMOS25; -NET "buttons_i[5]" IOSTANDARD = LVCMOS25; -NET "buttons_i[4]" IOSTANDARD = LVCMOS25; -NET "buttons_i[3]" IOSTANDARD = LVCMOS25; -NET "buttons_i[2]" IOSTANDARD = LVCMOS25; -NET "buttons_i[1]" IOSTANDARD = LVCMOS25; -NET "buttons_i[0]" IOSTANDARD = LVCMOS25; -NET "leds_o[7]" IOSTANDARD = LVCMOS25; -NET "leds_o[7]" DRIVE = 12; -NET "leds_o[7]" SLEW = SLOW; -NET "leds_o[6]" IOSTANDARD = LVCMOS25; -NET "leds_o[6]" DRIVE = 12; -NET "leds_o[6]" SLEW = SLOW; -NET "leds_o[5]" IOSTANDARD = LVCMOS25; -NET "leds_o[5]" DRIVE = 12; -NET "leds_o[5]" SLEW = SLOW; -NET "leds_o[4]" IOSTANDARD = LVCMOS25; -NET "leds_o[4]" DRIVE = 12; -NET "leds_o[4]" SLEW = SLOW; -NET "leds_o[3]" IOSTANDARD = LVCMOS25; -NET "leds_o[3]" DRIVE = 12; -NET "leds_o[3]" SLEW = SLOW; -NET "leds_o[2]" IOSTANDARD = LVCMOS25; -NET "leds_o[2]" DRIVE = 12; -NET "leds_o[2]" SLEW = SLOW; -NET "leds_o[1]" IOSTANDARD = LVCMOS25; -NET "leds_o[1]" DRIVE = 12; -NET "leds_o[1]" SLEW = SLOW; -NET "leds_o[0]" IOSTANDARD = LVCMOS25; -NET "leds_o[0]" DRIVE = 12; -NET "leds_o[0]" SLEW = SLOW; -NET "uart_rxd_i" IOSTANDARD = LVCMOS25; -NET "uart_txd_o" IOSTANDARD = LVCMOS25; - -NET "sys_clk_p_i" IOSTANDARD = LVDS_25; -NET "sys_clk_n_i" IOSTANDARD = LVDS_25; -NET "sys_rst_button_i" IOSTANDARD = "SSTL15" | TIG; - -NET "sys_rst_button_i" LOC = H10; - -# PlanAhead Generated physical constraints - -NET "sys_clk_n_i" LOC = H9; -NET "sys_clk_p_i" LOC = J9; - -################################################################################ -# Clock constraints -################################################################################ -NET "ADC_CLK_AB_P_I" TNM_NET = ADC_CLK_AB_P; - -#NET "CLK_TO_FPGA_P" TNM_NET = CLK_TO_FPGA_P; -#TIMESPEC TS_CLK_TO_FPGA_P = PERIOD "CLK_TO_FPGA_P" 246 MHz HIGH 50%; -#NET "EXT_TRIGGER_P" TNM_NET = EXT_TRIGGER_P; -#TIMESPEC TS_EXT_TRIGGER_P = PERIOD "EXT_TRIGGER_P" 246 MHz HIGH 50%; -NET "ADC_CLK_AB_P_I" CLOCK_DEDICATED_ROUTE = FALSE; - -################################################################################ -# FMC signals (FMC150 on ML605, LPC site) -################################################################################ -NET "ADC_N_EN_O" LOC="A33"; -NET "ADC_RESET_O" LOC="B32"; -NET "ADC_SDO_I" LOC="C32"; -NET "CDCE_N_EN_O" LOC="M26"; -NET "CDCE_N_PD_O" LOC="L31"; -NET "CDCE_N_RESET_O" LOC="M31"; -NET "CDCE_SDO_I" LOC="M27"; -NET "ADC_CHA_N_I<0>" LOC="E31"; -NET "ADC_CHA_N_I<1>" LOC="H30"; -NET "ADC_CHA_N_I<2>" LOC="J32"; -NET "ADC_CHA_N_I<3>" LOC="J29"; -NET "ADC_CHA_N_I<4>" LOC="H33"; -NET "ADC_CHA_N_I<5>" LOC="J34"; -NET "ADC_CHA_N_I<6>" LOC="H32"; -NET "ADC_CHA_P_I<0>" LOC="F31"; -NET "ADC_CHA_P_I<1>" LOC="G31"; -NET "ADC_CHA_P_I<2>" LOC="J31"; -NET "ADC_CHA_P_I<3>" LOC="K28"; -NET "ADC_CHA_P_I<4>" LOC="H34"; -NET "ADC_CHA_P_I<5>" LOC="K33"; -NET "ADC_CHA_P_I<6>" LOC="G32"; -NET "ADC_CHB_N_I<0>" LOC="K29"; -NET "ADC_CHB_N_I<1>" LOC="L26"; -NET "ADC_CHB_N_I<2>" LOC="G30"; -NET "ADC_CHB_N_I<3>" LOC="D32"; -NET "ADC_CHB_N_I<4>" LOC="E33"; -NET "ADC_CHB_N_I<5>" LOC="C34"; -NET "ADC_CHB_N_I<6>" LOC="B34"; -NET "ADC_CHB_P_I<0>" LOC="J30"; -NET "ADC_CHB_P_I<1>" LOC="L25"; -NET "ADC_CHB_P_I<2>" LOC="F30"; -NET "ADC_CHB_P_I<3>" LOC="D31"; -NET "ADC_CHB_P_I<4>" LOC="E32"; -NET "ADC_CHB_P_I<5>" LOC="D34"; -NET "ADC_CHB_P_I<6>" LOC="C33"; -NET "ADC_CLK_AB_N_I" LOC="K27"; -NET "ADC_CLK_AB_P_I" LOC="K26"; -#NET "CLK_TO_FPGA_N_I" LOC="B10"; -#NET "CLK_TO_FPGA_P_I" LOC="A10"; -#NET "EXT_TRIGGER_N_I" LOC="G33"; -#NET "EXT_TRIGGER_P_I" LOC="F33"; -NET "MON_N_EN_O" LOC="R31"; -NET "MON_N_INT_I" LOC="M25"; -NET "MON_N_RESET_O" LOC="R32"; -NET "MON_SDO_I" LOC="N25"; -NET "CDCE_PLL_STATUS_I" LOC="K31"; -NET "PRSNT_M2C_L_I" LOC="AD9"; -NET "CDCE_REF_EN_O" LOC="K32"; -NET "SPI_SCLK_O" LOC="N34"; -NET "SPI_SDATA_O" LOC="P34"; - -NET "DAC_DATA_N_O<0>" LOC="M32"; -NET "DAC_DATA_N_O<1>" LOC="P30"; -NET "DAC_DATA_N_O<2>" LOC="P32"; -NET "DAC_DATA_N_O<3>" LOC="R27"; -NET "DAC_DATA_N_O<4>" LOC="R29"; -NET "DAC_DATA_N_O<5>" LOC="N30"; -NET "DAC_DATA_N_O<6>" LOC="L30"; -NET "DAC_DATA_N_O<7>" LOC="N29"; -NET "DAC_DATA_P_O<0>" LOC="L33"; -NET "DAC_DATA_P_O<1>" LOC="P31"; -NET "DAC_DATA_P_O<2>" LOC="N32"; -NET "DAC_DATA_P_O<3>" LOC="R28"; -NET "DAC_DATA_P_O<4>" LOC="P29"; -NET "DAC_DATA_P_O<5>" LOC="M30"; -NET "DAC_DATA_P_O<6>" LOC="L29"; -NET "DAC_DATA_P_O<7>" LOC="N28"; -NET "DAC_DCLK_N_O" LOC="T26"; -NET "DAC_DCLK_P_O" LOC="R26"; -NET "DAC_FRAME_N_O" LOC="P27"; -NET "DAC_FRAME_P_O" LOC="N27"; -NET "DAC_N_EN_O" LOC="N33"; -NET "DAC_SDO_I" LOC="M33"; -NET "TXENABLE_O" LOC="B33"; - -# UP Status MMCM <-> Led signals GPIO_LED_C -#NET "UP_STATUS<2>" LOC="AP24" | IOSTANDARD = "LVCMOS25"; -# UP Status CDCE_PLL <-> Led signals GPIO_LED_W -#NET "UP_STATUS<1>" LOC="AD21" | IOSTANDARD = "LVCMOS25"; - -################################################################################ -# Clock Constraints -################################################################################ -NET "adc_clk_ab_n_i" TNM_NET = adc_clk_ab_n_i; -TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 16.276 ns HIGH 50%; -#TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 61.44 MHz HIGH 50%; -#TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 122.88 MHz HIGH 50%; -#TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 98.304 MHz HIGH 50%; -NET "adc_clk_ab_p_i" TNM_NET = adc_clk_ab_p_i; -TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 16.276 ns HIGH 50%; -#TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 61.44 MHz HIGH 50%; -#TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 122.88 MHz HIGH 50%; -#TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 98.304 MHz HIGH 50%; - -################################################################################ -# Timing Constraints -################################################################################ -INST "adc_cha_n_i<0>" TNM = TMN_fmc150_adc_cha_n; -INST "adc_cha_n_i<1>" TNM = TMN_fmc150_adc_cha_n; -INST "adc_cha_n_i<2>" TNM = TMN_fmc150_adc_cha_n; -INST "adc_cha_n_i<3>" TNM = TMN_fmc150_adc_cha_n; -INST "adc_cha_n_i<4>" TNM = TMN_fmc150_adc_cha_n; -INST "adc_cha_n_i<5>" TNM = TMN_fmc150_adc_cha_n; -INST "adc_cha_n_i<6>" TNM = TMN_fmc150_adc_cha_n; -TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_n_i" RISING; -#TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_n_i" RISING; -#TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_n_i" RISING; -INST "adc_cha_p_i<0>" TNM = TMN_fmc150_adc_cha_p; -INST "adc_cha_p_i<1>" TNM = TMN_fmc150_adc_cha_p; -INST "adc_cha_p_i<2>" TNM = TMN_fmc150_adc_cha_p; -INST "adc_cha_p_i<3>" TNM = TMN_fmc150_adc_cha_p; -INST "adc_cha_p_i<4>" TNM = TMN_fmc150_adc_cha_p; -INST "adc_cha_p_i<5>" TNM = TMN_fmc150_adc_cha_p; -INST "adc_cha_p_i<6>" TNM = TMN_fmc150_adc_cha_p; -TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_p_i" RISING; -#TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_p_i" RISING; -#TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_p_i" RISING; -INST "adc_chb_n_i<0>" TNM = TMN_fmc150_adc_chb_n; -INST "adc_chb_n_i<1>" TNM = TMN_fmc150_adc_chb_n; -INST "adc_chb_n_i<2>" TNM = TMN_fmc150_adc_chb_n; -INST "adc_chb_n_i<3>" TNM = TMN_fmc150_adc_chb_n; -INST "adc_chb_n_i<4>" TNM = TMN_fmc150_adc_chb_n; -INST "adc_chb_n_i<5>" TNM = TMN_fmc150_adc_chb_n; -INST "adc_chb_n_i<6>" TNM = TMN_fmc150_adc_chb_n; -TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_n_i" RISING; -#TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_n_i" RISING; -#TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_n_i" RISING; -INST "adc_chb_p_i<0>" TNM = TMN_fmc150_adc_chb_p; -INST "adc_chb_p_i<1>" TNM = TMN_fmc150_adc_chb_p; -INST "adc_chb_p_i<2>" TNM = TMN_fmc150_adc_chb_p; -INST "adc_chb_p_i<3>" TNM = TMN_fmc150_adc_chb_p; -INST "adc_chb_p_i<4>" TNM = TMN_fmc150_adc_chb_p; -INST "adc_chb_p_i<5>" TNM = TMN_fmc150_adc_chb_p; -INST "adc_chb_p_i<6>" TNM = TMN_fmc150_adc_chb_p; -TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_p_i" RISING; -#TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_p_i" RISING; -#TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_p_i" RISING; - -################################################################################ -# Crossing Clock Domain FIFO Constraints -################################################################################ - -#NET "fmc150_if_dma_0/fmc150_if_dma_0/USER_LOGIC_I/cmp_fmc150_testbench/adc_str_out" TNM_NET = "CLK_ADC_GRP"; -#NET "clock_generator_0/clock_generator_0/SIG_MMCM0_CLKOUT2" TNM_NET = "CLK_DMA_GRP"; - -#INST "*/gen_fifo_inst*" TPTHRU = "ASYNC_FIFO"; - -#TIMESPEC TS_CC_AB = FROM "CLK_ADC_GRP" THRU "ASYNC_FIFO" TO "CLK_DMA_GRP" TIG; -#TIMESPEC TS_CC_BA = FROM "CLK_DMA_GRP" THRU "ASYNC_FIFO" TO "CLK_ADC_GRP" TIG; diff --git a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd b/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd deleted file mode 100755 index f49f3d1e..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd +++ /dev/null @@ -1,755 +0,0 @@ --- Simple DBE simple design --- Created by Lucas Russo --- Date: 11/10/2012 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Memory core generator -use work.gencores_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Wishbone stream modules and interface -use work.wb_stream_pkg.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dbe_bpm_simple_top is - port( - ----------------------------------------- - -- Clocking pins - ----------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - ----------------------------------------- - -- Reset Button - ----------------------------------------- - sys_rst_button_i : in std_logic; - - ----------------------------------------- - -- FMC150 pins - ----------------------------------------- - --Clock/Data connection to ADC on FMC150 (ADS62P49) - adc_clk_ab_p_i : in std_logic; - adc_clk_ab_n_i : in std_logic; - adc_cha_p_i : in std_logic_vector(6 downto 0); - adc_cha_n_i : in std_logic_vector(6 downto 0); - adc_chb_p_i : in std_logic_vector(6 downto 0); - adc_chb_n_i : in std_logic_vector(6 downto 0); - - --Clock/Data connection to DAC on FMC150 (DAC3283) - dac_dclk_p_o : out std_logic; - dac_dclk_n_o : out std_logic; - dac_data_p_o : out std_logic_vector(7 downto 0); - dac_data_n_o : out std_logic_vector(7 downto 0); - dac_frame_p_o : out std_logic; - dac_frame_n_o : out std_logic; - txenable_o : out std_logic; - - --Clock/Trigger connection to FMC150 - --clk_to_fpga_p_i : in std_logic; - --clk_to_fpga_n_i : in std_logic; - --ext_trigger_p_i : in std_logic; - --ext_trigger_n_i : in std_logic; - - -- Control signals from/to FMC150 - --Serial Peripheral Interface (SPI) - spi_sclk_o : out std_logic; -- Shared SPI clock line - spi_sdata_o : out std_logic; -- Shared SPI data line - - -- ADC specific signals - adc_n_en_o : out std_logic; -- SPI chip select - adc_sdo_i : in std_logic; -- SPI data out - adc_reset_o : out std_logic; -- SPI reset - - -- CDCE specific signals - cdce_n_en_o : out std_logic; -- SPI chip select - cdce_sdo_i : in std_logic; -- SPI data out - cdce_n_reset_o : out std_logic; - cdce_n_pd_o : out std_logic; - cdce_ref_en_o : out std_logic; - cdce_pll_status_i : in std_logic; - - -- DAC specific signals - dac_n_en_o : out std_logic; -- SPI chip select - dac_sdo_i : in std_logic; -- SPI data out - - -- Monitoring specific signals - mon_n_en_o : out std_logic; -- SPI chip select - mon_sdo_i : in std_logic; -- SPI data out - mon_n_reset_o : out std_logic; - mon_n_int_i : in std_logic; - - --FMC Present status - prsnt_m2c_l_i : in std_logic; - - ----------------------------------------- - -- UART pins - ----------------------------------------- - - uart_txd_o : out std_logic; - uart_rxd_i : in std_logic; - - ----------------------------------------- - -- Button pins - ----------------------------------------- - buttons_i : in std_logic_vector(7 downto 0); - - ----------------------------------------- - -- User LEDs - ----------------------------------------- - leds_o : out std_logic_vector(7 downto 0) - ); -end dbe_bpm_simple_top; - -architecture rtl of dbe_bpm_simple_top is - - -- Top crossbar layout - -- Number of slaves - constant c_slaves : natural := 7; -- LED, Button, Dual-port memory, UART, DMA control port, FMC150 - -- Number of masters - constant c_masters : natural := 4; -- LM32 master. Data + Instruction, DMA read+write master - --constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB) - constant c_dpram_size : natural := 22528; -- in 32-bit words (64KB) - - -- Number of source/sink Wishbone stream components - constant c_sinks : natural := 1; - constant c_sources : natural := c_sinks; - - -- GPIO num pins - constant c_leds_num_pins : natural := 8; - constant c_buttons_num_pins : natural := 8; - - -- Counter width. It willl count up to 2^32 clock cycles - constant c_counter_width : natural := 32; - - -- Number of reset clock cycles (FF) - constant c_button_rst_width : natural := 255; - - -- WB SDB (Self describing bus) layout - constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) := - ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 64KB RAM - 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory - 2 => f_sdb_embed_device(c_xwb_dma_sdb, x"20000400"), -- DMA control port - 3 => f_sdb_embed_device(c_xwb_fmc150_sdb, x"20000500"), -- FMC control port - 4 => f_sdb_embed_device(c_xwb_uart_sdb, x"20000600"), -- UART control port - 5 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000700"), -- GPIO LED - 6 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000800") -- GPIO Button - --7 => f_sdb_embed_device(c_xwb_irqmngr_sdb, x"20000900") -- IRQ_MNGR - ); - - -- Self Describing Bus ROM Address. It will be an addressed slave as well. - constant c_sdb_address : t_wishbone_address := x"20000000"; - - -- Crossbar master/slave arrays - signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0); - signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0); - signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0); - signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0); - - -- Wishbone Stream source/sinks arrays - signal wbs_src_i : t_wbs_source_in_array(c_sources-1 downto 0); - signal wbs_src_o : t_wbs_source_out_array(c_sources-1 downto 0); - - -- Check the use of this kind of alias - alias wbs_sink_i is wbs_src_o; - alias wbs_sink_o is wbs_src_i; - - -- LM32 signals - signal clk_sys : std_logic; - signal lm32_interrupt : std_logic_vector(31 downto 0); - signal lm32_rstn : std_logic; - - -- Clocks and resets signals - signal locked : std_logic; - signal clk_sys_rstn : std_logic; - signal clk_adc_rstn : std_logic; - - signal rst_button_sys_pp : std_logic; - signal rst_button_adc_pp : std_logic; - - signal rst_button_sys : std_logic; - signal rst_button_adc : std_logic; - signal rst_button_sys_n : std_logic; - signal rst_button_adc_n : std_logic; - - -- Only one clock domain - signal reset_clks : std_logic_vector(1 downto 0); - signal reset_rstn : std_logic_vector(1 downto 0); - - -- 200 Mhz clocck for iodelatctrl - signal clk_200mhz : std_logic; - - -- Global Clock Single ended - signal sys_clk_gen : std_logic; - - -- GPIO LED signals - signal gpio_slave_led_o : t_wishbone_slave_out; - signal gpio_slave_led_i : t_wishbone_slave_in; - signal s_leds : std_logic_vector(c_leds_num_pins-1 downto 0); - -- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0); - - -- GPIO Button signals - signal gpio_slave_button_o : t_wishbone_slave_out; - signal gpio_slave_button_i : t_wishbone_slave_in; - - -- IRQ manager signals - --signal gpio_slave_irqmngr_o : t_wishbone_slave_out; - --signal gpio_slave_irqmngr_i : t_wishbone_slave_in; - - -- LEDS, button and irq manager signals - --signal r_leds : std_logic_vector(7 downto 0); - --signal r_reset : std_logic; - - -- Counter signal - signal s_counter : unsigned(c_counter_width-1 downto 0); - -- 100MHz period or 1 second - constant s_counter_full : integer := 100000000; - - -- FMC150 signals - signal clk_adc : std_logic; - - -- Chipscope control signals - signal CONTROL0 : std_logic_vector(35 downto 0); - signal CONTROL1 : std_logic_vector(35 downto 0); - - -- Chipscope ILA 0 signals - signal TRIG_ILA0_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA0_3 : std_logic_vector(31 downto 0); - - -- Chipscope ILA 1 signals - signal TRIG_ILA1_0 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_1 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_2 : std_logic_vector(31 downto 0); - signal TRIG_ILA1_3 : std_logic_vector(31 downto 0); - - --------------------------- - -- Components -- - --------------------------- - - -- Clock generation - component clk_gen is - port( - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - sys_clk_o : out std_logic - ); - end component; - - -- Xilinx Megafunction - component sys_pll is - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); - end component; - - -- Xilinx Chipscope Controller - component chipscope_icon_1_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Controller 2 port - component chipscope_icon_2_port - port ( - CONTROL0 : inout std_logic_vector(35 downto 0); - CONTROL1 : inout std_logic_vector(35 downto 0) - ); - end component; - - -- Xilinx Chipscope Logic Analyser - component chipscope_ila - port ( - CONTROL : inout std_logic_vector(35 downto 0); - CLK : in std_logic; - TRIG0 : in std_logic_vector(31 downto 0); - TRIG1 : in std_logic_vector(31 downto 0); - TRIG2 : in std_logic_vector(31 downto 0); - TRIG3 : in std_logic_vector(31 downto 0) - ); - end component; - - -- Functions - -- Generate dummy (0) values - function f_zeros(size : integer) - return std_logic_vector is - begin - return std_logic_vector(to_unsigned(0, size)); - end f_zeros; -begin - - -- Clock generation - cmp_clk_gen : clk_gen - port map ( - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - sys_clk_o => sys_clk_gen - ); - - -- Obtain core locking and generate necessary clocks - cmp_sys_pll_inst : sys_pll - port map ( - rst_i => '0', - clk_i => sys_clk_gen, - clk0_o => clk_sys, -- 100MHz locked clock - clk1_o => clk_200mhz, -- 200MHz locked clock - locked_o => locked -- '1' when the PLL has locked - ); - - -- Reset synchronization. Hold reset line until few locked cycles have passed. - -- Is this a safe approach to ADC reset domain? - cmp_reset : gc_reset - generic map( - g_clocks => 2 -- CLK_SYS + CLK_ADC - ) - port map( - free_clk_i => sys_clk_gen, - locked_i => locked, - clks_i => reset_clks, - rstn_o => reset_rstn - ); - - -- Generate button reset synchronous to each clock domain - -- Detect button positive edge of clk_sys - cmp_button_sys_ffs : gc_sync_ffs - port map ( - clk_i => clk_sys, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_sys_pp - ); - - -- Detect button positive edge of clk_adc - cmp_button_adc_ffs : gc_sync_ffs - port map ( - clk_i => clk_adc, - rst_n_i => '1', - data_i => sys_rst_button_i, - ppulse_o => rst_button_adc_pp - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_sys_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_sys, - rst_n_i => '1', - pulse_i => rst_button_sys_pp, - extended_o => rst_button_sys - ); - - -- Generate the reset signal based on positive edge - -- of synched sys_rst_button_i - cmp_button_adc_rst : gc_extend_pulse - generic map ( - g_width => c_button_rst_width - ) - port map( - clk_i => clk_adc, - rst_n_i => '1', - pulse_i => rst_button_adc_pp, - extended_o => rst_button_adc - ); - - rst_button_sys_n <= not rst_button_sys; - rst_button_adc_n <= not rst_button_adc; - - reset_clks(0) <= clk_sys; - reset_clks(1) <= clk_adc; - clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n; - clk_adc_rstn <= reset_rstn(1) and rst_button_adc_n; - - -- The top-most Wishbone B.4 crossbar - cmp_interconnect : xwb_sdb_crossbar - generic map( - g_num_masters => c_masters, - g_num_slaves => c_slaves, - g_registered => true, - g_wraparound => false, -- Should be true for nested buses - g_layout => c_layout, - g_sdb_addr => c_sdb_address - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- Master connections (INTERCON is a slave) - slave_i => cbar_slave_i, - slave_o => cbar_slave_o, - -- Slave connections (INTERCON is a master) - master_i => cbar_master_i, - master_o => cbar_master_o - ); - - -- The LM32 is master 0+1 - lm32_rstn <= clk_sys_rstn; - - cmp_lm32 : xwb_lm32 - generic map( - g_profile => "medium_icache_debug" - ) -- Including JTAG and I-cache (no divide) - port map( - clk_sys_i => clk_sys, - rst_n_i => lm32_rstn, - irq_i => lm32_interrupt, - dwb_o => cbar_slave_i(0), -- Data bus - dwb_i => cbar_slave_o(0), - iwb_o => cbar_slave_i(1), -- Instruction bus - iwb_i => cbar_slave_o(1) - ); - - -- Interrupts 31 downto 1 disabled for now. - -- Interrupt '0' is DMA completion. - lm32_interrupt(31 downto 1) <= (others => '0'); - - -- A DMA controller is master 2+3, slave 2, and interrupt 0 - cmp_dma : xwb_dma - port map( - clk_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(2), - slave_o => cbar_master_i(2), - r_master_i => cbar_slave_o(2), - r_master_o => cbar_slave_i(2), - w_master_i => cbar_slave_o(3), - w_master_o => cbar_slave_i(3), - interrupt_o => lm32_interrupt(0) - ); - - -- Slave 0+1 is the RAM. Load a input file containing a simple led blink program! - cmp_ram : xwb_dpram - generic map( - g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4 - g_init_file => "../../../embedded-sw/dbe.ram",--"../../top/ml_605/dbe_bpm_simple/sw/main.ram", - g_must_have_init_file => true, - g_slave1_interface_mode => PIPELINED, - g_slave2_interface_mode => PIPELINED, - g_slave1_granularity => BYTE, - g_slave2_granularity => BYTE - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - -- First port connected to the crossbar - slave1_i => cbar_master_o(0), - slave1_o => cbar_master_i(0), - -- Second port connected to the crossbar - slave2_i => cbar_master_o(1), - slave2_o => cbar_master_i(1) - --slave2_i => cc_dummy_slave_in, -- CYC always low - --slave2_o => open - ); - - -- Slave 3 is the FMC150 interface - cmp_xwb_fmc150 : xwb_fmc150 - generic map( - g_interface_mode => CLASSIC, - g_address_granularity => BYTE - --g_packet_size => 32, - --g_sim => 0 - ) - port map( - rst_n_i => clk_sys_rstn, - clk_sys_i => clk_sys, - --clk_100Mhz_i : in std_logic; - clk_200Mhz_i => clk_200mhz, - - ----------------------------- - -- Wishbone signals - ----------------------------- - - wb_slv_i => cbar_master_o(3), - wb_slv_o => cbar_master_i(3), - - ----------------------------- - -- Simulation Only ports! - ----------------------------- - sim_adc_clk_i => '0', - sim_adc_clk2x_i => '0', - - sim_adc_cha_data_i => f_zeros(14), - sim_adc_chb_data_i => f_zeros(14), - sim_adc_data_valid => '0', - - ----------------------------- - -- External ports - ----------------------------- - --Clock/Data connection to ADC on FMC150 (ADS62P49) - adc_clk_ab_p_i => adc_clk_ab_p_i, - adc_clk_ab_n_i => adc_clk_ab_n_i, - adc_cha_p_i => adc_cha_p_i, - adc_cha_n_i => adc_cha_n_i, - adc_chb_p_i => adc_chb_p_i, - adc_chb_n_i => adc_chb_n_i, - - --Clock/Data connection to DAC on FMC150 (DAC3283) - dac_dclk_p_o => dac_dclk_p_o, - dac_dclk_n_o => dac_dclk_n_o, - dac_data_p_o => dac_data_p_o, - dac_data_n_o => dac_data_n_o, - dac_frame_p_o => dac_frame_p_o, - dac_frame_n_o => dac_frame_n_o, - txenable_o => txenable_o, - - --Clock/Trigger connection to FMC150 - --clk_to_fpga_p_i : in std_logic; - --clk_to_fpga_n_i : in std_logic; - --ext_trigger_p_i : in std_logic; - --ext_trigger_n_i : in std_logic; - - -- Control signals from/to FMC150 - --Serial Peripheral Interface (SPI) - spi_sclk_o => spi_sclk_o, -- Shared SPI clock line - spi_sdata_o => spi_sdata_o,-- Shared SPI data line - - -- ADC specific signals - adc_n_en_o => adc_n_en_o, -- SPI chip select - adc_sdo_i => adc_sdo_i, -- SPI data out - adc_reset_o => adc_reset_o,-- SPI reset - - -- CDCE specific signals - cdce_n_en_o => cdce_n_en_o, -- SPI chip select - cdce_sdo_i => cdce_sdo_i, -- SPI data out - cdce_n_reset_o => cdce_n_reset_o, - cdce_n_pd_o => cdce_n_pd_o, - cdce_ref_en_o => cdce_ref_en_o, - cdce_pll_status_i => cdce_pll_status_i, - - -- DAC specific signals - dac_n_en_o => dac_n_en_o, -- SPI chip select - dac_sdo_i => dac_sdo_i, -- SPI data out - - -- Monitoring specific signals - mon_n_en_o => mon_n_en_o, -- SPI chip select - mon_sdo_i => mon_sdo_i, -- SPI data out - mon_n_reset_o => mon_n_reset_o, - mon_n_int_i => mon_n_int_i, - - --FMC Present status - prsnt_m2c_l_i => prsnt_m2c_l_i, - - -- ADC output signals - -- ADC data is interfaced through the wishbone stream interface (wbs_src_o) - adc_dout_o => open, - clk_adc_o => clk_adc, - - -- Wishbone Streaming Interface Source - wbs_source_i => wbs_src_i(0), - wbs_source_o => wbs_src_o(0) - ); - - -- Slave 4 is the UART - cmp_uart : xwb_simple_uart - generic map ( - g_interface_mode => PIPELINED, - g_address_granularity => BYTE - ) - port map ( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - slave_i => cbar_master_o(4), - slave_o => cbar_master_i(4), - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o - ); - - -- Slave 5 is the example LED driver - cmp_leds : xwb_gpio_port - generic map( - --g_interface_mode => CLASSIC; - g_address_granularity => BYTE, - g_num_pins => c_leds_num_pins, - g_with_builtin_tristates => false - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- Wishbone - slave_i => cbar_master_o(5), - slave_o => cbar_master_i(5), - desc_o => open, -- Not implemented - - --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0); - - gpio_out_o => s_leds, - --gpio_out_o => open, - gpio_in_i => s_leds, - gpio_oen_o => open - ); - - leds_o <= s_leds; - - --p_test_leds : process (clk_adc) - --begin - -- if rising_edge(clk_adc) then - -- if clk_adc_rstn = '0' then - -- s_counter <= (others => '0'); - -- s_leds <= x"55"; - -- else - -- if (s_counter = s_counter_full-1) then - -- s_counter <= (others => '0'); - -- s_leds <= s_leds(c_leds_num_pins-2 downto 0) & s_leds(c_leds_num_pins-1); - -- else - -- s_counter <= s_counter + 1; - -- end if; - -- end if; - -- end if; - --end process; - - -- Slave 1 is the example LED driver - --gpio_slave_led_i <= cbar_master_o(1); - --cbar_master_i(1) <= gpio_slave_led_o; - --leds_o <= not r_leds; - - -- There is a tool called 'wbgen2' which can autogenerate a Wishbone - -- interface and C header file, but this is a simple example. - --gpio : process(clk_sys) - --begin - -- if rising_edge(clk_sys) then - -- It is vitally important that for each occurance of - -- (cyc and stb and not stall) there is (ack or rty or err) - -- sometime later on the bus. - -- - -- This is an easy solution for a device that never stalls: - -- gpio_slave_led_o.ack <= gpio_slave_led_i.cyc and gpio_slave_led_i.stb; - - -- Detect a write to the register byte - -- if gpio_slave_led_i.cyc = '1' and gpio_slave_led_i.stb = '1' and - -- gpio_slave_led_i.we = '1' and gpio_slave_led_i.sel(0) = '1' then - -- Register 0x0 = LEDs, 0x4 = CPU reset - -- if gpio_slave_led_i.adr(2) = '0' then - -- r_leds <= gpio_slave_led_i.dat(7 downto 0); - -- else - -- r_reset <= gpio_slave_led_i.dat(0); - -- end if; - -- end if; - - -- Read to the register byte - -- if gpio_slave_led_i.adr(2) = '0' then - -- gpio_slave_led_o.dat(31 downto 8) <= (others => '0'); - -- gpio_slave_led_o.dat(7 downto 0) <= r_leds; - -- else - -- gpio_slave_led_o.dat(31 downto 2) <= (others => '0'); - -- gpio_slave_led_o.dat(0) <= r_reset; - -- end if; - --end if; - --end process; - - --gpio_slave_led_o.int <= '0'; - --gpio_slave_led_o.err <= '0'; - --gpio_slave_led_o.rty <= '0'; - --gpio_slave_led_o.stall <= '0'; -- This simple example is always ready - - -- Slave 6 is the example Button driver - cmp_buttons : xwb_gpio_port - generic map( - --g_interface_mode => CLASSIC; - g_address_granularity => BYTE, - g_num_pins => c_buttons_num_pins, - g_with_builtin_tristates => false - ) - port map( - clk_sys_i => clk_sys, - rst_n_i => clk_sys_rstn, - - -- Wishbone - slave_i => cbar_master_o(6), - slave_o => cbar_master_i(6), - desc_o => open, -- Not implemented - - --gpio_b : inout std_logic_vector(g_num_pins-1 downto 0); - - gpio_out_o => open, - gpio_in_i => buttons_i, - gpio_oen_o => open - ); - - -- Xilinx Chipscope - cmp_chipscope_icon_0 : chipscope_icon_2_port - port map ( - CONTROL0 => CONTROL0, - CONTROL1 => CONTROL1 - ); - - cmp_chipscope_ila_0 : chipscope_ila - port map ( - CONTROL => CONTROL0, - CLK => clk_sys, - TRIG0 => TRIG_ILA0_0, - TRIG1 => TRIG_ILA0_1, - TRIG2 => TRIG_ILA0_2, - TRIG3 => TRIG_ILA0_3 - ); - - -- FMC150 master output (slave input) control data - TRIG_ILA0_0 <= cbar_master_o(3).dat; - -- FMC150 master input (slave output) control data - TRIG_ILA0_1 <= cbar_master_i(3).dat; - -- FMC150 master control output (slave input) control signals - -- Partial decoding. Thus, only the LSB part of address matters to - -- a specific slave core - TRIG_ILA0_2(16 downto 0) <= cbar_master_o(3).cyc & - cbar_master_o(3).stb & - cbar_master_o(3).adr(9 downto 0) & - cbar_master_o(3).sel & - cbar_master_o(3).we; - - --TRIG_ILA0_2(31 downto 11) <= (others => '0'); - TRIG_ILA0_2(31 downto 17) <= (others => '0'); - - -- FMC150 master control input (slave output) control signals - TRIG_ILA0_3(4 downto 0) <= cbar_master_i(3).ack & - cbar_master_i(3).err & - cbar_master_i(3).rty & - cbar_master_i(3).stall & - cbar_master_i(3).int; - TRIG_ILA0_3(31 downto 5) <= (others => '0'); - - cmp_chipscope_ila_1 : chipscope_ila - port map ( - CONTROL => CONTROL1, - CLK => clk_adc, - TRIG0 => TRIG_ILA1_0, - TRIG1 => TRIG_ILA1_1, - TRIG2 => TRIG_ILA1_2, - TRIG3 => TRIG_ILA1_3 - ); - - -- FMC150 source output (sink input) stream data - TRIG_ILA1_0 <= wbs_src_o(0).dat; - -- FMC150 source input (sink output) stream data - --TRIG_ILA1_1 <= wbs_src_i(0).dat; - -- FMC150 source control output (sink input) stream signals - -- Partial decoding. Thus, only the LSB part of address matters to - -- a specific slave core - TRIG_ILA1_1(10 downto 0) <= wbs_src_o(0).cyc & - wbs_src_o(0).stb & - wbs_src_o(0).adr(3 downto 0) & - wbs_src_o(0).sel & - wbs_src_o(0).we; - TRIG_ILA1_1(31 downto 11) <= (others => '0'); - - -- FMC150 master control input (slave output) stream signals - TRIG_ILA1_2(3 downto 0) <= wbs_src_i(0).ack & - wbs_src_i(0).err & - wbs_src_i(0).rty & - wbs_src_i(0).stall; - TRIG_ILA1_2(31 downto 4) <= (others => '0'); - TRIG_ILA1_3(31 downto 0) <= (others => '0'); -end rtl; diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/Makefile b/hdl/top/ml_605/dbe_bpm_simple/sw/Makefile deleted file mode 100644 index 48fb2961..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -PLATFORM = lm32 - -OBJS_WRC = main.o gpio.o dma.o uart.o fmc150.o target/lm32/crt0.o - -CROSS_COMPILE ?= /opt/gcc-lm32/bin/lm32-elf- -CFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -I. -LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -nostdlib -T target/lm32/ram.ld - -CC=$(CROSS_COMPILE)gcc -OBJCOPY=$(CROSS_COMPILE)objcopy -OBJDUMP=$(CROSS_COMPILE)objdump -CFLAGS= $(CFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude $(PTPD_CFLAGS) -Iptp-noposix/PTPWRd -LDFLAGS= $(LDFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude -SIZE = $(CROSS_COMPILE)size -OBJS=$(OBJS_PLATFORM) $(OBJS_WRC) $(OBJS_PTPD) $(OBJS_PTPD_FREE) -OUTPUT=main - -all: $(OBJS) - $(SIZE) -t $(OBJS) - ${CC} -o $(OUTPUT).elf $(OBJS) $(LDFLAGS) - ${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin - ${OBJDUMP} -d $(OUTPUT).elf > $(OUTPUT)_disasm.S - ./genraminit $(OUTPUT).bin 0 > $(OUTPUT).ram - -clean: - rm -f $(OBJS) $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram $(OUTPUT)_disasm.S - -%.o: %.c %.h - ${CC} $(CFLAGS) $(PTPD_CFLAGS) $(INCLUDE_DIR) $(LIB_DIR) -c $^ -o $@ diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/dma.c b/hdl/top/ml_605/dbe_bpm_simple/sw/dma.c deleted file mode 100644 index 12709450..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/dma.c +++ /dev/null @@ -1,27 +0,0 @@ -#include "dma.h" - -/* DMA user interface definition */ -inline int read_is_addr(dma_t dma) -{ - return dma->RD_ADDR; -} - -inline void write_is_addr(dma_t dma, int addr) -{ - dma->WR_ADDR = (uint32_t) addr; -} - -inline int read_strd(dma_t dma) -{ - return dma->RD_STRD; -} - -inline void write_strd(dma_t dma, int strd) -{ - dma->WR_STRD = (uint32_t) strd; -} - -inline int read_tr_count(dma_t dma) -{ - return dma->TR_COUNT; -} diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/fmc150.c b/hdl/top/ml_605/dbe_bpm_simple/sw/fmc150.c deleted file mode 100644 index ea4ffd7c..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/fmc150.c +++ /dev/null @@ -1,3 +0,0 @@ -#include "board.h" -#include "inttypes.h" -#include "fmc150.h" diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/genraminit b/hdl/top/ml_605/dbe_bpm_simple/sw/genraminit deleted file mode 100755 index 410bd34965a01f82b454914d70c14396d42da49d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8698 zcmeHMeQaCR6~DHV)cuOnQXsT!^_VLa)VgV#RtCg)Y2x&yGi@p96h6v}6FZHmV|Vs5 zO{*fpQqYVk%Oo_=rU|4?Q>Fcb#1<8pwshSH{4p6l>=uWp5NXEOFDZ@DMUqolOTT0YqgZkB+Hf_6WKoL^r}4w7)rRw& zpfbM=x33%PZMc2jwApZ;BUDewhO4Pbu+YaZd5eDmQyhT%#S!?VkN?4YRu&>FZF_Qw zUzFB8h1|DR14r^O70=F;kk);VWa|3tIVm3_nYuhXCFKms)YaJ+rTh@d)Wz8sq&z?} zb!~P+%J-2>U78(}@;;I&yt9WPZ~mYs|K@{w{#||ipL2VAd#0ye^lCz%KI4~U`marz zC_W3tPbMa)Z+fBe<;8xXKR#u;OXpDl|@$$*t!z@4nXf5?B{CcmIL2 zLqkJB-`W%C0@>X$u?X!@yXMN%5`u5u1HaSJP-*7C*@+1%gG+7sM=t33+_{)uXjr$N zZ1dsy%~Ru#TyQ_Spj=rLec01Nx)WBS%rGDv1)aTEn_AdZyud@^u8 zl8*&u^phJuZuE=D$#s{A053-JW?(LoKOTUm4+IdvOQFck?{(zA?8#r&&wT0W$^X6h z_7`yd@ej-!H@{8eKa&3}lE2)Q|FEO9>ViIg7GvUK?tQ)RKmf5%23jJ8SfDim&L1h5 zf%TEX@jx4fLFlY+?HKjwW966So%LVK@rM!D2fy_3`I33VtMpn|se+%9LXfixPRTKe_h*_KKru-ZM)WZZl`fXe``Cs)dhMARU|<_ z!N2kp=m`v~UxCv5jgsrwKH(Z|ajjXl$V=Y{0buk^Q~bPCnjnSdmhR@(UB0D9ykp|d z)wkcWHEbA!^SUzO5CpL1(O%6q$09!utLv(s)%rgfOo5sQeWinc0xt)fi$8?or?mk_Uk zQ%Zr?Y5pd?Ug2X6n&cQCRx+)rl(;?q7GxRAtn5!n=_5{3=D5r$*{{m2+W!AJ?^m5I zJ*@thClvjWqQ6jdQqk8GeM`}QDeA0mXJ_Ya{`LC@aw#*nDUwJm;#?3hi zZoAo%g$QPkj+oH_P%~rEVdk)PiDwRrU@C3KgB?41Hk#3cN;;Uz1qX5oY&;V&5hQ6i znjIFw*wGZ~v#6P|N*<19vWax6N-$8Ci6^6Ept!?HQv?&K1adPzihKwH%F?l@85P0! zurZX0j>L`O7;IS*!9g>f$)Z7vJT!bL`1!--W`C9Zm&IV|5wpvH<1@d>{auz8eeS} zC2!4x<>JOBt*VUXSA+Pdyx-zN`Yv+e=7860#%aE~#KJg)B)%{XVc>4DTxgDV@0a=& z|9Rd#r0_n~FP@L1s-71e_0;qKgsf+!XmiB>hZ0{Q<{jhYd5JId|Cg%WDX#{ulFopw z6*qd{(2YyL(e6Khx@wGvVjca@rT)V4umXWviFnd!Iwf9yz5(2iuQBI1*&y|$YE^b8 z@D}{<&hbNMfVJ+6?vwb!dDmY@|9Bmo-j^%f*9bbix2K=h(fGSuYr7grwO5Yjh zpwg#%5K8jw6?Ch_B~+Dl1NT=UmT+Gk{iMWetha;FWYTuUCk8WS*39ANV-S~hoxOYZ z8IhiQdU5k-7+qD;u1;G~ENvW2rU#-)LvBlrXl_(s%Xv5%H{-G3_HA1?3o0-Yu~Cw? z;!couwz1sE$Wd-5yt_*_)4i|buCT!pHN$+R6}bnNtsIP}P!;W>rN_h=(M%?K)QG2I z!sxnpcgI~looK^WA}=$Au`{w~M@Pii)7^bfxYy|I*bxa+H{}iGU^ZvS?KthBt@}#r z9#hl!#**$Sjkw%nTNj; -#include - -int main(int argc, char *argv[]) -{ - if(argc < 3) return -1; - FILE *f = fopen(argv[1],"rb"); - if(!f) return -1; - unsigned char x[4]; - int i=0; - int n = atoi(argv[2]); - - while(!feof(f)){ - fread(x,1,4,f); - printf("write %x %02X%02X%02X%02X\n", i++, x[0],x[1],x[2],x[3]); - } - - for(;iSODR = (1<CODR = (1<DDR |= (1<DDR &= ~(1<PSR & (1< - -#if defined( __GNUC__) -#define PACKED __attribute__ ((packed)) -#else -#error "Unsupported compiler?" -#endif - -#ifndef __WBGEN2_MACROS_DEFINED__ -#define __WBGEN2_MACROS_DEFINED__ -#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset)) -#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset)) -#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1)) -#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1< - -#if defined( __GNUC__) -#define PACKED __attribute__ ((packed)) -#else -#error "Unsupported compiler?" -#endif - -#ifndef __WBGEN2_MACROS_DEFINED__ -#define __WBGEN2_MACROS_DEFINED__ -#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset)) -#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset)) -#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1)) -#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1< - -#if defined( __GNUC__) -#define PACKED __attribute__ ((packed)) -#else -#error "Unsupported compiler?" -#endif - -#ifndef __WBGEN2_MACROS_DEFINED__ -#define __WBGEN2_MACROS_DEFINED__ -#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset)) -#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset)) -#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1)) -#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1< - -/* Type definitions */ -typedef volatile struct UART_WB * uart_t; - -int mprintf(char const *format, ...); - -/* UART API */ -void uart_init(uart_t uart); -void uart_write_byte(uart_t uart, int b); -void uart_write_string(uart_t uart, char *s); -int uart_poll(uart_t uart); -int uart_read_byte(uart_t uart); - -#endif diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/main.c b/hdl/top/ml_605/dbe_bpm_simple/sw/main.c deleted file mode 100644 index 6f7e0c88..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/main.c +++ /dev/null @@ -1,73 +0,0 @@ -#include "gpio.h" -#include "dma.h" -//#include "fmc150.h" -#include "uart.h" - -/* Each loop iteration takes 4 cycles. -* It runs at 100MHz. -* Sleep 0.2 second. -*/ -#define LED_DELAY (100000000/4/5) -#define UART_DELAY (100000000/4/5) - -static inline int delay(int x) -{ - while(x--) asm volatile("nop"); -} - -/* Placeholder for IRQ vector */ -void _irq_entry(void){} - -int main(void) -{ - int i, j; - gpio_t leds = (volatile struct GPIO_WB *) BASE_LEDS_ADDR; - gpio_t buttons = (volatile struct GPIO_WB *) BASE_BUTTONS_ADDR; - dma_t dma = (volatile struct DMA_WB *) BASE_DMA_ADDR; - uart_t uart = (volatile struct UART_WB *) BASE_UART_ADDR; - - /* Initialize Board. Should be in a speparete function and file */ - uart_init(uart); - - /* It would be nice to employ a callback system. For this to work, - a hardware timer should be running with a eishbone interface - and a interrupt pin to LM32 processor */ - - /* Test UART */ - uart_write_byte(uart, 'A'); - delay(UART_DELAY); - uart_write_byte(uart, 'B'); - delay(UART_DELAY); - uart_write_byte(uart, 'C'); - delay(UART_DELAY); - uart_write_byte(uart, 'D'); - delay(UART_DELAY); - uart_write_byte(uart, 'E'); - delay(UART_DELAY); - uart_write_byte(uart, 'F'); - delay(UART_DELAY); - uart_write_byte(uart, 'G'); - delay(UART_DELAY); - uart_write_byte(uart, 'H'); - delay(UART_DELAY); - - /* Test LEDs */ - while (1) { - /* Rotate the LEDs */ - for (i = 0; i < 8; ++i) { - // Set led at position i - gpio_out(leds, i, 1); - - /* Each loop iteration takes 4 cycles. - * It runs at 100MHz. - * Sleep 0.2 second. - */ - delay(LED_DELAY); - - // Clear led at position i - gpio_out(leds, i, 0); - } - } - - return 0; -} diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/crt0.S b/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/crt0.S deleted file mode 100755 index de7de225..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/crt0.S +++ /dev/null @@ -1,259 +0,0 @@ -/**************************************************************************** -** -** Name: crt0ram.S -** -** Description: -** Implements boot-code that calls LatticeDDInit (that calls main()) -** Implements exception handlers (actually, redirectors) -** -** $Revision: $ -** -** Disclaimer: -** -** This source code is intended as a design reference which -** illustrates how these types of functions can be implemented. It -** is the user's responsibility to verify their design for -** consistency and functionality through the use of formal -** verification methods. Lattice Semiconductor provides no warranty -** regarding the use or functionality of this code. -** -** -------------------------------------------------------------------- -** -** Lattice Semiconductor Corporation -** 5555 NE Moore Court -** Hillsboro, OR 97214 -** U.S.A -** -** TEL: 1-800-Lattice (USA and Canada) -** (503)268-8001 (other locations) -** -** web: http://www.latticesemi.com -** email: techsupport@latticesemi.com -** -** -------------------------------------------------------------------------- -** -** Change History (Latest changes on top) -** -** Ver Date Description -** -------------------------------------------------------------------------- -** 3.8 Apr-15-2011 Added __MICO_USER__HANDLER__ preprocessor to -** allow customers to implement their own handlers for: -** DATA_ABORT, INST_ABORT -** -** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor -** option to exclude invoking MicoISRHandler -** to reduce code-size in apps that don't use -** interrupts -** -** 3.0 Mar-25-2008 Added Header -** -**--------------------------------------------------------------------------- -*****************************************************************************/ - -/* - * LatticeMico32 C startup code. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* From include/sys/signal.h */ -#define SIGINT 2 /* interrupt */ -#define SIGTRAP 5 /* trace trap */ -#define SIGFPE 8 /* arithmetic exception */ -#define SIGSEGV 11 /* segmentation violation */ - -//#define MICO32_FULL_CONTEXT_SAVE_RESTORE - - -/* Exception handlers - Must be 32 bytes long. */ - .section .boot, "ax", @progbits - - .global _start -_start: - - .global _reset_handler - .type _reset_handler, @function -_reset_handler: - xor r0, r0, r0 - wcsr IE, r0 - wcsr IM, r0 - mvhi r1, hi(_reset_handler) - ori r1, r1, lo(_reset_handler) - wcsr EBA, r1 - calli _crt0 - nop - .size _reset_handler, .-_reset_handler - -.extern _irq_entry -.org 0xc0 - .global _interrupt_handler - .type _interrupt_handler, @function -_interrupt_handler: - sw (sp+0), ra - calli _save_all - mvi r1, SIGINT -#ifndef __MICO_NO_INTERRUPTS__ - calli _irq_entry -#else - wcsr IE, r0 -#endif - bi _restore_all_and_return - nop - nop - nop - -.org 0x100 - .global _crt0 - .type _crt0, @function -_crt0: - /* Clear r0 */ - xor r0, r0, r0 - /* Setup stack and global pointer */ - mvhi sp, hi(_fstack) - ori sp, sp, lo(_fstack) - mvhi gp, hi(_gp) - ori gp, gp, lo(_gp) - - mvhi r1, hi(_fbss) - ori r1, r1, lo(_fbss) - mvi r2, 0 - mvhi r3, hi(_ebss) - ori r3, r3, lo(_ebss) - sub r3, r3, r1 - calli memset - mvi r1, 0 - mvi r2, 0 - mvi r3, 0 - calli main - -loopf: - bi loopf - - .global _save_all - .type _save_all, @function -_save_all: -#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE - addi sp, sp, -128 -#else - addi sp, sp, -60 -#endif - sw (sp+4), r1 - sw (sp+8), r2 - sw (sp+12), r3 - sw (sp+16), r4 - sw (sp+20), r5 - sw (sp+24), r6 - sw (sp+28), r7 - sw (sp+32), r8 - sw (sp+36), r9 - sw (sp+40), r10 -#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE - sw (sp+44), r11 - sw (sp+48), r12 - sw (sp+52), r13 - sw (sp+56), r14 - sw (sp+60), r15 - sw (sp+64), r16 - sw (sp+68), r17 - sw (sp+72), r18 - sw (sp+76), r19 - sw (sp+80), r20 - sw (sp+84), r21 - sw (sp+88), r22 - sw (sp+92), r23 - sw (sp+96), r24 - sw (sp+100), r25 - sw (sp+104), r26 - sw (sp+108), r27 - sw (sp+120), ea - sw (sp+124), ba - /* ra and sp need special handling, as they have been modified */ - lw r1, (sp+128) - sw (sp+116), r1 - mv r1, sp - addi r1, r1, 128 - sw (sp+112), r1 -#else - sw (sp+52), ea - sw (sp+56), ba - /* ra and sp need special handling, as they have been modified */ - lw r1, (sp+60) - sw (sp+48), r1 - mv r1, sp - addi r1, r1, 60 - sw (sp+44), r1 -#endif -// xor r1, r1, r1 -// wcsr ie, r1 - ret - .size _save_all, .-_save_all - - .global _restore_all_and_return - .type _restore_all_and_return, @function - /* Restore all registers and return from exception */ -_restore_all_and_return: -// addi r1, r0, 2 -// wcsr ie, r1 - lw r1, (sp+4) - lw r2, (sp+8) - lw r3, (sp+12) - lw r4, (sp+16) - lw r5, (sp+20) - lw r6, (sp+24) - lw r7, (sp+28) - lw r8, (sp+32) - lw r9, (sp+36) - lw r10, (sp+40) -#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE - lw r11, (sp+44) - lw r12, (sp+48) - lw r13, (sp+52) - lw r14, (sp+56) - lw r15, (sp+60) - lw r16, (sp+64) - lw r17, (sp+68) - lw r18, (sp+72) - lw r19, (sp+76) - lw r20, (sp+80) - lw r21, (sp+84) - lw r22, (sp+88) - lw r23, (sp+92) - lw r24, (sp+96) - lw r25, (sp+100) - lw r26, (sp+104) - lw r27, (sp+108) - lw ra, (sp+116) - lw ea, (sp+120) - lw ba, (sp+124) - /* Stack pointer must be restored last, in case it has been updated */ - lw sp, (sp+112) -#else - lw ra, (sp+48) - lw ea, (sp+52) - lw ba, (sp+56) - /* Stack pointer must be restored last, in case it has been updated */ - lw sp, (sp+44) -#endif - nop - eret - .size _restore_all_and_return, .-_restore_all_and_return - diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/irq.c b/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/irq.c deleted file mode 100644 index cb2c8fed..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/irq.c +++ /dev/null @@ -1,36 +0,0 @@ -#include "irq.h" - -void disable_irq() -{ - unsigned int ie, im; - unsigned int Mask = ~1; - - /* disable peripheral interrupts in case they were enabled */ - asm volatile ("rcsr %0,ie":"=r"(ie)); - ie &= (~0x1); - asm volatile ("wcsr ie, %0"::"r"(ie)); - - /* disable mask-bit in im */ - asm volatile ("rcsr %0, im":"=r"(im)); - im &= Mask; - asm volatile ("wcsr im, %0"::"r"(im)); -} - -void enable_irq() -{ - unsigned int ie, im; - unsigned int Mask = 1; - - /* disable peripheral interrupts in-case they were enabled*/ - asm volatile ("rcsr %0,ie":"=r"(ie)); - ie &= (~0x1); - asm volatile ("wcsr ie, %0"::"r"(ie)); - - /* enable mask-bit in im */ - asm volatile ("rcsr %0, im":"=r"(im)); - im |= Mask; - asm volatile ("wcsr im, %0"::"r"(im)); - - ie |= 0x1; - asm volatile ("wcsr ie, %0"::"r"(ie)); -} diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/ram.ld b/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/ram.ld deleted file mode 100644 index 86ec2e94..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/target/lm32/ram.ld +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Simulator Link script for Lattice Mico32. - * Contributed by Jon Beniston - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -OUTPUT_FORMAT("elf32-lm32") -ENTRY(_start) -/*INPUT() */ -GROUP(-lgcc -lc) - -MEMORY -{ - ram : ORIGIN = 0x00000000, LENGTH = 0x10000 -} - -SECTIONS -{ - - .boot : { *(.boot) } > ram - - /* Code */ - .text : - { - . = ALIGN(4); - _ftext = .; - _ftext_rom = LOADADDR(.text); - *(.text .stub .text.* .gnu.linkonce.t.*) - *(.gnu.warning) - KEEP (*(.init)) - KEEP (*(.fini)) - /* Constructors and destructors */ - KEEP (*crtbegin*.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin*.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - KEEP (*(.jcr)) - _etext = .; - } > ram =0 - - /* Exception handlers */ - .eh_frame_hdr : { *(.eh_frame_hdr) } > ram - .eh_frame : { KEEP (*(.eh_frame)) } > ram - .gcc_except_table : { *(.gcc_except_table) *(.gcc_except_table.*) } > ram - - /* Read-only data */ - .rodata : - { - . = ALIGN(4); - _frodata = .; - _frodata_rom = LOADADDR(.rodata); - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.rodata1) - _erodata = .; - } > ram - - /* Data */ - .data : - { - . = ALIGN(4); - _fdata = .; - _fdata_rom = LOADADDR(.data); - *(.data .data.* .gnu.linkonce.d.*) - *(.data1) - SORT(CONSTRUCTORS) - _gp = ALIGN(16) + 0x7ff0; - *(.sdata .sdata.* .gnu.linkonce.s.*) - _edata = .; - } > ram - - /* BSS */ - .bss : - { - . = ALIGN(4); - _fbss = .; - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - _end = .; - PROVIDE (end = .); - } > ram - - /* First location in stack is highest address in RAM */ - PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4); - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/hdl/top/ml_605/dbe_bpm_simple/sw/uart.c b/hdl/top/ml_605/dbe_bpm_simple/sw/uart.c deleted file mode 100644 index c938c5b5..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sw/uart.c +++ /dev/null @@ -1,40 +0,0 @@ -#include - -#include "board.h" -#include "uart.h" - -#define CALC_BAUD(baudrate) \ - ( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \ - (CPU_CLOCK >> 8)) / (CPU_CLOCK >> 7) ) - -void uart_init(uart_t uart) -{ - uart->BCR = CALC_BAUD(UART_BAUDRATE); -} - -void uart_write_byte(uart_t uart, int b) -{ - if (b == '\n') - uart_write_byte(uart, '\r'); - while (uart->SR & UART_SR_TX_BUSY) ; - uart->TDR = b; -} - -void uart_write_string(uart_t uart, char *s) -{ - while (*s) - uart_write_byte(uart, *(s++)); -} - -int uart_poll(uart_t uart) -{ - return uart->SR & UART_SR_RX_RDY; -} - -int uart_read_byte(uart_t uart) -{ - if (!uart_poll(uart)) - return -1; - - return uart->RDR & 0xff; -} diff --git a/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd b/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd deleted file mode 100644 index 61c2fc62..00000000 --- a/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --- MMCM_BASE : In order to incorporate this function into the design, --- VHDL : the following instance declaration needs to be placed --- instance : in the body of the design code. The instance name --- declaration : (MMCM_BASE_inst) and/or the port declarations after the --- code : "=>" declaration maybe changed to properly reference and --- : connect this function to the design. All inputs and outputs --- : must be connected. - --- Library : In addition to adding the instance declaration, a use --- declaration : statement for the UNISIM.vcomponents library needs to be --- for : added before the entity declaration. This library --- Xilinx : contains the component declarations for all Xilinx --- primitives : primitives and points to the models that will be used --- : for simulation. - --- Copy the following two statements and paste them before the --- Entity declaration, unless they already exist. - -library UNISIM; -use UNISIM.vcomponents.all; - -library ieee; -use ieee.std_logic_1164.all; - -entity sys_pll is - generic( - -- 200 MHz input clock - g_clkin_period : real := 5.000; - g_clkbout_mult_f : real := 5.000; - - -- 100 MHz output clock - g_clk0_divide_f : real := 10.000; - -- 200 MHz output clock - g_clk1_divide : integer := 5 - ); - port( - rst_i : in std_logic := '0'; - clk_i : in std_logic := '0'; - clk0_o : out std_logic; - clk1_o : out std_logic; - locked_o : out std_logic - ); -end sys_pll; - -architecture syn of sys_pll is - - signal s_mmcm_fbin : std_logic; - signal s_mmcm_fbout : std_logic; - - signal s_clk0 : std_logic; - signal s_clk1 : std_logic; -begin - - -- MMCM_BASE: Base Mixed Mode Clock Manager - -- Virtex-6 - -- Xilinx HDL Language Template, version 13.4 - - -- Clock PLL - cmp_mmcm : MMCM_ADV - generic map( - BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => g_clkbout_mult_f, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => g_clk0_divide_f, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => g_clk1_divide, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - - CLKIN1_PERIOD => g_clkin_period, - REF_JITTER1 => 0.010, - -- Not used. Just to bypass Xilinx errors - -- Just input g_clkin_period input clock period - CLKIN2_PERIOD => g_clkin_period, - REF_JITTER2 => 0.010 - ) - port map( - -- Output clocks - CLKFBOUT => s_mmcm_fbout, - CLKFBOUTB => open, - CLKOUT0 => s_clk0, - CLKOUT0B => open, - CLKOUT1 => s_clk1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => s_mmcm_fbin, - CLKIN1 => clk_i, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_o, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => rst_i - ); - - -- Global clock buffers for "cmp_mmcm" instance - cmp_clkf_bufg : BUFG - port map( - O => s_mmcm_fbin, - I => s_mmcm_fbout - ); - - cmp_clkout0_buf : BUFG - port map( - O => clk0_o, - I => s_clk0 - ); - - cmp_clkout1_buf : BUFG - port map( - O => clk1_o, - I => s_clk1 - ); - -end syn; - diff --git a/hdl/top/pcie/.gitignore b/hdl/top/pcie/.gitignore deleted file mode 100644 index 0f813e23..00000000 --- a/hdl/top/pcie/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -#editor temporary files -*~ - diff --git a/hdl/top/pcie/Manifest.py b/hdl/top/pcie/Manifest.py deleted file mode 100644 index 78cf0c83..00000000 --- a/hdl/top/pcie/Manifest.py +++ /dev/null @@ -1,7 +0,0 @@ -if (syn_device == "xc7k325t"): - files = "top_k7.vhd" -elif (syn_device == "xc7a200t"): - files = "top_a7.vhd" -elif (syn_device == "xc6vlx240t"): - files = "top_ml605.vhd" - diff --git a/hdl/top/pcie/top_afck.vhd b/hdl/top/pcie/top_afck.vhd deleted file mode 100644 index fbcdea45..00000000 --- a/hdl/top/pcie/top_afck.vhd +++ /dev/null @@ -1,275 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -library work; -use work.abb64Package.all; -use work.ipcores_pkg.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity top is - generic ( - SIMULATION : string := "FALSE" - ); - port ( - --DDR3 memory pins - ddr3_dq : inout std_logic_vector(C_DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0); - ddr3_addr : out std_logic_vector(C_DDR_ROW_WIDTH-1 downto 0); - ddr3_ba : out std_logic_vector(C_DDR_BANK_WIDTH-1 downto 0); - ddr3_ras_n : out std_logic; - ddr3_cas_n : out std_logic; - ddr3_we_n : out std_logic; - ddr3_reset_n : out std_logic; - ddr3_ck_p : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0); - ddr3_cke : out std_logic_vector(C_DDR_CKE_WIDTH-1 downto 0); - ddr3_cs_n : out std_logic_vector(0 downto 0); - ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0); - ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0); - -- PCIe transceivers - pci_exp_rxp : in std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_rxn : in std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0); - -- Necessity signals - ddr_sys_clk_p : in std_logic; - ddr_sys_clk_n : in std_logic; - pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin) - pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock - sys_rst_n : in std_logic - ); -end entity top; - -architecture arch of top is - - signal ddr_sys_clk_i : std_logic; - signal ddr_sys_rst_i : std_logic; - signal ddr_axi_aclk_o : std_logic; - signal sys_rst_n_c : std_logic; - - signal pll_clkin : std_logic; - signal pll_clkfbout : std_logic; - signal pll_clkout0 : std_logic; - signal pll_locked : std_logic; - - signal wbone_clk : std_logic; - signal wbone_addr : std_logic_vector(31 downto 0); - signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_we : std_logic; - signal wbone_sel : std_logic_vector(0 downto 0); - signal wbone_stb : std_logic; - signal wbone_ack : std_logic; - signal wbone_cyc : std_logic; - signal wbone_rst : std_logic; - -begin - bpm_pcie_i: entity work.bpm_pcie - generic map( - SIMULATION => SIMULATION - ) - port map( - --DDR3 memory pins - ddr3_dq => ddr3_dq, - ddr3_dqs_p => ddr3_dqs_p, - ddr3_dqs_n => ddr3_dqs_n, - ddr3_addr => ddr3_addr, - ddr3_ba => ddr3_ba, - ddr3_ras_n => ddr3_ras_n, - ddr3_cas_n => ddr3_cas_n, - ddr3_we_n => ddr3_we_n, - ddr3_reset_n => ddr3_reset_n, - ddr3_ck_p => ddr3_ck_p, - ddr3_ck_n => ddr3_ck_n, - ddr3_cke => ddr3_cke, - ddr3_cs_n => ddr3_cs_n, - ddr3_dm => ddr3_dm, - ddr3_odt => ddr3_odt, - -- PCIe transceivers - pci_exp_rxp => pci_exp_rxp, - pci_exp_rxn => pci_exp_rxn, - pci_exp_txp => pci_exp_txp, - pci_exp_txn => pci_exp_txn, - -- Necessity signals - ddr_sys_clk => ddr_sys_clk_i, - ddr_sys_rst => ddr_sys_rst_i, - pci_sys_clk_p => pci_sys_clk_p, - pci_sys_clk_n => pci_sys_clk_n, - pci_sys_rst_n => sys_rst_n_c, - - -- DDR memory controller AXI4 interface -- - -- Slave interface clock - ddr_axi_aclk_o => ddr_axi_aclk_o, - ddr_axi_aresetn_o => open, - -- Slave Interface Write Address Ports - ddr_axi_awid => (others => '0'), - ddr_axi_awaddr => (others => '0'), - ddr_axi_awlen => (others => '0'), - ddr_axi_awsize => (others => '0'), - ddr_axi_awburst => (others => '0'), - ddr_axi_awlock => '0', - ddr_axi_awcache => (others => '0'), - ddr_axi_awprot => (others => '0'), - ddr_axi_awqos => (others => '0'), - ddr_axi_awvalid => '0', - ddr_axi_awready => open, - -- Slave Interface Write Data Ports - ddr_axi_wdata => (others => '0'), - ddr_axi_wstrb => (others => '0'), - ddr_axi_wlast => '0', - ddr_axi_wvalid => '0', - ddr_axi_wready => open, - -- Slave Interface Write Response Ports - ddr_axi_bid => open, - ddr_axi_bresp => open, - ddr_axi_bvalid => open, - ddr_axi_bready => '1', - -- Slave Interface Read Address Ports - ddr_axi_arid => (others => '0'), - ddr_axi_araddr => (others => '0'), - ddr_axi_arlen => (others => '0'), - ddr_axi_arsize => (others => '0'), - ddr_axi_arburst => (others => '0'), - ddr_axi_arlock => '0', - ddr_axi_arcache => (others => '0'), - ddr_axi_arprot => (others => '0'), - ddr_axi_arqos => (others => '0'), - ddr_axi_arvalid => '0', - ddr_axi_arready => open, - -- Slave Interface Read Data Ports - ddr_axi_rid => open, - ddr_axi_rdata => open, - ddr_axi_rresp => open, - ddr_axi_rlast => open, - ddr_axi_rvalid => open, - ddr_axi_rready => '1', - --/ DDR memory controller interface - -- Wishbone interface -- - -- uncomment when instantiating in another project - CLK_I => wbone_clk, - RST_I => wbone_rst, - ACK_I => wbone_ack, - DAT_I => wbone_mdin, - ADDR_O => wbone_addr(28 downto 0), - DAT_O => wbone_mdout, - WE_O => wbone_we, - STB_O => wbone_stb, - SEL_O => wbone_sel(0), - CYC_O => wbone_cyc, - --/ Wishbone interface - -- Additional exported signals for instantiation - ext_rst_o => wbone_rst - ); - - Wishbone_mem_large: if (SIMULATION = "TRUE") generate - wb_mem_sim : - entity work.wb_mem - generic map( - AWIDTH => 16, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - Wishbone_mem_sample: if (SIMULATION = "FALSE") generate - wb_mem_syn : - entity work.wb_mem - generic map( - AWIDTH => 7, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - --temporary clock assignment - wbone_clk <= pll_clkin; - - sys_reset_n_ibuf : IBUF - port map ( - O => sys_rst_n_c, - I => sys_rst_n - ); - - ddr_inclk_buf : IBUFGDS - generic map( - IBUF_LOW_PWR => false - ) - port map - (o => pll_clkin, - i => ddr_sys_clk_p, - ib => ddr_sys_clk_n - ); - - plle2_adv_inst : PLLE2_ADV - generic map - (bandwidth => "high", - compensation => "zhold", - divclk_divide => 5, - clkfbout_mult => 64, - clkfbout_phase => 0.000, - clkout0_divide => 8, - clkout0_phase => 0.000, - clkout0_duty_cycle => 0.500, - clkin1_period => 8.000, - ref_jitter1 => 0.010) - port map - -- output clocks - (clkfbout => pll_clkfbout, - clkout0 => pll_clkout0, - clkout1 => open, - clkout2 => open, - clkout3 => open, - clkout4 => open, - clkout5 => open, - -- input clock control - clkfbin => pll_clkfbout, - clkin1 => pll_clkin, - clkin2 => '0', - -- tied to always select the primary input clock - clkinsel => '1', - -- ports for dynamic reconfiguration - daddr => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Other control and status signals - LOCKED => pll_locked, - PWRDWN => '0', - RST => '0'); - - -- Output buffering - ------------------------------------- - clkout1_buf : BUFG - port map - (O => ddr_sys_clk_i, - I => pll_clkout0 - ); - - ddr_sys_rst_i <= not(pll_locked); - -end architecture; diff --git a/hdl/top/pcie/top_afcv3.vhd b/hdl/top/pcie/top_afcv3.vhd deleted file mode 100644 index fbcdea45..00000000 --- a/hdl/top/pcie/top_afcv3.vhd +++ /dev/null @@ -1,275 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -library work; -use work.abb64Package.all; -use work.ipcores_pkg.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity top is - generic ( - SIMULATION : string := "FALSE" - ); - port ( - --DDR3 memory pins - ddr3_dq : inout std_logic_vector(C_DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0); - ddr3_addr : out std_logic_vector(C_DDR_ROW_WIDTH-1 downto 0); - ddr3_ba : out std_logic_vector(C_DDR_BANK_WIDTH-1 downto 0); - ddr3_ras_n : out std_logic; - ddr3_cas_n : out std_logic; - ddr3_we_n : out std_logic; - ddr3_reset_n : out std_logic; - ddr3_ck_p : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0); - ddr3_cke : out std_logic_vector(C_DDR_CKE_WIDTH-1 downto 0); - ddr3_cs_n : out std_logic_vector(0 downto 0); - ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0); - ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0); - -- PCIe transceivers - pci_exp_rxp : in std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_rxn : in std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0); - -- Necessity signals - ddr_sys_clk_p : in std_logic; - ddr_sys_clk_n : in std_logic; - pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin) - pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock - sys_rst_n : in std_logic - ); -end entity top; - -architecture arch of top is - - signal ddr_sys_clk_i : std_logic; - signal ddr_sys_rst_i : std_logic; - signal ddr_axi_aclk_o : std_logic; - signal sys_rst_n_c : std_logic; - - signal pll_clkin : std_logic; - signal pll_clkfbout : std_logic; - signal pll_clkout0 : std_logic; - signal pll_locked : std_logic; - - signal wbone_clk : std_logic; - signal wbone_addr : std_logic_vector(31 downto 0); - signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_we : std_logic; - signal wbone_sel : std_logic_vector(0 downto 0); - signal wbone_stb : std_logic; - signal wbone_ack : std_logic; - signal wbone_cyc : std_logic; - signal wbone_rst : std_logic; - -begin - bpm_pcie_i: entity work.bpm_pcie - generic map( - SIMULATION => SIMULATION - ) - port map( - --DDR3 memory pins - ddr3_dq => ddr3_dq, - ddr3_dqs_p => ddr3_dqs_p, - ddr3_dqs_n => ddr3_dqs_n, - ddr3_addr => ddr3_addr, - ddr3_ba => ddr3_ba, - ddr3_ras_n => ddr3_ras_n, - ddr3_cas_n => ddr3_cas_n, - ddr3_we_n => ddr3_we_n, - ddr3_reset_n => ddr3_reset_n, - ddr3_ck_p => ddr3_ck_p, - ddr3_ck_n => ddr3_ck_n, - ddr3_cke => ddr3_cke, - ddr3_cs_n => ddr3_cs_n, - ddr3_dm => ddr3_dm, - ddr3_odt => ddr3_odt, - -- PCIe transceivers - pci_exp_rxp => pci_exp_rxp, - pci_exp_rxn => pci_exp_rxn, - pci_exp_txp => pci_exp_txp, - pci_exp_txn => pci_exp_txn, - -- Necessity signals - ddr_sys_clk => ddr_sys_clk_i, - ddr_sys_rst => ddr_sys_rst_i, - pci_sys_clk_p => pci_sys_clk_p, - pci_sys_clk_n => pci_sys_clk_n, - pci_sys_rst_n => sys_rst_n_c, - - -- DDR memory controller AXI4 interface -- - -- Slave interface clock - ddr_axi_aclk_o => ddr_axi_aclk_o, - ddr_axi_aresetn_o => open, - -- Slave Interface Write Address Ports - ddr_axi_awid => (others => '0'), - ddr_axi_awaddr => (others => '0'), - ddr_axi_awlen => (others => '0'), - ddr_axi_awsize => (others => '0'), - ddr_axi_awburst => (others => '0'), - ddr_axi_awlock => '0', - ddr_axi_awcache => (others => '0'), - ddr_axi_awprot => (others => '0'), - ddr_axi_awqos => (others => '0'), - ddr_axi_awvalid => '0', - ddr_axi_awready => open, - -- Slave Interface Write Data Ports - ddr_axi_wdata => (others => '0'), - ddr_axi_wstrb => (others => '0'), - ddr_axi_wlast => '0', - ddr_axi_wvalid => '0', - ddr_axi_wready => open, - -- Slave Interface Write Response Ports - ddr_axi_bid => open, - ddr_axi_bresp => open, - ddr_axi_bvalid => open, - ddr_axi_bready => '1', - -- Slave Interface Read Address Ports - ddr_axi_arid => (others => '0'), - ddr_axi_araddr => (others => '0'), - ddr_axi_arlen => (others => '0'), - ddr_axi_arsize => (others => '0'), - ddr_axi_arburst => (others => '0'), - ddr_axi_arlock => '0', - ddr_axi_arcache => (others => '0'), - ddr_axi_arprot => (others => '0'), - ddr_axi_arqos => (others => '0'), - ddr_axi_arvalid => '0', - ddr_axi_arready => open, - -- Slave Interface Read Data Ports - ddr_axi_rid => open, - ddr_axi_rdata => open, - ddr_axi_rresp => open, - ddr_axi_rlast => open, - ddr_axi_rvalid => open, - ddr_axi_rready => '1', - --/ DDR memory controller interface - -- Wishbone interface -- - -- uncomment when instantiating in another project - CLK_I => wbone_clk, - RST_I => wbone_rst, - ACK_I => wbone_ack, - DAT_I => wbone_mdin, - ADDR_O => wbone_addr(28 downto 0), - DAT_O => wbone_mdout, - WE_O => wbone_we, - STB_O => wbone_stb, - SEL_O => wbone_sel(0), - CYC_O => wbone_cyc, - --/ Wishbone interface - -- Additional exported signals for instantiation - ext_rst_o => wbone_rst - ); - - Wishbone_mem_large: if (SIMULATION = "TRUE") generate - wb_mem_sim : - entity work.wb_mem - generic map( - AWIDTH => 16, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - Wishbone_mem_sample: if (SIMULATION = "FALSE") generate - wb_mem_syn : - entity work.wb_mem - generic map( - AWIDTH => 7, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - --temporary clock assignment - wbone_clk <= pll_clkin; - - sys_reset_n_ibuf : IBUF - port map ( - O => sys_rst_n_c, - I => sys_rst_n - ); - - ddr_inclk_buf : IBUFGDS - generic map( - IBUF_LOW_PWR => false - ) - port map - (o => pll_clkin, - i => ddr_sys_clk_p, - ib => ddr_sys_clk_n - ); - - plle2_adv_inst : PLLE2_ADV - generic map - (bandwidth => "high", - compensation => "zhold", - divclk_divide => 5, - clkfbout_mult => 64, - clkfbout_phase => 0.000, - clkout0_divide => 8, - clkout0_phase => 0.000, - clkout0_duty_cycle => 0.500, - clkin1_period => 8.000, - ref_jitter1 => 0.010) - port map - -- output clocks - (clkfbout => pll_clkfbout, - clkout0 => pll_clkout0, - clkout1 => open, - clkout2 => open, - clkout3 => open, - clkout4 => open, - clkout5 => open, - -- input clock control - clkfbin => pll_clkfbout, - clkin1 => pll_clkin, - clkin2 => '0', - -- tied to always select the primary input clock - clkinsel => '1', - -- ports for dynamic reconfiguration - daddr => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Other control and status signals - LOCKED => pll_locked, - PWRDWN => '0', - RST => '0'); - - -- Output buffering - ------------------------------------- - clkout1_buf : BUFG - port map - (O => ddr_sys_clk_i, - I => pll_clkout0 - ); - - ddr_sys_rst_i <= not(pll_locked); - -end architecture; diff --git a/hdl/top/pcie/top_kc705.vhd b/hdl/top/pcie/top_kc705.vhd deleted file mode 100644 index d1f961eb..00000000 --- a/hdl/top/pcie/top_kc705.vhd +++ /dev/null @@ -1,221 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -library work; -use work.abb64Package.all; -use work.ipcores_pkg.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity top is - generic ( - SIMULATION : string := "FALSE" - ); - port ( - --DDR3 memory pins - ddr3_dq : inout std_logic_vector(C_DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0); - ddr3_addr : out std_logic_vector(C_DDR_ROW_WIDTH-1 downto 0); - ddr3_ba : out std_logic_vector(C_DDR_BANK_WIDTH-1 downto 0); - ddr3_ras_n : out std_logic; - ddr3_cas_n : out std_logic; - ddr3_we_n : out std_logic; - ddr3_reset_n : out std_logic; - ddr3_ck_p : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0); - ddr3_cke : out std_logic_vector(C_DDR_CKE_WIDTH-1 downto 0); - ddr3_cs_n : out std_logic_vector(0 downto 0); - ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0); - ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0); - -- PCIe transceivers - pci_exp_rxp : in std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_rxn : in std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0); - pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0); - -- Necessity signals - ddr_sys_clk_p : in std_logic; - ddr_sys_clk_n : in std_logic; - pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin) - pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock - sys_rst_n : in std_logic --Reset to PCIe core - ); -end entity top; - -architecture arch of top is - - signal ddr_sys_clk_i : std_logic; - signal ddr_sys_rst_i : std_logic; - signal ddr_axi_aclk_o : std_logic; - signal sys_rst_n_c : std_logic; - - signal wbone_clk : std_logic; - signal wbone_addr : std_logic_vector(31 downto 0); - signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_we : std_logic; - signal wbone_sel : std_logic_vector(0 downto 0); - signal wbone_stb : std_logic; - signal wbone_ack : std_logic; - signal wbone_cyc : std_logic; - signal wbone_rst : std_logic; - -begin - bpm_pcie_i : entity work.bpm_pcie - generic map( - SIMULATION => SIMULATION - ) - port map( - --DDR3 memory pins - ddr3_dq => ddr3_dq, - ddr3_dqs_p => ddr3_dqs_p, - ddr3_dqs_n => ddr3_dqs_n, - ddr3_addr => ddr3_addr, - ddr3_ba => ddr3_ba, - ddr3_cs_n => ddr3_cs_n, - ddr3_ras_n => ddr3_ras_n, - ddr3_cas_n => ddr3_cas_n, - ddr3_we_n => ddr3_we_n, - ddr3_reset_n => ddr3_reset_n, - ddr3_ck_p => ddr3_ck_p, - ddr3_ck_n => ddr3_ck_n, - ddr3_cke => ddr3_cke, - ddr3_dm => ddr3_dm, - ddr3_odt => ddr3_odt, - -- PCIe transceivers - pci_exp_rxp => pci_exp_rxp, - pci_exp_rxn => pci_exp_rxn, - pci_exp_txp => pci_exp_txp, - pci_exp_txn => pci_exp_txn, - -- Necessity signals - ddr_sys_clk => ddr_sys_clk_i, - ddr_sys_rst => ddr_sys_rst_i, - pci_sys_clk_p => pci_sys_clk_p, - pci_sys_clk_n => pci_sys_clk_n, - pci_sys_rst_n => sys_rst_n_c, - - -- DDR memory controller AXI4 interface -- - -- Slave interface clock - ddr_axi_aclk_o => ddr_axi_aclk_o, - ddr_axi_aresetn_o => open, - -- Slave Interface Write Address Ports - ddr_axi_awid => (others => '0'), - ddr_axi_awaddr => (others => '0'), - ddr_axi_awlen => (others => '0'), - ddr_axi_awsize => (others => '0'), - ddr_axi_awburst => (others => '0'), - ddr_axi_awlock => '0', - ddr_axi_awcache => (others => '0'), - ddr_axi_awprot => (others => '0'), - ddr_axi_awqos => (others => '0'), - ddr_axi_awvalid => '0', - ddr_axi_awready => open, - -- Slave Interface Write Data Ports - ddr_axi_wdata => (others => '0'), - ddr_axi_wstrb => (others => '0'), - ddr_axi_wlast => '0', - ddr_axi_wvalid => '0', - ddr_axi_wready => open, - -- Slave Interface Write Response Ports - ddr_axi_bid => open, - ddr_axi_bresp => open, - ddr_axi_bvalid => open, - ddr_axi_bready => '1', - -- Slave Interface Read Address Ports - ddr_axi_arid => (others => '0'), - ddr_axi_araddr => (others => '0'), - ddr_axi_arlen => (others => '0'), - ddr_axi_arsize => (others => '0'), - ddr_axi_arburst => (others => '0'), - ddr_axi_arlock => '0', - ddr_axi_arcache => (others => '0'), - ddr_axi_arprot => (others => '0'), - ddr_axi_arqos => (others => '0'), - ddr_axi_arvalid => '0', - ddr_axi_arready => open, - -- Slave Interface Read Data Ports - ddr_axi_rid => open, - ddr_axi_rdata => open, - ddr_axi_rresp => open, - ddr_axi_rlast => open, - ddr_axi_rvalid => open, - ddr_axi_rready => '1', - --/ DDR memory controller interface - - -- Wishbone interface -- - -- uncomment when instantiating in another project - CLK_I => wbone_clk, - RST_I => wbone_rst, - ACK_I => wbone_ack, - DAT_I => wbone_mdin, - ADDR_O => wbone_addr(28 downto 0), - DAT_O => wbone_mdout, - WE_O => wbone_we, - STB_O => wbone_stb, - SEL_O => wbone_sel(0), - CYC_O => wbone_cyc, - --/ Wishbone interface - -- Additional exported signals for instantiation - ext_rst_o => wbone_rst - ); - - Wishbone_mem_large: if (SIMULATION = "TRUE") generate - wb_mem_sim : - entity work.wb_mem - generic map( - AWIDTH => 16, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - Wishbone_mem_sample: if (SIMULATION = "FALSE") generate - wb_mem_syn : - entity work.wb_mem - generic map( - AWIDTH => 7, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - --temporary clock assignment - wbone_clk <= ddr_axi_aclk_o; - - sys_reset_n_ibuf: IBUF - port map ( - O => sys_rst_n_c, - I => sys_rst_n - ); - - ddr_sys_rst_i <= not sys_rst_n_c; - - ddr_inclk_buf: IBUFGDS - port map( - o => ddr_sys_clk_i, - i => ddr_sys_clk_p, - ib => ddr_sys_clk_n - ); - -end architecture; - diff --git a/hdl/top/pcie/top_ml605.vhd b/hdl/top/pcie/top_ml605.vhd deleted file mode 100644 index f43c5f41..00000000 --- a/hdl/top/pcie/top_ml605.vhd +++ /dev/null @@ -1,239 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -library work; -use work.abb64Package.all; -use work.bpm_pcie_ml605_priv_pkg.all; - -library UNISIM; -use UNISIM.VComponents.all; - -entity top is - generic ( - SIMULATION : string := "FALSE"; - -- **** - -- PCIe core parameters - -- **** - constant pcieLanes : integer := 4; - PL_FAST_TRAIN : string := "FALSE"; - PIPE_SIM_MODE : string := "FALSE"; - --*************************************************************************** - -- Necessary parameters for DDR core support - -- (dependent on memory chip connected to FPGA, not to be modified at will) - --*************************************************************************** - constant DDR_DQ_WIDTH : integer := 64; - constant DDR_PAYLOAD_WIDTH : integer := 256; - constant DDR_DQS_WIDTH : integer := 8; - constant DDR_DM_WIDTH : integer := 8; - constant DDR_ROW_WIDTH : integer := 14; - constant DDR_BANK_WIDTH : integer := 3; - constant DDR_CK_WIDTH : integer := 1; - constant DDR_CKE_WIDTH : integer := 1; - constant DDR_ODT_WIDTH : integer := 1 - ); - port ( - --DDR3 memory pins - ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0); - ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0); - ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0); - ddr3_cs_n : out std_logic_vector(0 downto 0); - ddr3_ras_n : out std_logic; - ddr3_cas_n : out std_logic; - ddr3_we_n : out std_logic; - ddr3_reset_n : out std_logic; - ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0); - ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0); - ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0); - ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0); - -- PCIe transceivers - pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0); - pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0); - pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0); - pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0); - -- Necessity signals - ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL) - ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL) - sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin) - sys_clk_n : in std_logic; --100 MHz PCIe Clock - sys_rst_n : in std_logic --Reset to PCIe core - ); -end entity top; - -architecture arch of top is - - -- WISHBONE SLAVE interface: - -- Single-Port RAM with Asynchronous Read - -- - component WB_MEM is - generic( - AWIDTH : natural range 2 to 29 := 7; - DWIDTH : natural range 8 to 128 := 64 - ); - port( - CLK_I : in std_logic; - ACK_O : out std_logic; - ADR_I : in std_logic_vector(AWIDTH-1 downto 0); - DAT_I : in std_logic_vector(DWIDTH-1 downto 0); - DAT_O : out std_logic_vector(DWIDTH-1 downto 0); - STB_I : in std_logic; - WE_I : in std_logic - ); - end component; - - signal ddr_sys_clk_i : std_logic; - signal ddr_sys_rst_i : std_logic; - signal ddr_ui_clk : std_logic; - - signal pll_clkin : std_logic; - signal pll_clkfbout : std_logic; - signal pll_clkout0 : std_logic; - signal pll_locked : std_logic; - - signal wbone_clk : std_logic; - signal wbone_addr : std_logic_vector(31 downto 0); - signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0); - signal wbone_we : std_logic; - signal wbone_sel : std_logic_vector(0 downto 0); - signal wbone_stb : std_logic; - signal wbone_ack : std_logic; - signal wbone_cyc : std_logic; - signal wbone_rst : std_logic; - -begin - bpm_pcie : bpm_pcie_ml605 - generic map( - SIMULATION => SIMULATION, - -- **** - -- PCIe core parameters - -- **** - pcieLanes => pcieLanes, - PL_FAST_TRAIN => PL_FAST_TRAIN, - PIPE_SIM_MODE => PIPE_SIM_MODE - ) - port map( - --DDR3 memory pins - ddr3_dq => ddr3_dq, - ddr3_dqs_p => ddr3_dqs_p, - ddr3_dqs_n => ddr3_dqs_n, - ddr3_addr => ddr3_addr, - ddr3_ba => ddr3_ba, - ddr3_cs_n => ddr3_cs_n, - ddr3_ras_n => ddr3_ras_n, - ddr3_cas_n => ddr3_cas_n, - ddr3_we_n => ddr3_we_n, - ddr3_reset_n => ddr3_reset_n, - ddr3_ck_p => ddr3_ck_p, - ddr3_ck_n => ddr3_ck_n, - ddr3_cke => ddr3_cke, - ddr3_dm => ddr3_dm, - ddr3_odt => ddr3_odt, - -- PCIe transceivers - pci_exp_rxp => pci_exp_rxp, - pci_exp_rxn => pci_exp_rxn, - pci_exp_txp => pci_exp_txp, - pci_exp_txn => pci_exp_txn, - -- Necessity signals - ddr_sys_clk_p => ddr_sys_clk_i, - sys_clk_p => sys_clk_p, - sys_clk_n => sys_clk_n, - sys_rst_n => sys_rst_n, - - -- DDR memory controller interface -- - -- uncomment when instantiating in another project - ddr_core_rst => ddr_sys_rst_i, - memc_ui_clk => ddr_ui_clk, - memc_ui_rst => open, - memc_cmd_rdy => open, - memc_cmd_en => '0', - memc_cmd_instr => (others => '0'), - memc_cmd_addr => (others => '0'), - memc_wr_en => '0', - memc_wr_end => '0', - memc_wr_mask => (others => '0'), - memc_wr_data => (others => '0'), - memc_wr_rdy => open, - memc_rd_data => open, - memc_rd_valid => open, - ---- memory arbiter interface - memarb_acc_req => '0', - memarb_acc_gnt => open, - --/ DDR memory controller interface - - -- Wishbone interface -- - -- uncomment when instantiating in another project - CLK_I => wbone_clk, - RST_I => wbone_rst, - ACK_I => wbone_ack, - DAT_I => wbone_mdin, - ADDR_O => wbone_addr(28 downto 0), - DAT_O => wbone_mdout, - WE_O => wbone_we, - STB_O => wbone_stb, - SEL_O => wbone_sel(0), - CYC_O => wbone_cyc, - --/ Wishbone interface - -- Additional exported signals for instantiation - ext_rst_o => wbone_rst - ); - - Wishbone_mem_large: if (SIMULATION = "TRUE") generate - wb_mem_sim : - wb_mem - generic map( - AWIDTH => 16, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - Wishbone_mem_sample: if (SIMULATION = "FALSE") generate - wb_mem_syn : - wb_mem - generic map( - AWIDTH => 7, - DWIDTH => 64 - ) - port map( - CLK_I => wbone_clk, --in std_logic; - ACK_O => wbone_ack, --out std_logic; - ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0); - DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0); - DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0); - STB_I => wbone_stb, --in std_logic; - WE_I => wbone_we --in std_logic - ); - - end generate; - - --temporary clock assignment - wbone_clk <= ddr_ui_clk; - - - ddr_inclk_bufgds : IBUFGDS - generic map( - DIFF_TERM => TRUE, - IBUF_LOW_PWR => FALSE - ) - port map( - O => ddr_sys_clk_i, - I => ddr_sys_clk_p, - IB => ddr_sys_clk_n - ); - - ddr_sys_rst_i <= wbone_rst; - -end architecture; From d4f4332bd9647f66bd0be46931b6c684ff0af9af Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 4 Sep 2024 13:00:14 -0300 Subject: [PATCH 13/17] Delete useless remote build scripts hdlmake doesn't support remote builds anymore [1], no need to keep these scripts arround. [1] from the hdlmake git history: commit 62ee528176c39c9cfc6ded37dd14e23e3cd7c40f Author: Javier D. Garcia-Lasheras Date: Tue Aug 2 00:15:09 2016 +0200 Disable remote synthesis functionality: web interface as replacement --- .../dbe_bpm2_bo_sirius/build_bitstream_remote.sh | 11 ----------- .../build_bitstream_remote.sh | 11 ----------- .../dbe_bpm2_sr_sirius/build_bitstream_remote.sh | 11 ----------- .../build_bitstream_remote.sh | 11 ----------- hdl/syn/afc_v3/dbe_pbpm/build_bitstream_remote.sh | 11 ----------- .../dbe_pbpm_with_dcc/build_bitstream_remote.sh | 11 ----------- 6 files changed, 66 deletions(-) delete mode 100755 hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_bitstream_remote.sh delete mode 100755 hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_bitstream_remote.sh delete mode 100755 hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_bitstream_remote.sh delete mode 100755 hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_bitstream_remote.sh delete mode 100755 hdl/syn/afc_v3/dbe_pbpm/build_bitstream_remote.sh delete mode 100755 hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_bitstream_remote.sh diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_pbpm/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_pbpm/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_pbpm/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_bitstream_remote.sh b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND From 0cd3067a967068ece867037b9a1437c6ff37c3c1 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 3 Sep 2024 15:14:09 -0300 Subject: [PATCH 14/17] Improve the Vivado version parsing script Use patern matching after invoking 'vivado -version'. On some conditions, Vivado prints warnings to stdout, breaking the synthesis descriptor generator. --- hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh | 2 +- .../afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_synthesis_sdb.sh | 2 +- hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh | 2 +- .../afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_synthesis_sdb.sh | 2 +- hdl/syn/afc_v3/dbe_pbpm/build_synthesis_sdb.sh | 2 +- hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_synthesis_sdb.sh | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh index 1bc5ee57..8f4249c4 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh @@ -8,7 +8,7 @@ set -u # Maximum of 16 chars SYNTH_INFO_PROJECT="bpm-gw-bo-sirius" SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) +SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2) SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_synthesis_sdb.sh index 1bc5ee57..8f4249c4 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_synthesis_sdb.sh +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/build_synthesis_sdb.sh @@ -8,7 +8,7 @@ set -u # Maximum of 16 chars SYNTH_INFO_PROJECT="bpm-gw-bo-sirius" SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) +SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2) SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh index c370434d..625d9553 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh @@ -8,7 +8,7 @@ set -u # Maximum of 16 chars SYNTH_INFO_PROJECT="bpm-gw-sr-sirius" SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) +SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2) SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_synthesis_sdb.sh index c370434d..625d9553 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_synthesis_sdb.sh +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/build_synthesis_sdb.sh @@ -8,7 +8,7 @@ set -u # Maximum of 16 chars SYNTH_INFO_PROJECT="bpm-gw-sr-sirius" SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) +SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2) SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" diff --git a/hdl/syn/afc_v3/dbe_pbpm/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_pbpm/build_synthesis_sdb.sh index 676b961d..9c15f43c 100755 --- a/hdl/syn/afc_v3/dbe_pbpm/build_synthesis_sdb.sh +++ b/hdl/syn/afc_v3/dbe_pbpm/build_synthesis_sdb.sh @@ -7,7 +7,7 @@ set -u SYNTH_INFO_PROJECT="pbpm-gw" SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) +SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2) SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" diff --git a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_synthesis_sdb.sh b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_synthesis_sdb.sh index 676b961d..9c15f43c 100755 --- a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_synthesis_sdb.sh +++ b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/build_synthesis_sdb.sh @@ -7,7 +7,7 @@ set -u SYNTH_INFO_PROJECT="pbpm-gw" SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) +SYNTH_INFO_VER=$(vivado -version | grep 'Vivado v[0-9]\{4\}.*' -m 1 | cut -d' ' -f2 | cut -d 'v' -f2) SYNTH_INFO_COMMAND="../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" From d542910e4add8de45f4e068fccefc157d6b82d49 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Thu, 5 Sep 2024 09:00:49 -0300 Subject: [PATCH 15/17] Remove leftover test_adc_clk synth target Forgot to delete this in bc9c4515edc2eb91e3bc93ab893332dc1b921933 --- hdl/syn/afc_v3/test_adc_clk/Manifest.py | 13 ------------- 1 file changed, 13 deletions(-) delete mode 100755 hdl/syn/afc_v3/test_adc_clk/Manifest.py diff --git a/hdl/syn/afc_v3/test_adc_clk/Manifest.py b/hdl/syn/afc_v3/test_adc_clk/Manifest.py deleted file mode 100755 index 987bb204..00000000 --- a/hdl/syn/afc_v3/test_adc_clk/Manifest.py +++ /dev/null @@ -1,13 +0,0 @@ -target = "xilinx" -action = "synthesis" - -syn_device = "xc7a200t" -syn_grade = "-1" -syn_package = "ffg1156" -syn_top = "dbe_bpm_dsp" -syn_project = "dbe_bpm_dsp" -syn_tool = "vivado" - -machine_pkg = "uvx_130M" - -modules = { "local" : [ "../../../top/afc_v3/vivado/test_adc_clk" ] } From 70859a24fe572aed1c9a146836e285f4517a7076 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 3 Sep 2024 14:20:58 -0300 Subject: [PATCH 16/17] Harmonize all Vivado synthesis and implementation flags Now all targets have the same synthesis and implementation flags. Also changes the optimization strategy to "ExploreWithRemap" to improve timing closure. --- hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py | 8 ++++++-- hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py | 5 ++++- hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py | 7 +++++-- hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py | 3 +++ hdl/syn/afc_v3/dbe_pbpm/Manifest.py | 7 +++++-- hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py | 9 +++++++++ 6 files changed, 32 insertions(+), 7 deletions(-) diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py index 8fdc4177..b18518ea 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py @@ -19,17 +19,21 @@ ["steps.synth_design.args.retiming", "1"], ["steps.synth_design.args.assert", "1"], ["steps.opt_design.args.verbose", "1"], + ["steps.opt_design.args.directive", "ExploreWithRemap"], ["steps.opt_design.is_enabled", "1"], - ["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"], + ["steps.phys_opt_design.args.directive", "Explore"], ["steps.phys_opt_design.args.more options", "-verbose"], ["steps.phys_opt_design.is_enabled", "1"], - ["steps.post_route_phys_opt_design.args.directive", "AddRetime"], + ["steps.route_design.args.directive", "NoTimingRelaxation"], + ["steps.route_design.args.more options", "-tns_cleanup"], + ["steps.post_route_phys_opt_design.args.directive", "Explore"], ["steps.post_route_phys_opt_design.args.more options", "-verbose"], ["steps.post_route_phys_opt_design.is_enabled", "1"], ["steps.write_bitstream.args.verbose", "1"], ["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"] ] + board = "afc" # For appending the afc_ref_design.xdc to synthesis diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py index e121c55b..af97e71c 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py @@ -19,15 +19,18 @@ ["steps.synth_design.args.retiming", "1"], ["steps.synth_design.args.assert", "1"], ["steps.opt_design.args.verbose", "1"], + ["steps.opt_design.args.directive", "ExploreWithRemap"], ["steps.opt_design.is_enabled", "1"], ["steps.phys_opt_design.args.directive", "Explore"], ["steps.phys_opt_design.args.more options", "-verbose"], ["steps.phys_opt_design.is_enabled", "1"], + ["steps.route_design.args.directive", "NoTimingRelaxation"], + ["steps.route_design.args.more options", "-tns_cleanup"], ["steps.post_route_phys_opt_design.args.directive", "Explore"], ["steps.post_route_phys_opt_design.args.more options", "-verbose"], ["steps.post_route_phys_opt_design.is_enabled", "1"], ["steps.write_bitstream.args.verbose", "1"], - ["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"], + ["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"] ] board = "afc" diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py index 556d7fac..0851472f 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py @@ -19,11 +19,14 @@ ["steps.synth_design.args.retiming", "1"], ["steps.synth_design.args.assert", "1"], ["steps.opt_design.args.verbose", "1"], + ["steps.opt_design.args.directive", "ExploreWithRemap"], ["steps.opt_design.is_enabled", "1"], - ["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"], + ["steps.phys_opt_design.args.directive", "Explore"], ["steps.phys_opt_design.args.more options", "-verbose"], ["steps.phys_opt_design.is_enabled", "1"], - ["steps.post_route_phys_opt_design.args.directive", "AddRetime"], + ["steps.route_design.args.directive", "NoTimingRelaxation"], + ["steps.route_design.args.more options", "-tns_cleanup"], + ["steps.post_route_phys_opt_design.args.directive", "Explore"], ["steps.post_route_phys_opt_design.args.more options", "-verbose"], ["steps.post_route_phys_opt_design.is_enabled", "1"], ["steps.write_bitstream.args.verbose", "1"], diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py index fbaf8c6e..66ae1ddf 100755 --- a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py @@ -19,10 +19,13 @@ ["steps.synth_design.args.retiming", "1"], ["steps.synth_design.args.assert", "1"], ["steps.opt_design.args.verbose", "1"], + ["steps.opt_design.args.directive", "ExploreWithRemap"], ["steps.opt_design.is_enabled", "1"], ["steps.phys_opt_design.args.directive", "Explore"], ["steps.phys_opt_design.args.more options", "-verbose"], ["steps.phys_opt_design.is_enabled", "1"], + ["steps.route_design.args.directive", "NoTimingRelaxation"], + ["steps.route_design.args.more options", "-tns_cleanup"], ["steps.post_route_phys_opt_design.args.directive", "Explore"], ["steps.post_route_phys_opt_design.args.more options", "-verbose"], ["steps.post_route_phys_opt_design.is_enabled", "1"], diff --git a/hdl/syn/afc_v3/dbe_pbpm/Manifest.py b/hdl/syn/afc_v3/dbe_pbpm/Manifest.py index ec86df19..a12e24ef 100755 --- a/hdl/syn/afc_v3/dbe_pbpm/Manifest.py +++ b/hdl/syn/afc_v3/dbe_pbpm/Manifest.py @@ -14,11 +14,14 @@ ["steps.synth_design.args.retiming", "1"], ["steps.synth_design.args.assert", "1"], ["steps.opt_design.args.verbose", "1"], + ["steps.opt_design.args.directive", "ExploreWithRemap"], ["steps.opt_design.is_enabled", "1"], - ["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"], + ["steps.phys_opt_design.args.directive", "Explore"], ["steps.phys_opt_design.args.more options", "-verbose"], ["steps.phys_opt_design.is_enabled", "1"], - ["steps.post_route_phys_opt_design.args.directive", "AddRetime"], + ["steps.route_design.args.directive", "NoTimingRelaxation"], + ["steps.route_design.args.more options", "-tns_cleanup"], + ["steps.post_route_phys_opt_design.args.directive", "Explore"], ["steps.post_route_phys_opt_design.args.more options", "-verbose"], ["steps.post_route_phys_opt_design.is_enabled", "1"], ["steps.write_bitstream.args.verbose", "1"], diff --git a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py index eb573bd2..b054c41a 100755 --- a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py +++ b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py @@ -14,7 +14,16 @@ ["steps.synth_design.args.retiming", "1"], ["steps.synth_design.args.assert", "1"], ["steps.opt_design.args.verbose", "1"], + ["steps.opt_design.args.directive", "ExploreWithRemap"], ["steps.opt_design.is_enabled", "1"], + ["steps.phys_opt_design.args.directive", "Explore"], + ["steps.phys_opt_design.args.more options", "-verbose"], + ["steps.phys_opt_design.is_enabled", "1"], + ["steps.route_design.args.directive", "NoTimingRelaxation"], + ["steps.route_design.args.more options", "-tns_cleanup"], + ["steps.post_route_phys_opt_design.args.directive", "Explore"], + ["steps.post_route_phys_opt_design.args.more options", "-verbose"], + ["steps.post_route_phys_opt_design.is_enabled", "1"], ["steps.write_bitstream.args.verbose", "1"], ["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"] ] From 68d62d190ce6637c7542205bb3192ca7ba993b3f Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Thu, 5 Sep 2024 09:21:20 -0300 Subject: [PATCH 17/17] Add script to check if timing passes More convenient than opening the Vivado GUI to checking for timing violations. --- hdl/syn/afc_v3/check_timing.tcl | 13 +++++++++++++ hdl/syn/afc_v3/dbe_bpm2_bo_sirius/check_timing.sh | 3 +++ .../dbe_bpm2_bo_sirius_with_dcc/check_timing.sh | 3 +++ hdl/syn/afc_v3/dbe_bpm2_sr_sirius/check_timing.sh | 3 +++ .../dbe_bpm2_sr_sirius_with_dcc/check_timing.sh | 3 +++ hdl/syn/afc_v3/dbe_pbpm/check_timing.sh | 3 +++ hdl/syn/afc_v3/dbe_pbpm_with_dcc/check_timing.sh | 3 +++ 7 files changed, 31 insertions(+) create mode 100644 hdl/syn/afc_v3/check_timing.tcl create mode 100755 hdl/syn/afc_v3/dbe_bpm2_bo_sirius/check_timing.sh create mode 100755 hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/check_timing.sh create mode 100755 hdl/syn/afc_v3/dbe_bpm2_sr_sirius/check_timing.sh create mode 100755 hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/check_timing.sh create mode 100755 hdl/syn/afc_v3/dbe_pbpm/check_timing.sh create mode 100755 hdl/syn/afc_v3/dbe_pbpm_with_dcc/check_timing.sh diff --git a/hdl/syn/afc_v3/check_timing.tcl b/hdl/syn/afc_v3/check_timing.tcl new file mode 100644 index 00000000..23169b1e --- /dev/null +++ b/hdl/syn/afc_v3/check_timing.tcl @@ -0,0 +1,13 @@ +set wns [get_property STATS.WNS [get_runs impl_1]] +set whs [get_property STATS.WHS [get_runs impl_1]] + +puts "WNS: ${wns}" +puts "WHS: ${whs}" + +if {($wns < 0) || ($whs < 0)} { + puts "Failed timing!" + exit 1 +} else { + puts "Passed timing." + exit 0 +} diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/check_timing.sh b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/check_timing.sh new file mode 100755 index 00000000..87a8aee5 --- /dev/null +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius/check_timing.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +vivado dbe_bpm2.xpr -mode batch -source ../check_timing.tcl diff --git a/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/check_timing.sh b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/check_timing.sh new file mode 100755 index 00000000..3e8691f3 --- /dev/null +++ b/hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/check_timing.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +vivado dbe_bpm2_with_dcc.xpr -mode batch -source ../check_timing.tcl diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/check_timing.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/check_timing.sh new file mode 100755 index 00000000..87a8aee5 --- /dev/null +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius/check_timing.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +vivado dbe_bpm2.xpr -mode batch -source ../check_timing.tcl diff --git a/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/check_timing.sh b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/check_timing.sh new file mode 100755 index 00000000..3e8691f3 --- /dev/null +++ b/hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/check_timing.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +vivado dbe_bpm2_with_dcc.xpr -mode batch -source ../check_timing.tcl diff --git a/hdl/syn/afc_v3/dbe_pbpm/check_timing.sh b/hdl/syn/afc_v3/dbe_pbpm/check_timing.sh new file mode 100755 index 00000000..11c0d8f5 --- /dev/null +++ b/hdl/syn/afc_v3/dbe_pbpm/check_timing.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +vivado dbe_pbpm.xpr -mode batch -source ../check_timing.tcl diff --git a/hdl/syn/afc_v3/dbe_pbpm_with_dcc/check_timing.sh b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/check_timing.sh new file mode 100755 index 00000000..5bb3e54c --- /dev/null +++ b/hdl/syn/afc_v3/dbe_pbpm_with_dcc/check_timing.sh @@ -0,0 +1,3 @@ +#!/bin/sh + +vivado dbe_pbpm_with_dcc.xpr -mode batch -source ../check_timing.tcl